19-0435; Rev 0; 9/95 KIT ATION EVALU E L B A IL AVA Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface ________________________Applications Industrial-Control Systems Robotics Data-Acquisition Systems Automatic Testing Systems Medical Instruments Telecommunications Functional Diagram appears at end of data sheet. ____________________________Features ♦ 12-Bit Resolution, 1/2LSB Linearity ♦ Single +5V Supply Operation ♦ Software-Selectable Input Ranges: ±10V, ±5V, 0V to +10V, 0V to +5V (MAX196) ±VREF, ±VREF/2, 0V to +VREF, 0V to +VREF/2 (MAX198) ♦ Internal 4.096V or External Reference ♦ Fault-Protected Input Multiplexer ♦ 6 Analog Input Channels ♦ 6µs Conversion Time, 100ksps Sampling Rate ♦ Internal or External Acquisition Control ♦ Two Power-Down Modes ♦ Internal or External Clock ______________Ordering Information PART TEMP. RANGE MAX196ACNI 0°C to +70°C PIN-PACKAGE 28 Narrow Plastic DIP MAX196BCNI MAX196ACWI MAX196BCWI MAX196ACAI MAX196BCAI 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP Ordering Information continued at end of data sheet. __________________Pin Configuration TOP VIEW CLK 1 28 DGND CS 2 27 V DD D11 3 26 WR D10 4 25 RD D9 5 D8 6 MAX196 MAX198 D7 7 24 INT 23 REF 22 REFADJ D6 8 21 CH5 D5 9 20 CH4 D4 10 19 CH3 D3 11 18 CH2 D2 12 17 CH1 D1 13 16 CH0 D0 14 15 AGND DIP/SO/SSOP/Ceramic SB ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-722-8266 for free samples or literature. 1 MAX196/MAX198 _______________General Description The MAX196/MAX198 multirange, 12-bit data-acquisition systems (DAS) require only a single +5V supply for operation, yet convert analog signals at their inputs up to ±10V (MAX196) and ±4V (MAX198). These systems provide six analog input channels that are independently software programmable for a variety of ranges: ±10V, ±5V, 0V to +10V, and 0V to +5V for the MAX196; ±VREF, ±VREF/2, 0V to +VREF, and 0V to +VREF/2 for the MAX198. This range switching increases the effective dynamic range to 14 bits and provides the flexibility to interface ±12V, ±15V, and 4mA to 20mA powered sensors to a single +5V system. In addition, these converters are fault protected to ±16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, 100ksps throughput rate, software-selectable internal/external clock, internal/external acquisition control, 12-bit parallel interface, and internal 4.096V or external reference. Two programmable power-down modes (STBYPD, FULLPD) provide low-current shutdown between conversions. In STBYPD mode, the reference buffer remains active, eliminating start-up delays. The MAX196/MAX198 employ a standard microprocessor (µP) interface. A three-state data I/O port is configured to operate with 16-bit data buses, and dataaccess and bus-release timing specifications are compatible with most popular µPs. All logic inputs and outputs are TTL/CMOS compatible. These devices are available in 28-pin DIP, wide SO, SSOP (55% smaller in area than wide SO), and ceramic SB packages. For 8+4 bus interface, see the MAX197 and the MAX199 data sheets. An evaluation kit will be available after December 1995 (MAX196EVKIT-DIP). MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +7V AGND to DGND.....................................................-0.3V to +0.3V REF to AGND..............................................-0.3V to (VDD + 0.3V) REFADJ to AGND.......................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V) Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V) CH0–CH5 to AGND ..........................................................±16.5V Continuous Power Dissipation (TA = +70°C) Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW Wide SO (derate 12.50mW/°C above +70°C)..............1000mW SSOP (derate 9.52mW/°C above +70°C) ......................762mW Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW Operating Temperature Ranges MAX196_C_ I/MAX198_C_ I .................................0°C to +70°C MAX196_E_ I/MAX198_E_ I ...............................-40°C to +85°C MAX196_MYI/MAX198_MYI.............................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY (Note 1) Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL ±1/2 MAX196B/MAX198B ±1 ±1 Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching MAX196A/MAX198A ±3 MAX196B/MAX198B ±5 MAX196A/MAX198A ±5 MAX196B/MAX198B ±0.1 Bipolar ±0.5 Unipolar Bipolar LSB LSB LSB ±10 Unipolar Gain Error (Note 2) Gain Temperature Coefficient (Note 2) Bits MAX196A/MAX198A LSB MAX196A/MAX198A ±7 MAX196B/MAX198B ±10 MAX196A/MAX198A ±7 MAX196B/MAX198B LSB ±10 Unipolar 3 Bipolar 5 ppm/°C DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p (MAX196) or ±4.096Vp-p (MAX198), fSAMPLE = 100ksps) Signal-to-Noise + Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR MAX196A/MAX198A 70 MAX196B/MAX198B 69 Up to the 5th harmonic dB -85 80 -78 dB dB Channel-to-Channel Crosstalk 50kHz, VIN = ±5V (MAX196) or ±4V (MAX198) (Note 3) Aperture Delay External CLK mode/external acquisition control 15 ns External CLK mode/external acquisition control <50 ps 10 ns Aperture Jitter 2 Internal CLK mode/internal acquisition control (Note 4) -86 _______________________________________________________________________________________ dB Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3 µs ANALOG INPUT Track/Hold Acquisition Time fCLK = 2.0MHz -3dB rolloff Small-Signal Bandwidth ±10V or ±VREF range 5 ±5V or ±VREF/2 range 2.5 0V to 10V or 0V to VREF range 2.5 0V to 5V or 0V to VREF/2 range Unipolar MAX198 Input Voltage Range (see Table 3) VIN MAX196 Bipolar MAX198 Unipolar MAX196 1.25 0 MAX196 IIN MAX196 Bipolar MAX198 ∆VIN ∆IIN Input Resistance Input Capacitance 10 0 5 0 VREF 0 VREF/2 -10 10 -5 5 -VREF VREF -VREF/2 VREF/2 V 720 0V to 10V range 0V to 5V range 360 MAX198 Input Current MHz 0.1 10 ±10V range -1200 720 ±5V range -600 360 ±VREF range -1200 10 ±VREF/2 range -600 10 Unipolar 21 Bipolar 16 (Note 5) µA kΩ 40 pF 4.116 V INTERNAL REFERENCE REF Output Voltage REF Output Tempco (Contact Maxim Applications for guaranteed temperature drift specifications) Output Short-Circuit Current Load Regulation VREF TC VREF TA = +25°C 4.096 15 MAX196_E/MAX198_E 30 MAX196_M/MAX198_M 40 0mA to 0.5mA output current (Note 6) Capacitive Bypass at REF REFADJ Adjustment Range ppm/°C 30 mA 10 mV 4.7 REFADJ Output Voltage Buffer Voltage Gain 4.076 MAX196_C/MAX198_C 2.465 With recommended circuit (Figure 1) µF 2.500 2.535 V ±1.5 % 1.6384 V/V _______________________________________________________________________________________ 3 MAX196/MAX198 ELECTRICAL CHARACTERISTICS (continued) MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.18 V REFERENCE INPUT (buffer disabled, reference input applied to REF pin) Input Voltage Range 2.4 VREF = 4.18V Input Current Input Resistance Normal, or STANDBY power-down mode FULL power-down mode 10 kΩ FULL power-down mode 5 MΩ VDD - 50mV VDD V 4.75 5.25 Normal mode, bipolar ranges Supply Current Power-Supply Rejection Ratio (Note 8) IDD PSRR µA 1 Normal, or STANDBY power-down mode REFADJ Threshold for Buffer Disable POWER REQUIREMENTS Supply Voltage 400 18 Normal mode, unipolar ranges 6 10 STANDBY power-down mode 700 850 FULL power-down mode (Note 7) 60 120 External reference = 4.096V ±0.1 ±1/2 Internal reference ±1/2 V mA µA LSB TIMING Internal Clock Frequency fCLK External Clock Frequency Range fCLK tACQI Acquisition Time tACQE Conversion Time tCONV CCLK = 100pF 1.25 1.56 0.1 Internal acquisition External CLK 3.0 Internal CLK 3.0 External acquisition (Note 9) After FULLPD or STBYPD 6.0 Internal CLK, CCLK = 100pF 6.0 5.0 7.7 Power-up (Note 10) Reference Buffer Settling 10.0 100 Internal CLK, CCLK = 100pF To 0.1mV REF bypass capacitor fully discharged MHz µs 5 External CLK Bandgap Reference Start-Up Time MHz 2.0 3.0 External CLK Throughput Rate 2.00 62 CREF = 4.7µF CREF = 33µF µs ksps 200 µs 8 60 ms DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS) (Note 11) Input High Voltage VINH Input Low Voltage VINL 2.4 Input Leakage Current IIN VIN = 0V or VDD Input Capacitance CIN (Note 5) 4 _______________________________________________________________________________________ V 0.8 V ±10 µA 15 pF Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V 15 pF DIGITAL OUTPUTS (D11–D0, INT) Output Low Voltage VOL VDD = 4.75V, ISINK = 1.6mA Output High Voltage VOH VDD = 4.75V, ISOURCE = 1mA Three-State Output Capacitance COUT (Note 5) VDD - 1 V TIMING CHARACTERISTICS (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS Pulse Width tCS 80 ns WR Pulse Width tWR 80 ns CS to WR Setup Time tCSWS 0 ns CS to WR Hold Time tCSWH 0 ns CS to RD Setup Time tCSRS 0 ns CS to RD Hold Time tCSRH 0 CLK to WR Setup Time tCWS 100 ns CLK to WR Hold Time tCWH 50 ns ns Data Valid to WR Setup tDS 60 Data Valid to WR Hold tDH 0 RD Low to Output Data Valid tDO Figure 2, CL = 100pF (Note 12) 120 ns RD High to Output Disable tTR (Note 13) 70 ns RD Low to INT High Delay tINT1 120 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: ns ns Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges. External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB. Ground “on” channel; sine wave applied to all “off” channels. Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz. Guaranteed by design. Not tested. Use static loads only. Tested using internal reference. PSRR measured at full-scale. External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD = high control byte. Not subject to production testing. Provided for design guidance only. All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V. tDO is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V. tTR is defined as the time required for the data lines to change by 0.5V. _______________________________________________________________________________________ 5 MAX196/MAX198 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) fTONE = 10kHz fSAMPLE = 100kHz -20 fSAMPLE = 100kHz 0.050 0 -40 -60 -80 -0.050 -100 -0.100 -120 0 1000 2000 3000 4000 25 MAX196/8-4 0.4 VDD = 5V ±0.25V 0.2 VREF (V) PSRR (LSB) REF CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE 100Hz -0.2 0.18 0.16 0.14 0.12 0.10 -70 -50 -30 -10 10 30 50 70 90 110 130 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE 0.33 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) MAX196/8-6 CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB) 0 -0.6 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) 120Hz -0.4 4.080 0.20 100 POWER-SUPPLY REJECTION RATIO vs. TEMPERATURE 4.090 -55 -35 -15 10 INPUT FREQUENCY (kHz) 4.095 AV = 1.6384 +2.5V INTERNAL REFERENCE REFADJ 10.5 1 50 FREQUENCY (kHz) REFERENCE OUTPUT VOLTAGE (VREF) vs. TEMPERATURE 4.085 11.0 10.0 0 DIGITAL CODE 4.100 11.5 MAX196/8-5 0.100 MAX196/8-7 AMPLITUDE (dB) 0.150 -0.150 6 12.0 EFFECTIVE NUMBER OF BITS 0.200 MAX196/8-2 0 MAX196/8-1 0.250 EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY FFT PLOT MAX196/8-3 INTEGRAL NONLINEARITY vs. DIGITAL CODE INTEGRAL NONLINEARITY (LSB) MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface 0.32 0.31 0.30 0.29 0.28 0.27 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (°C) _______________________________________________________________________________________ Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface PIN NAME FUNCTION CLK Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode, place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical with CCLK = 100pF. Chip Select, active low 1 2 CS 3–14 D11–D0 15 AGND 16–21 CH0–CH5 Analog Input Channels 22 REFADJ Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect to VDD when using an external reference at the REF pin. 23 REF Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. 24 INT INT goes low when conversion is complete and output data is ready. 25 RD If CS is low, a falling edge on RD will enable a read operation on the data bus. 26 WR In the internal acquisition mode, when CS is low, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR starts an acquisition, and a second rising edge on WR ends acquisition and starts a conversion cycle. 27 VDD +5V Supply. Bypass with 0.1µF capacitor to AGND. 28 DGND Three-State Digital I/O, D11 = MSB Analog Ground Digital Ground _______________Detailed Description +5V Converter Operation 510k 100k The MAX196/MAX198 multirange, fault-tolerant ADCs use successive approximation and internal input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. The 12-bit parallel-output format provides easy interface to microprocessors (µPs). Figure 3 shows the MAX196/MAX198 in the simplest operational configuration. REFADJ 0.01µF MAX196 MAX198 24k Figure 1. Reference-Adjust Circuit Analog-Input Track/Hold +5V 3k DOUT 3k CLOAD DOUT CLOAD a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL Figure 2. Load Circuits for Enable Time In the internal acquisition control mode (control bit D5 set to 0), the T/H enters its tracking mode on WR’s rising edge, and enters its hold mode when the internally timed (6 clock cycles) acquisition interval ends. In bipolar mode and unipolar mode (MAX196 only), a lowimpedance input source, which settles in less than 1.5µs, is required to maintain conversion accuracy at the maximum conversion rate. When the MAX198 is configured for unipolar mode, the input does not need to be driven from a low-impedance source. The acquisition time (tAZ) is a function of the source output resistance (RS), the channel input resistance (RIN), and the T/H capacitance. _______________________________________________________________________________________ 7 MAX196/MAX198 ______________________________________________________________Pin Description MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface Acquisition time is calculated as follows: For 0V to VREF: tAZ = 9 x (RS + RIN) x 16pF For 0V to VREF/2: tAZ = 9 x (RS + RIN) x 32pF where RIN = 7kΩ and tAZ is never less than 2µs (0V to VREF range) or 3µs (0V to VREF/2 range). In the external acquisition control mode (D5 = 1), the T/H enters its tracking mode on the first WR rising edge and enters its hold mode when it detects the second WR rising edge with D5 = 0 (see External Acquisition section). Input Bandwidth The ADC’s input tracking circuitry has a 5MHz smallsignal bandwidth. When using the internal acquisition mode with an external clock frequency of 2MHz, a 100ksps throughput rate can be achieved. It is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended (MAX274/MAX275 continuous-time filters). Input Range and Protection 1 CLK DGND 28 100pF µP CONTROL INPUTS 25 RD 26 WR 2 CS 3 4 5 6 7 8 9 10 11 12 13 14 MAX196 MAX198 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 27 VDD 23 REF 22 4.7µF REFADJ 4.7µF 0.01µF 0.01µF INT CH5 CH4 CH3 CH2 CH1 CH0 AGND 24 +5V OUTPUT STATUS 21 20 19 18 17 16 ANALOG INPUTS 15 µP DATA BUS Figure 4 shows the equivalent input circuit. The fullscale input voltage depends on the voltage at the reference (VREF). The MAX196 uses a scaling factor, which allows input voltage ranges of ±10V, ±5V, 0V to +10V, or 0V to +5V with a 4.096V voltage reference (Table 1). Program the desired range by setting the appropriate control bits (D3, D4) in the control byte (Tables 2 and 3). The MAX198 does not use a scaling factor, so its input voltage range directly corresponds with the reference voltage. It can be programmed for input voltages of ±VREF, ±VREF/2, 0V to VREF, or 0V to VREF/2 (Table 3). When an external reference is applied at REFADJ, the voltage at REF is given by VREF = 1.6384 x VREFADJ (2.4V < VREF < 4.18V). The input channels are overvoltage protected to ±16.5V. This protection is active even if the device is in power-down mode. Even with VDD = 0V, the input resistive network provides current-limiting that adequately protects the device. Digital Interface Figure 3. Operational Diagram BIPOLAR VOLTAGE REFERENCE S1 UNIPOLAR 5.12k OFF R1 CH_ Input data (control byte) and output data are multiplexed on a three-state parallel interface. This parallel I/O can easily be interfaced with a µP. CS, WR, and RD control the write and read operations. CS is the standard chip-select signal, which enables a µP to address the MAX196/MAX198 as an I/O port. When high, it disables the WR and RD inputs and forces the interface into a high-Z state. CHOLD S2 T/H OUT ON S3 R2 HOLD TRACK TRACK HOLD S4 S1 = BIPOLAR/UNIPOLAR SWITCH R1 = 12.5kΩ (MAX196) OR 5.12kΩ (MAX198) S2 = INPUT MUX SWITCH R2 = 8.67kΩ (MAX196) OR ∞ (MAX198) S3, S4 = T/H SWITCH Table 1. Full Scale and Zero Scale (MAX196 only) RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE 0 to +5 0 — VREF x 1.2207 0 to +10 0 — VREF x 2.4414 ±5 — -VREF x 1.2207 VREF x 1.2207 ±10 — -VREF x 2.4414 VREF x 2.4414 Figure 4. Equivalent Input Circuit 8 _______________________________________________________________________________________ Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198 Table 2. Control-Byte Format D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) PD1 PD0 ACQMOD RNG BIP A2 A1 A0 BIT NAME 7, 6 PD1, PD0 These two bits select the clock and power-down modes (Table 4). 5 ACQMOD 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition 4 RNG 3 BIP 2, 1, 0 A2, A1, A0 DESCRIPTION Selects the full-scale voltage magnitude at the input (Table 3). Selects unipolar or bipolar conversion mode (Table 3). These are address bits for the input mux to select the “on” channel (Table 5). Table 3. Range and Polarity Selection INPUT RANGE (V) (MAX196) INPUT RANGE (V) (MAX198) 0 0 to 5 1 0 to 10 0 ±5 ±VREF/2 1 ±10 ±VREF BIP RNG 0 0 1 1 Table 4. Clock and Power-Down Selection PD1 PD0 DEVICE MODE 0 0 Normal Operation / External Clock Mode 0 to VREF/2 0 1 Normal Operation / Internal Clock Mode 0 to VREF 1 0 Standby Power-Down (STBYPD); clock mode is unaffected 1 1 Full Power-Down (FULLPD); clock mode is unaffected Table 5. Channel Selection A2 A1 A0 CH0 0 0 0 ∗ 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 CH1 CH2 CH3 CH4 CH5 ∗ ∗ ∗ ∗ ∗ _______________________________________________________________________________________ 9 MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface Input Format The control byte is latched into the device, on pins D7–D0, during a write cycle. Table 2 shows the controlbyte format. duration is internally timed. Conversion starts when this six-clock-cycle acquisition interval (3µs with f CLK = 2MHz) ends (see Figure 5). External Acquisition Use the external acquisition timing mode for precise control of the sampling aperture and/or independent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, terminates acquisition and starts conversion on WR’s rising edge (Figure 6). However, if the second control byte contains ACQMOD = 1, an indefinite acquisition interval is restarted. The address bits for the input mux must have the same values on the first and second write pulses. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Mode section). Output Data Format The output data format is binary in unipolar mode and twos-complement binary in bipolar mode. When reading the output data, CS and RD must be low. How to Start a Conversion Conversions are initiated with a write operation, which selects the mux channel and configures the MAX196/ MAX198 for either a unipolar or bipolar input range. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD bit in the input control byte offers two options for acquiring the signal: internal or external. The conversion period lasts for 12 clock cycles in either internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle will abort the conversion and start a new acquisition interval. How to Read a Conversion A standard interrupt signal, INT, is provided to allow the device to flag the µP when the conversion has ended and a valid result is available. INT goes low when conversion is complete and the output data is ready (Figures 5 and 6). It returns high on the first read cycle or if a new control byte is written. Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose tCS CS tACQI tCSWS tCSRH tCSRS tCSWH tWR tCONV WR tDH tDS CONTROL BYTE D7–D0 ACQMOD ="0" tINT1 INT RD tTR tD0 HIGH-Z DOUT DATA VALID Figure 5. Conversion Timing Using Internal Acquisition Mode 10 ______________________________________________________________________________________ HIGH-Z Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198 tCSRS tCS tCSRH CS tCSWS tWR tACQI tCSHW tCONV WR tDH tDS D7–D0 CONTROL BYTE ACQMOD = "1" CONTROL BYTE ACQMOD = "0" tINT1 INT RD tD0 tTR DATA VALID DOUT Figure 6. Conversion Timing Using External Acquisition Mode Internal Clock Mode Select internal clock mode to free the µP from the burden of running the SAR conversion clock. To select this mode, write the control byte with D7 = 0 and D6 = 1. A 100pF capacitor between the CLK pin and ground sets this frequency to 1.56MHz nominal. Figure 7 shows a linear relationship between the internal clock period and the value of the external capacitor used. INTERNAL CLOCK PERIOD (ns) Clock Modes The MAX196/MAX198 operate with either an internal or an external clock. Control bits (D6, D7) select either internal or external clock mode. Once the desired clock mode is selected, changing these bits to program power-down will not affect the clock mode. In each mode, internal or external acquisition can be used. At power-up, external clock mode is selected. 2000 1500 1000 500 0 0 50 100 150 200 250 300 350 CLOCK PIN CAPACITANCE (pF) External Clock Mode Select external clock mode by writing the control byte with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR timing relationships in internal and external acquisition modes, with an external clock. A 100kHz to 2.0MHz external clock with 45% to 55% duty cycle is required for proper operation. Operating at clock frequencies lower than 100kHz will cause a voltage droop across the hold capacitor, and subsequently degrade performance. Figure 7. Internal Clock Period vs. Clock Pin Capacitance ______________________________________________________________________________________ 11 MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWS WR ACQMOD = "0" tCWH WR GOES HIGH WHEN CLK IS HIGH ACQUISITION ENDS ACQUISITION STARTS CONVERSION STARTS CLK WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS LOW Figure 8a. External Clock and WR Timing (Internal Acquisition Mode) ACQUISITION ENDS ACQUISITION STARTS CONVERSION STARTS CLK tCWS tDH WR ACQMOD = "0" ACQMOD = "1" WR GOES HIGH WHEN CLK IS HIGH ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWH tDH WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS LOW ACQMOD = "0" Figure 8b. External Clock and WR Timing (External Acquisition Mode) 12 ______________________________________________________________________________________ Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface REF Power-On Reset At power-up, the internal power-on reset circuitry sets INT high and puts the device in normal operation/external clock mode. This state is selected to keep the internal clock from loading the external clock driver when the part is used in external clock mode. 4.096V 26 4.7µF CREF MAX196 MAX198 AV = 1.638 REFADJ 25 Internal or External Reference The MAX196/MAX198 can operate with either an internal or external reference. An external reference can be connected to either the REF pin or the REFADJ pin (Figure 9). To use the REF input directly, disable the internal buffer by tying REFADJ to VDD. Using the REFADJ input eliminates the need to buffer the reference externally. When the reference is applied at REFADJ, bypass REFADJ with a 0.01µF capacitor to AGND. The REFADJ internal buffer gain is trimmed to 1.6384 to provide 4.096V at the REF pin from a 2.5V reference. Internal Reference The internally trimmed 2.50V reference is gained through the REFADJ buffer to provide 4.096V at REF. Bypass the REF pin with a 4.7µF capacitor to AGND and the REFADJ pin with a 0.01µF capacitor to AGND. The internal reference voltage is adjustable to ±1.5% (±65 LSBs) with the reference-adjust circuit of Figure 1. External Reference At REF and REFADJ, the input impedance is a minimum of 10kΩ for DC currents. During conversions, an external reference at REF must be able to deliver 400µA DC load currents, and must have an output impedance of 10Ω or less. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor to AGND. With an external reference voltage of less than 4.096V at the REF pin or less than 2.5V at the REFADJ pin, the increase in the ratio of the RMS noise to the LSB value (FS / 4096) results in performance degradation (loss of effective bits). 0.01µF 10k 2.5V Figure 9a. Internal Reference REF 26 4.096V 4.7µF CREF MAX196 MAX198 AV = 1.638 VDD REFADJ 25 10k 2.5V Figure 9b. External Reference, Reference at REF REF 26 4.096V 4.7µF CREF MAX196 MAX198 AV = 1.638 REFADJ Power-Down Mode To save power, you can put the converter into lowcurrent shutdown mode between conversions. Two programmable power-down modes are available: STBYPD and FULLPD. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte. When power-down is asserted, it becomes effective only after the end of conversion. In all power-down modes, the interface remains active and conversion MAX196/MAX198 __________Applications Information 10k 25 2.5V 0.01µF 2.5V Figure 9c. The external reference overdrives the internal reference. ______________________________________________________________________________________ 13 MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface results may be read. Input overvoltage protection is active in all power-down modes. The device returns to normal operation on the first WR falling edge during write operation. Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7µF capacitor at the REF pin. This is a “DC” state that does not degrade after power-down of any duration. Therefore, you can use any sampling rate with this mode, without regard to start-up delays. However, in FULLPD mode, only the bandgap reference is active. Connect a 33µF capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-down ends. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less OUTPUT CODE FULL-SCALE TRANSITION 11... 111 1 LSB = FS 4096 than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50µs for settling time. Throughput rates of 10ksps offer typical supply currents of 470µA, using the recommended 33µF capacitor value. Auto-Shutdown Selecting STBYPD on every conversion automatically shuts the MAX196/MAX198 down after each conversion without requiring any start-up time on the next conversion. Transfer Function Output data coding for the MAX196/MAX198 is binary in unipolar mode with 1LSB = (FS / 4096) and twoscomplement binary in bipolar mode with 1LSB = [(2 x |FS|) / 4096]. Code transitions occur halfway between successive-integer LSB values. Figures 10 and 11 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale (FS) values, refer to Table 1. OUTPUT CODE 1 LSB = 011... 111 011... 110 11... 110 11... 101 000... 001 000... 000 111... 111 00... 011 100... 010 00... 010 100... 001 00... 001 100... 000 00... 000 0 1 2 FS 3 INPUT VOLTAGE (LSB) Figure 10. Unipolar Transfer Function 14 FS - 3/2 LSB -FS 0V INPUT VOLTAGE (LSB) Figure 11. Bipolar Transfer Function ______________________________________________________________________________________ +FS - 1 LSB 2FS 4096 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198 Layout, Grounding, and Bypassing Careful printed circuit board layout is essential for best system performance. For best performance, use a ground plane. To reduce crosstalk and noise injection, keep analog and digital signals separate. Digital ground lines can run between digital signal lines to minimize interference. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1µF and 4.7µF capacitors to AGND to minimize high- and low-frequency fluctuations. If the supply is excessively noisy, connect a 5Ω resistor between the supply and V DD , as shown in Figure 12. SUPPLY GND +5V 4.7µF R* = 5Ω 0.1µF ** VDD AGND DGND +5V DGND DIGITAL CIRCUITRY MAX196 MAX198 * OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE Figure 12. Power-Supply Grounding Connection _________________________________________________________Functional Diagram REF CH5 CH4 CH3 CH2 CH1 CH0 SIGNAL CONDITIONING BLOCK & OVERVOLTAGE TOLERANT MUX REFADJ AV = 1.638 10k +2.5V REFERENCE T/H CHARGE REDISTRIBUTION 12-BIT DAC COMP 12 CLK CS WR RD CLOCK SUCCESSIVEAPPROXIMATION REGISTER CONTROL LOGIC & LATCHES 8 INT 12 THREE-STATE, BIDIRECTIONAL I/O INTERFACE MAX196 MAX198 VDD AGND DGND D0–D11 12-BIT DATA BUS ______________________________________________________________________________________ 15 MAX196/MAX198 Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface _Ordering Information (continued) PART TEMP. RANGE ___________________Chip Topography PIN-PACKAGE MAX196BC/D 0°C to +70°C MAX196AENI -40°C to +85°C 28 Narrow Plastic DIP MAX196BENI -40°C to +85°C 28 Narrow Plastic DIP MAX196AEWI -40°C to +85°C 28 Wide SO MAX196BEWI -40°C to +85°C 28 Wide SO MAX196AEAI -40°C to +85°C 28 SSOP MAX196BEAI -40°C to +85°C 28 SSOP MAX196AMYI -55°C to +125°C 28 Narrow Ceramic SB** MAX196BMYI -55°C to +125°C 28 Narrow Ceramic SB** MAX198ACNI 0°C to +70°C 28 Narrow Plastic DIP MAX198BCNI 0°C to +70°C 28 Narrow Plastic DIP MAX198ACWI 0°C to +70°C 28 Wide SO MAX198BCWI 0°C to +70°C 28 Wide SO MAX198ACAI 0°C to +70°C 28 SSOP MAX198BCAI 0°C to +70°C 28 SSOP MAX198BC/D 0°C to +70°C Dice* MAX198AENI -40°C to +85°C 28 Narrow Plastic DIP MAX198BENI -40°C to +85°C 28 Narrow Plastic DIP MAX198AEWI -40°C to +85°C 28 Wide SO MAX198BEWI -40°C to +85°C 28 Wide SO MAX198AEAI -40°C to +85°C 28 SSOP MAX198BEAI -40°C to +85°C 28 SSOP MAX198AMYI -55°C to +125°C 28 Narrow Ceramic SB** MAX198BMYI -55°C to +125°C 28 Narrow Ceramic SB** D11 CLK V DD CS DGND Dice* V CC WR D10 RD D9 INT D8 REF D7 0.231" (5.870mm) REFADJ CH5 D6 CH4 D5 D4 CH3 D3 CH2 D1 D2 CH0 D0 AGND CH1 0.144" (3.659mm) TRANSISTOR COUNT: 2956 SUBSTRATE CONNECTED TO GND * Dice are specified at TA = +25°C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.