ON NCP4304AMNTWG Secondary side synchronous rectification driver for high efficiency smps topology Datasheet

NCP4304A, NCP4304B
Secondary Side
Synchronous Rectification
Driver for High Efficiency
SMPS Topologies
The NCP4304A/B is a full featured controller and driver tailored to
control synchronous rectification circuitry in switch mode power
supplies. Due to its versatility, it can be used in various topologies such
as flyback, forward and Half Bridge Resonant LLC.
The combination of externally adjustable minimum on and off times
helps to fight the ringing induced by the PCB layout and other
parasitic elements. Therefore, a reliable and noise less operation of the
SR system is insured.
The extremely low turn off delay time, high sink current capability
of the driver and automatic package parasitic inductance
compensation system allow to maximize synchronous rectification
MOSFET conduction time that enables further increase of SMPS
efficiency.
Finally, a wide operating VCC range combined with two versions of
driver voltage clamp eases implementation of the SR system in 24 V
output applications.
Features
• Self-Contained Control of Synchronous Rectifier in CCM, DCM, and
QR Flyback Applications
• Precise True Secondary Zero Current Detection with Adjustable
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Threshold
Automatic Parasitic Inductance Compensation Input
Typically 40 ns Turn off Delay from Current Sense Input to Driver
Zero Current Detection Pin Capability up to 200 V
Optional Ultrafast Trigger Interface for Further Improved
Performance in Applications that Work in Deep CCM
Disable Input to Enter Standby or Low Consumption Mode
Adjustable Minimum On Time Independent of VCC Level
Adjustable Minimum Off Time Independent of VCC Level
5 A/2.5 A Peak Current Sink/Source Drive Capability
Operating Voltage Range up to 30 V
Gate Drive Clamp of Either 12 V (NCP4304A) or 6 V (NCP4304B)
Low Startup and Standby Current Consumption
Maximum Frequency of Operation up to 500 kHz
SOIC−8 Package
These are Pb-Free Devices
Typical Applications
•
•
•
•
Notebook Adapters
High Power Density AC/DC Power Supplies
Gaming Consoles
All SMPS with High Efficiency Requirements
© Semiconductor Components Industries, LLC, 2013
March, 2013 − Rev. 1
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MARKING
DIAGRAM
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
4304x
ALYW G
G
NCP
4304x
ALYWG
G
DFN8
CASE 488AF
1
4304x
= Specific Device Code
x = A or B
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(*Note: Microdot may be in either location)
PINOUT INFORMATION
VCC
Min_Toff
Min_Ton
Trig/Disable
1
2
3
4
8
7
6
5
DRV
GND
COMP
CS
(NOTE: For DFN the exposed pad must be either
unconnected or preferably connected to ground.
The GND pin must be always connected to ground.)
ORDERING INFORMATION
Package
Shipping†
NCP4304ADR2G
SOIC−8
(Pb−Free)
2500 /
Tape & Reel
NCP4304BDR2G
SOIC−8
(Pb−Free)
2500 /
Tape & Reel
NCP4304AMNTWG
DFN8
(Pb−Free)
4000 /
Tape & Reel
NCP4304BMNTWG
DFN8
(Pb−Free)
4000 /
Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCP4304/D
NCP4304A, NCP4304B
Figure 1. Typical Application Example – LLC Converter
+
Vbulk
TR1
R1
C1
C2
+Vout
D3
+
+
Vcc
FLYBACK
C3
CONTROL
CIRCUITRY
FB
C5
M2
D4
GND
C4
DRV
M1
CS
R3
R4
R2
D5
R5
OK1
R6
Figure 2. Typical Application Example − DCM or QR Flyback Converter
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2
NCP4304A, NCP4304B
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
1
VCC
Supplies the driver
Pin Description
2
Min_toff
Minimum off time adjust
Adjust the minimum off time period by connecting resistor to ground.
3
Min_ton
Minimum on time adjust
Adjust the minimum on time period by connecting resistor to ground.
4
TRIG/Disable
Forced reset input
This ultrafast input turns off the SR MOSFET in CCM applications. Activates
sleep mode if pulled up for more than 100 ms.
5
CS
Current sense of the SR
MOSFET
This pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn off detection threshold is 0 mV. A resistor in series with this
pin can modify the turn off threshold if needed.
6
COMP
Compensation inductance
connection
Use as a Kelvin connection to auxiliary compensation inductance. If SR MOSFET package parasitic inductance compensation is not used (like for SMT
MOSFETs), connect this pin directly to GND pin.
7
GND
IC ground
Ground connection for the SR MOSFET driver and VCC decoupling capacitor.
Ground connection for minimum ton, toff adjust resistors and trigger input.
GND pin should be wired directly to the SR MOSFET source terminal/soldering point using Kelvin connection.
8
DRV
Gate driver output
VCC supply terminal of the controller. Accepts up to 30 V continuously.
Driver output for the SR MOSFET.
VDD
Generator Min TOFF START
Enable SET
MINIMUM OFF
TIME
GENERATOR
VDD
CS
ZCD Reset
COMP
1k5
MINIMUM ON
TIME
GENERATOR
Min_TON
&
ZCD SET
DETECTION CS
&
COMPENSATION
&
&
S
Q
R
Q
DRIVER
DRV Out
DRV
OR
VDD
Enable RESET
100 mA
Blanking of CS
during
Min TOFF, Min TON
DRV Set Enable
DRV Reset
Min_TOFF
VCC
MANAGEMENT
UVLO
VCC
Generator Min TON START
TIMER
VDD
Sleep Mode
100 ms
INV
GND
One shoot
ZCD Reset
Trig/Disable
S
Q
R
Q
&
10 mA
OR
INV
VTH = 2 V
Trigger Blanking
150 ns
during DRV rising edge
INV
One shoot
150 ns
Figure 3. Internal Circuit Architecture
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NCP4304A, NCP4304B
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
IC supply voltage
Rating
−0.3 to 30
V
VDRV
Driver output voltage
−0.3 to 17
V
VCS
Current sense input dc voltage
−4 to 200
V
VCsdyn
Current sense input dynamic voltage (tpw = 200 ns)
−10 to 200
V
VTRIG
Trigger input voltage
−0.3 to 10
V
VMin_ton, VMin_toff
Min_Ton and Min_Toff input voltage
−0.3 to 10
V
I_Min_Toff, I_Min_Toff
Min_Ton and Min_Toff current
−10 to +10
mA
Static voltage difference between GND and COMP pins (internally clamped)
−3 to 10
V
Dynamic voltage difference between GND and COMP pins (tpw = 200 ns)
−10 to 10
V
−5 to 5
mA
180
°C/W
180
°C/W
VGND−COMP
VGND−COMP_dyn
ICOMP
Current into COMP pin
Thermal Resistance Junction−to−Air, SOIC − A/B versions
RqJA
mm2
RqJA
Thermal Resistance Junction−to−Air, DFN − A/B versions, 50
spreader
− 1.0 oz. Copper
RqJA
Thermal Resistance Junction−to−Air, DFN − A/B versions, 600 mm2 − 1.0 oz. Copper
spreader
80
°C/W
TJmax
Maximum junction temperature
160
°C
TSmax
Storage Temperature Range
−60 to +150
°C
TLmax
Lead temperature (Soldering, 10 s)
300
°C
2
kV
200
V
ESD Capability, Human Body Model except pin VCS – pin 5, HBM ESD Capability on
pin 5 is 650 V
ESD Capability, Machine Model
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Machine Model Method 200 V pre JEDEC Standard JESD22−A115−A
2. This device meets latchup tests defined by JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC
= 12 V, Cload = 0 nF, R_min_ton = R_min_toff = 10 kW, Vtrig = 0 V, f_CS = 100 kHz, DC_CS = 50%, VCS_high = 4 V, VCS_low = −1 V unless
otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION
VCC_on
Turn−on threshold level (VCC going up)
1
9.3
9.9
10.5
V
VCC_off
Minimum operating voltage after turn−on (VCC going down)
1
8.3
8.9
9.5
V
VCC_hyste
VCC hysteresis
1
0.6
1.0
1.4
V
ICC1_A
ICC1_B
Internal IC consumption (no output load on pin 8, Fsw = 500 kHz,
Ton_min = 500 ns, Toff_min = 620 ns)
1
−
−
4.5
4.0
6.6
6.2
mA
ICC2_A
ICC2_B
Internal IC consumption (Cload = 1 nF on pin 8, Fsw = 400 kHz,
Ton_min = 500 ns, Toff_min = 620 ns)
1
−
−
9.0
6.5
12
9
mA
ICC3_A
ICC3_B
Internal IC consumption (Cload = 10 nF on pin 8, Fsw = 400 kHz,
Ton_min = 500 ns, Toff_min = 620 ns)
1
−
−
57.0
35.0
80
65
mA
ICC_StartUp
Startup current consumption (VCC = VCC_on − 0.1 V, no switching at
CS pin)
1
−
35
75
mA
ICC_Disable_1
Current consumption during disable mode (No switching at CS pin,
Vtrig = 5 V)
1
−
45
90
mA
ICC_Disable_2
Current consumption during disable mode (CS pin is switching,
Fsw = 500 kHz, VCS_high = 4 V, VCS_low =−1 V, Vtrig = 5 V)
1
−
200
330
mA
3. Guaranteed by design.
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NCP4304A, NCP4304B
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC
= 12 V, Cload = 0 nF, R_min_ton = R_min_toff = 10 kW, Vtrig = 0 V, f_CS = 100 kHz, DC_CS = 50%, VCS_high = 4 V, VCS_low = −1 V unless
otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
DRIVE OUTPUT
tr_A
Output voltage rise−time for A version (Cload = 10 nF)
8
−
120
−
ns
tr_B
Output voltage rise−time for B version (Cload = 10 nF)
8
−
80
−
ns
tf_A
Output voltage fall−time for A version (Cload = 10 nF)
8
−
50
−
ns
tf_B
Output voltage fall−time for B version (Cload = 10 nF)
8
−
35
−
ns
Roh
Driver source resistance (Note 3)
8
−
1.8
7
W
Rol
Driver sink resistance
8
−
1
2
W
Output source peak current
8
−
2.5
−
A
IDRV_pk(sink)
Output sink peak current
8
−
5
−
A
VDRV(min_A)
Minimum drive output voltage for A version (VCC = VCCoff + 200 mV)
8
8.3
−
−
V
VDRV(min_B)
IDRV_pk(source)
Minimum drive output voltage for B version (VCC = VCCoff + 200 mV)
8
4.5
−
−
V
VDRV(CLMP_A)
Driver clamp voltage for A version (12 < VCC < 28, Cload = 1 nF)
8
10
12
14.3
V
VDRV(CLMP_B)
Driver clamp voltage for B version (12 < VCC < 28, Cload = 1 nF)
8
5
6
8
V
CS INPUT
Tpd_on
The total propagation delay from CS input to DRV output turn on
(Vcs goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected
to GND)
5, 8
−
60
90
ns
Tpd_off
The total propagation delay from CS input to DRV output turn off
(Vcs goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to
GND), (Note 3)
5, 8
−
40
55
ns
Ishift_CS
Current sense input current source (VCS = 0 V)
5
95
100
105
mA
Vth_cs_on
Current sense pin turn−on input threshold voltage
5, 8
−120
−85
−50
mV
Vth_cs_off
Current sense pin turn−off threshold voltage, COMP pin connected
to GND (Note 3)
5, 8
−1
−
0
mV
Compensation inverter gain
5,6,8
1
mA
Gcomp
ICS_Leakage
Current Sense input leakage current, VCS = 200 Vdc
5
−1
−
−
−
TRIGGER/DISABLE INPUT
ttrig_pw_min
Minimum trigger pulse width (Note 3)
4
30
−
−
ns
Vtrig
Trigger input threshold voltage (Vtrig goes up)
4
1.5
−
2.5
V
tp_trig
Propagation delay from trigger input to the DRV output (Vtrig goes up
from 0 to 5 V, tr_trig = 5 ns)
4
−
13
30
ns
Light load turn off filter duration
4
70
100
130
ms
4
−
−
10
us
Blanking time of trigger/dis during DRV rising edge (VCS < Vth_cs_on,
single pulse on trigger/dis ttrig_pw = 50 ns)
4
−
120
−
ns
Trigger input pull down current (Vtrig = 5 V)
4
−
10
−
mA
ttrig_light_load
ttrig_light_load_rec. IC operation recovery time when leaving light load disable mode
(Vtrig goes down from 5 to 0 V, tf_trig = 5 ns)
tt_blank
Itrig
MINIMUM Ton AND Toff ADJUST
Ton_min
Minimum Ton period (RT_on_min = 0 W)
3
−
130
−
ns
Toff_min
Minimum Toff period (RT_off_min = 0 W)
2
560
600
690
ns
Ton_min
Minimum Ton period (RT_on_min = 10 kW)
3
0.9
1.0
1.1
ms
Toff_min
Minimum Toff period (RT_off_min = 10 kW)
2
0.9
1.0
1.1
ms
Ton_min
Minimum Ton period (RT_on_min = 50 kW)
3
−
4.8
−
ms
Toff_min
Minimum Toff period (RT_off_min = 50 kW)
2
−
4.8
−
ms
3. Guaranteed by design.
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NCP4304A, NCP4304B
TYPICAL CHARACTERISTICS
8.880
9.890
8.870
9.880
8.860
8.850
VCCoff (V)
VCCon (V)
9.870
9.860
8.840
8.830
9.850
8.820
9.840
8.810
9.830
8.800
9.820
−40 −25 −10 5
20
35
50
65
80
95
8.790
−40 −25 −10 5
110 125
50
65
80
95
TEMPERATURE (°C)
Figure 4. VCC Startup Voltage
Figure 5. VCC Turn−off Voltage
1.040
44
1.035
42
110 125
ICC_Startup (mA)
40
1.025
1.020
1.015
38
36
1.010
34
1.005
32
1.000
−40 −25 −10 5
20
35
50
65
80
95
30
−40 −25 −10
110 125
5
20
35
50
65
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. VCC Hysteresis
Figure 7. Startup Current
VDRV(H)_A (V) @ VCC = 12 V AND Cload 10 nF
VCC_Hyste (V)
35
TEMPERATURE (°C)
1.030
VDRV(H)_A (V) @ VCC = 12 V AND Cload 1 nF
20
12.0
95
110 125
95
110 125
12.065
11.9
12.060
11.8
12.055
11.7
12.050
11.6
11.5
12.045
11.4
12.040
11.3
12.035
11.2
12.030
11.1
11.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
12.025
−40 −25 −10 5
20
35
50
65
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Driver High Level – A Version,
VCC = 12 V and Cload = 1 nF
Figure 9. Driver High Level – A Version,
VCC = 12 V and Cload = 10 nF
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VDRV(H)_B (V) @ VCC = 12 V AND Cload 10 nF
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6.0
5.9
−40 −25 −10 5
20
35
50
65
80
95
110 125
7.65
7.60
7.55
7.50
7.45
7.40
7.35
7.30
7.25
7.20
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
Figure 10. Driver High Level – B Version,
VCC = 12 V and Cload = 1 nF
Figure 11. Driver High Level – B Version,
VCC = 12 V and Cload = 10 nF
9.10
6.40
9.05
6.30
9.00
8.95
8.90
8.85
6.20
6.10
6.00
5.90
8.80
8.75
−40 −25 −10 5
20
35
50
65
80
95
110 125
5.80
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Minimal Driver High Level−A
Version, VCC_OFF + 0.2 V and Cload = 0 nF
Figure 13. Minimal Driver High Level−B
Version, VCC_OFF + 0.2 V and Cload = 0 nF
14.0
13.8
13.6
13.4
13.2
13.0
12.8
12.6
12.4
12.2
12.0
−40 −25 −10 5
20
35
50
65
80
95
VDRV(CLMP_A) (V) @ VCC = 28 V AND CLOAD = 10 nF
VDRV(CLMP_A) (V) @ VCC = 28 V AND CLOAD = 1 nF
7.70
TEMPERATURE (°C)
VDRV(min_B) (V)
VDRV(min_A) (V)
VDRV(H)_B (V) @ VCC = 12 V AND Cload 1 nF
NCP4304A, NCP4304B
110 125
TEMPERATURE (°C)
15.0
14.5
14.0
13.5
13.0
12.5
−40 −25 −10 5
Figure 14. Driver Clamp Level−A Version, VCC
= 28 V and Cload = 1 nF
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
Figure 15. Driver Clamp Level−A Version, VCC
= 28 V and Cload = 10 nF
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7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
−40 −25 −10 5
20
35
50
65
80
95
110 125
VDRV(CLMP_B) (V) @ VCC = 28 V AND CLOAD =
10 nF
VDRV(CLMP_B) (V) @ VCC = 28 V AND CLOAD = 1 nF
NCP4304A, NCP4304B
8.2
8.0
7.8
7.6
7.4
7.2
7.0
−40 −25 −10 5
35
50
65
80
95
110 125
TEMPERATURE (°C)
Figure 16. Driver Clamp Level−B Version, VCC
= 28 V and Cload = 1 nF
Figure 17. Driver Clamp Level−B Version, VCC
= 28 V and Cload = 10 nF
45.0
40.0
50.0
35.0
TPD_OFF (ns)
40.0
30.0
20.0
30.0
25.0
20.0
15.0
10.0
10.0
5.0
0.0
−40 −25 −10 5
20
35
50
65
80
95
0.0
−40 −25 −10 5
110 125
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. CS to DRV Turn−on Propagation
Delay
Figure 19. CS to DRV Turn−off Propagation
Delay
101.0
−40.0
100.5
−50.0
−60.0
VTH_CS_on (mV)
100.0
Ishift_CS (mA)
20
TEMPERATURE (°C)
60.0
TPD_ON (ns)
8.4
99.5
99.0
98.5
−70.0
−80.0
−90.0
−100.0
98.0
−40 −25 −10 5
20
35
50
65
80
95
−110.0
−40 −25 −10 5
110 125
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. CS Pin Shift Current
Figure 21. CS Turn−on Threshold
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2.12
16.0
2.10
14.0
2.08
12.0
2.06
10.0
Tp_trig (ns)
Vtrig (V)
NCP4304A, NCP4304B
2.04
2.02
4.0
1.98
2.0
20
35
50
65
80
95
110 125
0.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Trigger Input Threshold Voltage
Figure 23. Progagation Delay from Trigger
Input to DRV Turn−off
9.210
101.5
9.205
Trig−light_load_rec (ms)
101.0
Triglight_load (ms)
6.0
2.00
1.96
−40 −25 −10 5
100.5
100.0
99.5
9.200
9.195
9.190
9.185
9.180
99.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
9.175
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. Light Load Transition Timer
Duration
Figure 25. Light Load to Normal Operation
Recovery Time
165.0
16.0
164.0
Ton_min (ns) @ Rt_on_min = 0 W
18.0
14.0
12.0
ITrig (mA)
8.0
10.0
8.0
6.0
4.0
2.0
0.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
163.0
162.0
161.0
160.0
159.0
158.0
157.0
156.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. Trigger Input Pulldown Current
Figure 27. Minimum on Time @ Rt_on_min = 0 W
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NCP4304A, NCP4304B
994.5
998.5
Toff_min (ns) @ Rt_off_min = 10 W
Ton_min (ns) @ Rt_on_min = 10 W
999.0
998.0
997.5
997.0
996.5
996.0
995.5
995.0
994.5
994.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
994.0
993.5
993.0
992.5
992.0
991.5
991.0
−40 −25 −10 5
TEMPERATURE (°C)
4880
4940
4860
4920
4820
4800
4780
4760
4740
4720
4700
5
20
35
50
65
80
95
110 125
50
65
80
95
110 125
4900
4880
4860
4840
4820
4800
4780
4760
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 30. Minimum On Time @ Rt_on_min =
53 W
Figure 31. Minimum Off Time @ Rt_off_min =
53 W
625.0
5.00
620.0
4.95
615.0
4.90
610.0
4.85
ICC1_A (mA)
Toff_min (ns) @ Rt_off_min = 50 W
4680
−40 −25 −10
35
Figure 29. Minimum Off Time @ Rt_off_min =
10 W
Ton_min (ns) @ Rt_on_min = 50 W
Toff_min (ns) @ Rt_off_min = 50 W
Figure 28. Minimum On Time @ Rt_on_min =
10 W
4840
20
TEMPERATURE (°C)
605.0
600.0
4.80
4.75
595.0
4.70
590.0
4.65
585.0
−40 −25 −10 5
20
35
50
65
80
95
110 125
4.60
−40 −25 −10 5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 32. Minimum Off Time @ Rt_off_min =
0W
Figure 33. Internal IC Consumption (A Version,
No Load on Pin 8, FSW = 500 kHz,
Ton_min = 500 ns, Toff_min = 620 ns)
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NCP4304A, NCP4304B
4.200
9.35
4.180
9.30
4.140
ICC2_A (mA)
ICC1_B (mA)
4.160
4.120
4.100
4.080
4.060
9.25
9.20
9.15
9.10
4.040
4.020
−40 −25 −10
5
20 35 50 65 80
TEMPERATURE (°C)
95
9.05
−40 −25 −10 5
110 125
Figure 34. Internal IC Consumption (B version,
No Load on Pin 8, FSW = 500 kHz,
Ton_min = 500 ns, Toff_min = 620 ns)
95
110 125
Figure 35. Internal IC Consumption (A Version,
Cload = 1 nF on Pin 8, FSW = 400 kHz,
Ton_min = 500 ns, Toff_min = 620 ns)
7.60
52.8
52.7
7.40
52.6
ICC3_A (mA)
7.20
7.00
6.80
6.60
52.5
52.4
52.3
52.2
52.1
6.40
52.0
6.20
−40 −25 −10
5
20 35 50 65 80
TEMPERATURE (°C)
95
110 125
51.9
−40 −25 −10 5
Figure 36. Internal IC Consumption
(B Version, Cload = 1 nF on Pin 8, FSW =
400 kHz, Ton_min = 500 ns, Toff_min = 620 ns)
20 35 50 65 80
TEMPERATURE (°C)
34.5
34.0
33.5
33.0
32.5
−40 −25 −10 5
20
95
110 125
Figure 37. Internal IC Consumption (A Version,
Cload = 10 nF on Pin 8, FSW = 400 kHz,
Ton_min = 500 ns, Toff_min = 620 ns)
35.0
ICC3_B (mA)
ICC2_B (mA)
20 35 50 65 80
TEMPERATURE (°C)
35
50
65
80
95
110 125
TEMPERATURE (°C)
Figure 38. Internal IC Consumption (B Version, Cload
= 10 nF on Pin 8, FSW = 400 kHz, Ton_min = 500 ns,
Toff_min = 620 ns)
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NCP4304A, NCP4304B
APPLICATION INFORMATION
General Description
of −10 mV to −5 mV, the NCP4304A/B offers a turn off
threshold of 0 mV that in combination with a low RDS(on) SR
MOSFET significantly reduces the turn off current
threshold and improves efficiency.
To overcome issues after turn on and off events, the
NCP4304A/B provides adjustable minimum on time and off
time blanking periods. Blanking times can be adjusted
independently of IC VCC using resistors connected to GND.
If needed, blanking periods can be modulated using
additional components.
An ultrafast trigger input helps to implement synchronous
rectification systems in CCM applications (like CCM
flyback or forward). The time delay from trigger input to
driver turn off event is 10 ns (typicaly). Additionally, the
trigger input can be used to disable the IC and activate a low
consumption standby mode. This feature can be used to
decrease standby consumption of an SMPS.
Finally, the NCP4304A/B features a special input that can
be used to automatically compensate for SR MOSFET
parasitic inductance effect. This technique achieves the
maximum available on−time and thus optimizes efficiency
when a MOSFET in standard package (like TO−220 or
TO247) is used. If a SR MOSFET in SMT package with
negligible inductance is used, the compensation input is
connected to GND pin.
The NCP4304A/B is designed to operate either as a
standalone IC or as a companion IC to a primary side
controller to help achieve efficient synchronous
rectification in switch mode power supplies. This controller
features a high current gate driver along with high−speed
logic circuitry to provide appropriately timed drive signals
to a synchronous rectification MOSFET. With its novel
architecture, the NCP4304A/B has enough versatility to
keep the synchronous rectification efficient under any
operating mode.
The NCP4304A/B works from an available bias supply
with voltage range from 10.4 V to 28 V (typical). The wide
VCC range allows direct connection to the SMPS output
voltage of most adapters such as notebook and LCD TV
adapters. As a result, the NCP4304A/B simplifies circuit
operation compared to other devices that require specific
bias power supplies (e.g. 5 V). The high voltage capability
of the VCC is also a unique feature designed to allow
operation for a broader range of applications.
Precise turn off threshold of the current sense comparator
together with accurate offset current source allows the user
to adjust for any required turn off current threshold of the SR
MOSFET switch using a single resistor. Compared to other
SR controllers that provide turn off thresholds in the range
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NCP4304A, NCP4304B
Zero Current Detection and Parasitic Inductance
Compensation
rectification MOSFET is depicted with it’s parasitic
inductances to demonstrate operation of the compensation
system.
Figure 39 shows the internal connection of the ZCD
circuitry on the current sense input. The synchronous
Figure 39. ZCD Sensing Circuitry Functionality
When the voltage on the secondary winding of the SMPS
reverses, the body diode of M1 starts to conduct current and
the voltage of M1’s drain drops approximately to −1 V. The
CS pin sources current of 100 mA that creates a voltage drop
on the Rshift_cs resistor. Once the voltage on the CS pin is
lower than Vth_cs_on threshold, M1 is turned on. Because of
parasitic impedances, significant ringing can occur in the
application. To overcome sudden turn−off due to mentioned
ringing, the minimum conduction time of the SR MOSFET
is activated. Minimum conduction time can be adjusted
using R_Min_Ton resistor.
The SR MOSFET is turned−off as soon as the voltage on
the CS pin is higher than Vth_cs_off. For the same ringing
reason, a minimum off time timer is asserted once the
turn-off is detected. The minimum off time can be externally
adjusted using R_Min_Toff resistor. MOSFET M1 conducts
when the secondary current decreases, therefore the turn−off
time depends on its RDS(on). The 0 mV threshold provides
an optimum switching period usage while keeping enough
time margin for the gate turn off. The Rshift_cs resistor
provides the designer with the possibility to modify
(increase) the actual turn-off current threshold.
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NCP4304A, NCP4304B
Figure 40. ZCD Comparators Thresholds and Blanking Periods Timing
If no Rshift_cs resistor is used, the turn−on and turn−off
thresholds are fully given by the CS input specification
(please refer to parametric table). Once non−zero Rshift_cs
resistor is used, both thresholds move down (i.e. higher
MOSFET turn off current) as the CS pin offset current
causes a voltage drop that is equal to:
V_Rshift_cs + Rshift_cs * Ishift_cs
Note that Rshift_cs impact on turn−on threshold is less
critical compare to turn−off threshold.
If using a SR MOSFET in TO−220 package (or other
package which features leads), the parasitic inductance of
the package leads causes a turn−off current threshold
increase. This is because current that flows through the SR
MOSFET has quite high di(t)/dt that induces error voltage
on the SR MOSFET leads inductance. This error voltage,
that is proportional to the secondary current derivative,
shifts the CS input voltage to zero when significant current
still flows through the channel. Zero current threshold is thus
detected when current still flows through the SR MOSFET
channel – please refer to Figure 41 for better understanding.
As a result, the SR MOSFET is turned−off prematurely and
the efficiency of the SMPS is not optimized.
(eq. 1)
Final turn−on and turn−off thresholds can be then calculated
as:
VCS_turn_on + Vth_CS_on * (Rshift_cs * Ishift_cs)
(eq. 2)
VCS_turn_off + Vth_CS_off * (Rshift_cs * Ishift_cs)
(eq. 3)
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NCP4304A, NCP4304B
Figure 41. Waveforms from SR System Using MOSFET in TO−220 Package Without Parasitic Inductance
Compensation – SR MOSFET Channel Conduction Time is Reduced
Note that the efficiency impact of the error caused by
parasitic inductance increases with lower Rds_on
MOSFETs and/or higher operating frequency.
The NCP4304A/B offers a way to compensate for
MOSFET parasitic inductances effect - refer to Figure 42.
Figure 42. Package Parasitic Inductances Compensation Principle
comparator thus “sees” between its terminals a voltage that
would be seen on the SR MOSFET channel resistance in
case the lead inductances wouldn’t exist. The current sense
comparator of the NCP4304A/B is thus able to detect the
secondary current zero crossing very precisely. More over,
the secondary current turn−off threshold is then di(t)/t
independent thus the NCP4304A/B allows to increase
operating frequency of the SR system. One should note that
the parasitic resistance of compensation inductance should
Dedicated input (COMP) offers the possibility to use an
external compensation inductance (wire strap or PCB). If
the value of this compensation inductance is Lcomp = Ldrain
+ Lsource, the compensation voltage created on this
inductance is exactly the same as the sum of error voltages
created on drain and source parasitic inductances i.e. VLdrain
+ Vlsource. The internal analog inverter (Figure 39) inverts
compensation voltage Vl_comp and offsets the current
sense comparator turn−off threshold. The current sense
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NCP4304A, NCP4304B
compensated SR system can be seen in Figure 43. One can
see the conduction time has been significantly increased and
turn−off current reduced.
be as low as possible compared to the SR MOSFET channel
and leads resistance otherwise compensation is not efficient.
Typical value of compensation inductance for a TO−220
package is 7 nH. Waveforms from the application with
Figure 43. Waveforms SR System Using MOSFET in TO−220 Package with Parasitic Inductance Compensation –
SR MOSFET Channel Conduction Time is Optimized
comparator. Ideally the CS turn–off comparator should
detect voltage that is caused by secondary current directly on
the SR MOSFET channel resistance. Practically this is not
possible because of the bonding wires, leads and soldering.
To assure the best efficiency results, a Kelvin connection of
the SR controller to the power circuitry should be
implemented (i.e. GND pin should be connected to the SR
MOSFET source soldering point and current sense pin
should be connected to the SR MOSFET drain soldering
point). Any impact of PCB parasitic elements on the SR
controller functionality is then avoided. Figures 44 and 45
show examples of SR system layouts using parasitic
inductance compensation (i.e. for low RDS(on) MOSFET in
TO−220 package ) and not using compensation (i.e. for
higher RDS(on) MOSFET in TO−220 package or SMT
package MOSFETs).
Note that using the compensation system is only
beneficial in applications that are using a low RDS(on)
MOSFET in non−SMT package. Using the compensation
method allows for optimized efficiency with a standard
TO220 package that in turn results in reduced costs, as the
SMT MOSFETs usually require reflow soldering process
and more expensive PCB.
From the above paragraphs and parameter tables it is
evident that turn−off threshold precision is quite critical. If
we consider a SR MOSFET with Rds_on of 1 mW, the 1 mV
error voltage on the CS pin results in a 1 A turn−off current
threshold difference. Thus the PCB layout is very critical
when implementing the SR system. Note that the CS
turn−off comparator as well as compensation inputs are
referred to the GND pin. Any parasitic impedance (resistive
or inductive − talking about mW and nH values) can cause
a high error voltage that is then evaluated by the CS
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NCP4304A, NCP4304B
NCP4304
Figure 44. Recommended Layout When Parasitic
Inductance Compensation is Used
Figure 45. Recommended Layout When Parasitic
Inductance Compensation is Not Used
Trigger/Disable input
2.5 V) the driver is disabled immediately, except during
DRV rising edge when trigger/dis is blanked for 150 ns. If
the trigger signal is high for more than 100 ms the driver
enters standby mode. The IC consumption is reduced below
100 mA during the standby mode. The device recovers
operation in 10 ms when the trigger voltage is increased to
exit standby mode. Trigger/dis input is superior to CS input
except blanking period. Trigger/dis signal turns−OFF the SR
MOSFET or disable its turn−ON if trigger/dis is pulled
above Vtrig.
The NCP4304A/B features an ultrafast trigger input that
exhibits a typically of 10 ns delay from its activation to the
turn−off of the SR MOSFET. The main purpose of this input
is to turn-off the SR MOSFET in applications operating in
CCM mode via a signal coming from the primary side or
direct synchronization SR MOSFET turn−on and turn−off
event according to primary controller signals. The
NCP4304A/B operation can be disabled using the
trigger/dis input. If the trigger/dis input is pulled high (above
trigger/dis
Figure 46. Trigger Input Internal Circuitry
pulled LOW and CS (Vds) is still under Vth_cs_ON threshold
then the DRV is turned−ON (t7 marker).
Time markers t14 and t15 in Figure 47 demonstrate
situation when CS (Vds) is above Vth_cs_ON threshold and
trigger/dis is pulled down. In this case the driver stays LOW
(t12 to t15 marker).
Figure 47 depicts driver turn−ON events. Turn−ON of the
SR MOSFET is possible if CS (Vds) signal falls under
Vth_cs_ON threshold and trigger/dis is pulled LOW (t1 to t3
time interval).
When the CS (Vds) reached the Vth_cs_ON threshold and
trigger/dis is pulled HIGH the driver stays LOW (t6, t7 time
markers) if the trigger/dis is HIGH. If the trigger/dis is
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NCP4304A, NCP4304B
Trig/Dis
Figure 47. DRV Turn ON Events
spikes that are present on the trigger/dis input pin during the
SR MOSFET turn−on process. DRV response to the short
needle pulse on the trigger/dis pin is depicted in Figure 48
– this short pulse turns−on the DRV for 150 ns.
The trigger/dis input is blanked for 150 ns after DRV set
signal to avoid undesirable behavior during SR MOSFET
turn−ON event. The blanking time in combination with high
threshold voltage (2 V) prevent triggering on ringing and
Trig/Dis
Figure 48. Trigger Needle Pulse and Trigger Blank Sequence
Advantage of the trigger blanking time during DRV
turn−ON event is evident from Figure 49. Rising edge of the
DRV signal may cause additional spikes on the trigger/dis
input. These spikes, in combination with ultra−fast
performance of the trigger logic, could turn−OFF the SR
MOSFET in inappropriate time. Implementation of the
trigger blanking time period helps to avoid such situation.
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NCP4304A, NCP4304B
Trig/Dis
Figure 49. Trigger Blanking Masked−out Noise in Trigger Signal During Switch−ON Event
Figure 50 depicts driver turn−OFF events in details. If the
CS (Vds) stays below Vth_cs_OFF threshold driver is
turned−OFF according to rising edge of the trigger/dis
signal. Trigger/dis can turn−OFF the driver also during
minimum−ON time period (time marker t2 and t3 in
Figure 50).
Figure 51 depicts another driver turn−OFF events in
details. Driver is turned−OFF according to the CS (Vds)
signal (t2 marker) and only after minimum−ON time
elapsed. Trigger/dis signal needs to be LOW during this
event. If the CS (Vds) voltage reaches Vth_cs_OFF
threshold before minimum−ON time period ends and
trigger/dis pin is LOW the DRV is turned−OFF on the falling
edge of the minimum−ON time period (t4 and t6 time
markers in Figure 51).
Figure 52 depicts performance of the NCP4304A/B
controller when trigger pin is permanently pulled LOW. In
this case the DRV is turned ON and OFF according to the CS
(Vds) signal. The driver can be turned off only after
minimum−ON time period elapsed. The driver is
turned−ON in the time when CS (Vds) reaches Vth_cs_ON
threshold (t1− t2, t5 – t6, t9 – t10 markers). DRV is
turned−OFF if CS (Vds) signal reaches Vth_cs_OFF threshold
(t4 marker). The DRV ON−time is prolonged till
minimum−ON time period falling edge if the CS (Vds)
reaches Vth_cs_OFF before minimum−ON time period
elapsed (t7 − t8, t11 − t12 markers).
Figure 53 depicts entering into the sleep mode. If the
trigger/dis is pulled up for more than 100 ms the
NCP4304A/B enters low consumption mode. The DRV
stays LOW (disabled) during entering sleep mode.
Figure 54 shows sleep mode transition 2nd case – i.e.
trigger rising edge comes during the trigger blank period.
Figure 55 depicts entering into sleep mode and wake−up
sequence.
Figures 56 and 57 show wake−up situations in details. If
the NCP4304A/B is in sleep mode and Trigger/dis is pulled
LOW NCP4304A/B requires up to 10 ms period to recover
all internal circuitry to normal operation mode. The driver
is then enabled in the next cycle of CS (Vds) signal only. The
DRV stays LOW during waking−up time period.
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NCP4304A, NCP4304B
Trig/Dis
Figure 50. Driver Turn−OFF Events Based on the Trigger Input
Trig/Dis
Figure 51. Driver OFF Sequence Chart 2
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NCP4304A, NCP4304B
Trig/Dis
Figure 52. Trigger/dis is LOW Sequence Chart
Trig/Dis
Figure 53. Trigger/dis from LOW to HIGH Sequence 1
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NCP4304A, NCP4304B
Trig/Dis
Figure 54. Trigger/dis from LOW to HIGH Sequence 2
Trig/Dis
Figure 55. Sleep Mode Sequence
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NCP4304A, NCP4304B
Trig/Dis
Figure 56. Waking−up Sequence
Trig/Dis
Figure 57. Wake−up Time Sequence
sequence elapses in time t4 the DRV is turned ON. In time
t5 Trigger signal rises up and terminates this cycle of the CS
signal in time t5. Next cycle starts in time t6. Trigger enables
DRV and Vds is under Vth_cs_ON threshold voltage so DRV
turns ON in time t6. Trigger signal rises up to HIGH level in
time t7, consequently DRV turns OFF and this starts
minimum OFF time generator. Because minimum OFF time
period is longer then the rest of time to the end of cycle of
Vds − DRV is disabled.
Figure 58 shows IC behavior in case the trigger signal
features two pulses during one cycle of the Vds (CS) signal.
Trigger enables driver at time t1 and DRV turns ON because
the Vds voltage is under Vth_cs_ON threshold voltage. The
trigger signal and consequently DRV output fall down in
time t2. The minimum OFF time generator is triggered in
time t2. Trigger drops down to LOW level in time t3 but
there is still minimum OFF time sequence present so the
DRV output stays low. When the minimum OFF time
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NCP4304A, NCP4304B
Trig/Dis
Figure 58. IC Behavior When Multiple Trigger Pulses Appear on Trigger Input
can be for instance prepared on a small toroidal ferrite core
with diameter of 8 mm. Proper safety insulation between
primary and secondary sides can be easily assured by using
triple insulated wire for one or even both windings.
The primary MOSFET gate voltage rising edge is delayed
by external circuitry consisting of transistors Q1, Q2 and
surrounding components. The primary MOSFET is thus
turned−on with a slight delay so that the secondary
controller turns−off the SR MOSFET by trigger signal prior
to the primary switching. This method reduces the
commutation losses and the SR MOSFET drain voltage
spike, which results in improved efficiency.
It is also possible to use capacitive coupling (use
additional capacitor with safety insulation) between the
primary and secondary to transmit the trigger signal. We do
not recommend this technique as the parasitic capacitive
currents between primary and secondary may affect the
trigger signal and thus overall system functionality.
Note that the trigger input is an ultrafast input that is
sensitive even to very narrow voltage pulses. Thus it is wise
to keep this input on a low impedance path and provide it
with a clean triggering signal in the time this input is enabled
by internal logic.
A typical application schematic of a CCM flyback
converter with the NCP4304A/B driver can be seen in
Figure 59. In this application the trigger signal is taken
directly from the flyback controller driver output and
transmitted to the secondary side by pulse transformer TR2.
Because the trigger input is edge sensitive, it is not necessary
to transmit the entire primary driver pulse to the secondary.
The coupling capacitor C5 is used to allow pulse transformer
core reset and also to prepare a needle pulse (a pulse with
width lower than 100 ns) to be transmitted to the
NCP4304A/B trigger input. The advantage of needle trigger
pulse usage is that the required volt−second product of the
pulse transformer is very low and that allows the designer to
use very small and cheap magnetics. The trigger transformer
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NCP4304A, NCP4304B
+
Vbulk
C3
+
+
FLYBACK
CONTROL
CIRCUITRY DRV
FB
+Vout
D3
Delay generator
Vcc
TR1
R5
C2
R2
Q2
D1
M2
D4
C7
C4
GND
C6
Q1
M1
CS
R3
R1
C1
D2
R9
R10
R6
R4
D5
Trig
R7
OK1
TR2
C5
R11
Figure 59. Typical Application Schematic when NCP4304A/B is Used in CCM Flyback Converter
Minimum Ton and Toff Adjustment
timers avoid false triggering on the CS input after the
MOSFET is turned on or off. The adjustment is based on an
internal timing capacitance and external resistors connected
to the GND pin – refer to Figure 60 for better understanding.
The NCP4304A/B offers adjustable minimum ON and
OFF time periods that ease the implementation of the
synchronous rectification system in a power supply. These
Figure 60. Internal Circuitry of MINTon_generator (MINToff_generator works in the same way)
Current through the Min_ton adjust resistor can be
calculated as:
I R_Ton_min +
V ref
R Ton_min
T on_min + C t @
(eq. 4)
V ref
I R_Ton_min
+ Ct +
V
ref
V
ref
R Ton_min
(eq. 5)
+ C t @ R Ton_min
As the same current is used for the internal timing
capacitor (Ct) charging, one can calculate the minimum
on−time duration using this equation.
As can be seen from Equation 5, the minimum ON and
OFF times are independent of the Vref or Vcc level. The
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NCP4304A, NCP4304B
internal capacitor size would be too high if we would use
directly IR_Ton_min current thus this current is decreased by
the internal current mirror ratio. One can then calculate the
minimum Ton and Toff blanking periods using below
equations:
T off_min + 9.56 * 10 −11 * R T_off_min ) 5.397 * 10 −8 [ms]
(eq. 7)
Note that the internal timing comparator delay affects the
accuracy of equations Equations 6 and 7 when minimum
Ton/Toff times are selected near to their minimum possible
values. Please refer to Figure 61 and 62 for measured
minimum on and off time charts.
T on_min + 9.82 * 10 −11 * R T_on_min ) 4.66 * 10 −8 [ms]
6
6
5
5
4
4
Toff_MIN (ms)
Ton_MIN (ms)
(eq. 6)
3
2
2
1
1
0
3
0
10
20
30
40
50
0
60
0
10
20
30
40
50
Rmin_Ton (kW)
Rmin_Toff (kW)
Figure 61. Min_Ton Adjust Characteristic
Figure 62. Min_Toff Adjust Characteristic
60
to modulate blanking periods by using an external NPN
transistor – refer to Figure 63. The modulation signal can be
derived based on the load current or feedback regulator
voltage.
The absolute minimum Ton duration is internally clamped
to 300 ns and minimum Toff duration to 600 ns in order to
prevent any potential issues with the minimum Ton and/or
Toff input being shorted to GND.
Some applications may require adaptive minimum on and
off time blanking periods. With NCP4304A/B it is possible
Figure 63. Possible Connection for Min T_on and Min T_off Modulation
may then be too short. To overcome possible issues with the
LLC operating under low line and light load conditions, one
can prolong the minimum off time blanking period by using
resistors Rdrain1 and Rdrain2 connected from the opposite SR
MOSFET drain – refer to Figure 64.
In LLC applications with a very wide operating frequency
range it is necessary to have very short minimum on time and
off time periods in order to reach the required maximum
operating frequency. However, when a LLC converter
operates under low frequency, the minimum off time period
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NCP4304A, NCP4304B
Trig/Dis
Trig/Dis
Figure 64. Possible Connection for Min Toff Prolongation in LLC Application with Wide Operating Frequency
Range
Note that Rdrain1 and Rdrain2 should be designed in such
a way that the maximum pulse current into the Min_Toff
adjust pin is below 10 mA. Voltage on the min Toff and Ton
pins is clamped by internal zener protection to 10 V.
off process always starts before the drain to source voltage
rises up significantly. Therefore, the MOSFET switch
always operates under Zero Voltage Switching (ZVS)
conditions when implemented in a synchronous
rectification system.
The following steps show how to approximately calculate
the power dissipation and DIE temperature of the
NCP4304A/B controller. Note that real results can vary due
to the effects of the PCB layout on the thermal resistance.
Power Dissipation Calculation
It is important to consider the power dissipation in the
MOSFET driver of a SR system. If no external gate resistor
is used and the internal gate resistance of the MOSFET is
very low, nearly all energy losses related to gate charge are
dissipated in the driver. Thus it is necessary to check the SR
driver power losses in the target application to avoid over
temperature and to optimize efficiency.
In SR systems the body diode of the SR MOSFET starts
conducting before turn on because the Vth_cs_on threshold
level is below 0 V. On the other hand, the SR MOSFET turn
Step 1 – MOSFET Gate−to−Source Capacitance:
During ZVS operation the gate to drain capacitance does
not have a Miller effect like in hard switching systems
because the drain to source voltage is close to zero and its
change is negligible.
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NCP4304A, NCP4304B
C iss + C gs ) C gd
C rss + C gd
C oss + C ds ) C gd
Figure 65. Typical MOSFET Capacitance Dependency on VDS and VGS Voltage
The total driving loss can be calculated using the selected
gate driver clamp voltage and the input capacitance of the
MOSFET:
Therefore, the input capacitance of a MOSFET operating
in ZVS mode is given by the parallel combination of the gate
to source and gate to drain capacitances (i.e. Ciss capacitance
for given gate to source voltage). The total gate charge,
Qg_total, of most MOSFETs on the market is defined for hard
switching conditions. In order to accurately calculate the
driving losses in a SR system, it is necessary to determine the
gate charge of the MOSFET for operation specifically in a
ZVS system. Some manufacturers define this parameter as
Qg_ZVS. Unfortunately, most datasheets do not provide this
data. If the Ciss (or Qg_ZVS) parameter is not available then
it will need to be measured. Please note that the input
capacitance is not linear (as shown Figure 65) and it needs
to be characterized for a given gate voltage clamp level.
P DRV_total + V CC @ V clamp @ C g_ZVS @ f SW
Where:
VCC
Vclamp
Cg_ZVS
(eq. 8)
is the supply voltage
is the driver clamp voltage
is the gate to source capacitance of the
MOSFET in ZVS mode
fsw
is the switching frequency of the target
application
The total driving power loss won’t only be dissipated in
the IC, but also in external resistances like the external gate
resistor (if used) and the MOSFET internal gate resistance
(Figure 66). Because NCP4304A/B features a clamped
driver, it’s high side portion can be modeled as a regular
driver switch with equivalent resistance and a series voltage
source. The low side driver switch resistance does not drop
immediately at turn−off, thus it is necessary to use an
equivalent value (Rdrv_low_eq) for calculations. This method
simplifies power losses calculations and still provides
acceptable accuracy. Internal driver power dissipation can
then be calculated using Equation 9:
Step 2 – Gate Drive Losses Calculation:
Gate drive losses are affected by the gate driver clamp
voltage. Gate driver clamp voltage selection depends on the
type of MOSFET used (threshold voltage versus channel
resistance). The total power losses (driving loses and
conduction losses) should be considered when selecting the
gate driver clamp voltage. Most of today’s MOSFETs for SR
systems feature low RDS(on) for 5 V Vgs voltage and thus it
is beneficial to use the B version. However, there is still a big
group of MOSFETs on the market that require higher gate
to source voltage − in this case the A version should be used.
Figure 66. Equivalent Schematic of Gate Drive Circuitry
http://onsemi.com
28
NCP4304A, NCP4304B
P DRV_IC +
ǒ
Ǔ
R drv_low_eq
1
@ C g_ZVS @ V clamp 2 @ f SW @
) C g_ZVS @ V clamp @ f SW @ ǒV CC * V clampǓ
2
R drv_low_eq ) R g_ext ) R g_int
)
ǒ
Ǔ
R drv_high_eq
1
@ C g_ZVS @ V clamp 2 @ f SW @
2
R drv_high_eq ) R g_ext ) R g_int
Where:
Rdrv_low_eq is the Ddriver low side switch
equivalent resistance (1.55 W)
Rdrv_high_eq is the driver high−side switch
equivalent resistance (7 W)
is the external gate resistor (if used)
Rg_ext
Rg_int
is the internal gate resistance of the MOSFET
P ICC + V CC @ I CC
The DIE temperature can be calculated now that the total
internal power losses have been determined (driver losses
plus internal IC consumption losses). The SO−8 package
thermal resistance is specified in the maximum ratings table
for a 35 mm thin copper layer with no extra copper plates on
any pin (i.e. just 0.5 mm trace to each pin with standard
soldering points are used).
The DIE temperature is calculated as:
In this step, power dissipation related to the internal IC
consumption is calculated. This power loss is given by the
ICC current and the IC supply voltage. The ICC current
depends on switching frequency and also on the selected min
Ton and Toff periods because there is current flowing out
from the min Ton and Toff pins. The most accurate method
for calculating these losses is to measure the ICC current
when Cload = 0 nF and the IC is switching at the target
frequency with given min_Ton and min_Toff adjust
resistors. Refer also to Figure 67 for typical IC consumption
charts when the driver is not loaded. IC consumption losses
can be calculated as:
T DIE + ǒP DRV_IC ) P ICCǓ @ R qJ*A ) T A (eq. 11)
Where:
PDRV_IC
PIcc
RqJA
is the IC driver internal power dissipation
is the IC control internal power dissipation
is the thermal resistance from junction to
ambient
is the ambient temperature
TA
180
400
160
POWER CONSUMTION (mW)
POWER CONSUMTION (mW)
(eq. 10)
Step 4 – IC DIE Temperature Arise Calculation:
Step 3 – IC Consumption Calculation:
A Version,
VCC = 30 V
140
120
B Version,
VCC = 30 V
100
80
A Version,
VCC = 12 V
60
40
B Version,
VCC = 12 V
20
0
50
(eq. 9)
100
150
200
250
300
350
400
450
500
350
300
A Version,
VCC = 30 V
250
200
B Version,
VCC = 30 V
A Version,
VCC = 12 V
150
100
B Version,
VCC = 12 V
50
0
50
100
150
200
250
300
350
400
450
OPERATING FREQUENCY (kHz)
OPERATING FREQUENCY (kHz)
Figure 67. IC Power Consumption as a
Function of Frequency for Cload = 0 nF,
RTon min = RToff min = 5 kW
Figure 68. IC Power Consumption as a
Function of Frequency for Cload = 1 nF,
RTon min = RToff min = 5 kW
http://onsemi.com
29
500
NCP4304A, NCP4304B
POWER CONSUMTION (mW)
800
A Version,
VCC = 30 V
700
B Version,
VCC = 30 V
600
500
400
300
200
B Version,
VCC = 12 V
100
0
50
A Version,
VCC = 12 V
100
150
200
250
300
350
400
450
500
OPERATING FREQUENCY (kHz)
Figure 69. IC Power Consumption as a Function of Frequency for Cload = 10 nF, RTon_min = RToff_min = 5 kW
http://onsemi.com
30
NCP4304A, NCP4304B
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
S
M
J
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
31
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP4304A, NCP4304B
PACKAGE DIMENSIONS
DFN8 4x4
CASE 488AF−01
ISSUE C
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
L1
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
EXPOSED Cu
DETAIL B
ÇÇÇÇ
A
(A3)
A1
C
D2
ÇÇÇ
Ç
1
e
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
8X
ALTERNATE
CONSTRUCTIONS
SEATING
PLANE
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
SOLDERING FOOTPRINT*
L
2.21
4
Ç ÇÇ
8
MOLD CMPD
DETAIL B
SIDE VIEW
K
ÇÇ
ÇÇ
ÉÉ
TOP VIEW
NOTE 4
DETAIL A
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL
CONSTRUCTIONS FOR TERMINALS.
L
L
8X
0.63
E2
8X
4.30 2.39
b
0.10 C A B
0.05 C
PACKAGE
OUTLINE
NOTE 3
BOTTOM VIEW
8X
0.80
PITCH
0.35
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP4304/D