TIV 675 OPA875 SBOS340 – DECEMBER 2006 Single 2:1 High-Speed Video Multiplexer FEATURES • • • • • • • • DESCRIPTION 700MHz SMALL-SIGNAL BANDWIDTH (AV = +2) 425MHz, 4VPP BANDWIDTH 0.1dB GAIN FLATNESS to 200MHz 4ns CHANNEL SWITCHING TIME LOW SWITCHING GLITCH: 40mVPP 3100V/µs SLEW RATE 0.025%/0.025° DIFFERENTIAL GAIN, PHASE HIGH GAIN ACCURACY: 2.0V/V ±0.4% APPLICATIONS • • • • • The OPA875 offers a very wideband, single-channel 2:1 multiplexer in an SO-8 or a small MSOP-8 package. Using only 11mA, the OPA875 provides a gain of +2 video amplifier channel with > 425MHz large-signal bandwidth (4VPP). Gain accuracy and switching glitch are improved over earlier solutions using a new input stage switching approach. This technique uses current steering as the input switch while maintaining an overall closed-loop design. With > 700MHz small-signal bandwidth at a gain of 2, the OPA875 gives a typical 0.1dB gain flatness to > 200MHz. RGB SWITCHING LCD PROJECTOR INPUT SELECT WORKSTATION GRAPHICS ADC INPUT MUX DROP-IN UPGRADE TO LT1675-1 System power may be reduced using the chip enable feature for the OPA875. Taking the chip enable line high powers down the OPA875 to < 300µA total supply current. Muxing multiple OPA875 outputs together, then using the chip enable to select which channels are active, increases the number of possible inputs. EN Where three channels are required, consider using the OPA3875 for the same level of performance. Ch 0 75W OPA875 (Patented) 75W Out OPA875 RELATED PRODUCTS DESCRIPTION Ch 1 75W SEL Channel Select OPA3875 Triple-Channel OPA875 OPA692 225MHz Video Buffer OPA693 700MHz Video Buffer 2:1 Video Multiplexer Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated OPA875 www.ti.com SBOS340 – DECEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING OPA875 SO-8 D –40°C to +85°C OPA875 OPA875 MSOP-8 DGK –40°C to +85°C BPL ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA875ID Rails, 75 OPA875IDR Tape and Reel, 2500 OPA875IDGKT Tape and Reel, 250 OPA875IDGKR Tape and Reel, 2500 ABSOLUTE MAXIMUM RATINGS Over operating temperature range, unless otherwise noted. OPA875 UNIT ±6.5 Power Supply Internal Power Dissipation V See Thermal Analysis Input Voltage Range ±VS V –40 to +125 °C Lead Temperature (soldering, 10s) +260 °C Operating Junction Temperature +150 °C Continuous Operating Junction Temperature +140 °C Human Body Model (HBM) 2000 V Charge Device Model (CDM) 1500 V Machine Model 200 V Storage Temperature Range ESD Rating: PIN CONFIGURATION Table 1. TRUTH TABLE OPA875 2 Top View SELECT ENABLE VOUT 1 0 R0 0 0 R1 X 1 Off MSOP, SO OPA875 Channel 0 (V0) 1 8 +VS GND 2 7 Chip Enable (EN) Channel 1 (V1) 3 6 Output (VOUT) -VS 4 5 Channel Select (SEL) Submit Documentation Feedback 402W 402W OPA875 www.ti.com SBOS340 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS: VS = ±5V At G = +2, RL = 150Ω, unless otherwise noted. OPA875 MIN/MAX OVER TEMPERATURE TYP PARAMETER AC PERFORMANCE CONDITIONS +25°C +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) B See Figure 1 Small-Signal Bandwidth VO = 200mVPP, RL = 150Ω 700 525 515 505 MHz min Large-Signal Bandwidth VO = 4VPP, RL = 150Ω 425 390 380 370 MHz min B VO = 200mVPP 200 MHz typ C Maximum Small-Signal Gain VO = 200mVPP, RL = 150Ω, f = 5MHz 2.0 2.02 2.03 2.05 V/V max B Minimum Small-Signal Gain VO = 200mVPP, RL = 150Ω, f = 5MHz 2.0 1.98 1.97 1.95 V/V min B 10MHz, VO = 2VPP, RL = 150Ω –66 –64 –63 –62 dBc max B Input Voltage Noise f > 100kHz 6.7 7.0 7.2 7.4 nV/√Hz max B Input Current Noise f > 100kHz 3.8 4.2 4.6 4.9 pA/√Hz max B NTSC Differential Gain RL = 150Ω 0.025 % typ C NTSC Differential Phase RL = 150Ω 0.025 C Slew Rate VO = ±2V 3100 VO = 0.5V Step Bandwidth for 0.1dB Gain Flatness SFDR Rise Time and Fall Time ° typ V/µs min B 460 ps typ C VO = 1.4V Step 600 ps typ C RL = 150Ω ±0.05 ±0.25 ±0.3 ±0.35 % max A ±3 ±9 ±10 ±12 mV max A 2800 2700 2600 CHANNEL-TO-CHANNEL PERFORMANCE Gain Match Output Offset Voltage Mismatch Crosstalk f < 50MHz, RL = 150Ω –65 dB typ C RL = 150Ω 4 ns typ C Turn On 9 ns typ C Turn Off 60 ns typ C SEL (Channel Select) Switching Glitch Both Inputs to Ground, At Matched Load 40 mVPP typ C EN (Chip-Select) Switching Glitch Both Inputs to Ground, At Matched Load 30 mVPP typ C 50MHz, Chip Disabled (EN = High) –70 dB typ C CHANNEL AND CHIP-SELECT PERFORMANCE SEL (Channel Select) Switching Time EN (Chip Select) Switching Time Off Isolation Maximum Logic 0 EN, A0, A1 0.8 0.8 0.8 V max A Minimum Logic 1 EN, A0, A1 2.0 2.0 2.0 V min A EN Logic Input Current 0V to 4.5V 25 35 45 50 µA max A SEL Logic Input Current 0V to 4.5V 55 70 85 100 µA max A RIN = 0Ω, G = +2V/V ±2.5 ±14 ±15.8 ±17 mV max A ±50 ±50 µV/°C max B ±19.5 ±20.5 µA max A ±40 ±40 nA/°C max B 1.5 1.6 % max A DC PERFORMANCE Output Offset Voltage Average Output Offset Voltage Drift ±5 Input Bias Current ±18 Average Input Bias Current Drift Gain Error (from 2V/V) VO = ±2V 0.4 1.4 INPUT Input Voltage Range ±2.8 V min C Input Resistance 1.75 MΩ typ C Channel Selected 0.9 pF typ C Channel Deselected 0.9 pF typ C Chip Disabled 0.9 pF typ C Input Capacitance (1) (2) (3) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +14°C at high temperature limit for over temperature specifications. Submit Documentation Feedback 3 OPA875 www.ti.com SBOS340 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2, RL = 150Ω, unless otherwise noted. OPA875 MIN/MAX OVER TEMPERATURE TYP PARAMETER CONDITIONS +25°C +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) A OUTPUT ±3.5 ±3.4 ±3.35 ±3.3 V min VO = 0V, Linear Operation ±70 ±50 ±45 ±40 mA min A Chip enabled 0.3 Ω typ C Chip Disabled, Maximum 800 912 915 918 Ω max A Chip Disabled, Minimum 800 688 685 682 Ω min A Chip Disabled 2 pF typ C Output Voltage Range Output Current Output Resistance Output Capacitance POWER SUPPLY ±5 Specified Operating Voltage V typ C Minimum Operating Voltage ±3.0 ±3.0 ±3.0 V min B Maximum Operating Voltage ±6.0 ±6.0 ±6.0 V max A Maximum Quiescent Current Chip Selected, VS = ±5V 11 11.5 11.7 12 mA max A Minimum Quiescent Current Chip Selected, VS = ±5V 11 10 9.5 9 mA min A Maximum Quiescent Current Chip Deselected 300 500 550 600 µA max A (+PSRR) Input-Referred 56 50 48 47 dB min A (–PSRR) Input-Referred 55 51 49 48 dB min A –40 to +85 °C typ C Power-Supply Rejection Ratio THERMAL CHARACTERISTICS Specified Operating Range D Package Thermal Resistance θJA 4 Junction-to-Ambient D SO-8 +100 °C/W typ C DGK MSOP-8 +140 °C/W typ C Submit Documentation Feedback OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V At G = +2 and RL = 150Ω, unless otherwise noted. LARGE-SIGNAL FREQUENCY RESPONSE 6 0.2 5 0.1 4 0 3 -0.1 2 -0.2 VO = 500mVPP RL = 150W G = +2V/V 1 -0.3 0 1 0 Normalized Gain (dB) 0.3 Normalized Gain Flatness (dB) Gain (dB) SMALL-SIGNAL FREQUENCY RESPONSE 7 10M 100M -2 -3 5VPP 4VPP -6 1G 0 200M 400M DISABLE FEEDTHROUGH vs FREQUENCY 2.5 0 2.0 -10 1.0 Small-Signal 0.4VPP 0.1 0.5 0 0 -0.1 -0.5 -0.2 -1.0 -0.3 -1.5 -0.4 -2.0 100MHz Square-Wave Input -0.5 Input-Referred BW = +5V -20 Isolation (dB) 1.5 Large-Signal Offset Voltage (V) Large-Signal 4VPP 0.2 -30 -40 -50 -60 -70 -80 -90 -2.5 -100 Time (1ns/div) 1M 10M 100M 1G Frequency (Hz) Figure 3. Figure 4. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 8 80 7 Gain to Capacitive Load (dB) 70 60 50 RS (W) Small-Signal Offset Voltage (V) 0.3 1G 800M Figure 2. NONINVERTING PULSE RESPONSE RL = 150W G = +2V/V 600M Frequency (Hz) Figure 1. 0.4 1VPP 2VPP Frequency (Hz) 0.5 500mVPP -4 -5 -0.4 1M -1 40 30 20 10 0.1dB Peaking Targeted CL = 10pF 6 5 4 3 CL = 47pF 2 1 RS 0 (1) CL -1 1kW CL = 22pF 75W -2 0 CL = 100pF x2 75W NOTE: (1) 1kW is optional. -3 1 10 100 1000 1M 10M 100M 400M Frequency (Hz) Capacitive Load (pF) Figure 5. Figure 6. Submit Documentation Feedback 5 OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE -40 VO = 2VPP f = 10MHz -65 2nd-Harmonic -70 -75 -80 3rd-Harmonic -85 -50 -55 -60 -70 -75 -85 dBc = dB Below Carrier -95 ±2.5 ±3.0 ±3.5 ±4.0 1k Supply Voltage (±VS) Figure 7. Figure 8. -60 -55 2nd-Harmonic -60 -65 -70 -75 -80 3rd-Harmonic -85 -90 -65 -70 2nd-Harmonic -75 -80 -85 3rd-Harmonic -90 -95 dBc = dB Below Carrier 10M 0.5 100M 2.5 3.5 4.5 5.5 Output Voltage Swing (VPP) Figure 9. Figure 10. 6.5 7.0 OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 -50 -60 1.5 Frequency (Hz) TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS RL = 100W Load Power at Matched 50W Load dBc = dB Below Carrier 4 1W Internal Power Limit 3 2 -70 VOUT (V) Third-Order Spurious Level (dBc) ±6.0 -105 1M 50MHz -80 20MHz 100W Load Line 1 25W Load Line 0 -1 -2 10MHz 50W Load Line -3 -90 1W Internal Power Limit -4 -100 -6 -4 -2 0 2 4 6 8 10 -5 -200 -150 -100 -50 0 50 IO (mA) Single-Tone Load Power (dBm) Figure 11. 6 ±5.5 RL = 150W f = 10MHz -100 dBc = dB Below Carrier -95 ±5.0 HARMONIC DISTORTION vs OUTPUT VOLTAGE -55 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 ±4.5 Resistance (W) VO = 2VPP RL = 150W -45 3rd-Harmonic -80 HARMONIC DISTORTION vs FREQUENCY -40 2nd-Harmonic -65 -90 dBc = dB Below Carrier -90 100 VO = 2VPP RL = 150W f = 10MHz -45 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 Figure 12. Submit Documentation Feedback 100 150 200 OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 VSEL RL = 150W VIN_RI = 400MHz, 1VPP VIN_RO = 0VDC Output Voltage VSEL VIN_Ch0 = +0.5VDC VIN_Ch1 = -0.5VDC Time (5ns/div) Figure 14. Output (mV) DISABLE/ENABLE TIME Output Voltage (V) CHANNEL SWITCHING GLITCH 20 At Matched Load 10 0 -10 7.5 5.0 VSEL 2.5 0 -2.5 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 Output Voltage VEN Channel Select (V) -20 VIN_Ch1 = 0V VIN_Ch0 = 200MHz, 1VPP Time (10ns/div) Time (20ns/div) Figure 15. Figure 16. DISABLE/ENABLE SWITCHING GLITCH CHANNEL-TO-CHANNEL CROSSTALK 15 0 At Matched Load Input-Referred -10 -20 -30 -5 -40 -10 -15 VEN 5.0 2.5 0 -2.5 Time (100ns/div) Output (V) 5 0 Enable Voltage (V) Output (mV) 10 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 Time (5ns/div) Figure 13. 30 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 Channel Select (V) Output Voltage 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 Enable Voltage (V) Output Voltage (V) CHANNEL-TO-CHANNEL SWITCHING TIME Channel Select (V) Output Voltage (V) CHANNEL SWITCHING 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -50 Ch 0 Selected Ch 1 Driven -60 -70 -80 Ch 1 Selected Ch 0 Driven -90 -100 -110 1M 10M 100M 1G Frequency (Hz) Figure 17. Figure 18. Submit Documentation Feedback 7 OPA875 www.ti.com SBOS340 – DECEMBER 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At G = +2 and RL = 150Ω, unless otherwise noted. CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY INPUT IMPEDANCE vs FREQUENCY 10M Disabled 1k 1M Input Impedance (W) Output Impedance (W) 10k 100 10 100k 1 10k 1k Enabled 0.1 100k 1M 10M 100M 100 100k 1G 1M 10M Frequency (Hz) Figure 19. PSRR vs FREQUENCY SUPPLY CURRENT vs TEMPERATURE 18 16 +PSRR 14 Supply Current (mA) Power-Supply Rejection Ratio (dB) -PSRR 50 40 30 20 10 12 10 8 6 4 2 1k 10k 100k 1M 10M 100M 1G -50 75 IB 2.0 4 1.5 2 0 50 75 100 125 Voltage Noise (nV/ÖHz) Current noise (pA/ÖHz) 6 25 125 INPUT VOLTAGE AND CURRENT NOISE VOS 2.5 100 100 Input Bias Current (mA) Output Offset Voltage (mV) 50 Figure 22. 1.0 10 Voltage Noise (6.7nV/ÖHz) Input Current Noise (3.8pA/ÖHz) 1 10 100 1k 10k 100k Frequency (Hz) Ambient Temperature (°C) Figure 23. 8 25 Figure 21. 8 0 0 Ambient Temperature (°C) TYPICAL DC DRIFT OVER TEMPERATURE -25 -25 Frequency (Hz) 3.0 -50 1G Figure 20. 60 0 100 100M Frequency (Hz) Figure 24. Submit Documentation Feedback 1M 10M 100M OPA875 www.ti.com SBOS340 – DECEMBER 2006 APPLICATIONS INFORMATION 1-BIT HIGH-SPEED PGA TRANSMIT/RECEIVE SWITCH The OPA875 can be used as a 1-bit, high-speed programmable gain amplifier (PGA) when used in conjunction with another amplifier. Figure 25 shows the OPA695 used twice with one amplifier configured in a unity-gain structure, and the other amplifier configured in a gain of +8V/V. The OPA875 can be used as a transmit/receive switch in which the receive channel is disconnected, when the OPA875 is switched from channel 0 to channel 1, to prevent the transmit pulse from going through the receive signal chain. This architecture is shown in Figure 26. When channel 0 is selected, the overall gain to the matched load of the OPA875 is 0dB. When channel 1 is selected, this circuit delivers an 18dB gain to the matched load. HIGH ISOLATION RGB VIDEO MUX Three OPA875s can be used as a triple, 2:1 video MUX (see Figure 27). This configuration has the advantage of having higher R to G to B isolation than a comparable and more integrated solution does, such as the OPA3875, especially at higher frequencies. This comparison is shown in Figure 28. +5V +5V OPA695 OPA875 50W Channel 0 -5V 523W IN 50W Source x1 50W x2 50W 50W Channel 1 +5V 50W Load x1 OPA695 -5V -5V 402W 57.6W Figure 25. 1-Bit, High-Speed PGA OPA875 Receive Channel Channel 0 x1 x2 Channel 1 x1 Figure 26. Transmit/Receive Switch Submit Documentation Feedback 9 OPA875 www.ti.com SBOS340 – DECEMBER 2006 4-INPUT RGB ROUTER OPA875_A Ch 0 Two OPA875s can be used together to form a four-input RGB router. The router for the red component is shown in Figure 29. x1 ROUT x2 OPA875 Ch 1 x1 R1 x1 RO 69W OPA875_B Ch 0 x2 x1 R2 x1 EN GOUT x2 Ch 1 x1 R3 x1 RO 69W OPA875_C Ch 0 75W x1 R4 x1 EN BOUT x2 Ch 1 Red Out x2 Chip Select x1 Figure 29. 4-Input RGB Router Figure 27. High Isolation RGB Video MUX 0 Input-Referred -10 Crosstalk (dB) -20 -30 When connecting OPA875 outputs together, maintain a gain of +1 at the load. The OPA875 operates at a gain of +6dB; thus, matching resistance must be selected to achieve –6dB attenuation. OPA3875 OPA3875 All Hostile Adjacent Channel Crosstalk Crosstalk The set of equations to solve are shown in Equation 1 and Equation 2. Here, the impedance of interest is ZO = 75Ω. OPA875_C Ch. 0 Driven Adjacent Channel Crosstalk -40 RO = ZO || (R + RF + RG) -50 1+ -60 OPA875 OPA875_A All Hostile Ch. 1 Driven, Adjacent Crosstalk Channel Crosstalk -70 -80 -90 1 10 100 RF RG =2 RF + RG = 804W RF = RG (2) 1G Frequency (MHz) Solving for RO with n devices connected together, we get Equation 3: Figure 28. All-Hostile and Adjacent Channel Crosstalk RO = 75 ´ (n - 1) + 804 The configuration of the three OPA875 devices used is shown in Figure 27. Note that for the test, the OPA875_B was measured when both the OPA875_A and OPA875_C were driven for all hostile crosstalk and only the OPA875_A or OPA875_C was driven for the adjacent channel crosstalk. 10 (1) Submit Documentation Feedback 2 ´ 1+ 241200 [75 ´ (n - 1) + 804] 2 -1 (3) OPA875 www.ti.com SBOS340 – DECEMBER 2006 Results for n varying from 2 to 6 are given in Table 2. Table 2. Series Resistance versus Number of Parallel Outputs NUMBER OF OPA875s RO (Ω) 2 69 3 63.94 4 59.49 5 55.59 6 52.15 The two major limitations of this circuit are the device requirements for each OPA875 and the acceptable return loss because of the mismatch between the load (75Ω) and the matching resistor. DESIGN-IN TOOLS DEMONSTRATION FIXTURES A printed circuit board (PCB) is available to assist in the initial evaluation of circuit performance using the OPA875. The fixture is offered free of charge as an unpopulated PCB, delivered with a user's guide. The summary information for this fixture is shown in Table 3. Table 3. OPA875 Demonstration Fixture PRODUCT PACKAGE ORDERING NUMBER LITERATURE NUMBER OPA875IDGK MSOP-8 DEM-TIV-MSOP-1A SBOU044 OPA875ID SO-8 DEM-TIV-SO-1A SBOU045 The demonstration fixture can be requested at the Texas Instruments web site at (www.ti.com) through the OPA875 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA875 is available through the Texas Instruments web site at www.ti.com. These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. OPERATING SUGGESTIONS DRIVING CAPACITIVE LOADS One of the most demanding, yet very common load conditions is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed device such as the OPA875 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the device open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This isolation resistor does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS versus capacitive load and the resulting frequency response at the load; see Figure 5. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA875. Long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA875 output pin (see the Board Layout Guidelines section). DC ACCURACY The OPA875 offers excellent DC signal accuracy. Parameters that influence the output DC offset voltage are: • Output offset voltage • Input bias current • Gain error • Power-supply rejection ratio • Temperature Submit Documentation Feedback 11 OPA875 www.ti.com SBOS340 – DECEMBER 2006 Leaving both temperature and gain error parameters aside, the output offset voltage envelope can be described as shown in Equation 4: VOSO_envelope = VOSO + (RS·Ib) x G ± |5 - (VS+)| x 10 ± |-5 - (VS-)| x 10 - PSRR+ 20 - PSRR20 (4) With: VOSO: Output offset voltage RS: Input resistance seen by R0, R1, G0, G1, B0, or B1. Ib: Input bias current G: Gain VS+: Positive supply voltage VS–: Negative supply voltage PSRR+: Positive supply PSRR PSRR–: Negative supply PSRR Evaluating the front-page schematic, using a worst-case, +25°C offset voltage, bias current and PSRR specifications and operating at ±6V, gives a worst-case output equal to Equation 5: - 50 20 ±14mV + 75W x ±18mA x 2 ± |5 - 6| x 10 - 51 20 ± |-5 - (-6)| x 10 = ±22.7mV are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 4dBm/tone into a matched 50Ω load (that is, 1VPP for each tone at the load, which requires 4VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show a 82dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. NOISE PERFORMANCE The OPA875 offers an excellent balance between voltage and current noise terms to achieve low output noise. As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The device input voltage noise and the input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 30 shows this device noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. (5) +5V DISTORTION PERFORMANCE The OPA875 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2X rate while the 3rd-harmonic increases at a little less than the expected 3X rate. Where the test power doubles, the 2nd-harmonic increases only by less than the expected 6dB, whereas the 3rd-harmonic increases by less than the expected 12dB. This also shows up in the two-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels 12 OPA875 en +1 RS ib eO +2 +1 e RS -5V Channel Select EN Figure 30. Noise Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 6 shows the general form for the output noise voltage using the terms shown in Figure 30. eo = 2 2 2 en + (ibRS) + 4kTRS Submit Documentation Feedback (6) OPA875 www.ti.com SBOS340 – DECEMBER 2006 Dividing this expression by the device gain (2V/V) gives the equivalent input-referred spot noise voltage at the noninverting input as shown in Equation 7. en = 2 2 en + (ibRS) + 4kTRS (7) Evaluating these two equations for the OPA875 circuit and component values shown in Figure 30 gives a total output spot noise voltage of 13.6nV/√Hz and a total equivalent input spot noise voltage of 6.8nV/√Hz. This total input-referred spot noise voltage is higher than the 6.7nV/√Hz specification for the mux voltage noise alone. This number reflects the noise added to the output by the bias current noise times the source resistor. THERMAL ANALYSIS Heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as discussed in this document. In no case should the maximum junction temperature be allowed to exceed +150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 × RL), where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA875IDGK in the circuit of Figure 30 operating at the maximum specified ambient temperature of +85°C with its outputs driving a grounded 100Ω load to +2.5V: 2 PD = 10V x 11mA + (5 [4 x (100W || 804W) ] ) = 180mW Maximum TJ = +85°C + (0.18mW x 140°C/W) = 110°C This worst-case condition does not exceed the maximum junction temperature. Normally, this extreme case is not encountered. Careful attention to internal power dissipation is required. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier such as the OPA875 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pin can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 9, 11, 13, and 15) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA875. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and printed circuit board (PCB) trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Other network components, such as noninverting input termination resistors, should also be placed close to the package. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Submit Documentation Feedback 13 OPA875 www.ti.com SBOS340 – DECEMBER 2006 Estimate the total capacitive load and set RS from the plot of Figure 5. Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA875 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the Distortion versus Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA875 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA875 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in Figure 5. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. 14 e) Socketing a high-speed part like the OPA875 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA875 onto the board. INPUT AND ESD PROTECTION The OPA875 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 31. +VCC External Pin Internal Circuitry -VCC Figure 31. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA875), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible because high values degrade both noise performance and frequency response. Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA875ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA875IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA875IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA875IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA875IDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA875IDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA875IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA875IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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