TI AFE0064 64 channel analog front end for digital x-ray detector Datasheet

AFE0064
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64 Channel Analog Front End for Digital X-Ray Detector
Check for Samples :AFE0064
FEATURES
1
•
•
DESCRIPTION
64 Channels
28.32 µSec Min Scan Time (including
integration and data transfer for all 64
channels)
7.5 MHz Max Data Transfer Rate
Noise 824 e-RMS with 30 pF Sensor Capacitor
in 1.2 pC Range
Integral Nonlinearity: ±0.006% of FSR
Eight Adjustable Full Scale Ranges (0.13 pC
min to 9.5 pC max)
Built in CDS (signal sample – offset sample)
Selectable Integration Up/Down Mode
Low Power: 175 mW
NAP Mode: 49.5 mW
14 mm × 14 mm 128 Pin TQFP Package
•
•
•
•
•
•
•
•
•
The AFE0064 is a 64 channel analog front end
designed to suit the requirements of flat panel
detector based digital X-ray systems.
The device includes 64 integrators, a PGA for full
scale charge level selection, correlated double
sampler, 64 as to 2 multiplexer, and two differential
output drivers.
Hardware selectable Integration polarity allows
integration of a positive or negative charge and
provides more flexibility in system design. In addition,
the device features TFT (Thin Film Transistor from
Flat Panel Detector) charge injection compensation.
This feature helps maximize the usable signal charge
range of the device.
The nap feature enables substantial power saving.
This is especially useful for power saving during long
X-ray exposure periods.
APPLICATIONS
•
•
•
•
The AFE0064 is available in a 128 pin TQFP
package.
Digital Radiography
CT Scanners
Baggage Scanners
Infrared Spectroscopy
ORDERING INFORMATION (1)
MODEL
INTEGRAL
LINEARITY
% of FS
POWER
DISSIPATION
MIN SCAN
TIME
(µSec)
NUMBER OF
CHANNELS
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
AFE0064
0.006
175 mW
28.32
64
TQFP
PBK
–40 to 85°C
(1)
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
AFE0064IPBK
90(5+1)
AFE0064IPBKR
1000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
AFE0064
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
CDS-0
To
integrators
CHARGE INJECTION
DF_SM,
VT-A,
VT-B
Sh-s
IN
<00>
IN-0
Sh-r
VDD
VSS
CDS-1
Sh-s
IN
<01>
+
IN-1
Sig
Rst
Sh-r
-
AFE0064
+
Sig
Rst
-
X1
Differential
Output
Driver
OUTP_0
OUTM_0
X1
Differential
Output
Driver
OUTP_1
OUTM_1
CDS-62
Sh-s
IN
<62>
IN-62
Sh-r
o/p
control
CDS-63
SMT_MD
ENTRI
Sh-s
IN
<63>
IN-63
Sh-r
P_REF
RPi
RMi
EXT_C
PREF
REF GEN
REFP
REFM
2
TIMINGS AND CONTROL
INTG, IRST, SHS, SHR, CLK, PDZ,
NAPZ, ENTRI, STI, PGA 0-2, INTUPZ
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STO, EOC
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
IN <n> to VSS
–0.3 V to +VDD + 0.3 V
VDD to AGND
–0.3 V to 5 V
Digital input voltage to GND
–0.3 V to (+VDD + 0.3 V)
Digital output to GND
–0.3 V to (+VDD + 0.3 V)
Operating temperature range
–40°C to 85°C
Storage temperature range
–65°C to 150°C
Junction temperature (TJmax)
TQFP package (2)
(1)
(2)
150°C
(TJ max – TA)/ θJA
Power dissipation
θJA Thermal impedance
45°C/W
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Device confirms to MSL level 3 at 260°C as per JEDEC -033.
SPECIFICATIONS
TA = 25 to 85°C, +VDD = 3.3 V, fCLK = 15 MHz for sequential mode and 3.75 MHz for simultaneous mode, scan time = 28.32
µs (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT RANGE
Range 0
0.13
ρC
Range 1
0.25
ρC
Range 2
0.5
ρC
Range 3
1.2
ρC
Range 4
2.4
ρC
Range 5
4.8
ρC
Range 6
7.2
ρC
Range 7
9.6
ρC
Input current
30
µA
Integrator positive input voltage
1.66
1.68
1.70
V
–(REFPREFM)
±1.4
(REFPREFM)
V
ANALOG OUTPUT
Differential full scale analog output
For all ranges
Output common-mode voltage
(REFP+REFM)/2
1.55
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SPECIFICATIONS (continued)
TA = 25 to 85°C, +VDD = 3.3 V, fCLK = 15 MHz for sequential mode and 3.75 MHz for simultaneous mode, scan time = 28.32
µs (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY
Noise in electrons referred to input of
integrator
C-sensor (1)1= 30 pF, Range 3, 14 µSec
integration time
824
C-sensor (1) = 20 pF, Range 3 14 µSec integration
time
600
(1)
C-sensor = 30 pF, Range 3, 270 µSec
integration time
e-
1400
Integral nonlinearity
±0.006
Analog input channel leakage current
This current is integrated and reflects as a part of
offset error.
Channel to channel full-scale error
matching
For ranges 3 to 7
Offset error
Device output offset, resulting from integration of
input leakage current
% of
FSR (2)
2
Channel to channel offset error
matching
pA
±0.7
% of
FSR (2)
±0.07
% of
FSR (2)
±0.07
% of
FSR (2)
±0.002
mV
Integrator input offset:(difference
between integrator positive and
negative terminal)
Integrator input offset mean across channels
Integrator input offset matching across
channels
±3 sigma limit of integrator input offset across
channels
±1.5
mV
Channel to channel crosstalk
Aggressor channel with full scale charge to next
adjacent channel
0.08
% of
FSR (2)
EXTERNAL REFERENCE INPUT
REFP
2.24
2.25
+VDD 0.85
REFM
0.84
0.85
0.86
Input current
P_REF output
P_REF current source capacity
V
V
50
nA
1.68
V
±1
mA
POWER SUPPLY REQUIREMENTS
Power supply voltage, +VDD
Power supply current
3.2
3.3
3.6
During operation
53
58
During NAP
15
mA
10
µSec
Power up time from NAP
mA
DIGITAL INPUT OUTPUT
Logic levels
VIH
0.8×VDD
VDD+0.1
VIL
–0.1
0.2×VDD
VOH
IOH = -500 µA
VOL
IOL = 500 µA
VDD–0.4
0.4
TEMPERATURE RANGE
Operating free air
(1)
(2)
4
0
85
°C
C-Sensor is total external capacitance seen at IN(x) pin. This includes capacitance of all the TFT switches connected to that node and
the routing capacitance.
FSR is full-scale range. There are eight ranges from 0.13 pC to 9.6 pC.
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TIMING REQUIREMENTS
TA = 0 to 85°C, +VDD = 3.3 V
PARAMETER
MIN
TYP
MAX
UNIT
(1)
µSec
SAMPLING AND CONVERSION RELATED
t-scan
Scan time, See Figure 1, Figure 7
28.3
2
See
t1
IRST, SHR, SHS, STI high duration, See Figure 1, Figure 7
30
nSec
t2
Setup time, STI falling edge to first clock rising edge, See Figure 1, Figure 7
30
nSec
t2
Setup time, IRST falling edge to first clock rising edge, See Figure 1, Figure 7
30
nSec
t3
Delay time, 133rd clock rising edge to SHR rising edge, See Figure 1, Figure 7
400
nSec
t4
Delay time, SHR rising edge to INTG rising edge, See Figure 1, Figure 7
30
nSec
t5
INTG high duration (TFT on time), See Figure 1, Figure 7
14
t6
Delay time, INTG falling edge to SHS rising edge, See Figure 1, Figure 7
4.5
µSec
t7
Delay time, SHS rising edge to IRST rising edge, See Figure 1
30
nSec
t8
Delay time, SHS rising edge to STI rising edge, See Figure 1, Figure 7
30
nSec
t9
Hold time, STI falling edge to IRST falling edge, See Figure 1, Figure 7
10
In sequential mode
In simult mode
(1)
(2)
Clock (CLK) frequency
See
(2)
µSec
nSec
1
15
0.25
3.75
MHz
OUTP or OUTM settling time to 16 bit accuracy with 30 pF load and full scale
step
375
nSec
OUTP or OUTM settling time to 16 bit accuracy with 15 pF load and full scale
step
250
nSec
See max specification for t5 and minimum specification for CLK frequency. Also see the section Running the Device at Higher Scan
Time.
There is no real limit on maximum integration time, however as integration time increases the offset value changes due to integration of
leakage current (2 pA typical) also the 1/f noise contribution to output increases, refer to the typical noise numbers at 14 and 270 µSec
integration time in the Specifications table and also see Figure 28 .
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DEVICE INFORMATION
PIN ASSIGNMENTS
I
N
1
5
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
IN25
IN26
IN27
IN28
IN29
IN30
IN31
IN32
IN33
IN34
IN35
IN36
IN37
IN38
IN39
IN40
IN41
IN42
IN43
IN44
IN45
IN46
IN47
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I
N
1
4
I
N
1
3
I
N
1
2
S
M
E
T
R R
X
I I
V V V VV E E VV V V V- S
N NI I I I I I I I I I T
1 1 N N N NN N N NN N - NS S D SD F F SS S D SMT
1 0 9 8 7 6 5 4 3 2 1 0 C CS S D S D P MS S S D S D I
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 9 9 96
2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 9 8 7 95
8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
94
93
92
91
90
89
88
87
86
85
84
83
AFEXR0064
82
( Top View)
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 66
3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 65
I
N
4
8
I
N
4
9
I
N
5
0
I
N
5
1
I
N
5
2
I
N
5
3
I
N
5
4
I
N
5
5
I
N
5
6
I
N
5
7
I
N
5
8
I
N
5
9
I
N
6
0
I
N
6
1
I
N
6
2
PGA-0
PGA-1
PGA-2
INTUPZ
ENTRI
VSS
VSS
NAPZ
PDZ
VDD
VSS
VSS
OUTP-0
OUTM-0
VSS
VDD
VSS
VSS
OUTP-1
OUTM-1
VSS
VDD
VSS
VSS
DF-SM
VSS
CLK
SHR
SHS
IRST
INTG
VSS
I V PV V V VV V V NV V V VS E
N S - S S D SDT T CS D D ST O
S D D SOC
6 S RS S D SD- A B
3
E
F
PIN FUNCTIONS
PIN
NUMBER
NAME
I/O
DESCRIPTION
ANALOG INPUT PINS
113..128
IN<0>…
IN<15>
I
Analog input channels from 0 to 63
1.. 48
IN<16>…
IN<63>
I
84
OUTP-0
O
Driver 0-analog output positive terminal
83
OUTM-0
O
Driver 0-analog output negative terminal
DIFFERENTIAL ANALOG OUTPUT PINS
Driver 0 outputs analog data for channels 31 to 0
6
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PIN FUNCTIONS (continued)
PIN
NUMBER
NAME
I/O
DESCRIPTION
78
OUTP-1
O
Driver 1-analog output positive terminal
77
OUTM-1
O
Driver 1-analog output negative terminal
Driver 1 outputs analog data for channels 63 to 32
Note that the device output is differential (OUTP-OUTM) with common mode of (OUTP+OUTM)/2
REFERENCE
105
REFP
I
Positive reference input
104
REFM
I
Negative reference input
Decouple REFP and REFM terminals to VSS with suitable capacitor and use low noise reference, noise on these terminals will add to noise
at output terminals.
112
EXT_C
O
Terminal available for decoupling internally generated integrator common-mode voltage (1.68 V).
Decouple this pin to VSS with 1 µF ceramic capacitor.
Internally connected to +ve terminals of all 64 integrators.
50
P_REF
O
Internally generated 1.68 V reference output available for referencing photodiode cathodes.
63
STO
O
Delayed ST for cascading next ASIC
64
EOC
O
End of data shifting, EOC is low during data read.
66
INTG
I
Filter bandwidth control for Signal sample (SHS). Filter BW is high when this signal is high and
filter BW is low when this signal is low. Typically this signal should go high with TFT switch turn on
and should go low ~0.5 µSec after TFT switch off.
67
IRST
I
Resets the integrator capacitors on rising edge of this input.
68
SHS
I
Device samples 'signal' level of integrator output(0 to 63) onto the respective CDS on rising edge
of this input.
69
SHR
I
Device samples 'reset' level of integrator output (0 to 63) onto the respective CDS on rising edge
of this input.
70
CLK
I
For simultaneous mode: Device serially outputs the analog voltage from each integrator channel
on each rising edge of CLK.
CONTROL PINS
For sequential mode: Device serially outputs the analog voltage from each integrator channel on
every fourth rising edge of CLK.
88
PDz
I
Low level puts device in powerdown mode.
89
NAPz
I
Low level puts device in NAP mode, this is useful for power saving during X-ray exposure period.
92
ENTRI
I
High on this pin enables 3-state of analog output drivers after shift out of data for all 64 channels.
97
STI
I
Rising edge resets the channel counter. Falling edge enables data transfer on OUTP and OUTM
terminals.
94
PGA-2
I
95
PGA-1
I
Selects eight different analog input ranges. Three bit word with these three bits represents binary
number corresponding to Analog Input Range. PGA-2 is MSB and PGA-0 is LSB. Example 000 is
range 0 and 100 is range 4.
96
PGA-0
I
93
INTUPz
I
High level selects 'integration-down' mode. In this mode device integrates positive pixel current
into each channels, starting from reset level (REFP) down to REFM low level selects
'integration-up' mode. In this mode the device integrates negative pixel current into each channel,
starting from reset level (REFM) up to REFP.
98
SMT-MD
I
High level selects simultaneous mode. Device outputs data simultaneously on both differential
output drivers OUTP-OUTM<0> and OUTP-OUTM<1> in this mode.
PGA-I/P RANGE SELECTION
MODE SELECTION
Low level on this input selects sequential mode. In this mode device output data for driver 0 is
skewed by two clocks from driver 1. This is useful when a two channel multiplexed ADC is used
after AFE.
POWER SUPPLY
53, 55, 60,
61, 75, 81,
87, 100, 106,
108
VDD
I
Device power supply
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PIN FUNCTIONS (continued)
PIN
NUMBER
NAME
49, 51, 52,
54, 59, 62,
65, 71, 73,
74, 76, 79,
80, 82, 85,
86, 90, 91,
99, 101, 102,
103, 107,
109, 110
VSS
I/O
DESCRIPTION
I
Ground for device power supply
TFT CHARGE INJECTION COMPENSATION
72
DF-SM
I
Digital control to dump compensation charge on integrator capacitor; this is useful to nullify the
effect of pixel TFT charge injection.
56
VT-A
I
External voltage to control the amount of charge dump for TFT charge injection compensation.
Charge dump = (V-voltage at 'EXT_C')*0.857 pC where V is external voltage at pins 56, 57. Short
pins 56 and 57 externally and apply external voltage for charge injection compensation.
57
VT-B
I
NC PINS
58, 111
These pins should be connected to VSS.
DESCRIPTIONS AND TIMING DIAGRAMS
IRST
CDS
Filt Bypass
SHR
Integrator
Reset Sample
(SHR)
LPF
Filt Bypass
SHS
+
SHS-SHR
Signal Sample
(SHS)
LPF
Figure 1. Integrator Channel Schematic
Figure 1 shows the typical schematic of an integrator channel. As shown, each integrator has a reset (IRST)
switch which resets the integrator output to the 'reset-level'. The device integrates input current while this switch
is open. There are two sample and hold circuits connected to each integrator output. SHR samples integrator
reset level output and SHS samples integrator output post integration of signal charge. The device subtracts the
SHR sample from the SHS sample. The difference is then available at device output in a differential format. This
action is called 'Correlated Double Sampling' (CDS). CDS removes integrator offset and low frequency noise
from device output.
Each sample and hold has a built-in low pass filter. This filter limits sampling bandwidth so as to limit sampled
noise to an acceptable level. Detailed functioning of individual blocks is described further with timing diagrams.
8
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t- Scan
t1
IRST
t7
t9
SHR
t4
INTG
t3
TFT ON (t5)
SHS
t1
~0.5 uSec
t1
t8
t6
STI
t2
CLK
DATA READ
EOC
Figure 2. Integration and Data Read
As shown in Figure 2, the device performs two functions, ‘Integration’ and ‘Data Read’ during each scan
(indicated by 't-Scan'). Signals IRST, SHR, SHS, INTG, CLK control 'Integration Function' and STI, CLK control
'Data Read Function'. EOC is a device output and a low level on the EOC pin indicates a data read is in
progress.
Charge Integration
Integration function consists of two phases namely ‘Reset’ and ‘Integration’.
IRST rising edge starts the ‘Reset’ phase which ends with SHR rising edge. Figure 3 shows the detailed timing
waveform for the reset phase.
IRST
CLK
Clk No in Sequential mode
Clk No in Simult mode
1
1
2
2
32
8
33
8
64
16
65
17
132
32
133
33
Integrator o/p at
reset level
TFT turned on
Reset Sample
Integrator
o/p
RST sample BW
limited by filter
LPF on
Internal Reset End
SHR
Device integrating input
channel leakage current
Device integrating acquired
charge
Figure 3. Timing Diagram Showing Details of Reset Phase
In this phase the device resets all 64 integration capacitors. This reset-level voltage depends on the integration
mode (selected by the INTUPz pin). Integrator output is reset to REFM for ‘integration-up’ mode and is reset to
REFP in ‘integration-down’ mode. Note that the integrator reset switch is on from IRST rising edge to the end of
the 32nd clock for sequential mode and up to the 8th clock for simultaneous mode. SHR and filter bypass
switches (see Figure 1) are on right from IRST rising edge to the 64th clock falling edge.
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In this period, the reset sample capacitor is tracking the integrator output voltage. On the 64th CLK falling edge,
the filter bypass switch is opened. This kicks in the low pass filter. The filter has a fixed time constant of 1 µSec
(160 kHz BW). The device samples and holds ( SHR switch opens) the integrator reset output at rising edge of
SHR. The low pass filter cuts off high frequency noise during sampling.
SHR
INTG
Signal sample BW
limited by filter
SHS
Signal Sample
LPFON
TFTOFF
TFTON
Reset Sample
Integrator
o/p
Figure 4. Timing Diagram Showing Details of Integration Phase
Here after the integration phase starts. The device integrates pixel charge during on time of the external TFT
switch. The device integrates pixel charge starting from the reset level (as described previously).
In integration up mode, the integrator output moves up from REFM (reset level). As shown in the Specifications
table there are 8 different ranges for the integrator. For any range, the device can linearly integrate input charge
until the integrator output reaches REFP.
In integration down mode, the integrator output moves down from REFP (reset level). For any analog input range
, the device can linearly integrate input charge until the integrator output reaches REFM.
It is clear that the linear output range for the integrator is ‘REFP-REFM’ volts. One can calculate the integrator
feedback capacitor with formula; Q = CV. Here Q is the specified charge for range ‘0 to 7’ and V is the linear
output range of the integrator (REFP-REFM). Refer to Table 1 for more details.
It is recommended to assert (pull high) the INTG signal along with TFT switch turn on. Note that the TFT switch
is external to the device, and the device still integrates without the INTG signal. INTG can be held high for 0.5
µSec after TFT switch turn off. This makes sure the SHS low pass filter is bypassed all through integration and
for 0.5 µSec after integration. This extra 0.5 µSec ensures charge injection during TFT switch turn off is settled
and the SHS sampling capacitor is tracking the integrator output. As shown in Figure 4, the device turns on the
LPF on the falling edge of INTG. Like SHR sampling, this filter has a 1 µSec time constant (160kHz BW), and it
cuts off high frequency noise during sampling. Timing ‘t6’ in the Timing Requirements table specifies that the
settling of voltage on the SHS capacitor is close to the 16 bit level while filter BW is low.
On the rising edge of SHS, the device samples and holds integrator output voltage on the correlated double
sampler (CDS). The CDS output voltage is proportional to the difference of the ‘SHS’ and ‘SHR’ samples. This
scheme removes offset and noise coming from integrator reset. The integration phase ends with the SHS falling
edge and data corresponding to all 64 channels is ready to read during the next ‘scan’.
Data Read:
Device output is differential even though the integrator output (internal to device) is single ended. Here is the
relation between integrator output and AFE0064 output ( OUTP and OUTM):
Case 1: ( Integrator up mode, INTUPz = 0)
10
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As explained before the device samples the integrator output twice, Reset sample ( SHR) and Signal sample
(SHS).
VOUTM = REFM + (VSHS – VSHR)
VOUTP = REFP – (VSHS – VSHR)
Case 2: (Integrator down mode, INTUPz = 1)
As explained before the device samples the integrator output twice, Reset sample ( SHR) and Signal sample
(SHS).
VOUTM = REFP + (VSHS – VSHR)
VOUTP = REFM – (VSHS – VSHR)
The differential output from the AFE0064 rejects common-mode noise from the board helping to maximize noise
performance of the system. The following table provides details of integrator feedback ranges, feedback
capacitor, and corresponding AFE0064 output at zero and full scale input charge.
Table 1. AFE0064 Range Selection to Device Analog Output Mapping
REFP
2.25
REFM
0.85
REFP-REFM
1.4
INTEGRATE UP MODE
(INTUPz=0), e– counting
Range
Typical FS
Charge Range
(Qr) pC
Int FB Cap= (Qr)/
(REFP-REFM)
… pF
0
0.13
0.0929
1
0.25
0.1786
2
0.5
0.3571
3
1.2
0.8571
4
2.4
1.7143
5
4.8
3.4286
6
7.2
5.1429
7
9.6
6.8571
INTEGRATE DOWN MODE
(INTUPz=1), hole+ counting
At 0 charge I/p
At FS charge I/p
At 0 charge I/p
At FS charge I/p
OUTP
OUTM
OUTP
OUTM
OUTP
OUTM
OUTP
OUTM
2.25
0.85
0.85
2.25
0.85
2.25
2.25
0.85
The following section provides detailed timing of data read. There are two output drivers. Data for channel
number 63 to 32 is available on output driver 1 and data for channel number 31 to 0 is available on output driver
0. Data from two drivers can be available simultaneously or sequentially depending on the status of pin
SMT_MD.
Figure 5. Device Data Read in Sequential Mode (SMT_MD = 0)
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A high pulse on STI activates the data read function and resets the channel counter to zero. As shown in
Figure 5, the device outputs the analog voltage from channel 63 on the first rising edge of CLK after STI falling
edge. Channel 63 to 32 data is available on the OUTP<1> and OUTM<1> terminals. Next the lower output
channel is connected to the output after four clocks.
Data on the OUTP<0> and OUTM<0> terminals is skewed by two clocks with respect to OUTP<1> and
OUTM<1>. Channel 31 to 0 data is available on the OUTP<0> and OUTM<0> terminals.
The skew between the two output drivers allows the user to connect a two channel multiplexed input ADC to the
AFE output.
The device output goes to 3-state after all of the data on the particular differential output driver ( 0 or 1) is
transferred, if ENTRI is tied to high level. Otherwise, both differential output drivers stay at output common-mode
voltage after data transfer.
Maximum Data Transfer Rate: As shown in Figure 5, the device outputs new channel data on every alternate
rising edge of the clock. Effectively the data transfer rate is one-half of the clock speed. The maximum data
transfer rate is 7.5 MHz as the device supports a maximum 15 MHz clock frequency.
Figure 6. Device Data Read in Simultaneous Mode ( SMT_MD=1)
A high level on the ‘SIMULT_MODE’ pin selects simultaneous mode. the device outputs data simultaneously on
both differential output drivers OUTP-OUTM<0> and OUTP-OUTM<1> in this mode. This means the device
outputs both Ch31 and Ch63 outputs on the first rising edge of the clock, Ch30 and Ch62 on the 2nd rising edge
and so on. This mode is useful when two separate single channel ADCs or one simultaneous sampling ADC is
used to digitize OUTP-OUTM<0> and OUTP-OUTM<1>. Unlike sequential mode, simultaneous mode needs only
33 clocks to read all 64 channels of data. In this case the output data transfer rate per output driver is the same
as the clock frequency. The device can work at a maximum clock frequency of 3.75 MHz.
Running the Device at Minimum Scan Time:
Minimum scan time is achieved if a data read overlaps the reset phase (as shown in Figure 1). This can be done
if an IRST rising edge and STI rising edge occur simultaneously. It is recommended to stop the clock after the
device receives 133 clocks after STI falling edge, if sequential mode selected (or 33 clocks if simultaneous mode
is selected). It is possible to keep the clock free running throughout the scan, but it can potentially deteriorate
noise performance. With t-scan (min) = t1+t2+132 (t-clk)+t3+t4+t5+0.5µSec+t6+t7 and all timing values used are
the minimum specified values, then t-scan (min) = 28.32 µSec.
Running the Device at Higher Scan Time (for lesser frame rate):
It is possible to run the device at a higher scan time to achieve a lesser frame rate without affecting performance.
(Note that violating the maximum limits on the specified timings and also the minimum specification on the clock
frequency results in charge leakage on the integration or CDS capacitors. This causes additional offset and gain
errors.)
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t - Scan
t1
IRST
t9
SHR
t4
INTG
t3
SHS
t1
TFT ON (t5)
t1
~0.5 mSec
t6
t8
STI
t2
CLK
WAIT
Additional
133 clocks
DATA READ
EOC
Figure 7. Device Operation at Higher Scan Times (sequential mode shown, however the same is possible
for simultaneous mode)
As shown in Figure 7, a data read can be started by issuing a STI pulse after SHS and well before IRST. In this
case the device goes into a ‘wait’ state after the data read is complete. The device remains in this wait state until
it receives IRST and STI rising edges. Note that the clock can be stopped (or kept running) in the wait state
however it is necessary to provide an additional 133 or 33 clocks after IRST falling edge depending on sequential
or simultaneous mode selection respectively. It is recommended to stop the clock after the device receives 133
or 33 clocks depending on mode selection until the next STI pulse. This helps to get maximum SNR from the
device. However it is allowed to use a free running clock.
Cascading Two AFE0064 Devices to Scan 128 Channels:
It is possible to cascade two AFE0064 devices to scan 128 channels. This feature is useful for sequential mode
and allows the use of a 4 channel, multiplexed input ADC for two AFEs.
In that case, STO of device 1 is connected to STI of device 2. Other control pins (INTG, IRTS, SHR, SHS, CLK)
of both devices are connected to each other.
As shown in figure 8, STO falling edge is delayed by one clock from STI falling edge. (STO falling edge aligns
with first clock falling edge.) Device 2 data out starts with the second clock rising edge (the first CLK rising edge
after STI falling edge for device 2). Effectively, data from the four output drivers of the two devices is presented
on every rising edge in the following sequence:
Clock 1,5,9...: OUT-1 of Device 1
Clock 2,6,10...: OUT-1 of Device 2
Clock 3,7,11...: OUT-0 of Device 1
Clock 4,8,12...: OUT-0 of Device 2
Note this output sequence when connecting a multiplexed input ADC at a device output.
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Data Read
STI #1
1
2
3
CLK
#1,2
OUTP –
OUTM <1> # 1
OUTP –
OUTM <0> # 1
4
5
6
7
Ch63
124
8
125
126
127
128
Ch62
130
131
132
133
Ch32
Ch30
Ch31
129
Ch1
Ch0
STO #1= STI #2
OUTP –
OUTM <1> # 2
OUTP –
OUTM <0> # 2
Ch127
Ch126
Ch95
Ch94
Ch96
Ch65
Ch64
Figure 8. Data Read with Two Devices in Cascade
This mode allows the use of a single, four channel, 15 MHz (or more) ADC for digitizing the data from 128
channels in single scan. In this mode the effective maximum data transfer rate is 15 MHz.
TFT Charge Injection Compensation: The AFE0064 allows compensation for the charge injected by the TFT
during turn on and turn off. During turn on, typically a TFT injects a positive charge forcing the integrator output
below zero. One way to handle this is to allow negative swing on the integrator. In that case the pixel charge is
integrated from the –ve value resulting from TFT charge injection. For this scheme the device output dynamic
range covers all voltage levels starting from fixed –ve voltage arising from maximum anticipated charge injection
to maximum positive voltage from the integrator. This can result in loss of dynamic range in the case where TFT
charge injection is less than the maximum anticipated charge injection.
To overcome this problem, the AFE0064 provides a special feature to compensate for positive or negative
charge during TFT turn on and opposite polarity charge during TFT turn off. The user can adjust the
compensation charge with the help of external voltage on the VTEST-A and VTEST-B pins.
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Pin 56,
57
V(EXT_C)
S1
C1 =
0.857 pC
S1
Compensation scheme
Pixel cap
TFT
Switch
Ch-n
IN-n
V(EXT_C)
IRST
SHR
SHS
TFT Switch on
DF-SM
INTG
TFT charge injection
Compensation charge
C1 charge injection
= (V at Pins 56,57 – V
at ‘EXT_C’)*
0.857pC
C1 charge injection
= -(V at pins 56,57 – V
at ‘EXT_C’)*
0.857pC
S1 on
S1\ off
S1 off
S1\ on
Figure 9. TFT Charge Injection Compensation Scheme
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As shown in Figure 9, the TFT injects a charge during turn on and an opposite polarity charge during turn off.
(For this example the injected charge during TFT turn on is positive.) This drives the integrator output –ve.
Depending on the magnitude of the injected charge, the integrator may saturate or may be within linear range.
The device starts integration from this –ve output voltage. At the end of integration the device sees an opposite
polarity charge injection roughly of the same magnitude. This opposite polarity charge may or may not nullify the
initial injected charge depending on whether the integrator was still within linear range or there was charge
leakage due to integrator output saturation. The voltage at pins 56, 57 can be adjusted so that the compensation
charge equals the TFT injected charge with opposite polarity. This nullifies the TFT injected charge both during
turn on and turn off, to always keep the integrator in the linear region. So for the positive charge injection during
TFT turn on, inject a –ve compensation charge. For this, the voltage at pins 56,57 needs to be set below the
voltage at 'EXT_C'. The device injects the charge on the falling edge of the DF_SM signal. The compensation
charge formulas are:
Compensation charge for TFT turn on = (V at pins 56,57 – V_'EXT_C') × 0.857 pC
Compensation charge for TFT turn off = –(V at pins 56,57 – V_'EXT_C') × 0.857 pC
Select voltage at pins 56,57 higher than the voltage at 'EXT_C' for compensating –ve charge during TFT turn on.
The device always injects an equal and opposite compensation charge at the rising edge of the DF_SM signal.
Allowing Limited Hole Counting (+ve charge) for Applications with Electron Counting (–ve charge) and
Vice a Versa:
The charge compensation scheme can be used to offset the integrator output at the start of integration so as to
allow a linear charge range in both directions. As discussed previously (refer to Figure 9), it is possible to inject a
fixed +ve or –ve charge at the start of integration. The device can integrate up or down starting from this offset
level. Note the integrator output is linear within the bounds of REFM and REFP. One can calculate the offset
charge at integration start as Qcomp = (V at pins 56,57 – V_'EXT_C') × 0.857 pC.
The resulting integrator o/p offset voltage in the case of integration up or down is given by the following formula:
In the case of integration up:
Vint_off = REFM – (Qcomp × Int FB cap) — Refer to Table 1 for the Int FB cap for the selected range.
Qcomp is negative for integration up, so that the integration output has a positive offset allowing headroom
for hole counting.
In the case of integration down:
Vint_off = REFP – (Qcomp × Int FB cap) — Refer to Table 1 for the Int FB cap for the selected range.
Qcomp is positive for integration up, so that the integration output has a negative offset allowing headroom
for electron counting.
As shown in Figure 10, DF_SM rising edge is pushed after SHS rising edge. This avoids opposite charge
injection which can corrupt integrator output.
16
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IRST
SHR
SHS
TFT Switch on
DF-SM
INTG
+ve charge
(Integrator down)
Compensation
charge
C1 charge injection
= (V at Pins 56,57 –
Voltage at ‘ECT_C’)*
0.857pC
-ve charge
(Integrator up)
Electron counting
REFP
Vint off
Integrator output
( internal)
For Integration
down mode
Hole counting
REFM
Reset sample
Signal sample
Electron counting
REFP
Integrator output
( internal)
For Integration up
mode
Hole counting
Vint_off
REFM
Reset sample
Device allows integration
with both polarity
Signal sample
Figure 10. Handling Bipolar Charge Range Using Charge Injection Scheme
Note the relation between the integrator output and AFE0064 output ( OUTP and OUTM) described in the Data
Read section.
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TYPICAL CHARACTERISTICS
HISTOGRAM OF OUTPUT OFFSET DRIFT WITH +VDD SUPPLY
VARIATION
HISTOGRAM OF OUTPUT OFFSET DRIFT WITH FREE-AIR
TEMPERATURE
900
450
TA = 45°C,
VDD = 3.2 V to 3.6 V,
Range = 9.6 pC
800
400
350
Count of Channels
Count of Channels
700
VDD = 3.2 V to 3.6 V,
Range = 1.2 pC
600
500
400
300
300
250
200
150
200
100
100
50
0
0
-0.4
-0.32
-0.24
-0.16
-0.08
0
0.08
-5
-4
Channel Output Offset Drift - mV/mV of VDD
-3
-2
-1
0
1
Channel Output Offset Drift - mV/°C
2
3
Figure 11.
Figure 12.
HISTOGRAM OF GAIN ERROR VARIATION WITH +VDD
HISTOGRAM OF GAIN ERROR DRIFT WITH FREE-AIR
TEMPERATURE
450
450
TA = 45°C,
VDD = 3.2 V to 3.6 V,
Range = 250 fC
400
350
300
300
Channels Count
350
250
200
150
200
150
3.75
4.375
2.5
3.125
1.25
1.875
0
0.625
-1.25
-0.625
-2.5
-1.875
0
-3.75
0
-3.125
50
-5
50
-4.375
100
Bin
VDD = 3.4 V,
Range = 250 fC
250
100
-5.625
Count of Channels
400
Bin
-5
0
5
10 15 20 25 30 35 40
Drift in Gain Error - ppm of Full Scale/°C
45
50
Gain Error Drift - PPM of Full Scale / mV 0f VDD
Figure 13.
18
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
RANGE
CHANNEL TO CHANNEL CROSSTALK
vs
CHANNEL NUMBER
14
0.08
TA = 45°C,
VDD = 3.4 V
0.07
Channel to Channel Crosstalk - %FS
Gain Error - %Full Scale
12
10
8
6
4
2
Stimulus 90% of FSR,
TA = 45°C, VDD = 3.4 V,
Aggressor Channel: 20,
Range: 9.6 pC
0.06
0.05
0.04
0.03
0.02
0.01
0
0
0
1
2
3
Range
4
5
6
-0.01
0
7
10
20
30
40
50
60
70
Channel Number
Figure 15.
Figure 16.
SCAN TO SCAN CROSSTALK
vs
CHANNEL NUMBER
COUNT OF CHANNELS
vs
LEAKAGE CURRENT DRIFT WITH +VDD
0.02
0.015
700
TA = 45°C,
Range = 2.4 pC
600
0.01
Count of Channels
Scan to Scan Crosstalk - %FS
800
Stimulus 90% of FSR
TA = 45°C,
VDD = 3.4 V,
Range = 9.6 pC,
0.005
0
-0.005
500
400
300
200
-0.01
100
0
-0.015
0 2
5
8
11
14
17
20
Channel Number
23
26
29
32
Bin
Figure 17.
0
0.05
0.1
0.15
Drift in Leakage Current - pA/V
0.2
0.25
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
COUNT OF CHANNELS
vs
LEAKAGE CURRENT DRIFT WITH FREE-AIR TEMPERATURE
NOISE
vs
CHANNEL NUMBER IN RANGE 0
720
450
400
VDD = 3.4 V,
Range =2.4 pC
700
680
Noise - in Electrons
Channel Count
350
300
250
200
150
640
620
TA = 45°C,
VDD = 3.4 V,
Range = 130 fC,
Bus Cap = 24 pF
600
100
580
50
0
660
-5
-4
-3
-2
-1
0
1
2
3
4
Leakage Current Drift - fA/°C
5
6
560
7
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Channel Number
Figure 19.
Figure 20.
NOISE
vs
CHANNEL NUMBER IN RANGE 1
NOISE
vs
CHANNEL NUMBER IN RANGE 2
720
780
TA = 45°C,
VDD = 3.4 V,
Range = 250 fC,
Bus Cap = 24 pF
700
760
Noise - in Electrons
Noise - in Electrons
740
680
660
640
620
720
700
680
TA = 45°C,
VDD = 3.4 V,
Range = 500 fC,
Bus Cap = 24 pF
660
640
600
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Channel Number
0
4
Figure 21.
20
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Channel Number
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
NOISE
vs
CHANNEL NUMBER IN RANGE 3
NOISE
vs
CHANNEL NUMBER IN RANGE 4
860
1040
840
1020
Noise - in Electrons
Noise - in Electrons
820
800
780
760
TA = 45°C,
VDD = 3.4 V,
Range = 1.2 pC,
Bus Cap = 24 pF
740
980
C
960
TA = 45°C,
VDD = 3.4 V,
Range = 2.4 pC,
Bus Cap = 24 pF
940
720
920
0
4
8
0
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Channel Number
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Channel Number
Figure 23.
Figure 24.
NOISE
vs
CHANNEL NUMBER IN RANGE 5
NOISE
vs
CHANNEL NUMBER IN RANGE 6
2120
1520
TA = 45°C,
VDD = 3.4 V,
Range = 4.8 pC,
Bus Cap = 24 pF
1500
2080
1480
1460
C
1440
TA = 45°C,
VDD = 3.4 V,
Range = 7.2 PC,
Bus Cap = 24 pF
2100
Noise - in Electrons
Noise - in Electrons
1000
2060
2040
C
2020
2000
1420
1980
1400
1380
1960
1940
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Channel Number
0
4
Figure 25.
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
Channel Number
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
NOISE
vs
CHANNEL NUMBER IN RANGE 7
NOISE
vs
INTEGRATION TIME
1400
2700
TA = 45°C,
VDD = 3.4 V,
2650 Range = 9.6 PC,
Bus Cap = 24 pF
1200
TA = 45°C,
VDD = 3.4 V,
Range = 1.2 pC,
Bus Cap = 24 pF
Noise - in e-
Noise - in Electrons
1000
2600
C
2550
600
2500
400
2450
200
0
10
2400
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
Channel Number
100
1000
Integration Time - ms
10000
Figure 27.
Figure 28.
NONLINEARITY ACROSS 30 DEVICES/64 CHANNELS
NONLINEARITY ACROSS 30 DEVICES/64 CHANNELS
4
2
min Performance
3
median Performance
Nonlinearity - 16 Bit Isbss
2
max Performance
1
0
-1
-2
-3
-4
0
TA = 45°C,
VDD = 3.4 V,
Bus Cap = 22 pF,
Range = 1.2 pC,
Output = Simult
20
min Performance
1
median Performance
Nonlinearity - 16 Bit Isbss
800
0
max Performance
-1
-2
-3
TA = 45°C,
VDD = 3.4 V,
Bus Cap = 22 pF,
Range = 9.6 pC,
Output = Simult
-4
-5
40
60
80
100
-6
0
20
Range - %
Figure 29.
40
60
Full Scale Output - %
80
100
Figure 30.
+VDD CURRENT
vs
FREE-AIR TEMPERATURE
54.5
54
VDD = 3.4 V
53.5
+VDD Current - mA
53
52.5
52
51.5
51
50.5
50
49.5
25
35
45
55
65
TA - Free-Air Temperature - °C
75
85
Figure 31.
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APPLICATION INFORMATION
INTERFACING FLAT PANEL DETECTOR (FPD)
The following figure shows interfacing a flat panel detector to an AFE0064. The flat panel detector is a matrix of
pixels. Each pixel consists of a photo diode and Thin Film Transistor switch. All of the pixels in a single row (or
column depending on the convention used) are connected to a single bus. This bus interfaces with a single
integrator. There is a separate integrator channel per row.
On X-Ray exposure (converted to light with scintillator) individual photo diodes acquire a charge proportional to
incident light intensity. This charge is sampled in self capacitance of the photo diode. The columns are scanned
one by one and the AFE0064 converts an individual photo diode charge into a proportional voltage.
Pixel
TFT Switch
Photo Diode
AFE0064
EXTC Internal
1.69 V
1 mF
FLAT PANEL
DETECTOR
ADC INTERFACE WITH AFE OUTPUT
Each AFE0064 has two differential output drivers as mentioned previously. AFE allows cascading of two devices
which can work together like a single 128 channel device. Refer to Figure 8 for the timing diagram.
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STO #1
STI #2
Contact TI sales for suitable ADC.
Figure 32. Typical Schematic Showing Four Channel ADC Interface with Two AFEs
RESETTING THE FPD PANEL
It is possible to reset the photo diodes using IRST. The integrator acts like a unity gain buffer during reset and
the device can source or sink 50 µA through each of the 64 input pins while in the reset phase. For example, to
reset a 10 pC charge it requires 10pC/50µA = 1/5 µSec.
Refer to Figure 3 for the reset timing details. The device is in the reset phase for 32/8 clocks after IRST rising
edge in sequential/simultaneous mode respectively. The reset duration is controlled by selecting a clock speed or
holding one of the 32/8 clocks for the required time in sequential/simultaneous mode respectively.
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AFE TRANSFER CHARACTERISTICS
3.5
Ideal P
3
Output Voltage
2.5
Practical P
2
1.5
1
Practical M
0.5
Ideal M
0
0
20
40
60
80 100
% input charge
120
140
160
The plot above shows AFE transfer characteristics in integrator down mode. (For integrator up mode the P and
M plots are interchanged.) AFE output is linear in the charge range bound by the rectangle shown.
The four corners of the rectangle in clockwise direction, starting with bottom left corner are as follows:
(0%, 0.85 V), (0%, 2.25 V), (100%, 2.25 V), (100%, 0.85 V) where REFP = 2.25 V and REFM = 0.85 V.
Beyond this range, the AFE output still responds to input charge however linearity is not specified. Linearity
deteriorates as the output reaches close to the rails.
One can detect overrange once the output is beyond the linear rectangle and select a higher AFE range. It is
also recommended to clamp the ADC input once it crosses 100% FS.
AFE REFERENCE DRIVING
Figure 33 shows generation of the 0.85 V and 2.25 V references for an AFE. Note that the device uses internal
buffers on the reference inputs. As a result, it is possible to share a reference to multiple AFEs in a system.
However, it is recommended to use a separate 100-Ω, 1-µF LPF for each individual AFE. Use 1% tolerance
resistors for dividing 2.5 V to 2.25 V and 0.85 V.
To filter inputs for
other AFE
reference
3.3V
Vin = ~3.3V
REF5025
GND
Vout = 2.5
10uF
300
ohm
2.25 V to AFE REFP
100 ohm
1uF
100 ohm
1uF
2.7k
1.5k+47ohm
0.85 V to AFE REFM
OPA2376
Filter for each AFE
Figure 33. Typical Reference Generation and Driving Circuit for the AFE0064
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :AFE0064
25
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
AFE0064IPBK
ACTIVE
LQFP
PBK
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AFE0064
AFE0064IPBKR
ACTIVE
LQFP
PBK
128
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AFE0064
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
AFE0064IPBKR
Package Package Pins
Type Drawing
LQFP
PBK
128
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
17.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
17.0
2.1
20.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AFE0064IPBKR
LQFP
PBK
128
1000
367.0
367.0
45.0
Pack Materials-Page 2
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