LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 LM98722 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation Check for Samples: LM98722 FEATURES APPLICATIONS • • • • • • 1 2 • • • • • • LVDS/CMOS Outputs LVDS/CMOS/Crystal Clock Source with PLL Multiplication Integrated Flexible Spread Spectrum Clock Generation CDS or S/H Processing for CCD or CIS sensors Independent Gain/Offset Correction for Each Channel Automatic per-Channel Gain and Offset Calibration Programmable Input Clamp Voltage Flexible CCD/CIS Sensor Timing Generator KEY SPECIFICATIONS • • • • • • • • • • • • • • • Maximum Input Level: – 1.2 or 2.4 Volt Modes – (both with + or - polarity option) ADC Resolution: 16-Bit ADC Sampling Rate: 45 MSPS INL: +18/-25 LSB (typ) Channel Sampling Rate: 22.5/22.5/15 MSPS PGA Gain Steps: 256 Steps PGA Gain Range: 0.64 to 8.3x Analog DAC Resolution: +/-9 Bits Analog DAC Range: +/-307mV or +/-614mV Digital DAC Resolution: +/-6 Bits Digital DAC Range: -2048 LSB to + 2016 LSB SNR: -74dB (@0dB PGA Gain) Power Dissipation: 630mW (LVDS) Operating Temp: 0 to 70°C Supply Voltage: 3.3V Nominal (3.0V to 3.6V range) Multi-Function Peripherals High-speed Currency/Check Scanners Flatbed or Handheld Color Scanners High-speed Document Scanners DESCRIPTION The LM98722 is a fully integrated, high performance 16-Bit, 45 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for higher speed CCD or CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a +/-9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three analog inputs. The signals are then routed to a 45MHz high performance analog-to-digital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of -74dB. The 16-bit ADC has excellent dynamic performance making the LM98722 transparent in the image reproduction chain. A very flexible integrated Spread Spectrum Clock Generation (SSCG) modulator is included to assist with EM compliance and reduce system costs. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated 2 Submit Documentation Feedback Product Folder Links: LM98722 Reference Generator PGA Digital Offset 16 Bit ADC Blue Ch Black Level White Level Correction CCD Timing Generator 16 Green Ch Black Level White Level Correction CLKOUT/ VC SH2 Data Out Config (CMOS/LVDS) INCLK- INCLK+ DOUT0/ TXOUT0- DOUT1/ TXOUT0+ DOUT2/ TXOUT1- DOUT3/ TXOUT1+ DOUT4/ TXOUT2- DOUT5/ TXOUT2+ DOUT6/ TXCLK- DOUT7/ TXCLK+ CLK VCLP Reference DAC CDS or Sample/Hold Amplifier COLOR3PGA[7:0] 3:1 MUX Red Ch Black Level White Level Correction CE SCLK SDO SDI SEN SSCG VCLP Reference Configuration Input Bias/ Clamping Black Level Offset DAC PGA COLOR2PGA[7:0] Serial Interface Data Output COLOR3ODDDAC[9:0] M U X CDS or Sample/Hold Amplifier Black Level Offset DAC Config Registers RESET CCD Timing Generator COLOR3EVENDAC[9:0] Input Bias/ Clamping COLOR2ODDDAC[9:0] M U X PGA COLOR1PGA[7:0] CAL Sensor Drivers COLOR2EVENDAC[9:0] Input Bias/ Clamping Black Level Offset DAC VD DGND DVB LM98722 OSB OSG OSR M U X CDS or Sample/Hold Amplifier COLOR1ODDDAC[9:0] COLOR1EVENDAC[9:0] VA AGND LM98722 SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com System Block Diagram CCD/CIS Sensor Analog Front End SPI Image Processor/ ASIC Motor Controllers LM98722 Overall Chip Block Diagram SH5 SH4 SH3 SH1 RS CP PHIC2 PHIC1 PHIB2 PHIB1 PHIA2 PHIA1 SH_R VREFT VREFB VCLP Figure 1. Chip Block Diagram Copyright © 2009–2013, Texas Instruments Incorporated LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 LM98722 Pin Out Diagram PHIC2 1 56 SH5 PHIC1 2 55 SH4 SH1 3 54 PHIB2 CE 4 53 PHIB1 CAL 5 52 VC RESET 6 51 DGND SH_R 7 50 PHIA2 SDI 8 49 PHIA1 SDO 9 48 CP SCLK 10 47 RS SEN 11 46 SH3 VA 12 45 CLKOUT/SH2 AGND 13 44 VC VA 14 43 VD VREFB 15 42 DGND VREFT 16 41 DOUT0/TXOUT0- VA 17 40 DOUT1/TXOUT0+ AGND 18 39 DOUT2/TXOUT1- VCLP 19 38 DOUT3/TXOUT1+ VA 20 37 DOUT4/TXOUT2- IBIAS 21 36 DOUT5/TXOUT2+ AGND 22 35 DOUT6/TXCLK- OSR 23 34 DOUT7/TXCLK+ AGND 24 33 INCLK- OSG 25 32 INCLK+ AGND 26 31 DVB OSB 27 30 CPOFILT1 CPOFILT2 28 29 DGND 56 Pin TSSOP (not to scale) Figure 2. TSSOP Package See Package Number DGG0056A Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 3 LM98722 SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Typical Application Diagram Serial Interface and Device Control Bus CCD Timing Generator Output Bus PHIC2 SH5 PHIC1 SH4 SH1 PHIB2 CE PHIB1 CAL CCD Clock Drivers DGND SH_R PHIA2 SDI PHIA1 SDO VA 0.1 PF 0.1 PF 0.1 PF RS SEN SH3 CLKOUT/SH2 AGND VC VA VD VREFB 0.1 PF 0.1 PF 0.1 PF AGND CCD Sensor & Output Signal Buffers 0.1 PF DGND CP SCLK VA 0.1 PF VC VC RESET VC 0.1 PF VD 0.1 PF DGND DGND VREFT D0/TXOUT0- VA D1/TXOUT0+ AGND D2/TXOUT1- VCLP D3/TXOUT1+ VA D4/TXOUT2- IBIAS D5/TXOUT2+ AGND D6/TXCLK- OSR D7/TXCLK+ AGND INCLK- OSG INCLK+ AGND LVDS Deserializer (DS90CR218A or equiv.) * 100: DVB OSB CPOFILT1 CPOFILT2 0.1 PF DGND DGND AGND DGND ASIC and Clock Gen 0.1 PF 3.3V 3.3V VA + 4.7 PF AGND VD VC + 4.7 PF * 100: used for LVDS INCLK only. If using CMOS INCLK, 100: is removed and INCLK- connected to DGND. DGND Figure 3. Typical Application Diagram 4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 Pin Descriptions (1) Pin Name I/O Typ Res Description 1 PHIC2 O D PU Configurable high speed sensor timing output. 2 PHIC1 O D PD Configurable high speed sensor timing output. 3 SH1 O D PU Configurable low speed sensor timing output. 4 CE I D Chip Serial Interface Address Setting Input CE Level Address VD 01 Float 10 DGND 00 5 CAL I D PD Initiate calibration sequence. Leave unconnected or tie to DGND if unused. 6 RESET I D PU Active-low master reset. NC when function not being used. 7 SH_R I D PD External request for an SH interval. 8 SDI I D PD Serial Interface Data Input. 9 SDO O D 10 SCLK I D PD Serial Interface shift register clock. 11 SEN I D PU Active-low chip enable for the Serial Interface. 12 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND. 13 AGND P Analog ground return. 14 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND. 15 VREFB O A Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground. 16 VREFT O A Top of ADC reference. Bypass with a 0.1μF capacitor to ground. 17 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND. 18 AGND P Analog ground return. 19 VCLP A Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 4.7μF capacitor to AGND. An external reference voltage may be applied to this pin. 20 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND. 21 IBIAS A Bias setting pin. Connect a 9.0 kOhm 1% resistor to AGND. 22 AGND P Analog ground return. 23 OSR A Analog input signal. Typically sensor Red output AC-coupled thru a capacitor. 24 AGND P Analog ground return. 25 OSG A Analog input signal. Typically sensor Green output AC-coupled thru a capacitor. 26 AGND P Analog ground return. 27 OSB A Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor. 28 CPOFILT2 A Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to CPOFILT1. 29 DGND P Digital ground return. 30 CPOFILT1 A Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to CPOFILT2. 31 DVB O D Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND. 32 INCLK+ I D Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation. 33 INCLK- I D Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock. 34 DOUT7/ O D Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode. O D Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode. O D Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode. IO O I I I Serial Interface Data Output. TXCLK+ 35 DOUT6/ TXCLK- 36 DOUT5/ TXOUT2+ (1) (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.). Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 5 LM98722 SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Pin Descriptions(1) (continued) Pin 37 Name DOUT4/ I/O Typ Res Description O D Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode. O D Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode. O D Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode. O D Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode. O D Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode. O D TXOUT238 DOUT3/ TXOUT1+ 39 DOUT2/ TXOUT1- 40 DOUT1/ TXOUT0+ 41 DOUT0/ TXOUT0- 42 DGND 43 VD P Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single 4.7μF capacitor should be used between the supply and the VD, VR and VC pins. 44 VC P Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor. 45 CLKOUT/SH2 O D Output clock for registering output data when using CMOS outputs, or a configurable low speed sensor timing output. 46 SH3 O D Configurable low speed sensor timing output. 47 RS O D Configurable high speed sensor timing output. 48 CP O D Configurable high speed sensor timing output. 49 PHIA1 O D Configurable high speed sensor timing output. 50 PHIA2 O D Configurable high speed sensor timing output. 51 DGND P Digital ground return. 52 VC P Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor. 53 PHIB1 O D Configurable high speed sensor timing output. 54 PHIB2 O D Configurable high speed sensor timing output. 55 SH4 O D Configurable low speed sensor timing output. 56 SH5 O D Configurable low speed sensor timing output. 6 PD Configurable sensor control output. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VA,VR,VD,VC) 4.2V Voltage on Any Input Pin(Not to exceed 4.2V) −0.3V to (VA + 0.3V) Voltage on Any Output Pin(execpt DVB and not to exceed 4.2V) −0.3V to (VA + 0.3V) DVB Output Pin Voltage Input Current at any pin other than Supply Pins 2.0V (4) ±25 mA Package Input Current (except Supply Pins) (4) ±50 mA Maximum Junction Temperature (TA) 150°C Thermal Resistance (θJA) <66°C/W Package Dissipation at TA = 25°C (5) ESD Rating (6) >1.89W Human Body Model 2500V Machine Model 250V −65°C to +150°C Storage Temperature Soldering process must comply with Texas Instrument’s Reflow Temperature Profile specifications. Refer to www.ti.com/packaging (1) (2) (3) (4) (5) (6) (7) (7) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Reflow temperature profiles are different for lead-free and non-lead-free packages. Operating Ratings (1) (2) 0°C ≤ TA ≤ +70°C Operating Temperature Range All Supply Voltage (1) (2) +3.0V to +3.6V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 7 LM98722 SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Electrical Characteristics The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. Parameter Test Conditions Min (1) Typ (2) Max (1) (3) Units CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb) VIH Logical “1” Input Voltage VIL Logical “0” Input Voltage VIHYST Logic Input Hysteresis IIH Logical “1” Input Current IIL Logical “0” Input Current 2.0 V 0.8 V 0.6 VIH = VD RESET,SEN 100 nA SH_R, SCLK, SDI, CAL 65 μA CE 30 nA RESETSEN -65 μA SH_R, SCLK, SDI, CAL -100 nA CE -30 μA VIL = DGND CMOS Digital Output DC Specifications (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC) VOH Logical “1” Output Voltage IOUT = -0.5mA VOL Logical “0” Output Voltage IOUT = 1.6mA IOS Output Short Circuit Current VOUT = DGND 18 VOUT= VD -25 VOUT = DGND 20 VOUT = VD -25 IOZ CMOS Output TRI-STATE Current 3.0 V 0.21 V mA nA CMOS Digital Output DC Specifications (CMOS Data Outputs) VOH Logical “1” Output Voltage IOUT = -0.5mA 2.3 V VOL Logical “0” Output Voltage IOUT = 1.6mA 0.12 V IOS Output Short Circuit Current VOUT = DGND 12 mA VOUT= VD -14 IOZ CMOS Output TRI-STATE Current VOUT = DGND 20 VOUT = VD -25 nA LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins) VIHL VILL Differential LVDS Clock RL = 100Ω High Threshold Voltage VCM (LVDS Input Common Mode Voltage)= 1.25V Differential LVDS Clock 200 mV -200 mV 2.0 V Low Threshold Voltage VIHC CMOS Clock INCLK- = DGND High Threshold Voltage VILC CMOS Clock 0.8 V 260 μA Low Threshold Voltage IIHL CMOS Clock 230 Input High Current IILC CMOS Clock -135 -120 μA Input Low Current (1) (2) (3) 8 Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. The analog inputs are protected as shown in Figure 4. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per Note 4 under the Absolute Maximum Ratings Table. However, input errors will be generated If the input goes above VA and below AGND. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 Electrical Characteristics (continued) The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. Parameter Test Conditions Min (1) Typ (2) Max (1) (3) Units mV LVDS Output DC Specifications VOD Differential Output Voltage VOS LVDS Output Offset Voltage IOS Output Short Circuit Current RL = 100Ω 280 390 490 1.08 1.20 1.33 V VOUT = 0V, RL = 100Ω 8.5 mA LVDS Output Data Format 139 162 mA LVDS Output Data Format (Powerdown) 3.1 4.5 mA CMOS Output Data Format (40 MHz) 137 161 mA LVDS Output Data Format 50 65 mA LVDS Output Data Format (Powerdown) 5.5 8 mA CMOS Output Data Format (ATE Loading of CMOS Outputs > 50 pF) (40 MHz) 48 62 mA Typical sensor outputs: 1 4 mA LVDS Output Data Format 630 736 mW LVDS Output Data Format (Powerdown) 28 32 mW CMOS Output Data Format (ATE Loading of CMOS Outputs > 50pF) (40 MHz) 600 740 mW CDS Gain=1x, PGA Gain=1x 2.3 CDS Gain=2x, PGA Gain= 1x 1.22 Power Supply Specifications IA ID IC VA Analog Supply Current VD Digital Output Driver Supply Current VC CCD Timing Generator Output Driver Supply Current SH1-SH5, PHIA, PHIB, PHIC, RS, CP (ATE Loading of CMOS Outputs > 50pF) PWR Average Power Dissipation Input Sampling Circuit Specifications VIN Input Voltage Level IIN_SH Sample and Hold Mode Source Followers Off Input Leakage Current CDS Gain = 1x 19 (-103) (-95) (-152) (-141) (-250) (-50) Vp-p 25 μA 50 μA 250 nA OSX = VA (OSX = AGND) Source Followers Off CDS Gain = 2x 33 OSX = VA (OSX = AGND) Source Followers On CDS Gain = 2x 20 OSX = VA (OSX = AGND) CSH Sample/Hold Mode CDS Gain = 1x 2.5 pF Equivalent Input Capacitance IIN_CDS RCLPIN CDS Gain = 2x 4 CDS Mode Source Followers Off 10 Input Leakage Current OSX = VA (OSX = AGND) CLPIN Switch Resistance (-250) pF 250 nA 55 Ω (-50) 16 (OSX to VCLP Node) Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 9 LM98722 SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. Parameter Test Conditions Min (1) Typ (2) Max (1) (3) Units VCLP Reference Circuit Specifications VVCLP ISC VCLP Voltage 000 VCLP Voltage Setting = 000 0.85VA V VCLP Voltage 001 VCLP Voltage Setting = 001 0.9VA V VCLP Voltage 010 VCLP Voltage Setting = 010 0.95VA V VCLP Voltage 011 VCLP Voltage Setting = 011 0.6VA V VCLP Voltage 100 VCLP Voltage Setting = 100 0.55VA V VCLP Voltage 101 VCLP Voltage Setting = 101 0.4VA V VCLP Voltage 110 VCLP Voltage Setting = 110 0.35VA V VCLP Voltage 111 VCLP Voltage Setting = 111 0.15VA V VCLP DAC Short Circuit Output Current 0001 xxxxb VCLP Config. Register = 30 mA 10 Bits Black Level Offset DAC Specifications Resolution Monotonicity Ensured by characterization Offset Adjustment Range CDS Gain = 1x Referred to AFE Input Minimum DAC Code = 0x000 -614 Maximum DAC Code = 0x3FF 614 mV CDS Gain = 2x Minimum DAC Code = 0x000 -307 Maximum DAC Code = 0x3FF 307 mV Offset Adjustment Range Minimum DAC Code = 0x000 -17500 -16130 Referred to AFE Output Maximum DAC Code = 0x3FF +16130 +17500 DAC LSB Step Size CDS Gain = 1x 1.2 mV Referred to AFE Output (32) (LSB) LSB DNL Differential Non-Linearity -0.85 +0.74/ -0.37 +2.4 LSB INL Integral Non-Linearity -2.5 +0.72/ -0.56 +2.5 LSB PGA Specifications Gain Resolution 8 Monotonicity Maximum Gain Minimum Gain PGA Function Bits Ensured by characterization CDS Gain = 1x 7.7 8.3 8.8 V/V CDS Gain = 1x 17.7 18.4 18.9 dB CDS Gain = 1x 0.58 0.64 0.70 V/V CDS Gain = 1x -4.7 -4.2 -3.5 dB Gain (V/V) = (180/(277-PGA Code)) Gain (dB) = 20LOG10(180/(277-PGA Code)) Channel Matching Minimum PGA Gain 3 Maximum PGA Gain 12.7 % ADC Specifications VREFT Top of Reference 2.07 V VREFB Bottom of Reference 0.89 V VREFT VREFB Differential Reference Voltage 10 1.06 1.18 Overrange Output Code 65535 Underrange Output Code 0 Submit Documentation Feedback 1.30 V Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 Electrical Characteristics (continued) The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. Parameter Min (1) Test Conditions Typ (2) Max (1) (3) Units Digital Offset “DAC” Specifications Resolution 7 Bits 32 LSB Digital Offset DAC LSB Step Size Referred to AFE Output Offset Adjustment Range Min DAC Code =7b0000000 -2048 Referred to AFE Output Mid DAC Code =7b1000000 0 Max DAC Code = 7b1111111 +2016 LSB Full Channel Performance Specifications DNL INL Differential Non-Linearity Integral Non-Linearity See (4) -0.999 +0.8/-0.7 2.5 LSB See (4) -75 +18/-25 75 LSB 26 LSB RMS Minimum PGA Gain (4) SNR Total Output Noise Channel to Channel Crosstalk (4) -76 dB 10 Maximum PGA Gain (4) -56 dB 96 LSB RMS Mode 3 26 Mode 2 17 LSB This parameter ensured by design and characterization. AC Timing Specifications The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. (1) Parameter Test Conditions Min (2) Typ (3) Max (2) Units Input Clock Timing Specifications fINCLK Input Clock Frequency INCLK = PIXCLK 0.66 15 (Mode 3) (Pixel Rate Clock) 1 22.5 (Mode 2) 1 22.5 (Mode 1) INCLK = ADCCLK (ADC Rate Clock) MHz 45 (Mode 3) 2 45 (Mode 2) MHz 22.5 (Mode 1) Tdc Input Clock Duty Cycle 40/60 50/50 60/40 % Full Channel Latency Specifications 3 Channel Mode Pipeline Delay tLAT3 2 Channel Mode Pipeline Delay tLAT2 (1) (2) (3) PIXPHASE0 24 PIXPHASE1 23 1/2 PIXPHASE2 23 PIXPHASE3 22 1/2 PIXPHASE0 21 PIXPHASE1 20 1/2 PIXPHASE2 20 PIXPHASE3 19 1/2 TADC TADC The analog inputs are protected as shown in Figure 4. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per Note 4 under the Absolute Maximum Ratings Table. However, input errors will be generated If the input goes above VA and below AGND. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level). Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 11 LM98722 SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com AC Timing Specifications (continued) The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.(1) Parameter 1 Channel Mode Pipeline Delay tLAT1 Test Conditions Min (2) Typ (3) PIXPHASE0 19 PIXPHASE1 18 1/2 PIXPHASE2 18 PIXPHASE3 17 1/2 Max (2) Units TADC SH_R Timing Specifications tSHR_S SH_R Setup Time 2 ns tSHR_H SH_R Hold Time 2 ns LVDS Output Timing Specifications TXpp0 TXCLK to Pulse Position 0 LVDS Output -0.46 0 0.46 ns TXpp1 TXCLK to Pulse Position 1 Specifications not 2.71 3.17 3.63 ns TXpp2 TXCLK to Pulse Position 2 tested in production. 5.89 6.35 6.81 ns TXpp3 TXCLK to Pulse Position 3 Min/Max ensured 9.06 9.52 9.98 ns TXpp4 TXCLK to Pulse Position 4 by design, 12.24 12.70 13.16 ns TXpp5 TXCLK to Pulse Position 5 characterization and statistical 15.41 15.87 16.33 ns TXpp6 TXCLK to Pulse Position 6 analysis. 18.59 19.05 19.51 ns 2 6 9 ns 15/22.5/22.5 MHz 45/45/22.5 MHz CMOS Output Timing Specifications fINCLK = 40MHz tCRDO CLKOUT Rising Edge to CMOS Output Data Transition INCLK = ADCCLK (ADC Rate Clock) Serial Interface Timing Specifications fSCLK <= fINCLK INCLK = PIXCLK (Pixel Rate Clock) fSCLK Input Clock Frequency Mode 3/2/1 fSCLK <= fINCLK INCLK = ADCCLK (ADC Rate Clock) Mode 3/2/1 SCLK Duty Cycle 50/50 ns tIH Input Hold Time 1.5 ns tIS Input Setup Time 2.5 ns tSENSC SCLK Start Time After SEN Low 1.5 ns tSCSEN SEN High after last SCLK Rising Edge 2.5 ns tSENW SEN Pulse Width INCLK present 6 TINCLK INCLK stopped (4) (5) 50 ns tOD Output Delay Time tHZ Data Output to High Z (4) (5) 12 11 14 ns 0.5 TSCLK If the input INCLK is divided down to a lower internal clock rate via the PLL, the parameter tSENW will be increased by the same factor. When the Spread Spectrum Clock Generation feature is enabled, tSENW should be increased by 1. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 LM98722 www.ti.com SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 VA I/O To Internal Circuitry AGND Figure 4. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 13 LM98722 SNAS487A – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (April 2013) to Revision A • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM98722 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM98722CCMT/NOPB ACTIVE TSSOP DGG 56 34 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 LM98722CCMT LM98722CCMTX/NOPB ACTIVE TSSOP DGG 56 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 LM98722CCMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM98722CCMTX/NOPB Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.5 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM98722CCMTX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 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