MP28255 21V, 4A, 500kHz Synchronous Step-down Converter The Future of Analog IC Technology DESCRIPTION FEATURES The MP28255 is a high frequency synchronous rectified step-down switch mode converter with built in internal power MOSFETs. It offers a very compact solution to achieve 4A continuous output current over a wide input supply range with excellent load and line regulation. The MP28255 operates at high efficiency over a wide output current load range. • • • • • • • • • • • • • Current mode operation provides fast transient response and eases loop stabilization. Full protection features include OCP and thermal shut down. The MP28255 requires a minimum number of readily available standard external components and is available in a space saving 3mm x 4mm 14-pin QFN package. Wide 4.5V to 21V Operating Input Range 4A Output Current Low RDS(ON) Internal Power MOSFETs Proprietary Switching Loss Reduction Technique Fixed 500kHz Switching Frequency External Soft-Start Sync from 300kHz to 2MHz External Clock Internal Compensation Integrated Bootstrap Diode Over-Current Protection and Hiccup Thermal Shutdown Output Adjustable from 0.8V Available in 14-pin QFN3x4 Package APPLICATIONS • • • • • Networking Systems Digital Set Top Boxes Personal Video Recorders Flat Panel Television and Monitors Distributed Power Systems For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. The information in this datasheet about the product and its associated technologies are proprietary and intellectual property of Monolithic Power Systems and are protected by copyright and pending patent applications TYPICAL APPLICATION 4.5V-21V 1 VIN IN BST 6 C1 22uF PG C4 0.1uF 9 PG R3 100K 11 C3 0.1uF ON/OFF 7 SW L1 2uH 2,3,4,5 1.2V/4A MP28255 VCC FB EN/SYNC SS GND 12,13 Rt 24K 8 10 C5 47nF R1 4.99K C2 47uF R2 10K AGND 14 MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 1 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS ORDERING INFORMATION Part Number* Package Top Marking Free Air Temperature (TA) MP28255EL 3x4 QFN14 28255 -20°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP28255EL–Z). For RoHS compliant packaging, add suffix –LF (e.g. MP28255EL–LF–Z) PACKAGE REFERENCE SS ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VIN ....................................... 22V VSW ..........................-0.3V (-5V for<10ns) to 23V VBS ....................................................... VSW + 6V All Other Pins ..................................-0.3V to +6V Operating Temperature.............. -20°C to +85°C Continuous Power Dissipation (TA = +25°C) (2) ……………………………………………....2.6W Junction Temperature ...............................150°C Lead Temperature ....................................260°C Storage Temperature ............... -65°C to +150°C Recommended Operating Conditions (3) Thermal Resistance (4) θJA θJC 3x4 QFN14 ............................. 48 ...... 11... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. Supply Voltage VIN ........................... 4.5V to 21V Maximum Junction Temp. (TJ) .............. +125°C MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 2 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Typical Values are at TA = 25°C. Parameters Supply Current (Shutdown) Supply Current (Quiescent) HS Switch On Resistance LS Switch On Resistance Symbol IIN Iq HSRDS-ON LSRDS-ON Switch Leakage SWLKG Current Limit (5) Oscillator Frequency Fold-back Frequency Maximum Duty Cycle Sync Frequency Range ILIMIT FSW FFB DMAX FSYNC Feedback Voltage VFB Feedback Current EN Rising Threshold EN Threshold Hysteresis IFB EN Input Current EN Turn Off Delay Power Good Rising Threshold Power Good Falling Threshold Power Good Delay Power Good Sink Current Capability Power Good Leakage Current Soft-start current VIN Under Voltage Lockout Threshold Rising VIN Under Voltage Lockout Threshold Hysteresis VCC Regulator VCC Load Regulation Soft-Start Period Thermal Shutdown Condition VEN = 0V VEN = 2V, VFB = 1V VEN = 0V, VSW = 0V or 12V VFB = 0.75V VFB = 300mV VFB = 700mV 5 425 85 0.3 TA = 25°C 789 -20°C < TA < 85°C VFB = 800mV 787 VEN RISING VEN HYS IEN Min 1 VEN = 2V VEN = 0V ENTd-Off PGVth-Hi PGVth-Lo PGTd VPG IPG LEAK Typ 0 0.7 120 20 Max Units µA mA mΩ mΩ 0 10 µA 5.6 500 0.25 90 805 10 1.3 0.4 2 0 5 0.9 0.7 20 Sink 4mA VPG = 3.3V Vss=0V INUVVth 2 A kHz fSW % MHz 821 mV 823 mV 50 1.6 nA V V µA 575 µs VFB VFB µs 0.4 V 10 nA µA 4.2 V 10 3.8 4.0 INUVHYS 880 mV VCC 5 5 4 150 V % ms °C Icc=5mA CSS=47nF TSD 2 6.5 Note: 5) Guaranteed by design. MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 3 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS PIN FUNCTIONS Pin # Name 1 IN 2,3,4,5 SW 6 BST 7 EN/SYNC 8 FB 9 PG 10, SS 11 VCC 12,13 GND 14 AGND Exposed Pad Description Supply Voltage. The MP28255 operates from a +4.5V to +21V input rail. C1 is needed to decouple the input rail. Use wide PCB traces and multiple vias to make the connection. Switch Output. Use wide PCB traces and multiple vias to make the connection. Bootstrap. A capacitor connected between SW and BS pins is required to form a floating supply across the high-side switch driver. EN=1 to enable the chip. External clock can be applied to EN pin for changing switching frequency. For automatic start-up, connect EN pin to VIN by proper EN resistor divider as Figure 2 shows. Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets the output voltage. To prevent current limit run away during a short circuit fault condition the frequency fold-back comparator lowers the oscillator frequency when the FB voltage is below 500mV. Power Good Output, the output of this pin is open drain. Power good threshold is 90% low to high and 70% high to low of regulation value. Soft-Start control input. SS controls the soft-start period. Connect a capacitor from SS to Gnd to set the soft-start period. Bias Supply. Decouple with 0.1µF~0.22µF cap. And the capacitance should be no more than 0.22µF. System Ground. This pin is the reference ground of the regulated output voltage. For this reason care must be taken in PCB layout. Signal Ground. AGND is not internally connected to System Ground, make sure AGND connected to system Ground in PCB layout. No Internal Connection. It is recommended to connect exposed pad to GND plane for optimal thermal performance. MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 4 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 1.2V, L=1.8uH, TA = +25ºC, unless otherwise noted. Enabled Supply Current vs. Input Voltage Disabled Supply Current vs. Input Voltage 1000 0.2 950 0.15 900 850 0.1 6 5.5 750 0 700 -0.05 650 600 VCC (V) 0.05 800 -0.1 5 10 15 20 25 3.5 0 10 15 20 Current Limit vs. Duty Cycle 4 2 10 DmaxLimit Minimum on time Limit 1 0.1 0 20 40 60 80 100 0 5 DUTY CYCLE (%) 10 15 20 25 INPUT VOLTAGE (V) Line Regulation 10 15 20 25 Load Regulation Operating Range Output Voltage (V) 6 5 INPUT VOLTAGE (V) 100 8 0 0 25 INPUT VOLTAGE (V) INPUT VOLTAGE (V) IPEAK(A) 5 NORMALIZED OUTPUT VOLTAGE(%) 0 4.5 VEN=0V -0.2 500 5 4 -0.15 VFB=1V 550 NORMALIZED OUTPUT VOLTAGE(%) Vcc Regulator Line Regulation 0.5 0.4 0.3 0.2 V IN=21V 0.1 V IN=12V 0 -0.1 V IN=4.5V -0.2 -0.3 -0.4 -0.5 0 1 2 3 4 OUTPUT CURRENT (A) Case Temperature Rise vs. Output Current 0.5 25 0.4 0.3 20 0.2 IO=0A 0.1 15 0 -0.1 -0.2 -0.3 IO=2A 10 IO=4A 5 -0.4 -0.5 0 0 5 10 15 20 INPUT CURRENT (V) 25 0 1 2 3 4 5 OUTPUT CURRENT (A) MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 5 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 1.2V, L=1.8uH, TA = +25ºC, unless otherwise noted. Efficiency vs. Output Current VOUT=1.2V VOUT=1.8V 90 90 80 80 70 V IN=12V V IN=4.5V 60 50 V IN=21V 40 30 Efficiency vs. Output Current VOUT=2.5V 100 90 V IN=12V 70 V IN=21V 60 80 V IN=4.5V EFFICIENCY (%) 100 EFFICIENCY (%) EFFICIENCY (%) 100 Efficiency vs. Output Current 50 40 30 50 40 30 20 20 10 10 10 0 0 1 2 3 4 OUTPUT CURRENT (A) V IN=4.5V V IN=21V 60 20 0 V IN=12V 70 0 0 1 2 3 OUTPUT CURRENT (A) 4 0 1 2 3 4 OUTPUT CURRENT (A) Efficiency vs. Output Current 100 VOUT=3.3V 90 EFFICIENCY (%) 80 V IN=12V 70 V IN=5V V IN=21V 60 50 40 30 20 10 0 0 1 2 3 4 OUTPUT CURRENT (A) MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 6 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 1.2V, L=1.8uH, TA = +25ºC, unless otherwise noted. Short Entry Short Recovery VOUT 1V/div VOUT 1V/div VSW 5V/div VSW 5V/div IINDUCTOR 5A/div IINDUCTOR 5A/div Power Up without Load VOUT 1V/div VSW 5V/div VIN 10V/div IINDUCTOR 5A/div 1ms/div 2ms/div Power Up with 4A Load 2ms/div Enable Startup without Load Enable Startup with 4A Load VOUT 1V/div VOUT 1V/div VOUT 1V/div VSW 5V/div VSW 5V/div VSW 5V/div VIN 10V/div VEN 5V/div VEN 5V/div IINDUCTOR 5A/div IINDUCTOR 5A/div IINDUCTOR 5A/div 2ms/div 2ms/div Input Ripple Voltage Output Ripple Voltage IOUT=4A IOUT=4A VOUT/AC 10mV/div VIN/AC 100mV/div 2ms/div Load Transient Response IOUT=2A-4A VOUT/AC 50mV/div VSW 5V/div VSW 5V/div IINDUCTOR 5A/div IOUT 2A/div MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 7 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS BLOCK DIAGRAM SS Figure 1—Function Block Diagram MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 8 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS OPERATION The MP28255 is a high frequency synchronous rectified step-down switch mode converter with built in internal power MOSFETs. It offers a very compact solution to achieve 4A continuous output current over a wide input supply range with excellent load and line regulation. The MP28255 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 90% of one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off Power Good Indicator When the FB is below 0.7VFB, the PG pin will be internally pulled low. When the FB is above 0.9VFB, the PG becomes an open-drain output. Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases, 0.1uF ceramic capacitor for decoupling purpose is required. Error Amplifier The error amplifier compares the FB pin voltage with the internal FB reference (VFB) and outputs a current proportional to the difference between the two. This output current is then used to charge or discharge the internal compensation network to form the COMP voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Enable/Sync Control EN/Sync is a digital control pin that turns the regulator on and off. Drive EN high to turn on the regulator, drive it low to turn it off. There is an internal 1MEG resistor from EN/Sync to GND thus EN/Sync can be floated to shut down the chip. 1) Enabled by external logic H/L signal The chip starts up once the enable signal goes higher than EN/SYNC input high voltage (2V), and is shut down when the signal is lower than EN/SYNC input low voltage (0.4V). To disable the chip, EN must be pulled low for at least 5µs. The input is compatible with both CMOS and TTL. 2) Enabled by Vin through voltage divider. Connect EN with VIN through a resistive voltage divider for automatic startup as the figure 2 shows. VIN REN1 EN REN2 Figure 2—Enable Divider Circuit Choose the value of the pull-up resistor REN1 and pull-down resistor REN2 to reset the automatic start-up voltage: (REN1 + REN2 || 1MΩ) REN2 || 1MΩ (REN1 + REN2 || 1MΩ) = VEN-FALLING ⋅ REN2 || 1MΩ VIN_START = VEN_RISING ⋅ VIN_STOP Figure 3—Startup Sequence Using EN Divider 3) Synchronized by External Sync Clock Signal The chip can be synchronized to external clock range from 300kHz up to 2MHz through this pin 2ms right after output voltage is set, with the internal clock rising edge synchronized to the external clock rising edge. MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 9 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS hiccup mode once the over current condition is removed. Figure 4—Startup Sequence Using External Sync Clock Signal Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP28255 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 4.0V while its falling threshold is a consistent 3.2V. External Soft-Start The soft-start is implemented to prevent the converter output voltage from overshooting during startup. When the chip starts, the internal circuitry generates a soft-start voltage (SS) ramping up from 0V to 1.2V. When it is lower than the internal FB reference (REF), SS overrides REF so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. The SS time can be set by external decoupled cap. The soft-start time can be caculated as below: t ss (ms) = Vref(V) × C5 (nF ) 10µA To reduce the susceptibility to noise, do not leave SS pin open. Use a capacitor with small value if you do not need soft function. Over-Current-Protection and Hiccup The MP28255 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. Meanwhile, output voltage starts to drop until FB is below the Under-Voltage (UV) threshold, typically 30% below the reference. Once a UV is triggered, the MP28255 enters hiccup mode to periodically restart the part. This protection mode is especially useful when the output is dead-short to ground. The average short circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. The MP28255 exits the Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, it shuts down the whole chip. When the temperature is lower than its lower threshold, typically 140°C, the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN through D1, M3, C4, L1 and C2 (Figure 5). If (VIN-VSW) is more than 5V, U2 will regulate M3 to maintain a 5V BST voltage across C4. SW Figure 5—Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. Three events can shut down the chip: EN low, VIN low and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 10 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS APPLICATION INFORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see Typical Application on page 1). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Typical Application on page 1). Choose R1 to be around 40.2kΩ for optimal transient response. R2 is then given by: R2 = R1 VOUT −1 VFB The T-type network is highly recommended when Vo is low, as Figure 6 shows. FB R1 Rt 1 VOUT R2 Figure 6— T-type Network Table 1 lists the recommended T-type resistors value for common output voltages. Table 1—Resistor Selection for Common Output Voltages VOUT (V) 1.05 1.2 1.5 1.8 2.5 3.3 5 R1 (kΩ) 4.99 4.99 4.99 4.99 40.2 40.2 40.2 R2 (kΩ) 16.5 10.2 5.76 4.02 19.1 13 7.68 Rt (kΩ) 24.9 24.9 24.9 24.9 0 0 0 L (uH) 1-4.7 1-4.7 1-4.7 1-4.7 1-4.7 1-4.7 1-4.7 COUT (uF, Ceramic) 47 47 47 47 47 47 47 Note: The above feedback resistor table applies to a specific load capacitor condition as shown in the table 1. Other capacitive loading conditions will require different values. Selecting the Inductor A 1µH to 10µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 15mΩ. For most designs, the inductance value can be derived from the following equation. L= Where ∆IL is the inductor ripple current. Choose inductor ripple current to be approximately 30% if the maximum load current, 4A. The maximum inductor peak current is: IL(MAX ) = ILOAD + ∆I L 2 Under light load conditions below 100mA, larger inductance is recommended for improved efficiency. Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 22µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: I C1 = ILOAD × VOUT ⎛⎜ VOUT × 1− VIN ⎜⎝ VIN ⎞ ⎟ ⎟ ⎠ The worse case condition occurs at VIN = 2VOUT, where: IC1 = ILOAD 2 For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum or ceramic. When electrolytic or tantalum capacitor is used, a small, high quality ceramic capacitor, i.e. 0.1µF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to VOUT × ( VIN − VOUT ) VIN × ∆IL × f OSC MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 11 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ∆VIN = ⎛ V ILOAD V × OUT × ⎜⎜ 1 − OUT VIN fS × C1 VIN ⎝ ⎞ ⎟⎟ ⎠ Selecting the Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: ∆VOUT = VOUT ⎛ V × ⎜⎜1 − OUT fS × L ⎝ VIN 3) 4) 5) 6) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. Route SW away from sensitive analog areas such as FB. Connect IN, SW, and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. Adding RC snubber circuit from IN pin to SW pin can reduce SW spikes. ⎞ ⎞ ⎛ 1 ⎟ ⎟⎟ × ⎜ R ESR + ⎜ 8 × f S × C2 ⎟⎠ ⎠ ⎝ Where L is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ∆VOUT = ⎛ ⎞ V × ⎜⎜1 − OUT ⎟⎟ VIN ⎠ × L × C2 ⎝ VOUT 8 × fS 2 Top Layer In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ∆VOUT = V VOUT ⎛ × ⎜⎜1 − OUT fS × L ⎝ VIN ⎞ ⎟⎟ × R ESR ⎠ The characteristics of the output capacitor also affect the stability of the regulation system. The MP28255 can be optimized for a wide range of capacitance and ESR values.. The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. PCB Layout PCB layout is very important to achieve stable operation. Please follow these guidelines and take Figure 7 for references. 1) 2) Keep the connection of input ground and GND pin as short and wide as possible. Keep the connection of input capacitor and IN pin as short and wide as possible. Bottom Layer Figure 7—PCB Layout External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external BST diode is: MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 12 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS z Duty cycle is high: D= VOUT >65% VIN In this case, an external BST diode is recommended from the VCC pin to BST pin, as shown in Figure 8 MP28255 Figure 8—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 13 MP28255 – 4A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS PACKAGE INFORMATION 3mm x 4mm QFN14 2.90 3.10 1.60 1.80 0.30 0.50 PIN 1 ID SEE DETAIL A PIN 1 ID MARKING 1 14 0.18 0.30 3.20 3.40 3.90 4.10 PIN 1 ID INDEX AREA 0.50 BSC 7 8 TOP VIEW BOTTOM VIEW 0.80 1.00 0.20 REF PIN 1 ID OPTION A 0.30x45º TYP. PIN 1 ID OPTION B R0.20 TYP. 0.00 0.05 SIDE VIEW DETAIL A 2.90 0.70 NOTE: 1.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VGED-3. 5) DRAWING IS NOT TO SCALE. 0.25 3.30 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP28255 Rev. 1.01 www.MonolithicPower.com 3/11/2011 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 14