EM78451 8-Bit Microcontroller Product Specification DOC. VERSION 1.2 ELAN MICROELECTRONICS CORP. May 2004 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Elan Information Technology Group Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220 Europe: Shenzhen: Shanghai: Elan Microelectronics Corp. (Europe) Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai Corporation, Ltd. Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600 Contents Contents 1 2 3 4 GENERAL DESCRIPTION................................................................................................... 1 FEATURES........................................................................................................................... 1 PIN ASSIGNMENT ............................................................................................................... 2 FUNCTION DESCRIPTION.................................................................................................. 3 4.1 Operational Registers .................................................................................................. 4 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 4.2 R0 (Indirect Address Register) ...................................................................................... 4 R1 (TCC) ....................................................................................................................... 4 R2 (Program Counter) & Stack...................................................................................... 4 R3 (Status Register) ...................................................................................................... 5 R4 (RAM Select Register) ............................................................................................. 6 R5~R8 (Port 5 ~ Port8).................................................................................................. 6 R9 (Port9) ...................................................................................................................... 6 RA (SPIRB: SPI Read Buffer)........................................................................................ 8 RB (SPIWB: SPI Write Buffer)....................................................................................... 8 RC (SPIS: SPI Status Register) .................................................................................... 8 RD (SPIC: SPI Control Register)................................................................................... 8 RE (TMR1: Timer1 register) .......................................................................................... 9 RF (PWP: Pulse width preset register)........................................................................ 10 R20~R3E (General Purpose Register)........................................................................ 10 R3F (Interrupt Status Register) ................................................................................... 10 Special Purpose Registers ......................................................................................... 10 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 A (Accumulator) ........................................................................................................... 10 CONT (Control Register) ............................................................................................. 10 IOC5 ~ IOC9 (I/O Port Control Register)......................................................................11 IOCC (T1CON: Timer1 control register) .......................................................................11 IOCD (Pull-high Control Register) ............................................................................... 12 IOCE (WDT Control Register) ..................................................................................... 12 IOCF (Interrupt Mask Register) ................................................................................... 13 4.3 TCC/WDT Presacler .................................................................................................. 15 4.4 I/O Ports ..................................................................................................................... 15 4.5 SERIAL PERIPHERAL INTERFACE MODE.............................................................. 17 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.6 Overview & Features ................................................................................................... 17 SPI Function Description ............................................................................................. 19 SPI Signal & Pin Description ....................................................................................... 21 Programming the related registers .............................................................................. 22 SPI Mode Timing ......................................................................................................... 25 Software Application of SPI ......................................................................................... 26 Timer 1 ....................................................................................................................... 30 4.6.1 4.6.2 Overview...................................................................................................................... 30 Function description .................................................................................................... 30 Product Specification (V1.2) 05.27.2004 • iii Contents 4.6.3 Programmed the related registers............................................................................... 31 4.7 RESET and Wake-up ................................................................................................. 32 4.8 Interrupt...................................................................................................................... 37 4.9 Oscillator .................................................................................................................... 38 4.9.1 4.9.2 4.9.3 Oscillator Modes.......................................................................................................... 38 Crystal Oscillator/Ceramic Resonators (XTAL) ........................................................... 39 RC Oscillator Mode ..................................................................................................... 40 4.10 Code Option Register................................................................................................. 42 4.11 Instruction Set ............................................................................................................ 43 5 6 4.12 Timing Diagrams ........................................................................................................ 46 ABSOLUTE MAXIMUM RATING ....................................................................................... 47 ELECTRICAL CHARACTERISTICS.................................................................................. 47 6.1 7 DC Characteristic ....................................................................................................... 47 6.2 AC Characteristic ....................................................................................................... 48 APPLICATION CIRCUIT .................................................................................................... 49 APPENDIX A Package Types: ................................................................................................................. 50 Specification Revision History Doc. Version iv • Revision Description Date 1.0 Initial version 1.1 Change Power on reset content 06/30/2003 1.2 Cancel Code Option LVDD 05/27/2004 Product Specification (V1.2) 05.27.2004 EM78451 8-Bit Microcontroller 1 GENERAL DESCRIPTION The EM78451 is an 8-bit microprocessor designed and developed with low-power and high speed CMOS technology. Its operation kernel is implemented with RISC-like architecture, and it is available in the mask ROM version. This device is also equipped with the Serial Peripheral Interface (SPI) function and an easy-implemented RS-232. The EM78451 is extremely suitable for wired communication. In fact, there are only fifty-eight (58) easy-to-learn instructions required plus the user’s program can be emulated with the EMC In-Circuit Emulator (ICE). 2 FEATURES Operating voltage ranges between: 2.3V~5.5V. Operating temperature ranges between: 0°C~70°C. Operating frequency ranges between (based on 2 clocks): • • 1Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V. Low power consumption: • • Less then 3 mA at 5V/4MHz Typically 10 µA during sleep mode (SPI) Serial Peripheral Interface is also available. 4K × 13 bits on chip ROM (EM78451). 11 Special function registers. 140× 8 bits On- chip general-purpose registers. 5 Bi-directional I/O ports (35 I/O pins). 3 LED Direct sinking pins with internal serial resistors. Built-in RC oscillator with external serial resistor, ±10% variation. Built-in power-on reset. Five stacks designed for subroutine nesting. 8-bit Real time clock/counter (TCC) with overflow interrupt. Two to four machine -clocks for each instruction cycle. Power down mode. I/O ports have a Programmable wake-up function from sleep circuit. Programmable free running on-chip watchdog timer. 12 Wake-up pins. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) •1 EM78451 8-Bit Microcontroller 2 Open-drain pins. 2 R-option pins. 32 Programmable pull-high input pins. Package types: • • 40 pin DIP 600mil : EM78451AP. 44 pin QFP: EM78451AQ. Four types of interrupts. • • • • SPI transmission completed interrupt. TCC overflow interrupt. Timer1 comparator match interrupt. PIN ASSIGNMENT V S S 1 40 IN T 2 39 R -O S C I D A T A 3 38 V D D C L K 4 37 P 90 5 36 P 71 P 91 26 P 87 P 55 16 25 P 86 P 56 17 24 P 85 P 57 18 23 P 84 P 80 19 22 P 83 P 81 20 21 P 82 NC NC P70 35 34 38 NC VDD 39 36 R-OSCI 40 37 VSS OSCO 41 DATA INT 42 CLK 24 23 22 15 11 21 P 54 25 10 P86 P 60 26 9 P85 27 27 8 20 14 P 61 28 7 P84 P 53 28 29 EM 78451A Q 6 19 13 P 62 30 5 P83 P 52 29 4 18 12 P 63 17 P 51 P 64 30 P82 11 P 65 31 31 NC P 50 32 32 3 16 10 33 2 15 9 S S /P 9 5 1 P81 S C K /P 9 4 P 90 P 91 S D I/ P 9 2 S D O /P 9 3 S C K /P 9 4 S S /P 9 5 P 50 P 51 P 52 P 53 P 54 P80 P 66 14 33 P57 8 13 P 67 S D O /P 9 3 12 P 72 34 P55 35 7 P56 6 43 P 70 44 O S C O S D I/P 9 2 EM78451AP/W M 3 External interrupt (/INT). P71 P72 P67 P66 P65 P64 P63 P62 P61 P60 P87 Fig. 1 Pin assignment Table 1 Pin description Symbol Pin No. Type R-OSCI 39 I OSCO 40 O P90~P95 5~10 I/O P80~P87 19~26 I/O P70~P72 37~35 I/O CLK 4 I/O 2• Function Description In XTAL mode: Crystal input; In internal C, external R mode: 56K ohm±5% pull high for 1.8432MHz. In XTAL mode: Crystal output; In RC mode: Instruction clock output. General bi-directional I/O port. All of its pins can be pulled-high by software. P90 and P91 are pin-change wake-up pins. General bi-directional I/O port. All of its pins can be pulled-high by software. P80 and P81 are also used as the R-option pins. LED direct-driving pin with internal serial resistor is used as output and is software defined. By connecting P74 and P76 together. P74 can be pulled-high by software and it is also a pin-change wake-up pin. P76 can be defined as an open-drain output. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller Symbol Pin No. Type DATA 3 I/O By connecting P75 and P77 together, P75 can be pulled-high by software and it is also a pin-change wake-up pin. P77 can be defined as an open-drain output. P60~P67 27~34 I/O General bi-directional port. All of its pins can be pulled-high by software, and pin-change wake-up pins. P50~P57 11~18 I/O VDD VSS 38 1 - /INT 2 I SDI SDO SCK /SS 7 8 9 10 I/O I/O I/O I/O 4 Function Description General bi-directional I/O port. All of its pins can be pulled-high * * by software. Power supply pin. Ground pin. An interrupt schmitt-triggered pin. The function of interrupt triggers at the falling edge. Users can enable it by software. The internal pull-up resistor is around 50K ohm. Serial data in for SPI Serial data out for SPI. Serial clock for SPI. /Slave select for SPI. FUNCTION DESCRIPTION W DT Tim er W DT Tim e-out PC STACK 1 STACK 2 Prescaler STACK 3 O scillator/ Tim m ing Control / INT STACK 4 ROM STACK 5 Interrupt Control R1(TCC) Sleep & W ake Up Control Instruction Register ALU Instruction Decoder RAM R3 ACC TM R1 R4 DAT A & CONT ROL BUS IOC5 R5 IOC6 R6 IOC7 R7 PPPPPPPP 55555555 01234567 PPPPPPPP 66666666 01234567 P 7 0 P 7 1 IOC8 R8 P 7 2 PPPPPPPP 88888888 01234567 IOC9 R9 P PP P 9 9 9 9 0 1 2 3 / / S S DD I O P 9 4 / S C K SPI ENG IN P 5 5 / / S S Fig. 2 Functional Block Diagram Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) •3 EM78451 8-Bit Microcontroller 4.1 Operational Registers 4.1.1 R0 (Indirect Address Register) R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). 4.1.2 R1 (TCC) It is increased by the instruction cycle clock. Written and read by program as any other register. 4.1.3 R2 (Program Counter) & Stack R2 and the hardware stacks are 12 bits wide. The structure is depicted in Fig. 3. Generates 4K × 13 on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. All the R2 bits are set to "1"s as RESET condition occurs. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows it to jump to any location on one page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the ninth and tenth bits (A8~A9) of PC are cleared. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and tenth bits of PC are cleared. Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",⋅⋅⋅⋅⋅) (except "TBL") will cause the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is limited to the first 256 locations of any program page. "TBL" allows a relative address to be added to the current PC (R2+A→R2), and contents of the ninth and tenth bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or third, 4th) 256th locations on one program page. 4• Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller In the case of EM78451, the most significant bit (A10,A11) will be loaded with the content of bit PS0 ~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions which writes to R2. All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle. CALL PC A11A10 A9A8 00 000 3FF 01 400 7FF A7 Stack 1 ~ A0 RET Stack 2 RETL Stack 3 RETI Stack 4 Stack 5 Page 0 001:Hareware interrupt location 002:Software interrupt (INT instruction) location Page 1 FFF:Reset location 10 800 BFF 11 C00 FFF Page 2 Page 3 Fig. 3 Program counter organization 4.1.4 R3 (Status Register) 7 6 5 4 3 2 1 0 GP PS1 PS0 T P Z DC C Bit 0 (C) Carry flag Bit 1 (DC) Auxiliary carry flag Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and the "WDTC" commands, or during power up and reset to 0 with WDT timeout. Bits 5 (PS0) ~ 6 (PS1) Page select bits. PS0~PS1 are used to pre-select a program memory page. When executing a "JMP", "CALL", or other instructions which causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be the page from where the subroutine was called, regardless of the current settings of PS0~PS1 bits. PS1 bit is not used (read as "0") and cannot be modified in EM78451. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) •5 EM78451 8-Bit Microcontroller PS1 PS0 Program memory page [Address] 0 0 1 1 0 1 0 1 Page 0 [000-3FF] Page 1 [400-7FF] Page 2 [800-BFF] Page 3 [C00-FFF] Bit 7 (GP) General read/write bit. 4.1.5 R4 (RAM Select Register) Bits 0~5 are used to select the registers (address: 00~3F) in the indirect addressing mode. Bits 6~7 determines which bank is activated among the 4 banks. If indirect addressing is not used, the RSR is used as an 8-bit general-purpose read/writer register. See the configuration of the data memory in Fig. 4. 4.1.6 R5~R8 (Port 5 ~ Port8) Four general 8 bits I/O registers Both P74 and P76 read or write data from the DATA pin, while both P75 and P77 read or write data from the CLK pin. 4.1.7 R9 (Port9) General 6-bit I/O registers. The values of the two most significant bits are read as "0". 6• Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller 00 R0 01 R1 (TCC) 02 R2 (PC) STACK 0 03 R3 (Status) STACK 1 04 R4 (RSR) STACK 2 05 R5 (Port 5) STACK 3 IOC5 06 R6 (Port 6) STACK 4 IOC6 07 R7 (Port 7) IOC7 08 R8 (Port 8) IOC8 09 R9 (Port 9) IOC9 0A RA 0B RB 0C RC IOCC 0D RD IOCD 0E RE IOCE 0F RF IOCF 10 11 16x8 Common Register 1E 1F 00 01 10 11 20 21 31x8 Bank Register 31x8 Bank Register 31x8 Bank Register 31x8 Bank Register (Bank 0) (Bank 1) (Bank 2) (Bank 3) 3E 3F R3F Fig. 4 Data Memory Configuration Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) •7 EM78451 8-Bit Microcontroller 4.1.8 RA (SPIRB: SPI Read Buffer) Address 0X0A Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIRB/RA SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0 SRB7~SRB0 are the 8-bit data when transmission is completed by SPI. 4.1.9 RB (SPIWB: SPI Write Buffer) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0B SPIWB/RB SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0 SWB7~SWB0 are the 8-bit data that is waiting for transmission by SPI. 4.1.10 RC (SPIS: SPI Status Register) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0C SPIS/RC -- -- -- TM1IF OD3 OD4 RBFIF RBF TM1IF (bit 4): 1 = In timer1 mode, receiving completed, and an interrupt occurs if enabled. 0 = In timer1 mode, receiving not completed, and an interrupt does not occur. OD3 (bit 3):Open Drain Control bit 1 = Open-Drain enable for SDO, 0 = Open-Drain disable for SDO. OD4 (bit 2):Open-Drain Control bit 1 = Open-Drain enable for SCK, 0 = Open-Drain disable for SCK. RBFIF (bit 1): Read Buffer Full Interrupt flag 1 = Receiving completed, SPIRB is fully exchanged, and an interrupt occur if enable. 0 = Receiving not completed; SPIRB has not fully exchanged. RBF (bit 0):Read Buffer Full flag 1 = Receiving completed; SPIRB is fully exchanged. 0 = Receiving not completed; and SPIRB has not fully exchanged. 4.1.11 RD (SPIC: SPI Control Register) 8• Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x0D SPIC/RD CES SPIE SRO SSE - Bit 2 Bit 1 Bit 0 SBRS2 SBRS1 SBRS0 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller CES (bit 7): Clock Edge Select bit 1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during high level. 0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during low level. SPIE (bit 6): SPI Enable bit 1= Enable SPI mode 0= Disable SPI mode SRO (bit 5): SPI Read Overflow bit 1 = A new data is received while the previous data is still being held in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users are required to read the SPIRB registers although only the transmission has been implemented. 0 = No overflow. NOTE This can only occur in slave mode. SSE (bit 4): SPI Shift Enable bit 1 = Start to shift, and keep on 1 while the current byte is still being transmitted. 0 = Reset as soon as the shifting is complete, and the next byte is ready to shift. NOTE This bit will reset to 0 at every one-byte transmission by the hardware SBRS (bit 2~bit 0): SPI Baud Rate Select bits SPI baud rate table is illustrated in the SPI section of this specification. 4.1.12 RE (TMR1: Timer1 register) Address 0X0E Name Bit 7 Bit 6 TMR1/RE TMR17 TMR16 Bit 5 Bit 4 TMR15 TMR14 Bit 3 Bit 2 TMR13 TMR12 Bit 1 Bit 0 TMR11 TMR10 TMR17~TMR10 is bit sets of timer1 register and it increases until the value matches PWP and then it resets to 0. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) •9 EM78451 8-Bit Microcontroller 4.1.13 RF (PWP: Pulse width preset register) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0F PWP/RF PWP7 PWP6 PWP5 PWP4 PWP3 PWP2 PWP1 PWP0 PWP7~PWP0 are the bit sets of pulse width preset in advance for the desired baud clock width. 4.1.14 R20~R3E (General Purpose Register) RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers. 4.1.15 R3F (Interrupt Status Register) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3F ISR/R3F - - - - TM1IF SPIIF EXIF TCIF Bit 0 (TCIF) TCC timer overflow interrupt flag. Set as TCC overflow; flag cleared by software. Bit 1 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software Bit 2 (SPIIF) SPI interrupt flag. Set by completion of data transmission, flag cleared by software. Bit 3 (TM1IF) Timer1 interrupt flag. Set by the comparator at Timer1 application, flag cleared by software. Bits 2~7 are not used and read as “0”. "1" means interrupt request, "0" means non-interrupt. R3F can be cleared by instruction, but cannot be set by instruction. IOCF is the interrupt mask register. Note that to read R3F will result of "logic AND" of R3F and IOCF. 4.2 Special Purpose Registers 4.2.1 A (Accumulator) Internal data transfer, or instruction operand holding. A non-addressable register. 4.2.2 10 • CONT (Control Register) 7 6 5 4 3 2 1 0 /PHEN /INT - - PAB PSR2 PSR1 PSR0 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller Bit 7 (/PHEN) I/O pin pull-high enable flag. 0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled. 1: The pull-high function is disabled. Bit 6 (INT) An interrupt enable flag cannot be written by the CONTW instruction. 0: interrupt masked by the DISI instruction. 1: interrupt enabled by the ENI or RETI instruction. Bit4, 5 Not used, and to be read as “0”. Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits. PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 0 0 1 1:2 1:4 1:1 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 Bits 0~3, and 7 of the CONT register are readable and writable. 4.2.3 IOC5 ~ IOC9 (I/O Port Control Register) "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output. Both P74 and P76 should not be defined as output pins at the same time; this also applies to both P75 and P77. Only the lower 6 bits of the IOC9 register are used. 4.2.4 IOCC (T1CON: Timer1 control register) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x0C T1CON/IOCC 0 0 0 0 0 Bit 2 Bit 1 Bit 0 TM1E TM1P1 TM1P0 TM1E (bit2): Timer1 Function Enable bit 1 = Enable timer1 function. 0 = Disable timer1 function as default. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 11 EM78451 8-Bit Microcontroller TM1P (bit1~bit0): Timer1 Prescaler bit Refer to the Timer1 prescaler table for FOSC illustration under the section “Timer1” on the subsequent pages. 4.2.5 IOCD (Pull-high Control Register) 7 6 5 4 3 2 1 0 S7 - - - /PU9 /PU8 /PU6 /PU5 The default values of /PU5, /PU6, /PU8, and /PU9 are “1” which means the pull-high function is disabled. /PU6 and /PU9 are “AND” gating with /PHEN, that is, when each one is written as“0,” pull high is enabled. S7 defines the driving ability of the P70-P72. 0: Normal output. 1: Enhance the driving ability of LED. 4.2.6 IOCE (WDT Control Register) 7 6 5 4 3 2 1 0 - ODE WDTE SLPC ROC - - /WUE Bit 0 (/WUE) This control bit is used to enable the wake-up function of P60~P67, P74~P75, and P90~P91. 0: Enable the wake-up function. 1: Disable the wake-up function. The /WUE bit can be read and written. Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins (P80, P81) to be read by the controller. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P81 pin or/and P80 pin to VSS by a 560KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P80 (P81) will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written. Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator stops, and the controller enters the LEEP2 mode) on the high-to-low transition and is enabled (the controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay of approximately 18 ms (oscillator start-up timer (OST)) before the next program instruction is executed. The OST is 12 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller always activated by wake-up from sleep mode whether the Code Option bit ENWDT is "0" or not. After waking up, the WDT is enabled if Code Option ENWDT is "1". The block diagram of SLEEP2 mode and wake-up caused by input triggered is depicted in Fig. 5. The SLPC bit can be read and written. Bit 5 (WDTE) Control bit used to enable Watchdog timer. The WDTE bit can be used only if ENWDT, the CODE Option bit, is "1". If the ENWDT bit is "1", then WDT can be disabled/enabled by the WDTE bit. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "0". That is, if the ENWDT bit is "0", WDT is always disabled regardless of what the WDTE bit is. The WDTE bit can be read and written. Bit 6 (ODE) Open-drain control bit. 0: Both P76 and P77 are normally I/O pins. 1: Both P76 and P77 pins have the open-drain function inside. The ODE bit can be read and written. Bits 1~2, and 7 Not used. 4.2.7 IOCF (Interrupt Mask Register) 7 6 5 4 3 2 1 0 - - - - TM1IE SPIIE EXIE TCIE Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt Bit 1 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt Bit 2 (SPIIE) SPI interrupt enable bit. 0: disable SPI interrupt 1: enable SPI interrupt Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 13 EM78451 8-Bit Microcontroller Bit 3 (TM1IE) TM1IE interrupt enable bit. 0: disable TM1IE interrupt 1: enable TM1IE interrupt Bits 4~7 Not used. Individual interrupt is enabled by setting its associated control bit in IOCF to "1". The IOCF Register could be read and written. /WUE Oscillator Enable Disable /WUE Reset Q Q Clear P D R CLK C L VCC Set 8 /WUE from S/W P60~P67 VCC /WUE /PHEN 4 P74~P75, P90~P91 Fig. 5 Block Diagram of Sleep Mode and Wake-up Circuits on I/O Ports 14 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller 4.3 TCC/WDT Presacler An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT at any given time, and the PAB bit of CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the prescale ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the WDTC or SLEP instructions. Fig. 6 depicts the circuit diagram of TCC/WDT. R1(TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction cycle (without the prescaler). The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during the normal mode by software programming (if Code Option bit ENWDT is "1"). Refer to WDTE bit of IOCE register. Without presacler, the WDT time-out period is approximately 18 ms1. 4.4 I/O Ports The I/O registers, from Port 5 to Port 9, are bi-directional tri-state I/O ports. P60~P67, P74~P75, and P90~P91 provide the internal pull-high. P60~P67, P74~P75, and P90~P95 provide programmable wake-up function through software. P76~P77 can have an open-drain output by software control. P80~P81 are the R-option pins which are enabled by software. When the R-option function is used, it is recommended that P80 and P81 should be used as output pins. During the R-option enabled state, P80 and P81 must be programmed as input pins. If an external resistor is connected to P80 (P81) for the R-option function, the current consumption, if necessary, should be taken as an important factor in the applications for low power consideration. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC5~IOC9) under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig. 7. Note that the reading path source of input and output pins is different when reading the I/O port. 1 NOTE: Vdd = 5V, set up time period = 16.2ms ± 5% Vdd = 3V, set up time period = 18.0ms ± 5% Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 15 EM78451 8-Bit Microcontroller Data Bus CLK(=Fosc/2) 1 M U X SYNC TCC(R1) 2 cycles 0 TCC overflow interrupt PAB 0 W DT 1 M U X 8- bit Counter PSR0~PSR2 8 - to - 1 MUX 0 W DTE 1 PAB MUX (in IOCE) W DT tim eout Fig. 6 Block Diagram of TCC WDT PCRD Q PORT 0 1 M U X P R D CLK Q C L Q P R Q C CLK L PCW R IOD D PDW R PDRD Fig. 7 (a) The Circuit of I/O Port and I/O Control Register 16 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller PCRD VCC ROC P D R CLK Q C L Q Weakly Pull-up P R D C CLK Q L PCWR IOD Q PORT 0 Rex* 1 M U X PDWR PDRD *The Rex is 560K ohm external resistor Fig. 7 (b) The Circuit of I/O Port with R-option (P80, P81) 4.5 SERIAL PERIPHERAL INTERFACE MODE 4.5.1 Overview & Features Overview: Figure 8, 9, and 10 shows how the EM78451 communicates with other devices through the SPI module. If EM78451 is a master controller, it sends clock through the SCK pin. A couple of 8-bit data are transmitted and received at the same time. However, if EM78451 is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted based on both the clock rate and the selected edge. Features: Operation in either Master mode or Slave mode, Three-wire or four-wire synchronous communication; that is, full duplex Programmable baud rates of communication, Programming clock polarity, (RD bit7) Interrupt flag available for the read buffer full, Up to 8 MHz (maximum) bit frequency, Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 17 EM78451 8-Bit Microcontroller SDO SPIR Reg SPIW SPIW Reg Reg /SS SPIS Reg SDI SPI Module Bit 7 Master Device SCK Slave Device Fig. 8 SPI Master/Slave Communication SDI SDO SCK /SS Vdd Master P50 P51 P52 P53 SDO SDI SCK /SS SDO SDI SCK /SS SDO SDI SCK /SS SDO SDI SCK /SS Slave Device 1 Slave Device 2 Slave Device 3 Slave Device 4 Fig. 9 The SPI Configuration of Single-Master and Multi-Slave 18 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller SDI SDO SCK /S S M aster1 or S lave1 SDI SDO SCK /S S M aster2 or P 50 S lave6 P 51 P 50 P 51 P 52 P 53 P 52 P 53 S lave 4 for M aster1/2 SDO SDI SCK /SS SDO SDI SCK /SS SDO SDI SCK /SS SDO SDI SCK /SS S lave 3 for M aster 1/2 S lave 2 for m aster 1 S lave 5 for M aster 2 Fig. 10 The SPI Configuration of Single-Master and Multi-Slave 4.5.2 SPI Function Description Read RBF RBFI Write SPIR SE reg SPIW reg Set to 1 Buffer Full Detector SPIS P92/SDI shift right reg bit 0 bit 7 SPIC reg P93/SDO Edge Select SBR0 ~SBR2 P95/ /SS / SS Tsco SBR2~SBR0 8 Noise Filter Clock Select 2 Prescaler 4, 8, 16, 32, 64 Edge Select P94/SCK TMR1/2 SPIC bit6 Fig. 11 SPI Block Diagram Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 19 EM78451 8-Bit Microcontroller SPI SPI Read Register (0X0A) 7~0 SPIWB /SS SPI Write Register (0X0B) 8-1 MUX SPI Mode Select Register 2 1 0 SPIC SDO SDI Shift Clock SPI Shift Buffer FOSC 1 0 7 6 4 1 0 T1CON SPIC SPIS 2 4 INTC SPIC 7~0 SPIRB DATA BUS Fig. 12 The Function Block Diagram of SPI Transmission The following describes the function of each block and explains how to carry out the SPI communication with the signals depicted in Fig.11 and Fig.12: P92/SDI:Serial Data In. P93/SDO:Serial Data Out. P94/SCK: Serial Clock. P95//SS:/Slave Select (Option). This pin (/SS) may be required during a slave mode. RBF: Set by Buffer Full Detector, and reset in software. RBIF:Set by Buffer Full Detector, and reset in software. Buffer Full Detector: Sets to 1, when an 8-bit shifting is completed. SSE:Loads the data in SPIS register, and begin to shift SPIS reg.:Shifting byte in and out. The MSB is shifted first. Both the SPIS and SPIW registers are loaded at the same time. Once the data are written, SPIS starts with the transmission / reception. The data received will be moved to the SPIR register, as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the RBFI (Read Buffer Full Interrupt) flag are then set. SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is completed. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register reads. SPIW reg.:Write buffer. The buffer will deny any attempt to write until the 8-bit shifting is completed. 20 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller The SSE bit will be kept in 1 if the communication is still undergoing. This flag must be cleared as the shifting is completed. Users can determine if the next write attempt is available. SBRS2~SBRS0: Programming the clock frequency/rates and sources. Clock Select:Selecting either the internal or the external clock as the shifting clock. Edge Select:Selecting the appropriate clock edges by programming the CES bit 4.5.3 SPI Signal & Pin Description The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in Fig. 9, are as follows: SDI/P92 (Pin 7): Serial Data In, Receive sequentially, the Most Significant Bit (MSB) first, the Least Significant Bit (LSB) last, Defined as high-impedance, if not selected, Program the same clock rate and clock edge to latch on both the master and slave devices, The byte received will update the transmitted byte, Both the RBF and the RBFIF bits (located in Register 0x0C) will be set as the SPI operation is completed. Timing is shown in Fig.13 and Fig. 14. SDO/P93 (Pin 8): Serial Data Out, Transmit sequentially; the Most Significant Bit (MSB) first, the Least Significant Bit (LSB) last, Program the same clock rate and clock edge to latch on both the master and slave devices, The byte received will update the transmitted byte, The CES (located in Register 0x0D) bit will be reset, as the SPI operation is completed. Timing is shown in Fig.13 and 14. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 21 EM78451 8-Bit Microcontroller SCK/P94 (Pin 9): Serial Clock Generated by a master device Synchronize the data communication on both the SDI and SDO pins The CES (located in Register 0x0D) is used to select the edge to communicate The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of communication The CES, SBR0, SBR1, and SBR2 bit have no effect in the slave mode Timing is show in Fig.13 and 14 /SS/P95 (Pin 10): Slave Select; negative logic, Generated by a master device to signify the slave(s) to receive data, Goes low before the first cycle of SCK appears and remains low until the last (eighth) cycle is completed, Ignores the data on the SDI and SDO pins when /SS is high, because the SDO is no longer driven. Timing is shown in Fig.13 and Fig. 14. 4.5.4 Programming the related registers The related registers for defining SPI mode are shown in Table 2 and 3. Table 2 Related Control Registers of the SPI Mode Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0D *SPIC/RD CES SPIE SRO SSE -- SBR2 SBR1 SBR0 0x0F INTC/IOCF -- -- -- -- TM1IE SPIIE EXIE TCIE SPIC: SPI Control Register. CES (bit 7): Clock Edge Select bit 1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level. 0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level. SPIE (bit 6): SPI Enable bit 1 = Enable SPI mode 0 = Disable SPI mode 22 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller SRO (bit 5): SPI Read Overflow bit 1 = A new data is received while the previous data is still being on hold in the SPIB register. Under this condition, the data in SPIS register will be destroyed. To avoid setting this bit, users should read the SPIRB register even if the transmission is implemented only. 0 = No overflow. NOTE This can only occur under slave mode. SSE (bit 4): SPI Shift Enable bit 1 = Start to shift, and stays on 1 while the current byte continues to transmit. 0 = Reset as soon as the shifting is completed, and the next byte is ready to shift. NOTE This bit can be reset by hardware only. SBRS (bit 2~0):SPI Baud Rate Select Bits SBRS2 (Bit 2) SBRS1 (Bit 1) SBRS0 (Bit 0) Mode Baud Rate 0 0 0 Master Fsco/2 0 0 1 Master Fsco/4 0 1 0 Master Fsco/8 0 1 1 Master Fsco/16 1 0 0 Master Fsco/32 1 0 1 Slave /SS enable 1 1 0 Slave /SS disable 1 1 1 Master TMR1/2 NOTE In master mode, /SS is disable. INTC: Interrupt control register Bit 3 (TM1IE) TM1IE interrupt enable bit. 0: disable TM1IE interrupt 1: enable TM1IE interrupt Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 23 EM78451 8-Bit Microcontroller Bit 2 (SPIIE) SPI interrupt enable bit. 0: disable SPI interrupt 1: enable SPI interrupt Bit 1 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt Table 3 Related Status/data Registers of the SPI Mode Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0X0A SPIRB/RA SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0 0x0B SPIWB/RB SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0 0 0 TM1IF OD3 OD4 0x0C SPIS/RC 0 RBFIF RBF SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to SPIRB from SPISR. The RBF bit and the RBFIF bit in the SPIS register will also be set. SPIWB: SPI Write Buffer. As transmitted data is loaded, the SPIS register stands by and starts to shift the data when sensing SCK edge with SSE set to “1”. SPIS: SPI Status register TM1IF (bit4): Timer1 interrupt flag. OD3 (bit 3): Open-Drain Control bit (P93) 1 = Open-drain enable for SDO, 0 = Open-drain disable for SDO. OD4 (bit 2): Open-drain Control bit (P94) 1 = Open-drain enable for SCK, 0 = Open-drain disable for SCK. RBFIF (bit 1): Read Buffer Full Interrupt flag 1 = Receive is completed, SPIB is full, and an interrupt occurs if enabled. 0 = Receive is ongoing, SPIB is empty. 24 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller RBF (bit 0): Read Buffer Full flag 1 = Receive is completed, SPIB is full. 0 = Receive is ongoing, SPIB is empty. 4.5.5 SPI Mode Timing The edge of SCK is selected by programming bit CES. The waveform shown in Fig.13 is applicable regardless of whether the EM78451 is under master or slave mode with /SS disabled. However, The waveform in Fig. 14 can only be implemented in slave mode with /SS enabled. Fig. 13 SPI Mode with /SS Disable Fig. 14 SPI Mode with /SS Enable Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 25 EM78451 8-Bit Microcontroller 4.5.6 Software Application of SPI Example for SPI: For Master ORG 0X0 SETTING: CLRA IOW 0X05 ;Set Port5 output IOW 0X06 ;Set Port6 output MOV 0X05,A MOV A,@0B11001111;Set prescaler for WDT CONTW MOV A,@0B00010001;Disable wakeup function IOW 0X0E MOV A,@0B00000000;Disable interrupt IOW 0X0F MOV A,@0x07 ;SDI input and SDO, SCK output IOW 0x09 MOV A,@0B10000000;Clear RBF and RBFIF flag MOV 0x0C,A MOV A,@0B11100000;Select clock edge and enable SPI MOV 0X0D,A START: WDTC BC 0X0C,1 ;Clear RBFIF flag MOV A,@0XFF MOV 0X05,A ;Show a signal at Port5 MOV 0X0A,A ;Move FF at read buffer MOV A,@0XAA ;Move AA at write buffer MOV 0X0B,A BS 0X0D,4 26 • ;Start to shift SPI data Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller NOP JBC 0X0D,4 ;Polling loop for checking SPI transmission completed JMP $-2 BC 0X03,2 CALL DELAY ;To catch the data from slaver MOV A,0X0A XOR A,@0X5A ;Compare the data from slaver JBS 0X03,2 JMP START FLAG: MOV A,@0X55 ;Show the signal when receiving correct data from slaver MOV 0X05,A CALL DELAY JMP START DELAY: ; (User’s program) EOP ORG 0XFFF JMP SETTING For Slaver ORG 0X0 INITI: JMP INIT ORG 0X2 INTERRUPT: ;Interrupt address MOV A,@0X55 MOV 0X06,A ;Show a signal at Port 6 when entering interrupt MOV A,@0B11100110;Enable SPI, /SS disabled MOV 0X0D,A BS 0X0D,4 ;Keep SSE at 1 to wait for SCK signal in order to shift data Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 27 EM78451 8-Bit Microcontroller MOV A,@0X00 as 00 ;Move 00 to write buffer in order to keep master’s read buffer MOV 0X0B,A BS 0X0D,4 ;Keep SSE at 1 to wait for SCK signal in order to shift data NOP JBC 0X0D,4 ;Polling loop for checking SPI transmission completed JMP $-2 BS 0X0D,4 ;Keep SSE at 1 to wait for SCK signal in order to shift data BC 0X03,2 MOV A,0X0A MOV 0X06,A ;Read master’s data from read buffer XOR A,@0XAA ;Check pass signal from read buffer JBS 0X03,2 JMP $-6 JMP SPI ORG 0X30 INIT: CLRA IOW 0X05 IOW 0X06 MOV 0x05,A MOV 0X06,A MOV A,@0XFF IOW 0X08 MOV A,@0B11001111;Set prescaler for WDT CONTW MOV A,@0B00010001;Disable wake-up function IOW 0X0E MOV A,@0B00000010;Enable external interrupt IOW 0XF ENI 28 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller MOV A,@0B00110111 IOW 0x09 BC 0X3F,1 ;Clear RBFIF flag NOP JBS 0X3F,1 ;Polling loop for checking interrupt occurrences JMP $-2 JMP INTERRUPT SPI: BS 0X0D,4 ;Keep SSE enabled as long as possible WDTC MOV A,@0X0F ;Show a signal when entering SPI loop MOV 0X06,A JBC 0X08,1 ;Choose P81 as a signal button JMP SPI MOV A,@0X5A ;Move 5A into write buffer when P81 button is pushed MOV 0X0B,A NOP JBC 0X0D,4 ;Polling loop for checking SPI transmission completed JMP $-2 BS 0XD,4 NOP NOP MOV A,@0XF0 ;Display at Port6 when P81 button is pushed MOV 0X06,A MOV A,@0X00 ;Send a signal to master to prevent infinite loop MOV 0X0B,A NOP JBC 0X0D,4 JMP $-2 BS 0X0D,4 BS 0x0C,7 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 29 EM78451 8-Bit Microcontroller BC 0x0C,1 NOP JMP SPI DELAY: ; (User’s program) EOP ORG 0XFFF JMP INITI 4.6 Timer 1 4.6.1 Overview Timer1(TMR1) is an eight-bit clock counter with a programmable prescaler. It is designed for the SPI module as a baud rate clock generator. TMR1 can be read, written, and cleared on any reset conditions. If employed, it can be turned down for power saving by setting TMR1EN bit [T1CON<2>] to 0. 4.6.2 Function description Fig. 15 shows TIMER1 block diagram. Each signal and block is described as follows: Fig. 15 TIMER1 Block Diagram OSC/4: Input clock. Prescaler: Option of 1:1, 1:4, 1:8, and 1:16 defined by T1P1 and T1P02(T1CON<1, 0>). It is cleared when a value is written to TMR1 or T1CON, and during any kind of reset as well. PWP: Pulse width preset register; the desired width of baud clock is written in advance. TMR1: Timer 1 register; TMR1 increases until it matches with PWP, and then resets to 0. If it is chosen optionally in the SPI mode, its output is fed as a shifting clock. 30 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller Comparator: To change the output status while a match occurs. The TMR1IF flag will be set at the same time. 4.6.3 Programmed the related registers The related registers for defining TMR1 are shown in Table 4 and Table 5 Table 4 Related Control Registers of the TMR1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0x0C SPIS/RC 0 0 0 TM1IF 0x0F INTC/IOCF 0 0 0 0 Bit 3 Bit 0 OD3 OD4 RBFIF RBF TM1IE SPIIE EXIE TCIE Bit 2 Bit 1 Bit 0 Table 5 Related Status/Data Registers of TMR1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 0X0E TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 0x0F PWP/RF PWP7 PWP6 PWP5 PWP4 PWP3 PWP2 PWP1 PWP0 0x0C T1CON/IOCC 0 0 0 0 0 TM1E TM1P1 TM1P0 TMR1: Timer1 Register TMR17~TMR10 is bit set of Timer1 register and it increases until the value matches the PWP and then it resets to 0. PWP: Pulse Width Preset Register PWP7~PWP0 is bit set of pulse width preset for the desire width of baud clock in advance. T1CON: Timer1 Control Register TM1E (bit2): Timer1 enable bit TM1P1 and TM1P0 (bit1~0): Timer1 prescaler for FSCO TM1P1 TM1P0 Prescaler Rate 0 0 1:1 0 1 1:4 1 0 1:8 1 1 1:16 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 31 EM78451 8-Bit Microcontroller 4.7 RESET and Wake-up A RESET is initiated by: (1) Power on reset, or (2) WDT timeout. (if enabled) VDD D Oscillator Q CLK CLK CLR Pow eron Reset Voltage Detector W DTE Setup Tim e W DT tim eout W DT Reset Fig. 16 Block Diagram of Reset The POR voltage of EM78451 ranges between 1.2V~1.8V. Under customer application, when power is OFF, Vdd must drop below 1.2V and remains OFF for 10us before power can be switched ON again. This way, the EM78451 will reset and work normally. The extra external reset circuit will work well if Vdd can rise at a very fast speed (50 ms or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problems. The device is kept in a RESET condition for a period of approximately 18ms2 (one oscillator start-up timer period) after the reset is detected. Fig.16 shows the block diagram of reset. Once the RESET occurs, the following functions are performed: The oscillator is running or it will be started. The Program Counter (R2) is set to all "1". When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared. All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared. The Watchdog timer is enabled if Code Option bit ENWDT is "1". The CONT register is set to all "1" except bit 6 (INT flag). 2 NOTE: Vdd = 5V, set up time period = 16.2ms ± 5% Vdd = 3V, set up time period = 18.0ms ± 5% 32 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller Bits 3,6 of IOCE register are cleared, bits 0,4~5 of IOCE register are set to "1". Bits 0 of R3F and bits 0 of IOCF registers are cleared. The sleep mode (power down) is achieved by executing the SLEP instruction (named as SLEEP1 MODE). While entering sleep mode, the WDT (if enabled) is cleared but keeps on running. The controller is awakened by WDT timeout (if enabled), and it will cause the controller to reset. The T and P flags of R3 are used to determine the source of the reset (wake-up). In addition to the basic SLEEP1 MODE, EM78451 has another sleep mode (caused by clearing "SLPC" bit of IOCE register, designated as SLEEP2 MODE). In the SLEEP2 MODE, the controller can be awakened by: (a) Any one of the wake-up pins is set to “0” (refer to Fig.17). Upon waking, the controller will continue to execute the program in-line. In this case, before entering SLEEP2 MODE, the wake-up function of the trigger sources (P60~P67, P74~P75, and P90~P91) should be selected (e.g. input pin) and enabled (e.g. pull-high, wake-up control). One caution should be noted is that after waking up, the WDT is enabled if Code Option bit ENWDT is "1". The WDT operation (to be enabled or disabled) should be appropriately controlled by software after waking up. (b) WDT time-out (if enabled). During wake-up, it will cause the controller to reset. Table 6 The Summary of the Initialized Values for Registers Address Name N/A IOC5 N/A N/A N/A N/A IOC6 IOC7 IOC8 IOC9 Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name C57 C56 C55 C54 C53 C52 C51 C50 Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name C67 C66 C65 C64 C63 C62 C61 C60 Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name C77 C76 C75 C74 C73 C72 C71 C70 Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name C87 C86 C85 C84 C83 C82 C81 C80 Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name C97 C96 C95 C94 C93 C92 C91 C90 Power-On 1 1 1 1 1 1 1 1 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 33 EM78451 8-Bit Microcontroller Address N/A 0x00 0x01 0x02 0x03 Name CONT R0(IAR) R1(TCC) R2(PC) R3(SR) Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name /PHEN /INT - - PAB Power-On 1 0 1 1 1 1 1 1 /RESET and WDT 1 P 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-On 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-Up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change **P **P **P **P **P **P **P **P Bit Name GP PS1 PS0 T P Z DC C Power-On 0 0 0 t t U U U /RESET and WDT 0 0 0 t t P P P Wake-Up from Pin Change P P P t t P P P - - - - - - Bit Name 0x04 0x05 0x06 R4(RSR) R5(P5) R6(P6) RSR.1 RSR.0 Power-On 0 0 U U U U U U /RESET and WDT 0 0 P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P P77 P76 P75 P74 P73 P72 P71 P70 Bit Name 34 • PSR2 PSR1 PSR0 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller Address Name 0x07 R7(P7) 0x08 0x09 0x0A R8(P8) R9(P9) RA(SPIRB ) Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On U U U U U U U U /RESET and WDT Wake-Up from Pin Change P P P P P P P P P P P P P P P P Bit Name P87 P86 P85 P84 P83 P82 P81 P80 Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name P97 P96 P95 P94 P93 P92 P91 P90 Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name SRB7 SRB6 Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P Bit Name 0x0B RB(SPIW B) 0x0D RC(SPIS) RD(SPIC) U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P IBDC TIIF OD3 RE(TMR1) RF(PWP) OD4 RBFIF RBF 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-Up from Pin Change P P P P P P P P Bit Name CES SPIE Power-On 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-Up from Pin Change P P P P P P P P SRO SPISE - SBRS SBRS SBRS 2 1 0 TMR1 TMR1 TMR1 TMR1 TMR1 TMR1 TMR1 TMR16 7 5 4 3 2 1 0 Power-On 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-Up from Pin Change P P P P P P P P Bit Name 0x0F ENSD OBDC O Power-On Bit Name 0x0E SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0 Power-On Bit Name 0x0C SRB5 SRB4 SRB3 SRB2 SRB1 SRB0 Power-On PWP7 PWP6 PWP5 PWP4 PWP3 PWP2 PWP1 PWP0 1 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) 1 1 1 1 1 1 1 • 35 EM78451 8-Bit Microcontroller Address 0x3F 0x0C 0x0D 0x0E 0x0F 0x10~0x3 E Name R3F(ISR) IOCC IOCD IOCE IOCF GPR Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name - - - - T1IF SPIIF EXIF TCIF Power-On U U U U 0 0 0 0 /RESET and WDT U U U U 0 0 0 0 Wake-Up from Pin Change U U U U P P P P Bit Name - - - - - T1E T1P1 T1P0 Power-On 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-Up from Pin Change P P P P P P P P Bit Name S7 - - - /PU9 /PU8 /PU6 /PU5 Power-On 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-Up from Pin Change P P P P P P P P Bit Name - ODE ROC - - /WUE Power-On U 0 1 1 0 U U 1 /RESET and WDT U 0 1 1 0 U U 1 Wake-Up from Pin Change U P 1 1 P U U P WTE SLPC Bit Name - - - - T1IE SPIIE EXIE TCIE Power-On U U U U 0 0 0 0 /RESET and WDT U U U U 0 0 0 0 Wake-Up from Pin Change U U U U P P P P Bit Name - - - - - - - - Power-On U U U U U U U U /RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P P ** To execute the next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition. X: Not used. U: Unknown or don’t care. P: Previous value before reset. Table 7 36 • t: Check Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller The Status of RST, T, and P of STATUS Register A RESET condition is initiated by the following events: 1. A power-on condition. 2. Watchdog timer time-out. The values of T and P, listed in Table 7 are used to check how the processor wakes up. Table 8 shows the events that may affect the status of T and P. Table 7 The Values of RST, T and P After RESET Reset Type T P Power on 1 1 WDT during Operating mode 0 P WDT wake-up during SLEEP1 mode 0 0 WDT wake-up during SLEEP2 mode 0 P Wake-Up on pin change during SLEEP2 mode P P T P *P: Previous status before reset Table 8 The Status of RST, T and P Being Affected by Events Event Power on 1 1 WDTC instruction 1 1 WDT time-out 0 *P SLEP instruction 1 0 Wake-Up on pin change during SLEEP2 mode P P *P: Previous value before reset 4.8 Interrupt The EM78451 has the following interrupts. 1. TCC overflow interrupt 2. External interrupt (/INT) 3. (SPI) Serial Peripheral Interface. Transmission completed interrupt. 4. Timer1 comparator completed interrupt. R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (if enabled) is generated, it will cause the next instruction to be fetched from address 001H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the R3F register. The interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 37 EM78451 8-Bit Microcontroller The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the execution of ENI instruction. Note that reading R3F will obtain the output of logic AND of R3F and IOCF (refer to Fig. 17). The RETI instruction will exit interrupt routine and enables the global interrupt (execution of ENI instruction). When an interrupt is generated by INT instruction (if enabled), it causes the next instruction to be fetched from address 002H. IRQn P Q R CLK C L Q D /IRQn interrupt IRQm RFRD R3F ENI/DISI P D R C CLK Q L IOD Q IOCFW R IOCF RESET IOCF RD RFW R Fig. 17 Interrupt input circuit 4.9 Oscillator 4.9.1 Oscillator Modes The EM78451 can operate in four different oscillator modes. There are high XTAL (HXT) oscillator mode, low XTAL (LXT) oscillator mode, External RC oscillator mode (ERC), and Internal C、External R oscillator mode. User can select one of them by programming MS, RCT, IRC, HLF and HLP in the Code Option Register. Table 9 depicts how these three modes are defined. Table 9 Oscillator Modes by MS, RCT. Mode 38 • MS RCT HLF High XTAL Oscillator 1 X 1 Low XTAL Oscillator 1 X 0 External RC Oscillator 0 1 X External R and Internal C Oscillator 0 0 X Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller NOTE X: Don’t care 4.9.2 Crystal Oscillator/Ceramic Resonators (XTAL) EM78451 can be driven by an external clock signal through the OSCI pin as shown in Fig 18. In most applications, pin OSCI and pin OSCO is connected with a crystal or ceramic resonator to generate oscillation. Fig 19 depicts such circuit. Table 10 provides the recommends values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor may be necessary for AT strip cut crystal or low frequency mode. OSCI Ext. Clock OSCO EM 78451 Fig. 18 Circuit for External Clock Input C1 OSCI EM 78451 XTAL OSCO RS C2 Fig. 19 Circuit for Crystal/Resonator Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 39 EM78451 8-Bit Microcontroller Table 10 Capacitor Selection Guide for Crystal Oscillator Ceramic Resonators Oscillator Type Frequency Mode Ceramic Resonator HXT LXT Crystal Oscillator HXT Frequency C1 (pF) C2 (pF) 455 KHz 1.0 MHz 2.0 MHz 4.0 MHz 32.768 KHz 100 KHz 200 KHz 455 KHz 1.0 MHz 2.0 MHz 4.0 MHz 10~150 40~80 20~40 10~30 25 25 25 20~40 15~30 15 15 10~150 40~80 20~40 10~30 15 25 25 20~150 15~30 15 15 330 330 C OSCI 7404 7404 7404 EM 78451 XTAL Fig. 20 Circuit for Crystal/Resonator-Series Mode 4.7K 10K VDD OSCI 7404 7404 EM 78451 10K XTAL C1 C2 Fig. 21 Circuit for Crystal/Resonator-Parallel Mode 4.9.3 RC Oscillator Mode For some applications that do not need a very precise timing calculation, the RC oscillator (Fig. 22 & Fig. 23) offers cost-effective savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. 40 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable because the NMOS cannot properly discharge the current of the capacitor. Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the way the PCB is layout, will affect the system frequency. VCC Rext OSCI EM 78451 Cext Fig. 22 Circuit for External RC Oscillator Mode V C C R e x t OSCI EM 78451 Fig. 23 Circuit for External R, Internal C Oscillator Mode Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 41 EM78451 8-Bit Microcontroller Calibrate frequency of External RC oscillator (For reference only) C ext 20pF 100pF 300pF R ext Fosc @5.0V,25℃ 3.3K 5.1K 10K 100K 3.3K 5.1K 10K 100K 3.3K 5.1K 10K 100K 3.4MHz 2.2MHz 1.3MHz 144KHz 1.39MHz 935KHz 500KHz 54.5KHz 740KHz 490KHz 255KHz 28KHz Internal C, external R Table (For reference only) External R (Ohm) Fosc @5.0V, 25℃ (Hz) 10K 12M 15K 7.7M 20K 5.7M 30K 3.65M 51K 2.24M 100K 1.14M 150K 749K 200K 559K 510K 214K 2M 56K 3.3M 32.8K 4.10 Code Option Register 0 1 2 3 4 5 6 ENWDT MS HLF - RCT DEL1 DEL0 Bit 0 (ENWDT): Watchdog Timer control. 1: Enable 0: Disable Bit 1 (MS): Oscillator type. 1: XTAL type 0: RC type 42 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller Bit 2 (HLF): Frequency mode. 1: High frequency (>32.768KHz) 0: Low frequency (=32.768KHz) Bit 3 : Reserved. The bit0 set to ”1” all the time Bit 4 (RCT): RC type. 1: External RC 0: Internal RC Bit 5 (DEL1) and Bit 6 (DEL0): Speed of SPI. DEL 1 DEL 0 Speed (MHz) Delay time (ns) Use Type 0 0 8 0 ns Not use SPI mode 0 1 2.5 50 ns 1 0 1 1 1 100 ns Not use Not use *Do not set DEL1 and DEL0 bits to all “1”, otherwise, the microprocessor will not work. The test code of EM78451 The following program must be added in order to heighten the liability of the mass production. The test code must not be executed during free running. Address Code Statement FFA 0006 IOW 0x06 FFB 0546 INC 0x06 FFC 01C6 DEC 0x06 FFD 01C5 DEC 0x05 FFE 0000 NOP 4.11 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. All instructions are executed within one single instruction cycle (consisting of 2 oscillator periods), unless the program counter is changed by: (a) Executing the instruction "MOV R2,A", "ADD R2,A", "TBL", or any other instructions that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ⋅⋅⋅⋅). (b) Executing CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ, DJZA) which were tested to be true. Under these cases, the execution takes two instruction cycles. In addition, the instruction set has the following features: (1). Every bit of any register can be set, cleared, or tested directly. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 43 EM78451 8-Bit Microcontroller (2). The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b" represents a bit field designator that selects the value for the bit, located in the register "R" and affects by the operation. "k" represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY HEX MNEMONIC 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0000 0001 0002 0003 0004 000r 0010 0011 0012 NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET 0 0000 0001 0011 0013 RETI 0 0000 0001 0100 0 0000 0001 rrrr 0014 001r CONTR IOR R 0 0000 0010 0000 0020 TBL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0 0 0 0 0 0 0 0 44 • 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0000 0000 0000 0000 0000 0000 0001 0001 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr OPERATION No Operation Decimal Adjust A A → CONT 0 → WDT, Stop oscillator 0 → WDT A → IOCR Enable Interrupt Disable Interrupt [Top of Stack] → PC [Top of Stack] → PC, Enable Interrupt CONT → A IOCR → A R2+A → R2, Bits 8~9 of R2 unchanged A→R 0→A 0→R R-A → A R-A → R R-1 → A R-1 → R A ∨ VR → A A ∨ VR → R A&R→A A&R→R A⊕R→A A⊕R→R A+R→A A+R→R R→A R→R /R → A /R → R R+1 → A R+1 → R R-1 → A, skip if zero R-1 → R, skip if zero R(n) → A(n-1), R(0) → C, C → A(7) R(n) → R(n-1), STATUS AFFECTED None C None T,P T,P None <Note1> None None None None None None <Note1> Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller INSTRUCTION BINARY HEX MNEMONIC 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr 06rr RLC R 0 0111 00rr rrrr 07rr SWAPA R 0 0 0 0 0 0 0 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b 1 00kk kkkk kkkk 1kkk CALL k 1 1 1 1 1 1 1 1 1 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E02 1Fkk JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k 0111 0111 0111 100b 101b 110b 111b 01kk 1000 1001 1010 1011 1100 1101 1110 1111 01rr 10rr 11rr bbrr bbrr bbrr bbrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0000 0010 kkkk kkkk OPERATION R(0) → C, C → R(7) R(n) → A(n+1), R(7) → C, C → A(0) R(n) → R(n+1), R(7) → C, C → R(0) R(0-3) → A(4-7), R(4-7) → A(0-3) R(0-3) ↔ R(4-7) R+1 → A, skip if zero R+1 → R, skip if zero 0 → R(b) 1 → R(b) if R(b)=0, skip if R(b)=1, skip PC+1 → [SP], (Page, k) → PC (Page, k) → PC k→A A∨k→A A&k→A A⊕k→A k → A, [Top of Stack] → PC k-A → A PC+1 → [SP], 002H → PC k+A → A STATUS AFFECTED C C None None None None None <Note2> None <Note3> None None None None None Z Z Z None Z,C,DC None Z,C,DC NOTE This instruction is applicable to IOC5 ~ IOC9, IOCD~IOCF only. This instruction is not recommended for RF operation. This instruction cannot operate on R3F. Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 45 EM78451 8-Bit Microcontroller 4.12 Timing Diagrams AC Test Input/Output W aveform 2.4 2.0 0.8 TEST POINTS 2.0 0.8 0.4 AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc 46 • Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller 5 ABSOLUTE MAXIMUM RATING Items Rating Temperature under bias 0°C to 70°C Storage temperature -65°C to 150°C Input voltage -0.3V to +6.0V Output voltage -0.3V to +6.0V DC to 20MHz Operating Frequency (2clk) 6 ELECTRICAL CHARACTERISTICS 6.1 DC Characteristic (Ta=0°C~70°C, VDD=5V±5%, VSS=0V) Symbol Parameter Condition XTAL VDD to 2.3V FXT FRC DC 8 XTAL VDD to 5V DC 20 RC VDD to 2.3V DC 4 DC 4 DC 4 XTAL VDD to 3V RC VDD to 3V Input Leakage Current Input High Voltage VDD=5V) VIL1 Input Low Voltage (VDD=5V) VILX1 Clock Input High Voltage (VDD=5V Clock Input Low Voltage (VDD=5V VIH2 Input High Voltage(VDD=3V) VIL2 Input Low Voltage (VDD=3V) VIHX2 VILX2 VOH1 VOH2 VOH3 Max 4 VIH1 VIHX1 Typ DC Two clocks Two clocks RC VDD to 5V IIL Min Clock Input High Voltage (VDD=3V) Clock Input Low Voltage (VDD=3V) Output High Voltage (Ports 5,6,8, P74~P77, P90~P92,P95~P97,and PF5~PF7) ±1 VIN = VDD, VSS 2.0 2.5 1.0 1.5 1.5 S7=1(IOCD Register bit7), IOH = -7.0mA S7=0(IOCD Register bit7), IOH = -7.0mA Output High Voltage (P93/SDO,P94/SCK) IOH = -5.0mA Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) 0.6 2.4 2 V V V V OSCI Output High Voltage (P70~P72) µA V 0.4 IOH = -8.0mA MHz V OSCI OSCI MHz V 0.8 OSCI Unit V V 2.4 V 2.4 2.4 V • 47 EM78451 8-Bit Microcontroller Symbol Parameter Condition Min VOL1 Output Low Voltage (Ports 5,6,8, P74~P77, P90~P92,P95~P97,and PF5~PF7)) IOL = 5.0mA VOL2 Output Low Voltage (P70~P72) S7=1(IOCD Register bit7), IOH = 10.0mA S7=0(IOCD Register bit7), IOH = 10.0mA Output Low Voltage (P93/SDO, P94/SCK) Output Low Voltage (P74~P77) VOL3 VOL4 0.4 V 0.8 0.4 IOL = 15.0mA 0.4 IPH2 Pull-high current (P74,P75) Pull-high active, input pin at VSS Operating supply current 0.4 IOL = 7.0mA Pull-high active, input pin at VSS ICC Unit V Pull-high current Power down current Max 0.4 IPH ISB Typ -50 -100 -240 1 All input and I/O pin at VDD, output pin floating, WDT enabled /RESET="High", Fosc=1.84324MHz (CK2="0"), output pin floating V µA mA 10 µA 3 mA 6.2 AC Characteristic (Ta=0°C~70°C, VDD=5V±5%, VSS=0V) Symbol Dclk Tins Ttcc Twdt Tdrh Parameter Input CLK duty cycle Instruction cycle time (CK2="0") TCC input period Watchdog timer period Device reset hold period Conditions RC Type Min Typ Max Unit 45 50 55 % DC ns 500 (Tins+20)/N* Ta=25°C Ta=25°C 18 183 ns ms ms N= selected prescaler ratio. 3 48 • NOTE: Vdd = 5V, set up time period = 16.2ms ± 5% Vdd = 3V, set up time period = 18.0ms ± 5% Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) EM78451 8-Bit Microcontroller 7 APPLICATION CIRCUIT EM78451 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice) • 49 EM78451 8-Bit Microcontroller APPENDIX A Package Types: OTP MCU 50 • Package Type Pin Count Package Size EM78451AP DIP 40 600 mil EM78451AQ QFP 44 Product Specification (V1.2) 05.27.2004 (This specification is subject to change without further notice)