ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85411 is a low skew, high performance 1-to-2 Differential-to-LVDS Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.The ICS85411 is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS85411 ideal for those clock distribution applications demanding well defined performance and repeatability. • 2 differential LVDS outputs ICS • 1 differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor bias on nCLK input • Output skew: 20ps (maximum) • Part-to-part skew: 250ps (maximum) • Additive phase jitter, RMS: 0.05ps (typical) • Propagation delay: 2.5 ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free package available • Industrial temperature information available upon request BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nCLK GND ICS85411 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View 85411AM www.icst.com/products/hiperclocks.html 1 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output 3, 4 Q1, nQ1 Output Differential output pair. LVDS interface levels. 5 GND Power Power supply ground. 6 nCLK Input 7 CLK Input 8 VDD Power Differential output pair. LVDS interface levels. Pulldown Inver ting differential clock input. Pullup Non-inver ting differential clock input. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 85411AM Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current V PP Peak-to-Peak Input Voltage Minimum Typical CLK VDD = VIN = 3.465V 5 µA nCLK VDD = VIN = 3.465V 150 µA CLK VDD = 3.465V, VIN = 0V nCLK VDD = 3.465V, VIN = 0V -150 µA -5 µA 0.15 Common Mode Input Voltage; NOTE 1, 2 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. 1.3 V VDD - 0.85 V TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage Test Conditions Minimum Typical Maximum Units 200 280 360 mV 0 40 mV 1.125 1.25 1.375 V 5 25 mV -20 ±1 +20 µA ∆ VOS VOS Magnitude Change IOFF Power Off Leakage IOSD Differential Output Shor t Circuit Current -3.5 -5 mA IOS Output Shor t Circuit Current -3.5 -5 mA VOH Output High Voltage 1.34 1.6 V VOL Output Low Voltage 85411AM 0.9 www.icst.com/products/hiperclocks.html 3 1.06 V REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±5% TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 650 MHz fMAX Output Frequency t PD Propagation Delay; NOTE 1 2.5 ns tsk(o) Output Skew; NOTE 2, 4 20 ps tsk(pp) 250 ps tR / tF Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time odc Output Duty Cycle tjit 1.5 (12KHz to 20MHz) 0.05 20% to 80% 150 350 > 500MHz 47 53 % 52 % 48 ≤ 500MHz All parameters measured at ƒ≤ 650MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 85411AM ps www.icst.com/products/hiperclocks.html 4 ps REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Input/Output Additive Phase Jitter -20 @ 200MHz (12KHz to 20MHz) = 0.05ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M 500M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 85411AM vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 5 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD 3.3V SCOPE nCLK Qx V 3.3V±5% Power Supply Float GND + - LVDS V Cross Points PP CMR CLK nQx GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy PART 2 Qy nQy Qx Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK 80% 80% CLK VOD Clock Outputs nQ0, nQ1 20% 20% tR Q0, Q1 tF tPD PROPAGATION DELAY OUTPUT RISE/FALL TIME VDD out Pulse Width t odc = PERIOD DC Input LVDS t PW 100 ➤ VOD/∆ VOD out ➤ Q0, Q1 ➤ nQ0, nQ1 t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 85411AM DIFFERENTIAL OUTPUT VOLTAGE SETUP www.icst.com/products/hiperclocks.html 6 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER VDD out LVDS ➤ DC Input LVDS ➤ out VOS/∆ VOS ➤ VDD IOFF ➤ POWER OFF LEAKAGE SETUP OFFSET VOLTAGE SETUP VDD VDD out DC Input ➤ out IOS LVDS DC Input ➤ IOSB IOSD out out OUTPUT SHORT CIRCUIT CURRENT SETUP 85411AM ➤ LVDS DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP www.icst.com/products/hiperclocks.html 7 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 2. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS + R1 100 - 100 Ohm Differential Transmission Line FIGURE 2. TYPICAL LVDS DRIVER TERMINATION 85411AM www.icst.com/products/hiperclocks.html 8 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V Zo = 50 Ohm 3.3V 3.3V R3 125 BY R4 125 LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 85411AM BY www.icst.com/products/hiperclocks.html 9 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85411 is: 636 85411AM www.icst.com/products/hiperclocks.html 10 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER FOR 8 LEAD SOIC TABLE 6. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 85411AM www.icst.com/products/hiperclocks.html 11 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85411AM 85411AM 8 lead SOIC 96 per tube 0°C to 70°C ICS85411AMT 85411AM 8 lead SOIC on Tape and Reel 2500 0°C to 70°C ICS85411AMLF 85411AMLF 8 lead "Lead Free" SOIC 96 per tube 0°C to 70°C ICS85411AMLFT 85411AMLF 8 lead "Lead Free" SOIC on Tape and Reel 2500 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85411AM www.icst.com/products/hiperclocks.html 12 REV. B JUNE 16, 2004 ICS85411 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER REVISION HISTORY SHEET Rev Table B T4 B T7 85411AM Page 1 4 5 12 Description of Change Features - added Additive Phase Jitter bullet. AC Characteristics table - added tjit row. Added Additive Phase Jitter Application Note Ordering Information Table - added Lead Free Par t Number. www.icst.com/products/hiperclocks.html 13 Date 6/9/04 6/16/04 REV. B JUNE 16, 2004