LTC3775 High Frequency Synchronous Step-Down Voltage Mode DC/DC Controller DESCRIPTION FEATURES n n n n n n n n n n n n n n Wide VIN Range: 4.5V to 38V Line Feedforward Compensation Low Minimum On-Time: tON(MIN) < 30ns Powerful Onboard MOSFET Drivers Leading Edge Modulation Voltage Mode Control ±0.75%, 0.6V Reference Voltage Accuracy Over Temperature VOUT Range: 0.6V to 0.8VIN Programmable, Cycle-by-Cycle Peak Current Limit Sense Resistor or RDS(ON) Current Sensing Programmable Soft-Start Synchronizable Fixed Frequency from 250kHz to 1MHz Selectable Pulse-Skipping or Forced Continuous Modes of Operation Low Shutdown Current: 14μA Typical Thermally Enhanced 3mm × 3mm QFN Package APPLICATIONS n n n Automotive Systems Telecom and Industrial Power Supplies Point of Load Applications The LTC®3775 is a high efficiency synchronous step-down switching DC/DC controller that drives an all N-channel power MOSFET stage from a 4.5V to 38V input supply voltage. A patented line feedforward compensation circuit and a high bandwidth error amplifier provide very fast line and load transient response. High step-down ratios are made possible by a low 30ns minimum on-time, allowing extremely low duty cycles MOSFET RDS(ON) current sensing maximizes efficiency. Alternatively, a sense resistor can be used for higher current limit accuracy. Continuous monitoring of the voltages across the top and bottom MOSFETs allows cycle-by-cycle control of the inductor current, configurable by external resistors. The soft-start function controls the duty cycle during start-up, providing a smooth output voltage ramp up. The operating frequency is user programmable from 250kHz to 1MHz and can be synchronized to an external clock. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5408150, 5481178, 5705919, 6580258, 5847554, 5055767. TYPICAL APPLICATION 330μF 35V ILIMT 0.01μF SENSE LTC3775 INTVCC BOOST ILIMB FB 330pF 3.9nF 0.1μF 0.36μH SS FREQ 10k 80 SW 39.2k 10k 90 TG 4.7k BG PGND VOUT 1.2V 470μF 15A 2.5V s2 VIN = 12V VOUT = 1.2V CONTINUOUS MODE SW FREQ = 500kHz 3 60 50 EFFICIENCY 2 40 30 20 MODE/SYNC 0 0.01 1 POWER LOSS 10 COMP RUN/SHDN SGND 4 70 0.1 1 10 LOAD CURRENT (A) POWER LOSS (W) 4.7μF VIN 5 100 EFFICIENCY (%) 3.16k 57.6k Efficiency and Power Loss vs Load Current VIN 5V TO 28V 0 100 3775 TA01a 3775 TA01b 3775f 1 LTC3775 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TG BOOST MODE/SYNC RUN/SHDN TOP VIEW 16 15 14 13 ILIMT 1 12 SW ILIMB 2 11 VIN 17 PGND FB 3 10 SENSE 5 6 7 8 SGND BG 9 INTVCC SS COMP 4 FREQ Supply Voltage VIN ......................................................... –0.3V to 40V BOOST ................................................... –0.3V to 46V BOOST-SW............................................... –0.3V to 6V SW ............................................................ –5V to 40V ILIMT .............................................................–0.3V to VIN SENSE.............................................................–5V to VIN INTVCC ......................................................... –0.3V to 6V RUN/SHDN................................................... –0.3V to 6V FB, MODE/SYNC ................................... –0.3V to INTVCC FREQ, ILIMB, SS..................................... –0.3V to INTVCC INTVCC RMS Currents... .........................................50mA Operating Junction Temperature Range (Note 2).................................................. –40°C to 125°C Storage Temperature Range................... –65°C to 150°C UD PACKAGE 16-LEAD (3mm s 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W (NOTE 3) EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3775EUD#PBF LTC3775EUD#TRPBF LDJK 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC3775IUD#PBF LTC3775IUD#TRPBF LDJK 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3775f 2 LTC3775 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply VIN VIN Supply Voltage IVIN Input DC Supply Current l 4.5 VFB = 0.7V (Note 5) VRUN = 0V 38 3.5 14 V mA μA RUN/SHDN Pin VRUN RUN/SHDN Pin Enable Threshold VSHDN RUN/SHDN Pin Shutdown Threshold VSHDN(HYST) RUN/SHDN Pin Shutdown Threshold Hysteresis IRUN RUN/SHDN Pin Source Current 1.19 VRUN/SHDN Rising VRUN/SHDN = 0V VRUN/SHDN = 1.5V 1.22 1.25 V 0.74 V 140 mV –1 –4 μA μA Error Amplifier VFB Feedback Pin Voltage ΔVFB Feedback Voltage Line Regulation l 0.597 0.5955 4.5V < VIN < 38V 0.600 0.603 0.6045 ±0.01 ΔVOUT Output Voltage Load Regulation 1V < VCOMP < 2V (Note 6) IFB FB Pin Input Current VFB = 0.6V –50 ICOMP COMP Pin Output Current Sourcing Sinking –0.5 1 f0dB Error Amplifier Unity-Gain Crossover Frequency ISS SS Pin Source Current RSS SS Pin Pull-Down Resistance in Current Limit 0.01 V V %/V 0.1 % 50 nA –1 mA mA (Note 6) 25 MHz VSS = 0V –1 μA 1.3 kΩ Soft-Start Current Limit ILIMB ILIMB Source Current l –9 –10 –11 ILIMT ILIMT Sink Current l 90 100 110 μA ISENSE SENSE Pin Input Current 1 μA VILIMT(MAX) Topside Current Limit Threshold (VIN-SENSE) VILIMT = 0.1V l 90 100 110 mV VILIMB(MAX) Bottom Side Current Limit Threshold (PGND-SW) VILIMB = 0.5V l 80 100 120 mV 4.9 5.2 5.5 V 0.01 %/V –1 –0.1 % 0.35 V μA INTVCC Low Dropout Voltage Regulator INTVCC LDO Regulator Output Voltage ΔVINTVCC(LINE) INTVCC Line Regulation 7.5V < VIN < 38V ΔVINTVCC(LOAD) INTVCC Load Regulation ΔIINTVCC = 0mA to 20mA INTVCC Regulator Dropout Voltage (VIN – VINTVCC) IINTVCC = 20mA VDROPOUT VUVLO INTVCC UVLO Voltage INTVCC Rising Hysteresis 3.0 3.6 0.5 4.2 V V 3775f 3 LTC3775 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fOSC Oscillator Frequency RFREQ = 39.2k l 425 500 575 kHz fHIGH fLOW Maximum Oscillator Frequency l 1000 Minimum Oscillator Frequency l fSYNC External Sync Frequency Range With Reference to Free Running Oscillator kHz –20 250 kHz 20 % tON(MIN) TG Minimum On-Time (Notes 6, 8) VMODE/SYNC = 0V 30 ns tOFF(MIN) TG Minimum Off-Time (Note 6) 300 ns DCMAX Maximum TG Duty Cycle fOSC = 500kHz VMODE MODE/SYNC Threshold MODE/SYNC Rising VMODE(HYST) RMODE/SYNC l 90 % 1.2 V MODE/SYNC Hysteresis 430 mV MODE/SYNC Input Resistance to SGND 50 kΩ Driver BG RUP Bottom Gate (BG) Pull-Up On-Resistance 2.5 Ω TG RUP Top Gate (TG) Pull-Up On-Resistance 2.5 Ω BG RDOWN Bottom Gate (BG) Pull-Down On-Resistance 1.0 Ω TG RDOWN Top Gate (TG) Pull-Down On-Resistance 1.5 Ω BG, TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CL = 3300pF (Note 7) 15 ns TG, BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CL = 3300pF (Note 7) 15 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3775E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statisitical process controls. The LTC3775I is guaranteed over the full –40°C to 125°C operating junction temperature range. The junction temperature, TJ, is calculated from the ambient temperature, TA, and power dissipation, PD, according to: TJ = TA + (PD • θJA) Note 3: Failure to solder the exposed pad of the UD package to the PC board will result in a thermal resistance much higher than 68°C/W. Note 4: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 5: Supply current in normal operation is dominated by the current needed to charge and discharge the external MOSFET gates. This current will vary with supply voltage and the external MOSFETs used. Note 6: Guaranteed by design, not subject to test. Note 7: Rise and fall times are measured using 10% and 90% levels. Delay and nonoverlap times are measured using 50% levels. Note 8: The LTC3775 leading edge modulation architecture does not have a minimum TG pulse width requirement. The TG minimum pulse width is limited by the SW node rise and fall times. 3775f 4 LTC3775 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current Efficiency vs Input Voltage 100 90 70 60 EFFICIENCY (%) EFFICIENCY (%) 80 PULSE-SKIPPING MODE 50 40 CONTINUOUS MODE 30 1.206 20 1.202 80 1.200 70 1A LOAD 1.198 60 VOUT = 1.2V CONTINUOUS MODE SW FREQ = 500kHz FIRST PAGE CIRCUIT 50 40 0.1 1 10 LOAD CURRENT (A) 100 4 8 12 16 20 INPUT VOLTAGE (V) 3775 G01 1.196 1.194 24 28 Line Regulation FB VOLTAGE (mV) 602 1.200 1.198 1.196 16 14 3775 G03 601 IL 10A/DIV 600 599 ILOAD 10A/DIV 24 28 597 –50 –25 50 25 75 0 TEMPERATURE (°C) 3775 G02 100 125 3775 G05 Positive Load Step in Forced Continuous Mode 50μs/DIV VIN = 12V VOUT = 1.2V LOAD STEP = 0A TO 10A TO 0A MODE/SYNC = 0V SW FREQ = 500kHz FIRST PAGE CIRCUIT Negative Load Step in Forced Continuous Mode VSW 20V/DIV VSW 20V/DIV VOUT(AC) 100mV/DIV VOUT(AC) 100mV/DIV IL 10A/DIV ILOAD 10A/DIV VOUT(AC) 100mV/DIV IL 10A/DIV ILOAD 10A/DIV ILOAD 10A/DIV 3775 G07 3775 G06 Load Step in Pulse-Skipping Mode IL 10A/DIV VIN = 12V 5μs/DIV VOUT = 1.2V LOAD STEP = 0A TO 10A MODE/SYNC = 0V SW FREQ = 500kHz FIRST PAGE CIRCUIT 10 12 8 6 LOAD CURRENT (A) VOUT(AC) 100mV/DIV 598 12 16 20 INPUT VOLTAGE (V) 4 Load Step in Forced Continuous Mode FB Voltage vs Temperature 1.202 8 2 603 VOUT = 1.2V LOAD = 1A 1.204 FIRST PAGE CIRCUIT 4 0 3775 G02 1.206 VOUT (V) 1.204 15A LOAD 10 0 0.01 VIN = 12V SW FREQ = 500kHz FIRST PAGE CIRCUIT VOUT (V) VIN = 12V VOUT = 1.2V SW FREQ = 500kHz FIRST PAGE CIRCUIT 90 1.194 Load Regulation 100 5μs/DIV VIN = 12V VOUT = 1.2V LOAD STEP = 10A TO 0A MODE/SYNC = 0V SW FREQ = 500kHz FIRST PAGE CIRCUIT 3775 G08 VIN = 12V 50μs/DIV VOUT = 1.2V LOAD STEP = 1A TO 11A TO 1A MODE/SYNC = INTVCC SW FREQ = 500kHz FIRST PAGE CIRCUIT 3775 G09 3775f 5 LTC3775 TYPICAL PERFORMANCE CHARACTERISTICS Pulse-Skipping Mode Waveform with 0.1A Load Switching Frequency vs Temperature Output Short-Circuit Waveform 550 IL 20A/DIV 0A LOAD IL 2A/DIV VSS 1V/DIV VSW 10V/DIV 3775 G10 20μs/DIV VIN = 12V VOUT = 1.2V CSS = 0.01μF FIRST PAGE CIRCUIT 520 510 500 490 480 470 450 –50 3775 G25 108 108 80 106 106 70 104 104 102 102 VIN = 40V ILIMT (μA) 60 50 40 ILIMT (μA) 110 VIN = 5V VIN = 12V VIN = 24V 100 98 98 96 96 20 94 94 10 92 92 90 –50 90 0.6 0.8 1.0 1.2 1.4 VCOMP (V) 1.6 1.8 2.0 –25 50 25 0 75 TEMPERATURE (°C) –0.2 10.6 –0.4 10.4 –0.6 10.2 –0.8 10.0 9.8 –1.4 –1.6 9.2 –1.8 125 3775 G15 12 16 20 24 28 32 INPUT VOLTAGE (V) –2.0 –50 36 40 3775 G14 35 30 –1.2 9.4 100 8 Shutdown Current vs Input Voltage –1.0 9.6 50 25 0 75 TEMPERATURE (°C) 4 INPUT CURRENT (μA) 0 10.8 IRUN (μA) 11.0 –25 125 IRUN vs Temperature ILIMB vs Temperature 9.0 –50 100 3775 G13 3775 G12 125 100 30 0 100 ILIMT vs Input Voltage 110 90 50 25 0 75 TEMPERATURE (°C) –25 3775 G11 ILIMT vs Temperature Duty Cycle vs VCOMP 100 DUTY CYCLE (%) 530 460 VIN = 12V 5μs/DIV VOUT = 1.2V LOAD = 0.1A MODE/SYNC = INTVCC SW FREQ = 500kHz FIRST PAGE CIRCUIT ILIMB (μA) SWITCHING FREQUENCY (kHz) 540 VOUT(AC) 100mV/DIV 25 20 15 10 5 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3775 G16 0 4 8 12 16 20 24 28 32 INPUT VOLTAGE (V) 36 40 3775 G17 3775f 6 LTC3775 TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Current vs Temperature Quiescent Current vs INTVCC 20 14 12 10 8 6 4 –0.2 6 –0.3 5 $INTVCC (%) QUIESCENT CURRENT (mA) 16 4 3 50 25 0 75 TEMPERATURE (°C) 100 125 –1.0 0 3.6 4.0 4.4 5.2 4.8 INTVCC (V) 5.6 6.0 0 10 30 40 20 INTVCC LOAD CURRENT (mA) 50 3775 G20 3775 G19 INTVCC Dropout INTVCC Dropout vs Temperature 0 TA = 25°C LOAD CURRENT = 20mA –0.2 –0.2 –0.4 –0.4 –0.6 –0.8 –1.0 –0.6 –0.9 3775 G18 0 –0.5 –0.8 INTVCC DROPOUT VOLTAGE (V) –25 –0.4 –0.7 2 1 2 VIN = 12V –0.1 7 INTVCC DROPOUT VOLTAGE (V) SHUTDOWN CURRENT (μA) 18 0 –50 INTVCC Load Regulation 0 8 0 10 30 40 20 INTVCC LOAD CURRENT (mA) 50 –0.6 –0.8 –1.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 3775 G21 125 3775 G22 BG Turn-Off Waveform Driving Renesas RJK0301 BG Turn-On Waveform Driving Renesas RJK0301 BG 1V/DIV BG 1V/DIV 0V 0V VIN = 12V 20ns/DIV VOUT = 1.2V LOAD = 1A MOSFET: RENESAS RJK0301 100 3775 G23 VIN = 12V 20ns/DIV VOUT = 1.2V LOAD = 1A MOSFET: RENESAS RJK0301 3775 G24 3775f 7 LTC3775 PIN FUNCTIONS ILIMT (Pin 1): Topside Current Limit Set Point. This pin has an internal 100μA pull-down current, allowing the topside current limit threshold to be programmed by an external resistor connected to VIN. See Current Limit Applications. can be connected to a sense resistor at the drain of the top MOSFET for more accurate current limit. VIN (Pin 11): Main Input Supply. Bypass this pin to PGND with a low ESR ceramic capacitor of value 1μF or greater (X5R or better). ILIMB (Pin 2): Bottom Side Current Limit Set Point. This pin has an internal 10μA pull-up current, allowing the bottom side current limit threshold to be programmed by an external resistor connected to SGND. See Current Limit Applications. SW (Pin 12): Switch Node. Connect this pin to the source of the upper power MOSFET. This pin is also used as the input to the bottom side current limit comparator and the zero-crossing reverse current comparator. FB (Pin 3): Error Amplifier Input. The FB pin is connected to a resistive divider from VOUT to SGND. The feedback loop compensation network is also connected to this pin. TG (Pin 13): Top Gate Drive. This pin drives the gate of the top N-channel MOSFET. The TG driver draws power from the BOOST pin and returns to the SW pin, providing true floating drive to the top MOSFET. COMP (Pin 4): Error Amplifier Output. Use an RC network between the COMP pin and the FB pin to compensate the feedback loop for optimum transient response. SS (Pin 5): Soft-Start. Connect this pin to an external capacitor, CSS, to implement a soft-start function. When the voltage on the SS pin is less than the 0.6V internal reference, the LTC3775 regulates the VFB voltage to the SS pin voltage instead of the 0.6V reference. FREQ (Pin 6): Frequency Set. A resistor connected from this pin to SGND sets the free-running frequency of the internal oscillator. See Applications Information section for resistor value selection details. SGND (Pin 7): Signal Ground. All the internal low power circuitry returns to the SGND pin. All feedback and softstart connections should return to SGND. SGND should be Kelvin connected to a single point near the negative terminal of the VOUT bypass capacitor. BG (Pin 8): Bottom Gate Drive. This pin drives the gate of the bottom N-channel synchronous switch MOSFET. This pin swings from PGND to INTVCC. INTVCC (Pin 9): Internal 5.2V Regulator Output. The gate driver and control circuits are powered from this voltage. Bypass this pin to power ground with a low ESR ceramic capacitor of value 4.7μF or greater (X5R or better). SENSE (Pin 10): Topside Current Sensing Input. Connect this pin to the switch node of the converter for top MOSFET RDS(ON) current sensing. Alternatively, this pin BOOST (Pin 14): Top Gate Driver Supply. This pin should be decoupled to SW with a 0.1μF low ESR ceramic capacitor. An external Schottky diode from INTVCC to BOOST creates a floating charge-pump supply at BOOST. No other external supplies are required. MODE/SYNC (Pin 15): Pulse-Skipping Mode Enable/Sync Pin. This multifunction pin provides pulse-skipping mode enable/disable control and an external clock input for synchronization of the internal oscillator. Pulling this pin below 1.2V (DC) or driving it with an external logic-level synchronization signal disables pulse-skipping mode operation and forces continuous operation. Pulling the pin above 1.2V enables pulse-skipping mode operation. This pin has an internal 50k pull-down resistor connected to SGND. RUN/SHDN (Pin 16): Enable/Shutdown Input. Pulling this pin above 1.22V enables the controller. Forcing this pin below 1.22V causes the driver outputs to pull low. Pulling this pin below 0.74V forces the LTC3775 into shutdown mode. While in shutdown, the INTVCC regulator and most internal circuitry turns off and the supply current drops below 14μA. This pin has an internal 1μA pull-up current that allows the LTC3775 to power up if this pin is left floating. PGND (Pin 17): Power Ground (Exposed Pad). The BG driver returns to this pin. Connect PGND to the source of the bottom power MOSFET and the VIN and INTVCC bypass capacitors. PGND is electrically isolated from SGND. The exposed pad of the QFN package is connected to PGND. 3775f 8 LTC3775 BLOCK DIAGRAM VIN VIN R5 RUN/SHDN 0.74V – + SHDN CHIP SHUTDOWN 1.22V INTVCC 3.6V – EN + REF – UVLO + CTLIM CBLIM FREQ MODE/SYNC 50k EXT SYNC MODE/SYNC DETECT FB R3 C3 MODE SENSE 0.6V SS + + – ILIMB INTVCC + – + – PGND VILIMB 0.2 • VILIMB PGND INTVCC TG VIN EA LINE FEEDFORWARD FB 0.66V PWM – + RILIMB 10μA BOOST – + VIN RILIMT RSENSE + – MODE ISS COMP C2 100μA INTVCC CSS C1 IREV OSC 1μA SS RA 0.6V ILIMT OVERTEMP RSET INTVCC + IRUN 1μA R4 RB INTVCC 5.2V REG VIN R2 CVCC SWITCH LOGIC AND ANTISHOOTTHROUGH DB CB QT SW INTVCC BG QB PGND L MAX SGND VOUT COUT 3775 BD 3775f 9 LTC3775 APPLICATIONS INFORMATION Operation (Refer to Block Diagram) The LTC3775 is a constant frequency, voltage mode controller for DC/DC step-down converters. It is designed to be used in a synchronous switching architecture with two external N-channel MOSFETs. For circuit operation, please refer to the Block Diagram. The LTC3775 uses voltage mode control in which the duty cycle is controlled directly by the error amplifier output. The error amplifier adjusts the voltage at the COMP pin by comparing the VFB pin with the 0.6V internal reference. When the load current increases, it causes a drop in the feedback voltage relative to the reference. The COMP voltage then rises, increasing the duty cycle until the LTC3775 output feedback voltage again matches the reference voltage. In normal operation, the top MOSFET is turned on when the PWM comparator changes state and is turned off by the internal oscillator. The PWM comparator maintains the proper duty cycle by comparing the error amplifier output (after being “compensated” by the line feedforward multiplier) to a sawtooth waveform generated by the oscillator. When the top MOSFET is turned off, the bottom MOSFET is turned on until the next cycle begins, or if pulse-skipping mode operation is enabled, until the inductor current reverses as determined by the reverse current comparator. Feedback Control The LTC3775 senses the output voltage at VOUT with an internal feedback op amp (see Block Diagram). This is a true op amp with a low impedance output, 80dB of openloop gain and a 25MHz gain-bandwidth product. The positive input is connected to an internal 0.6V reference, while the negative input is connected to the FB pin. The output is connected to COMP, which is in turn connected to the line feedforward circuit and from there to the PWM generator. Unlike many regulators that use a transconductance (gm) amplifier, the LTC3775 is designed to use an inverting summing amplifier topology with the FB pin configured as a virtual ground. This allows the feedback gain to be tightly controlled by external components. In addition, the voltage feedback amplifier allows flexibility in choosing pole and zero locations. In particular, it allows the use of “Type 3” compensation, which provides a phase boost at the LC pole frequency and significantly improves the control loop phase margin. In a typical LTC3775 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. All these components affect loop behavior and need to be accounted for in the loop compensation. The modulator consists of the PWM generator, the output MOSFET drivers and the external MOSFETs themselves. The modulator gain varies linearily with the input voltage. The line feedforward circuit compensates for this change in gain, and provides a constant gain from the error amplifier output to the inductor input regardless of input voltage. From a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from COMP to the inductor input and has a gain roughly equal to 30V/V. It has fairly benign AC behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. The external inductor/output capacitor combination makes a more significant contribution to loop behavior. These components cause a second order LC roll-off at the output with 180° phase shift. This roll-off is what filters the PWM waveform, resulting in the desired DC output voltage, but this phase shift causes stability issues in the feedback loop and must be frequency compensated. At higher frequencies, the reactance of the output capacitor approaches its ESR, and the roll-off due to the capacitor stops, leaving –20dB/decade and 90° of phase shift. At steady state, as shown in the Block Diagram, the output of the switching regulator is given the following equation ⎛ R ⎞ VOUT = VREF • ⎜ 1+ A ⎟ ⎝ RB ⎠ 3775f 10 LTC3775 APPLICATIONS INFORMATION Figure 1 shows a Type 3 amplifier. The transfer function of this amplifier is given by the following equation: ) ( )( )( ) The RC network across the error amplifier and the feedforward components R3 and C3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain frequency, fC. In theory, the zeros and poles are placed symmetrically around fC, and the spread between the zeros and the poles is adjusted to give the desired phase boost at fC. However, in practice, if the crossover frequency is much higher than the LC double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. If conditional stability is a concern, move the error amplifier’s zero to a lower frequency to avoid excessive phase dip. The following equations can be used to compute the feedback compensation component values: fSW = switching frequency fLC = 2π LCOUT 1 2π RESR COUT choose: fC = crossover frequency = ( ) ⎛ fLC ⎞ ⎛ fP2(RES) + ⎜⎝ 1+ f ⎟⎠ ⎜ 1+ f R2 C ⎝ C • ≈ 20 log RA ⎛ fC fLC + ⎜⎝ 1+ f f –f ESR ESR fP2(RES) – fZ2(RES) ⎞ ⎟ fZ2(RES) ⎠ ⎞ ⎛ fP2(RES)) ⎞ ⎟ ⎟ ⎜ 1+ f ⎠ C LC ⎠ ⎝ where AMOD is the modulator and line feedforward gain and is equal to: A MOD ≈ VIN(MAX ) • DCMAX VSAW = 40 V • 0.95 ≈ 30 V/ V 1.25V Once the value of resistor RA and the pole and zero locations have been decided, the values of C1, R2, C2, R3 and C3 can be obtained from the above equations. C2 VOUT C3 RA f 1 fZ2(RES) = C = 5 2π RA + R3 C3 ) 1 fP1(ERR) = fESR = 2πR2(C1|| C2) fP2(RES ) = 5fC = 2 R2 R3 RB VREF C1 – FB + –1 GAIN +1 0 COMP –1 PHASE (DEG) fSW 10 1 fZ1(ERR) = fLC = 2πR2C1 ( 2 ⎛ f ⎞ ⎛ f ⎞ ≈ 40 log 1+ ⎜ C ⎟ – 20 log 1+ ⎜ C ⎟ – 20 log AMOD ⎝ fESR ⎠ ⎝ fLC ⎠ Compensating a switching power supply feedback loop is a complex task. The applications shown in this data sheet show typical values, optimized for the power components shown. Though similar power components should suffice, substantially changing even one major power component may degrade performance significantly. Stability also may depend on circuit board layout. To verify the calculated component values, all new circuit designs should be prototyped and tested for stability. 1 fESR = A V(CROSSOVER) GAIN (dB) ( – 1+ sR2C1 ⎡⎣1+ s(RA + R3)C3 ⎤⎦ VCOMP = VOUT sRA C1+ C2 1+ s(C1|| C2 )R2 1+ sC3R3 Required error amplifier gain at frequency fC: FREQ –90 PHASE –180 BOOST –270 –380 3775 F01 Figure 1. Type 3 Amplifier Compensation 1 2πR3C3 3775f 11 LTC3775 APPLICATIONS INFORMATION Output Overvoltage Protection Soft-Start An overvoltage comparator, MAX, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The LTC3775 includes a soft-start circuit that provides a smooth output voltage ramp during start-up. The SS pin requires an external capacitor, CSS, to GND with the value determined by the required soft-start time. An internal 1μA current source charges CSS. When the voltage on the SS pin is less than the 0.6V internal reference, the LTC3775 regulates the VFB voltage to the SS pin voltage instead of the 0.6V reference. As the SS voltage rises linearly from 0V to 0.6V and beyond, the output voltage, VOUT , rises smoothly from zero to its final value. The total soft-start time can be calculated as: Run/Shutdown The LTC3775 can be put into a low power shutdown mode with quiescent current <14μA by pulling the RUN/SHDN pin below 0.74V. The RUN/SHDN pin can also be used as an accurate external UVLO (undervoltage lockout) input with a threshold of 1.22V. The driver outputs stay low if this pin is <1.22V. The external resistive divider R4 and R5 shown in the Block Diagram can be used to set the UVLO level based on VIN. The VIN voltage at which the switching starts is given by the following formula: UVLO (Upper) = 1.22V • (1 + R4/R5) – (1μA • R4) The RUN/SHDN pin has an internal 1μA pull-up for default turn-on if this pin is left floating. This 1μA pull-up current is included in the above UVLO calculation. When RUN/SHDN goes above 1.22V, this pull-up current is increased to 5μA. This provides some amount of hysteresis to the UVLO threshold. The lower UVLO level becomes: UVLO (Lower) = 1.22V • (1 + R4/R5) – (5μA • R4) So the amount of hysteresis is given by: t SOFTSTART = 0.9 • CSS 1μA The SS pin is pulled low in the following conditions: during an LDO undervoltage condition (INTVCC < 3.6V), during shutdown (RUN pin < 1.22V), during an overtemperature condition (TJ > 165°C) and during current limit. If either the top or bottom current limit comparator trips, the SS pin is pulled low until the inductor current regulates at around the current limit setting. Once the fault is cleared, SS will start charging up allowing the duty cycle and output voltage to increase gradually. Due to the current limit action on the SS pin, it is important to avoid an overcurrent condition during start-up of the power supply, or VOUT will fail to start up properly. UVLO (Hysteresis) = 4μA • R4 SWITCHOVER FROM PULSESKIPPING TO CONTINUOUS MODE VOUT 0.5V/DIV LTC3775 IL 5A/DIV VIN R4 R5 IRUN 1μA RUN 4μA 1.22V 0.74V – + TURN OFF TG EN – + CHIP SHUTDOWN SHDN 3775 F02 Figure 2. RUN Pin Control VSS 1V/DIV 2ms/DIV VIN = 12V VOUT = 1.2V CSS = 0.01μF MODE = 0V SW FREQ = 500kHz 3775 F03 Figure 3. Typical Start-Up Wavform for a Buck Converter Using the LTC3775 3775f 12 LTC3775 APPLICATIONS INFORMATION To prevent discharging a pre-biased VOUT, the LTC3775 always starts switching in pulse-skipping mode up to SS = 0.54V, regardless of the mode selected by the MODE/SYNC pin. Thus if VOUT > 0V during power-up, VOUT will remain at the pre-biased voltage (if there is no load) until the SS voltage catches up with VOUT, after which VOUT will track the SS ramp. The LTC3775 reverts to the selected mode once SS > 0.54V. Constant Switching Frequency The internal oscillator can be programmed from 250kHz to 1MHz with an external resistor from the FREQ pin to ground, in order to optimize component size, efficiency and noise for the specific application. The internal oscillator can also be synchronized to an external clock connected to the MODE/SYNC pin and can lock to a range of ±20% of the programmed free-running frequency. When locked to an external clock, pulse-skipping mode operation is automatically disabled. Constant frequency operation offers a number of benefits: inductor and capacitor values can be chosen for a precise operating frequency and the feedback loop can be similarly tightly specified. Noise generated by the circuit will always be at known frequencies. Subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the LTC3775. Thermal Shutdown The LTC3775 has a thermal detector that pulls the driver outputs low if the junction temperature of the chip exceeds 165°C. The thermal shutdown circuit has 25°C of hysteresis. is low during its on-time, the voltage drop from the drain to source is proportional to the current flow. Alternatively, for better accuracy, the topside current may be monitored with a sense resistor. The benefit of having two comparators is to allow continuous monitoring and cycle-by-cycle control of the inductor current regardless of the operating duty cycle. In high duty cycle operation the top MOSFET, QT , is on most of the time. Thus, a high side comparator is necessary to limit the output current during high duty cycle operation. Architectures that contain only one comparator to monitor the low side MOSFET will not effectively limit the output current during high duty cycle operation. Conversely, during low duty cycle operation, a low side comparator is necessary to limit the output current. Another common current sensing scheme uses a sense resistor in series with the inductor to allow continuous monitoring. However, this scheme restricts the range of VOUT due to the common mode range of the current limit comparator. The LTC3775 does not have this VOUT restriction. Figure 4 shows the current limit circuitry. The top current limit comparator, CTLIM monitors the current through the top MOSFET, QT , when TG is high. If the inductor current exceeds the current limit threshold when QT is on, QT turns off immediately and the bottom MOSFET, QB, turns on. The SENSE pin is the input for CTLIM. For applications where LTC3775 VIN CTLIM TURN OFF TG ILIMT + – 100μA TG RSENSE QT SENSE (OPT) 10μA ILIMB Current Limit CBLIM EXTEND BG 0.2 • VILIMB – + RILIMB SW VOUT + The LTC3775 includes an onboard cycle-by-cycle current limit circuit that limits the maximum output current to a user-programmed level. The current limit circuit consists of two comparators, CTLIM and CBLIM that monitor the voltage drop across the top and bottom MOSFETs respectively. Since the MOSFET ’s effective resistance, RDS(ON), VIN RILIMT PGND BG QB SGND 3775 F04 Figure 4. LTC3775 Current Limit Circuit 3775f 13 LTC3775 APPLICATIONS INFORMATION the upper MOSFET ’s RDS(ON) is used to sense current, connect the SENSE pin to the source of QT (the SW node). Alternatively, for accurate current sensing, connect this pin to a sense resistor located at the drain of QT . The reference input of CTLIM is connected to the ILIMT pin. Connect an external resistor, RILIMT , from the ILIMT pin to VIN to set the the current limit threshold. The voltage at the SENSE pin drops as the inductor current increases. CTLIM trips if the voltage at the SENSE pin goes below the voltage at the ILIMT pin causing TG to pull low and turn off QT . The bottom current limit comparator, CBLIM, monitors the current through the bottom MOSFET, QB, when BG is high. If the inductor current exceeds the current limit threshold when QB is on, QB remains on until the current drops below the threshold. The SW pin is the input for CBLIM. The reference input to CBLIM is derived from the voltage at the ILIMB pin. Connect an external resistor, RILIMB, from the ILIMB pin to SGND to set the current limit threshold. The inductor current flows from PGND to SW when QB is on (for a postitive load current). The SW node is therefore a negative voltage. The LTC3775 inverts the voltage at the SW pin before comparing it with the attenuated voltage (5×) at the ILIMB pin. BG stays high once CBLIM trips and TG remains low until the inductor current drops below the threshold. Figure 5 shows typical waveforms during output overload. IL 20A/DIV 0A LOAD VSS 1V/DIV 20μs/DIV VIN = 12V VOUT = 1.2V CSS = 0.01μF FIRST PAGE CIRCUIT 3775 F05 Figure 5. Typical Waveforms During Output Overload Current Limit Blanking Time The LTC3775 current limit circuit features a short blanking time following low-to-high and high-to-low transitions at the SW node. This prevents false tripping of the current limit circuit if there is ringing on the SW node. When the top gate, TG, goes high, the topside comparator, CTLIM, waits for 200ns before turning on to monitor the SENSE voltage. Likewise, when the bottom gate, BG, goes high the bottom side comparator, CBLIM, waits for 200ns before turning on to monitor the SW voltage. This means that the minimum TG and BG pulse is slightly more than 200ns during current limit. These blanking times do not, however, limit the duty cycle capability of the control loop. The LTC3775 control loop is capable of operation with a TG on-time as low as 30ns. If a sense resistor is employed on the top side, the LTC3775 automatically lowers the CTLIM blanking time from 200ns to 100ns. The CBLIM blanking time remains at 200ns. The blanking time can be reduced when a sense resistor is used because the SENSE pin connects to the drain of the top MOSFET which rings less than the SW node. The LTC3775 detects that a sense resistor is employed by checking that the SENSE pin stays high (equal to VIN) when BG is high. If the SENSE pin is connected to the SW node, SENSE will be at 0V when BG is high. The Current Sensing Input Pins The SENSE and ILIMT pins are inputs to the top current limit comparator, CTLIM. The top current limit threshold is set by the resistor, RILIMT , connected to the ILIMT pin and the ILIMT pin 100μA pull-down current. RILIMT should be placed close to the LTC3775 and the other end of RILIMT should run parallel with the SENSE trace to the Kelvin sense connection underneath the sense resistor, as shown in Figure 6. The sense resistor should be connected to the drain of the top power MOSFET and the VIN node using short, wide PCB traces. Ideally, the top terminal of the sense resistors will be immediately adjacent to the positive terminal of the input capacitor, as shown in Figure 7a. This path is a part of the high di/dt loop formed by the sense resistor, top power MOSFET, inductor and output capacitor. 3775f 14 LTC3775 APPLICATIONS INFORMATION Since the current limit comparator contains leading edge blanking, an external RC filter is not required for proper operation. However, an external filter can be designed by adding a capacitor across the SENSE and ILIMT pins (CF in Figure 7a). The filter component should be placed close to the SENSE and ILIMT pins. If RDS(ON) sensing is employed, the Kelvin sense connection should run from the SENSE pin and the RILIMT resistor to the source and drain terminals of the top power MOSFET respectively, as shown in Figure 7b. The external RC filter should not be added since the source terminal is switching. VIN TO RLIMIT RSENSE TO SENSE PIN 3775 F06 TOP MOSFET DRAIN Figure 6. Kelvin SENSE Connection for Topside Current Limiting Sensing VIN VIN CIN LTC3775 RLIMIT ILIMIT The bottom side current limit threshold is set by the resistor, RILIMB, from the ILIMB pin to SGND and the ILIMB pin 10μA pull-up current. The voltage at ILIMB is attenuated 5× internally before it is applied to the input of bottom current limit comparator, CBLIM. This voltage must be quiet. Connect RILIMB from the ILIMB pin to a quiet ground near the LTC3775 SGND pin. The other input of CBLIM is connected to the SW pin. The SW pin is also shared with the bottom gate driver and should be connected near the drain of the bottom MOSFET, QB. Pulse-Skipping Mode The LTC3775 can operate in one of two modes selectable with the MODE/SYNC pin: pulse-skipping mode or forced continuous mode. Pulse-skipping mode is selected when increased efficiency at light loads is desired, as shown in Figure 8. In this mode, the bottom MOSFET is turned off when inductor current reverses in order to minimize the efficiency loss due to reverse current flow. As the load current decreases (see Figure 9), the duty cycle is reduced to maintain regulation until the minimum on-time (50ns) is reached. When the load decreases below this point, the LTC3775 begins to skip cycles to maintain regulation. This reduces the frequency and improves efficiency by minimizing gate charge losses. In forced continuous mode, the bottom MOSFET is always on when the top MOSFET is off, allowing the inductor current to reverse at low currents. This mode is less efficient due to switching, but has the advantages of better transient RSENSE CF 100 SENSE 90 TG 80 SW Figure 7a. External Filter for Topside Current Sensing VIN VIN CIN LTC3775 70 60 50 PULSE-SKIPPING MODE 40 CONTINUOUS MODE 30 20 RLIMIT 10 ILIMIT QT TG SENSE 3775 F07b EFFICIENCY (%) 3775 F07a VIN = 12V VOUT = 1.2V SW FREQ = 500kHz FRONT PAGE CIRCUIT SW Figure 7b. Kelvin Connection for Topside RDS(ON) Sensing 0 0.01 0.1 1 10 LOAD CURRENT (A) 100 3775 F08 Figure 8. Efficiency in Pulse-Skipping/Forced Continuous Modes 3775f 15 LTC3775 APPLICATIONS INFORMATION PULSE-SKIPPING MODE FORCED CONTINUOUS 0A 0A 0A 0A 0A 0A DECREASING LOAD CURRENT 3775 F09 Figure 9. Comparison of Inductor Current Waveforms for Pulse-Skipping Mode and Forced Continuous Mode response at low load currents, constant frequency operation, and the ability to maintain regulation when sinking current. See Figure 8 for a comparison of the efficiency at light loads for each mode. In pulse-skipping mode, the LTC3775 reverse-current comparator, IREV , monitors the SW pin for zero crossing when the bottom gate, BG, is high. It turns off BG if the inductor current reverses and the SW voltage goes above GND. To prevent false tripping due to ringing on the SW node when BG is first turned on, there is a blanking time of 200ns similar to the bottom side current limit blanking. Under certain light load conditions, if the TG on-time is short, the inductor current may reverse during the IREV blanking time but the LTC3775 will only turn off BG after the blanking time. In applications where a low value inductor is used, the high di/dt of the inductor ripple current together with the parasitic series inductance of the bottom MOSFET, QB, and PCB trace inductance creates an opposing voltage to the voltage drop across the RDS(ON) of QB. This can cause IREV to trip early, before the inductor current reverses. The parasitic series inductance of the PCB trace can be minimized by connecting the SW pin closer to the drain of QB. INTVCC Regulator The LTC3775 features a P-channel low dropout linear regulator (LDO) that supplies power to the INTVCC pin from the VIN supply. INTVCC powers the gate drivers and much of the LTC3775’s internal circuitry. The LDO regulates the voltage at the INTVCC pin to 5.2V when VIN is greater than 6.5V. The INTVCC pin must be bypassed to ground with a low ESR (X5R or better) ceramic capcitor of at least 4.7μF. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers. An internal undervoltage lockout (UVLO) monitors the voltage on INTVCC to ensure that the LTC3775 has sufficient gate drive voltage. If the INTVCC voltage falls below the UVLO threshold of 3.1V, the gate drive outputs remain low. Thermal Considerations The LTC3775 is offered in a 3mm × 3mm QFN package (UD16) that has a thermal resistance RTH(JA) of 68°C/W. The UD16 package has a lead pitch of 0.5mm. The regulator can supply up to 50mA of gate drive load current. The expected LDO load current can be calculated from the gate charge requirement of the external MOSFET: IINTVCC = (fSW) • (QG(QT) + QG(QB)) + 3.5mA where: 3.5mA is the quiescent current of LTC3775 QG(QT) is the total gate charge of the top MOSFET QG(QB) is the total gate charge of the bottom MOSFET fSW is the switching frequency 3775f 16 LTC3775 APPLICATIONS INFORMATION Care must be taken to ensure that the maximum junction temperature of the LTC3775 is never exceeded. The junction temperature can be estimated using the following equations: PDISS = VIN • IINTVCC TJ = TA + PDISS • RTH(JA) As an example of the required thermal analysis, consider a buck converter with a 24V input voltage and an output voltage of 3.3V at 15A. The switching frequency is 500kHz and the maximum ambient temperature is 70°C. The power MOSFET used for this application is the Vishay Siliconix Si7884DP, which has a typical RDS(ON) of 7.5mΩ at VGS = 4.5V and 5.5mΩ at VGS = 10V. From the plot of VGS vs QG, the total gate charge at VGS = 5V is 18.5nC (the temperature coefficient of the gate charge is low). One power MOSFET is used for the top side and one for the bottom side. For the UD package: IINTVCC = 3.5mA + 2 • 18.5nC • 500kHz = 22mA PDISS = 24V • 22mA = 528mW TJ = 70°C + 528mW • 68°C/W = 105.9°C In this example, the junction temperature rise is 35.9°C. These equations demonstrate how the gate charge current typically dominates the quiescent current of the IC, and how the choice of the operating frequency and board heat sinking can have a significant effect on the thermal performance of the solution. To prevent the maximum junction temperature from being exceeded, the input supply current of the IC should be checked when operating in continuous mode (heavy load) at maximum VIN. A tradeoff between the operating frequency and the size of the power MOSFETs may need to be made in order to maintain a reliable junction temperature. Finally, it is important to verify the calculations by performing a thermal analysis of the final PCB using an infrared camera or thermal probe. Operation at Low Supply Voltage The LTC3775 has a minimum input voltage of 4.5V. The gate driver for the LTC3775 consists of a PMOS pull-up and an NMOS pull-down device, allowing the full INTVCC voltage to be applied to the gates during power MOSFET switching. Nonetheless, care should be taken to determine the minimum gate drive supply voltage (INTVCC) in order to choose the optimum power MOSFETs. Important parameters that can affect the minimum gate drive voltage are the minimum input voltage (VIN(MIN)), the LDO dropout voltage, the QG of the power MOSFETs, and the operating frequency. If the input voltage VIN is low enough for the INTVCC LDO to be in dropout, then the minimum gate drive supply voltage is: VINTVCC = VIN(MIN) – VDROPOUT The LDO dropout voltage is a function of the total gate drive current and the quiescent current of the IC (typically 3.5mA). A curve of dropout voltage versus output current for the LDO is shown in Figure 10. The temperature coefficient of the LDO dropout voltage is approximately 6000ppm/°C. See the INTVCC Regulator and Thermal Considerations sections for information about calculating the total quiescent current. 0 INTVCC DROPOUT VOLTAGE (V) The value of QG should come from the plot of VGS vs QG in the Typical Performance Characteristics section of the MOSFET data sheet. The value listed in the electrical specifications may be measured at a higher VGS, such as 10V, whereas the value of interest is at the 5V INTVCC gate drive voltage. TA = 25°C –0.2 –0.4 –0.6 –0.8 –1.0 0 10 30 40 20 INTVCC LOAD CURRENT (mA) 50 3775 F10 Figure 10. INTVCC LDO Dropout Voltage vs Current 3775f 17 LTC3775 APPLICATIONS INFORMATION After the calculations have been completed, it is important to measure the gate drive waveforms and the gate driver supply voltage (INTVCC to PGND) over all operating conditions (low VIN, nominal VIN and high VIN, as well as from light load to full load) to ensure adequate power MOSFET enhancement. Consult the power MOSFET data sheet to determine the actual RDS(ON) for the measured VGS, and verify your thermal calculations by measuring the component temperatures using an infrared camera or thermal probe. TG 10V/DIV VSW 10V/DIV VIN = 28V 20ns/DIV VOUT = 0.6V LOAD = 1A MODE/SYNC = 0V SW FREQ = 1MHz Operation at High Supply Voltage At high input voltages, the LTC3775’s internal LDO can dissipate a significant amount of power, which could cause the maximum junction temperature to be exceeded. Conditions such as a high operating frequency, or the use of more than one power MOSFET in parallel, could push the junction temperature rise to high levels. To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode at maximum VIN. See the Thermal Considerations section for calculation of the maximum junction temperature. 3775 F11 Figure 11. Minimum On-Time Waveforms in Forced Continuous Mode TG 10V/DIV VSW 10V/DIV Low Duty Cycle Operation The LTC3775 uses a leading edge modulation architecture. Because the top MOSFET turns on when the PWM comparator trips, the top MOSFET minimum on-time is not dependent on the propagation delay of the PWM comparator; it is only limited by the internal delays of the gate drivers and the rise/fall time of the power MOSFET gate. This allows the LTC3775 to operate in very low duty cycle applications with a large step-down ratio. Figure 11 shows minimum on-time waveforms for forced continuous mode operation. If pulse-skipping mode is selected, the LTC3775 allows the controller to skip pulses at light load, thereby reducing switching losses and improving the efficiency. Figure 12 shows waveforms of the minimum on-time in pulse-skipping mode. If the TG on-time is less than the blanking time of the topside current limit comparator, CTLIM, the topside comparator never trips during normal operation. The blanking time VIN = 28V 20ns/DIV VOUT = 0.6V LOAD = 1A MODE/SYNC = INTVCC SW FREQ = 1MHz 3775 F12 Figure 12. Minimum On-Time Waveforms in Pulse-Skipping Mode is 200ns for RDS(ON) sensing and 100ns when a sense resistor is used. For TG on-times smaller than the topside blanking times, the LTC3775 relies on the bottom current limit comparator, CBLIM, to monitor the inductor current. If CBLIM trips, the LTC3775 starts to skip pulses and at the same time pulls down the soft-start capacitor to limit the duty cycle. If VOUT drops sufficiently, the TG on-time can increase enough to turn on CTLIM and limit the peak inductor current. The minimum on-time of the application circuit can be calculated at maximum VIN: tON(MIN) = VOUT fSW • VIN(MAX ) 3775f 18 LTC3775 APPLICATIONS INFORMATION High Duty Cycle Operation The maximum duty cycle is limited by the LTC3775 internal oscillator reset time, the propagation delay of the PWM comparator and the BOOST pin supply refresh rate. The minimum off-time is typically 300ns. The top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage, VIN, decreases to a voltage close to VOUT , the controller will enter dropout and attempt to turn on the top MOSFET continuously. To avoid depleting the charge on the bootstrap capacitor, CB, the LTC3775 has an internal counter that turns on the bottom MOSFET every eight cycles for 200ns to refresh the bootstrap capacitor. Figure 13 shows maximum duty cycle operation with the 200ns BOOST pin supply refresh. step-down VIN to VOUT ratios, another consideration is the minimum on-time of the LTC3775 (see the Minimum On-Time Considerations section). A final consideration for operating frequency is that in noise-sensitive communications systems, it is often desirable to keep the switching noise out of a sensitive frequency band. The LTC3775 uses a constant frequency architecture that can be programmed over a 250kHz to 1MHz range with a single resistor from the FREQ pin to ground, as shown in Figure 14. The nominal voltage on the FREQ pin is 1.22V, and the current that flows from this pin is used to charge and discharge an internal oscillator capacitor. The value of RSET for a given operating frequency can be chosen from Figure 14 or from the following equation: RSET (kΩ) = 19500 f(kHz) The oscillator can also be synchronized to an external clock applied to the MODE/SYNC pin with a frequency in the range of ±20% of the programmed free-running frequency set by the FREQ pin. In this synchronized mode, pulse-skipping mode operation is disabled. The clock high level must exceed 1.5V for at least 25ns. The bottom MOSFET will turn-on following the rising edge of the external clock. TG 5V/DIV OSCILLATOR RESET BOOST PIN SUPPLY REFRESH BG 5V/DIV 1000 Figure 13. Maximum Duty Cycle Waveforms EXTERNAL COMPONENTS SELECTION 900 800 FREQUENCY (kHz) VIN = 4.5V 2μs/DIV VOUT = 4.2V LOAD = 0A SW FREQ = 500kHz 3775 F13 700 600 500 400 Operating Frequency 300 The choice of operating frequency and inductor value is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses and gate charge losses. However, lower frequency operation requires more inductance for a given amount of ripple current, resulting in a larger inductor size and higher cost. If the ripple current is allowed to increase, larger output capacitors may be required to maintain the same output ripple. For converters with high 200 0 10 20 30 40 50 60 70 80 90 100 RSET VALUE (kΩ) 3775 F14 Figure 14. Frequency Set Resistor (RSET) Value Top MOSFET Driver Supply An external bootstrap capacitor, CB, connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from 3775f 19 LTC3775 APPLICATIONS INFORMATION INTVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store at least 100 times the gate charge required by the top MOSFET. In most applications a 0.1μF to 1μF X5R or X7R dielectric capacitor is adequate. The reverse breakdown of the Schottky diode, DB, must be greater than VIN(MAX). Power MOSFET Selection The LTC3775 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the threshold voltage V(GS)TH, breakdown voltage V(BR)DSS, maximum current IDS(MAX), on-resistance RDS(ON) and input capacitance. The gate drive voltage is set by the 5.2V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3775 applications. If the INTVCC voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be considered. Pay close attention to the V(BR)DSS specification because most logic-level MOSFETs are limited to 30V or less. The MOSFETs selected should have a V(BR)DSS rating greater than the maximum input voltage and some margin should be added for transients and spikes. MOSFET input capacitance is a combination of several components but can be taken from the typical “gate charge” curve included on most data sheets (Figure 15). The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate VIN VGS MILLER EFFECT a CMILLER = (QB – QA)/VDS When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Top Gate Duty Cycle = VOUT VIN ⎛V –V ⎞ Bottom Gate Duty Cycle = ⎜ IN OUT ⎟ ⎝ ⎠ VIN The power dissipation for the top and bottom MOSFETs at maximum output current are given by: PTOP = ( )( )( VOUT 2 ρ I T( TOP) RDS(ON)(MAX ) VIN OUT(MAX ) ) ⎛ IOUT(MAX ) ⎞ + VIN2 ⎜ ⎟ RDR CMILLER • 2 ⎝ ⎠ ( )( ) ⎛ 1 ⎞ 1 + ⎜ ⎟ • fSW ⎝ INTVCC – VTH(IL ) VTH(IL ) ⎠ PBOT = ( )( )( VIN – VOUT IOUT(MAX )2 ρT(TOP) RDS(ON)(MAX ) VIN ) V b QIN capacitance as the drain voltage drops. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. To estimate the capacitance CMILLER, take the change in gate charge from points a and b on a manufacturer’s data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. + VGS +V DS – – 3775 F15 Figure 15. Gate Charge Characteristics where: RDR = Effective top driver resistance VTH(IL) = MOSFET data sheet specified typical gate threshold voltage at the specified drain current 3775f 20 LTC3775 APPLICATIONS INFORMATION CMILLER = Calulated Miller capacitance using the gate charge curve from the MOSFET data sheet fSW = Switching frequency Both MOSFETs have conduction losses (I2R) while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 12V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 12V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The bottom MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the bottom switch is on close to 100% of the period. Schottky Diode Selection An optional Schottky diode connected between the SW node (cathode) and the source of the bottom MOSFET (anode) conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing a charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed next to each other on the same layer of the PC board. Input Capacitor Selection The input bypass capacitor has three primary requirements: its ESR must be low to minimize the supply drop when the top MOSFETs turn on, its RMS current capability must be adequate to withstand the ripple current at the input, and its capacitance must be large enough to maintain the input voltage until the input supply can respond. Generally, a capacitor (particularly a non-ceramic type) that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. The input capacitor’s voltage rating should be at least 1.4 times the maximum input voltage. In continuous mode, the source current of the top N-channel MOSFET is approximately a square wave of duty cycle VOUT/ VIN. The maximum RMS capacitor current is given by: IRMS ≈ IOUT(MAX) VOUT ( VIN – VOUT ) VIN This formula has a maximum at VIN = 2VOUT , where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. Medium voltage (20V to 35V) ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have high voltage coefficients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytics’ higher ESR and dryout may require several to be used in parallel. Sanyo OS-CON SVP, SVPD series; Sanyo POSCAP TQC series or aluminum electrolytic capacitors from Panasonic WA series or Cornel Dublilier SPV series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low ESR and high bulk capacitance. Output Capacitor Selection The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ΔVOUT is approximately bounded by: ⎛ ⎞ 1 ΔVOUT ≤ ΔIL ⎜ ESR + 8 • fSW • COUT ⎟⎠ ⎝ where ΔIL is the inductor ripple current. 3775f 21 LTC3775 APPLICATIONS INFORMATION ΔIL may be calculated using the equation: ΔIL = VOUT ⎛ VOUT ⎞ 1– L • fSW ⎜⎝ VIN ⎟⎠ Since ΔIL increases with input voltage, the output ripple voltage is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Manufacturers such as Sanyo, Panasonic and Cornell Dublilier should be considered for high performance through-hole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has a good (ESR)(size) product. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to offset the effect of lead inductance. In surface mount applications, multiple capacitors may have to be connected in parallel to meet the ESR or transient current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent output capacitor choices are the Sanyo POSCAP TPD, POSCAP TPB, AVX TPS, AVX TPSV, the Kemet T510 series of surface mount tantalums,Kemet AO-CAPs or the Panasonic SP series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. current. Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency is obtained at low frequency with small ripple current. However, achieving high efficiency requires a large inductor and generates higher output voltage excursion during load transients. There is a tradeoff between component size, efficiency and operating frequency. Given a specified limit for ripple current, the inductor value can be obtained using the following equation: L= ⎛ ⎞ VOUT V • ⎜ 1 – OUT ⎟ fSW • ΔIL(MAX) ⎝ VIN(MAX) ⎠ Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mμ® cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. See the Curret Limit Programming section for calculation of the inductor saturation current. Current Limit Programming If current sensing is implemented with a sense resistor, the topside current limit can be programmed by setting RILIMT as follows: RILIMT = CF • RSENSE • IO(MAX ) + 0.5 • ΔIL ILIMIT(MIN) where: RSENSE = Sense resistor value IO(MAX) = Maximum output current Inductor Selection The inductor in a typical LTC3775 application circuit is chosen based on the required ripple current, its size and its saturation current rating. The inductor should not be allowed to saturate below the hard current limit threshold. The inductor value sets the ripple current, which is commonly chosen at around 40% of the anticipated full load ΔIL = Inductor ripple current (refer to the Output Capacitor Selection section). ILIMT(MIN) = ILIMT pin minimum pull-down current of 90μA CF = Correction factor to provide safety margin and account for RSENSE tolerance; use a value of CF = 1.2 is reasonable. 3775f 22 LTC3775 APPLICATIONS INFORMATION RILIMIT = ρT • RDS(ON)(QT )(MAX ) • IO(MAX ) + 0.5 • ΔIL ILIMIT(MIN) RDS(ON)(QT)(MAX) is the maximum MOSFET on-resistance typically specified at 25°C. The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.5%/°C as shown in Figure 16. For a maximum junction temperature of 100°C, using a value ρT = 1.4 is reasonable. The bottom side current limit can be programmed by setting RILIMB as follows: RILIMB = 5 • ρT • RDS(ON)(QB)(MAX ) • IO(MAX ) + 0.5 • ΔIL ILIMB(MIN) where ILIMB(MIN) = ILIMB pin minimum pull-up current of 9μA. The resulting values of RILIMT and RILIMB should be checked in an actual circuit to ensure that the current limit kicks in as expected. Circuits that use MOSFETs with low value RDS(ON) for current sensing should be checked carefully. The PCB trace resistance and parasitic inductance can significantly change the actual current limit threshold. Care should be taken to shorten the PCB trace at the SENSE, SW and PGND connections. The current limit setting also determines the worst-case peak current flowing in the inductor during an overload condition. The inductor saturation current rating needs to be higher than the worst-case peak inductor current: IL(SAT) ≥ ILIMT(MAX ) • RILIMT RSENSE(MIN) or IL(SAT) ≥ ILIMT(MAX ) • RILIMT RDSON(QT )(MIN) ILIMT(MAX) = ILIMT pin maximum pull-down current of 110μA ILIMB(MAX) = ILIMB pin maximum pull-up current of 11μA RDS(ON)(QT)(MIN) and RDS(ON)(QB)(MIN) are the power MOSFET minimum on-resistances. MOSFET data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) is the same percentage below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. The saturation current rating for the inductor should be determined at the maximum input voltage, maximum output current and the maximum expected core temperature. The saturation current ratings for most commercially available inductors drop at high temperature. To verify safe operation, it is a good idea to characterize the inductor’s core/winding temperature under the following conditions: 1) worst-case operating conditions, 2) maximum allowable ambient temperature and 3) with the power supply mounted in the final enclosure. Thermal characterization can be done by placing a thermocouple in intimate contact with the winding/core structure, or by burying the thermocouple within the windings themselves. 2.0 RT NORMALIZED ON-RESISTANCE If topside MOSFET RDS(ON) sensing is used, the RILIMT value is calculated from the following equation: 1.5 1.0 0.5 0 –50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3775 F16 Figure 16. Typical MOSFET RDS(ON) vs Temperature or IL(SAT ) ≥ (0.2 • ILIMB(MAX) ) • RILIMB RDSON(QB)(MIN) 3775f 23 LTC3775 APPLICATIONS INFORMATION MODE/SYNC Pin The MODE/SYNC pin is a dual function pin that can be used to program the operating mode or to synchronize the switching frequency to an external clock. Pulseskipping mode is enabled when the MODE/SYNC pin is above 1.2V. The mode is forced continuous when the pin is below 1.2V. If this pin is left floating, an internal 50k pull-down resistor defaults the selection to forced continuous mode. During power-up, the LTC3775 overrides this mode selection and operates in pulse-skipping mode to prevent the discharge of a pre-biased output capacitor. The internal LTC3775 oscillator can be synchronized to an external clock with a signal greater than 1.5V . A low-to-high transition on the MODE/SYNC pin resets the oscillator sawtooth waveform (high) and forces TG low (see Figure 17).The external oscillator frequency must be within ±20% of the frequency programmed by the RSET resistor, or else the part will revert to free-running mode. The internal oscillator locks to the external clock after the second clock transition is received. When external synchronization is detected, the LTC3775 will operate in forced continuous mode. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3775. Check the following in your layout: 1. Keep the signal and power grounds separate. The signal ground consists of the LTC3775 SGND pin and the (–) terminal of VOUT . The power ground consists of the optional Schottky diode anode, the source of the bottom side MOSFET, and the (–) terminal of the input capacitor. Connect the signal ground to the (–) terminal of the output capacitor. Also, try to connect the (–) terminal of the output capacitor as close as possible to the (–) terminals of the input capacitor. 2. The high di/dt loop formed by the top N-channel MOSFET, the bottom MOSFET and the CIN capacitor should have short leads and PC trace lengths to minimize high frequency noise and voltage stress from inductive ringing. 3. Connect the drain of the topside MOSFET directly to the (+) plate of CIN, and connect the source of the bottom side MOSFET directly to the (–) terminal of CIN. This capacitor provides the AC current to the MOSFETs. 4. Place the ceramic CINTVCC decoupling capacitor immediately next to the IC, between INTVCC and SGND. Likewise, the CB capacitor should also be next to the IC between BOOST and SW. 5. Place the small-signal components away from high frequency switching nodes (BOOST, SW, TG and BG). 6. For optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC3775 in order to keep the high impedance FB node short. 7. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC3775 is not shared with other converters. AC input current from another converter could cause substantial input voltage EXTERNAL CLOCK AT MODE/SYNC PIN PWM RAMP TG 3775 F17 Figure 17. External Synchronization 3775f 24 LTC3775 APPLICATIONS INFORMATION ripple, and this could interfere with the operation of the LTC3775. A few inches of PC trace or wire (L ≅ 100nH) between CIN of the LTC3775 and the actual source VIN should be sufficient to prevent input noise interference problems. 8. The top current limit programming resistor, RILIMT , should be placed close to the LTC3775 and the other end of RILIMT should run parallel to the SENSE trace to the Kelvin sense connection underneath the sense resistor. 9. The bottom current limit programming resistor, RILIMB, should be placed close to the LTC3775 and the other end of RILIMB should connect to SGND. 10. The SW pin should be connected to the drain of the bottom MOSFET. Checking Transient Response For all new LTC3775 PCB circuits, transient tests need to be performed to verify the proper feedback loop operation. The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ΔILOAD • (ESR), where ESR is the effective series resistance of COUT . ΔILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for excessive overshoot or ringing which would indicate a stability problem. Measuring transient response presents a challenge in two respects: obtaining an accurate measurement and generating a suitable transient for testing the circuit. Output measurements should be taken with a scope probe directly across the output capacitor. Proper high frequency probing techniques should be used. Do not use the 6" ground lead that comes with the probe! Use an adapter that fits on the tip of the probe and has a short ground clip to ensure that inductance in the ground path doesn’t cause a bigger spike than the transient signal being measured. The typical probe tip ground shield is spaced just right to span the leads of a typical output capacitor. In general, it is best to take this measurement with the 20MHz bandwidth limit on the oscilloscope turned on to limit high frequency noise. Note that microprocessor manufacturers typically specify ripple ≤20MHz, as energy above 20MHz is generally radiated (and not conducted) and does not affect the load even if it appears at the output capacitor. Now that we know how to measure the signal, we need to have something to measure. The ideal situation is to use the actual load for the test, switching it on and off while watching the output. If this isn’t convenient, a current step generator is needed. This generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the LTC3775 and the transient generator must be minimized. Figure 18 shows an example of a simple transient generator. Be sure to use a noninductive resistor as the load element. Many power resistors use an inductive spiral pattern and are not suitable for use here. A simple solution is to take ten 1/4W film resistors and wire them in parallel to get the desired value. This gives a noninductive resistive load which can dissipate 2.5W continuously or 250W if pulsed with a 1% duty cycle, enough for most LTC3775 circuits. Solder the MOSFET and the resistor(s) as close to the output of the LTC3775 circuit as possible and set up the signal generator to pulse at a 100Hz rate with a 1% duty cycle. This pulses the LTC3775 with 100μs transients 10ms apart, adequate for viewing the entire transient recovery time for both positive and negative transitions while keeping the load resistor cool. VOUT LTC3775 RLOAD PULSE GENERATOR 507 IRFZ44 OR EQUIVALENT 10k 0V TO 10V 100Hz, 1% DUTY CYCLE 3775 F18 LOCATE CLOSE TO THE OUTPUT Figure 18. Transient Load Generator 3775f 25 LTC3775 APPLICATIONS INFORMATION Design Example As a design example, take a supply with the following specifications: VIN = 5V to 26V (12V nominal), VOUT = 1.2V ±5%, IOUT(MAX) = 15A, f = 500kHz. First, verify the minimum on-time which occurs at maximum VIN: tON(MIN) = 1.2V = 92.3ns (26V )(500kHz ) The minimum on-time is lower than the top current limit comparator blanking time of 100ns with sense resistor sensing. The controller will rely on the bottom MOSFET RDS(ON) sensing at high VIN. Next, verify the maximum duty cycle which occurs at minimum VIN: 1.2V Maximum Duty Cycle = = 24% 5V This is below the LTC3775 maximum duty cycle of 90%. Next, calculate RSET to give the 500kHz operating frequency: RSET = 19500 = 39k 500 Next, choose the inductor value for about 40% ripple current at maximum VIN: L= 1.2V ⎛ 1.2 ⎞ 1– = 0.38μH (500kHz )(0.4)(15A ) ⎜⎝ 26 ⎟⎠ Select 0.36μH which is the nearest standard value. The resulting maximum ripple current is: ΔIL = 1.2V ⎛ 1.2V ⎞ 1– = 6.4A (500kHz )(0.36μH) ⎜⎝ 26V ⎟⎠ Next, choose the top and bottom MOSFET switch. Since the drain of each MOSFET will see the full supply voltage 26V (max) plus any ringing, choose a 30V MOSFET to provide a margin of safety. Because the top MOSFET is on for a short time, a RENESAS RJK0305DPB (RDS(ON) = 13mΩ (max), CMILLER = QGD/10V = 150pF, VGS(TH) = 2.5V, θJA = 40°C/W) is sufficient. Check its power dissipation at current limit with = ρ100°C = 1.4: P TOP = ( ) 1.2V 2 15A ) • 1.4 • 13mΩ ( 26 V 2 ⎛ 15A ⎞ + ( 26 V ) ⎜ (2.5Ω)(150pF ) ⎝ 2 ⎟⎠ ⎛⎛ 1 ⎞ 1 ⎞ ⎜⎝ ⎜⎝ 5.2 – 2.5 ⎟⎠ + 2.5 ⎟⎠ 500kHz = 0.19 W + 0.73W = 0.92W And double check the assumed TJ in the MOSFET: TJ = 70°C + (0.92W)(40°C/W) = 107°C The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary. A RENESAS RJK0301DPB (RDS(ON) = 4mΩ (max), θJA = 40°C/W) is chosen for the synchronous MOSFET. PBOT = ( ) 26 V – 1.2V 2 15A ) • 1.4 • 4mΩ = 1.26 W ( 26 V And double check the assumed TJ in the MOSFET: TJ = 70°C + (1.26W)(40°C/W) = 120°C Next, the INTVCC LDO current is calculated: IINTVCC = (500kHz)(8nC + 32nC) + 3.5mA = 23.5mA And double check the TJ in the LTC3775: TJ = 70°C + (23.5mA)(26V)(68°C/W) = 112°C Next, set the current limit resistors with a sense resistor of 3mΩ. 15A + 0.5 • 6.4A = 728Ω 90μA 15A + 0.5 • 6.4A = 56.62k RILIMB = 5 • 1.4 • 4mΩ • 9μA RILIMT = 1.2 • 3mΩ • Use the next higher standard values of 732Ω and 57.6k. 3775f 26 LTC3775 APPLICATIONS INFORMATION The worst-case peak inductor current based on a sense resistor tolerance of ±1% is IL(SAT) ≥ 110μA • 732Ω = 27.1A 2.97mΩ The input RMS current is highest at VIN(MIN) = 5V and IOUT(MAX) = 15A: IRMS ≈ 15A 1.2V ( 5V – 1.2V ) 5V = 6.4A CIN is chosen for an RMS current rating of >6.4A at 85°C. For the output capacitor, two low ESR OS-CON capacitors (470μF/5mΩ each) are used to minimize output voltage changes due to inductor current ripple and load steps. The ripple voltage will be: ⎛ 0.005 ⎞ 1 VOUT(RIPPLE) = 6.4A • ⎜ + ⎝ 2 8 • 500kHz • 470μF • 2 ⎟⎠ = 17.7mV However, a 0A to 15A load step will cause an output voltage change of at least: ΔVOUT(STEP) = (15A)(0.0025Ω) = 37.5mV 3775f 27 LTC3775 TYPICAL APPLICATIONS 5V to 26V Input, 1.2V/15A Output at 500kHz CF 220pF DB RSENSE 0.003Ω RILIMT 732Ω VIN ILIMT TG + VIN 5V TO 26V CIN1 330μF 35V QT RILIMB 57.6k CVCC 4.7μF CSS 0.01μF SENSE INTVCC BOOST CB 0.1μF L1 0.36μH LTC3775 RSET 39.2k C2 330pF RA 10k ILIMB SS SW FREQ BG FB + QB COUT 470μF 2.5V s2 VOUT 1.2V 15A PGND MODE/SYNC COMP RUN/SHDN SGND RB 10k R2 C1 4.7k 3.9nF 3775 TA02 COUT : SANYO 2R5TPD470M5 DB: CMDSH4E L1: IHLP-4040DZ-ER-R36-M11 QB: RJK0301DPB-00-J0 QT: RJK0305DPB-00-J0 3775f 28 LTC3775 TYPICAL APPLICATIONS 8V to 36V Input, 2.5V/10A Output at 500kHz CB 0.1μF R4 43.2k V BOOST IN RILIMB 133k R5 10k ILIMT DB ILIMB CVCC 4.7μF L1 1.2μH SW SS C2 330pF COUT 330μF 4V s3 + FREQ C3 1500pF VIN 8V TO 36V QT TG LTC3775 RSET 39.2k CIN1 330μF 35V SENSE INTVCC CSS 0.01μF + RILIMT 464Ω R SENSE 0.003Ω CF 220pF QB BG VOUT 2.5V 10A RUN/SHDN FB PGND MODE/SYNC COMP RA 10k R3 390Ω SGND RB 3.16k R2 C1 15k 2200pF 3775 TA03 COUT : SANYO 4TPD330M DB: CMDSH4E L1: TOKO FDA1254-1R2M QB,QT: INFINEON BSZ097N04LS Efficiency and Power Loss vs Load Current Load Step VIN = 12V 90 VOUT = 2.5V CONTINUOUS MODE 80 SW FREQ = 500kHz 70 3 50 EFFICIENCY 2 30 20 VOUT(AC) 100mV/DIV 4 60 40 Start-Up 5 POWER LOSS POWER LOSS (W) EFFICIENCY (%) 100 SWITCHOVER FROM PULSESKIPPING TO CONTINUOUS MODE VOUT 1V/DIV IL 5A/DIV IL 10A/DIV VSS 1V/DIV 1 10 0 0.01 0 0.1 1 LOAD CURRENT (A) 10 3775 TA03b VIN = 12V 50μs/DIV VOUT = 2.5V LOAD = 0A TO 10A TO 0A MODE = 0V SW FREQ = 500kHz 3775 TA03c VIN = 12V 2ms/DIV VOUT = 2.5V CSS = 0.01μF MODE = 0V SW FREQ = 500kHz 3775 TA03d 3775f 29 LTC3775 TYPICAL APPLICATIONS 24V Input, 12V/5A Output at 500kHz RILIMT 1.24k R5 10k VIN ILIMT TG QT RILIMB 56.2k CVCC 4.7μF CSS 0.01μF C2 330pF C3 330pF ILIMB SENSE INTVCC BOOST CB 0.1μF L1 4.7μH LTC3775 RSET 39.2k R3 2.05k VIN 24V CIN1 330μF 35V + DB R4 69.8k SS SW FREQ BG + QB RUN/SHDN FB PGND COUT 68μF 16V s2 VOUT 12V 5A MODE/SYNC COMP RA 191k SGND RB 10k R2 C1 7.68k 3.3nF 3775 TA04 COUT : SANYO 16TQC68M DB: CMDSH4E L1: IHLP-4040DZ-ER-4R7-M11 QB, QT: RJK0305DPB-00-JO Efficiency and Power Loss vs Load Current 2.5 VIN = 24V 90 VOUT = 12V 80 CONTINUOUS MODE SW FREQ = 500kHz 70 2.0 60 1.5 EFFICIENCY 40 30 1.0 POWER LOSS 20 0.5 POWER LOSS (W) EFFICIENCY (%) 100 50 Start-Up Load Step VOUT 5V/DIV VOUT(AC) 200mV/DIV IL 5A/DIV SWITCHOVER FROM PULSESKIPPING TO CONTINUOUS MODE VSS 1V/DIV IL 5A/DIV 10 0 0.01 1 0.1 LOAD CURRENT (A) 0 10 3775 TA04b VIN = 24V 50μs/DIV VOUT = 12V LOAD = 0A TO 5A TO 0A MODE = 0V SW FREQ = 500kHz 3775 TA04c VIN = 24V 2ms/DIV VOUT = 12V CSS = 0.01μF MODE = 0V SW FREQ = 500kHz 3775 TA04d 3775f 30 LTC3775 PACKAGE DESCRIPTION UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) 0.70 p0.05 3.50 p 0.05 1.45 p 0.05 2.10 p 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 p0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 p 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 s 45o CHAMFER R = 0.115 TYP 0.75 p 0.05 15 16 PIN 1 TOP MARK (NOTE 6) 0.40 p 0.10 1 1.45 p 0.10 (4-SIDES) 2 (UD16) QFN 0904 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 p 0.05 0.50 BSC 3775f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC3775 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3854 Small Footprint Wide VIN Range Synchronous Step-Down DC/DC Controller Fixed 400kHz Operating Frequency, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12 LTC3851A/ LTC3851A-1 No RSENSE™ Wide VIN Range Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16 LTC3878 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Controller Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16 LTC3879 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Controller Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16 LTC3703-5 High Voltage Synchronous Step-Down DC/DC Voltage Mode Controller 4.1V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.9VIN, Logic-Level Gate Driver, SSOP-16, TSSOP-28 LTC3703 High Voltage Synchronous Step-Down DC/DC Voltage Mode Controller 9.3V ≤ VIN ≤ 100V, 0.8V ≤ VOUT ≤ 0.9VIN, 9.3V to 15V Gate Driver, SSOP-16, TSSOP-28 LTC3850/ LTC3850-1/ LTC3850-2 Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC Controllers, RSENSE or DCR Current Sensing and Tracking Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz, 4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz, 4V ≤ VIN ≤ 24V, VOUT Up to 13.5V LTM®4600HV 10A DC/DC μModule Complete Power Supply High Efficiency, Compact Size, UltraFast™ Transient Response, 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTM4601AHV 12A DC/DC μModule Complete Power Supply High Efficiency, Compact Size, UltraFast Transient Response, 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTC3601 1.5A, 4MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Phase Lockable IQ = 300μA, 4V ≤ VIN ≤ 15V, VOUT(MIN) = 0.6V, 3mm × 3mm QFN-16, MSOP-16E LTC3603 2.5A, 3MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Phase Lockable IQ = 75μA, 4.5V ≤ VIN ≤ 15V, VOUT(MIN) = 0.6V, 4mm × 4mm QFN-20 LTC3605 5A, 4MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Frequency 800kHz to 4MHz, 4V ≤ VIN ≤ 15V, VOUT(MIN) = 0.6V, 4mm × 4mm QFN-24 LTC3608 8A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 18V, VOUT(MIN) = 0.6V, 7mm × 8mm QFN-52 LTC3609 6A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 32V, VOUT(MIN) = 0.6V, 7mm × 8mm QFN-52 LTC3610 12A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 24V, VOUT(MIN) = 0.6V, 9mm × 9mm QFN-64 LTC3611 10A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 32V, VOUT(MIN) = 0.6V, 9mm × 9mm QFN-64 LTC3824 Low IQ, High Voltage DC/DC Controller, 100% Duty Cycle Selectable Fixed Operating Frequency, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN, IQ = 40μA, MSOP-10E LTC3857/ LTC3857-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 24V, IQ = 50μA, LTC3868/ LTC3868-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 24V, 0.8V ≤ VOUT ≤ 14V, IQ = 170μA, LT®3845 Low IQ , High Voltage Synchronous Step-Down DC/DC Controller Adjustable Fixed Operating Frequency 100kHz to 500kHz, 4V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, IQ = 30μA, TSSOP-16 No RSENSE and UltraFast are trademarks of Linear Technology Corporation. 3775f 32 Linear Technology Corporation LT 1009 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009