HA-4900, HA-4902, HA-4905 Data Sheet October 20, 2005 FN2855.4 Precision Quad Comparators Features The HA-4900 series are monolithic, quad, precision comparators offering fast response time, low offset voltage, low offset current and virtually no channel-to-channel crosstalk for applications requiring accurate, high speed, signal level detection. These comparators can sense signals at ground level while being operated from either a single +5V supply (digital systems) or from dual supplies (analog networks) up to ±15V. The HA-4900 series contains a unique current driven output stage which can be connected to logic system supplies (VLOGIC+ and VLOGIC-) to make the output levels directly compatible (no external components needed) with any standard logic or special system logic levels. In combination analog/digital systems, the design employed in the HA-4900 series input and output stages prevents troublesome ground coupling of signals between analog and digital portions of the system. • Fast Response Time . . . . . . . . . . . . . . . . . . . . . . . . 130ns These comparators’ combination of features make them ideal components for signal detection and processing in data acquisition systems, test equipment and microprocessor/analog signal interface networks. For military grade product, refer to the HA-4902/883 data sheet. Pinout VL+ 1 2 -IN 1 3 - +IN 1 4 + V- 5 +IN 2 6 4 7 OUT 2 8 + -2 • Selectable Output Logic Levels • Active Pull-Up/Pull-Down Output Circuit. No External Resistors Required • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Threshold Detector • Zero Crossing Detector • Window Detector • Analog Interfaces for Microprocessors • High Stability Oscillators • Logic System Interfaces Ordering Information TEMP RANGE (oC) HA1-4900-2 HA1-4900-2 -55 to 125 16 Ld CERDIP F16.3 HA1-4902-2 HA1-4902-2 -55 to 125 16 Ld CERDIP F16.3 16 OUT 4 HA1-4905-5 HA1-4905-5 0 to 75 16 Ld CERDIP F16.3 15 -IN 4 HA3-4905-5 HA3-4905-5 0 to 75 16 Ld PDIP E16.3 14 +IN 4 HA9P4905-5 HA9P4905-5 0 to 75 16 Ld SOIC M16.3 13 V+ HA9P4905-5Z HA9P4905(See Note) 5Z 0 to 75 16 Ld SOIC (Pb-free) M16.3 + 12 +IN 3 - 11 -IN 3 10 OUT 3 9 VL- 1 • Single or Dual Voltage Supply Operation PART MARKING 1 3 -IN 2 + • Low Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . .10nA PART NUMBER HA-4900, HA-4902 (CERDIP) HA-4905 (PDIP, CERDIP, SOIC) TOP VIEW OUT 1 • Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0mV PACKAGE PKG. DWG. # NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-4900, HA-4902, HA-4905 Absolute Maximum Ratings Thermal Information Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 33V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Voltage Between VLOGIC+ and VLOGIC-. . . . . . . . . . . . . . . . . . .18V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Power Dissipation (Notes 1, 2) Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 85 25 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Ceramic Package) . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-4900-2, HA-4902-2. . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-4905-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Die Characteristics Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VNumber of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Die Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mils x 105 mils CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175oC for ceramic packages, and below 150oC for plastic packages. 2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and VLOGIC shown in curves of Power Dissipation vs Supply Voltages (see Performance Curves). The calculated T.P.D. is then located on the graph of Maximum Allowable Package Dissipation vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated T.P.D. (See Performance Curves). For instance, the combination of +15V, -15V, +5V, 0V (V+, V-, VLOGIC+, VLOGIC-) gives a T.P.D. of 350mW, the combination +15V, -15V, +15V, 0V gives a T.P.D. of 450mW. 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15V, VLOGIC+ = 5V, VLOGIC- = GND HA-4900-2 -55oC to 125oC HA-4902-2 -55oC to 125oC HA-4905-5 0oC to 75oC TEMP (oC) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 25 - 2 3 - 2 5 - 4 7.5 mV Full - - 4 - - 8 - - 10 mV 25 - 10 25 - 10 35 - 25 50 nA Full - - 35 - - 45 - - 70 nA 25 - 50 75 - 50 150 - 100 150 nA Full - - 150 - - 200 - - 300 nA 25 - - VIO + 0.3 - - VIO + 0.5 - - VIO + 0.5 mV Full - - VIO + 0.4 - - VIO + 0.6 - - VIO + 0.7 mV Common Mode Range Full V- - (V+) 2.4 V- - (V+) 2.6 V- - (V+) 2.4 V Differential Input Resistance 25 - 250 - - 250 - - 250 - MΩ Large Signal Voltage Gain 25 - 400 - - 400 - - 400 - kV/V Response Time (tPD(0)) (Note 7) 25 - 130 200 - 130 200 - 130 200 ns Response Time (tPD(1)) (Note 7) 25 - 180 215 - 180 215 - 180 215 ns PARAMETER INPUT CHARACTERISTICS Offset Voltage (Note 4) Offset Current Bias Current (Note 5) Input Sensitivity (Note 6) TRANSFER CHARACTERISTICS 2 HA-4900, HA-4902, HA-4905 Electrical Specifications VSUPPLY = ±15V, VLOGIC+ = 5V, VLOGIC- = GND (Continued) HA-4902-2 -55oC to 125oC HA-4900-2 -55oC to 125oC HA-4905-5 0oC to 75oC TEMP (oC) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Logic “Low State” (VOL) (Note 8) Full - 0.2 0.4 - 0.2 0.4 - 0.2 0.4 V Logic “High State” (VOH) (Note 8) Full 3.5 4.2 - 3.5 4.2 - 3.5 4.2 - V ISINK Full 3.0 - - 3.0 - - 3.0 - - mA ISOURCE Full 3.0 - - 3.0 - - 3.0 - - mA PARAMETER OUTPUT CHARACTERISTICS Output Voltage Level Output Current POWER SUPPLY CHARACTERISTICS Supply Current, IPS (+) 25 - 6.5 20 - 6.5 20 - 7 20 mA Supply Current, IPS (-) 25 - 4 8 - 4 8 - 5 8 mA Supply Current, IPS (Logic) 25 - 3.5 4 - 3.5 4 - 3.5 4 mA VLOGIC+ (Note 2) Full 0 - +15.0 0 - +15.0 0 - +15.0 V VLOGIC- (Note 2) Full -15.0 - 0 -15.0 - 0 -15.0 - 0 V Supply Voltage Range NOTES: 4. Minimum differential input voltage required to ensure a defined output state. 5. Input bias currents are essentially constant with differential input voltages up to ±9V. With differential input voltages from ±9V to ±15V, bias current on the more negative input can rise to approximately 500µA. This will also cause higher supply currents. 6. VCM = 0V. Input sensitivity is the worst case minimum differential input voltage required to guarantee a given output logic state. This parameter includes the effects of offset voltage and voltage gain. 7. For tPD(1); 100mV input step, -10mV overdrive. For tPD(0); -100mV input step, 10mV overdrive. Frequency ≈ 100Hz; Duty Cycle ≈ 50%; Inverting input driven. See Figure 1 for Test Circuit. All unused inverting inputs tied to +5V. 8. For VOH and VOL: ISINK = ISOURCE = 3.0mA. For other values of VLOGIC; VOH (Min) = VLOGIC + -1.5V. Test Circuit and Waveform +15V +5V tPD(1) tPD(0) OVERDRIVE VOUT DUT VTH = 0V + INPUT 100mV 100mV VTH = 0V OVERDRIVE -15V OUTPUT 1.5V 1.5V tPD(1) tPD(0) t=0 FIGURE 1. 3 t=0 HA-4900, HA-4902, HA-4905 Schematic Diagram R1 500Ω R9 4kΩ PR1 200kΩ R10 4kΩ Q1 Q11 Q2 R2 13kΩ R3 1kΩ R4 1kΩ Q12 Q13 Q14 D11A R6 2.5kΩ R7 2.5kΩ Q15 D4B D4A Q26 Q23 Q9D Q20 Q36 Q5 BIAS 3 BIAS 4 D9A Q9B Q9A Q9C Q18 Q21 Q17 -IN Q22 R20C 1kΩ R20B 1kΩ R20A 1kΩ Q33 Q30 Q34 R24 14kΩ R15 8kΩ MN2 R21 1kΩ R17 19kΩ MN1 Q32 R22 100Ω OUT MN6 D29B D35 Q10 R20D 1kΩ Q29 D39 R16 540Ω +IN BIAS 1 VLOGIC+ R12 Q29A 8kΩ Q38 Q28 Q37 Q7 Q4 R11 8kΩ Q24 Q25 D45 Q19 BIAS 2 R18 664Ω Q16 Q3 Q4C V+ R5 360Ω R14 5kΩ R23 MN5 100Ω Q31 VLOGICMN4 MN3 V- ONE FOURTH ONLY Applying the HA-4900 Series Comparators Supply Connections Power Supply Decoupling This device is exceptionally versatile in working with most available power supplies. The voltage applied to the V+ and Vterminals determines the allowable input signal range; while the voltage applied to the VL+ and VL- determines the output swing. In systems where dual analog supplies are available, these would be connected to V+ and V-, while the logic supply and return would be connected to VLOGIC+ and VLOGIC -. The analog and logic supply commons can be connected together at one point in the system, since the comparator is immune to noise on the logic supply ground. A negative output swing may be obtained by connecting VL+ to ground and VL- to a negative supply. Bipolar output swings (15VP-P, Max) may be obtained using dual supplies. In systems where only a single logic supply is available (+5V to 15V), V+ and VLOGIC+ may be connected together to the positive supply while V- and VLOGIC- are grounded. If an input signal could swing negative with respect the V- terminal, a resistor should be connected in series with the input to limit input current to < 5mA since the C-B junction of the input transistor would be forward biased. Decouple all power supply lines with 0.01µF ceramic capacitors to ground line located near the package to reduce coupling between channels or from external sources. Unused Inputs Inputs of unused comparator sections should be tied to a differential voltage source to prevent output “chatter.” Crosstalk Simultaneous high frequency operation of all other channels in the package will not affect the output logic state of a given channel, provided that its differential input voltage is sufficient to define a given logic state (∆VIN ≥ ±VOS). Low level or high impedance input lines should be shielded from other signal sources to reduce crosstalk and interference. 4 Response Time Fast rise time (<200ns) input pulses of several volts amplitude may result in delay times somewhat longer than those illustrated for 100mV steps. Operating speed is optimized by limiting the maximum differential input voltage applied, with resistor-diode clamping networks. Typical Applications Data Acquisition System In this circuit the HA-4900 series is used in conjunction with a D to A converter to form a simple, versatile, multi-channel analog input for a data acquisition system. In operation the processor first sends an address to the D to A, then the processor reads the digital word generated by the comparator outputs. To perform a simple comparison, the processor sets the D to A to a given reference level, then examines one or more comparator outputs to determine if their inputs are above or below the reference. A window comparison consists of two such cycles with 2 reference levels set by the D to A. One way to digitize the inputs would be for the processor to increment the D to A in steps. The D to A address, as each comparator switches, is the digitized level of the input. While stairstepping the D to A is slower than successive approximation, all channels are digitized during one staircase ramp. HA-4900, HA-4902, HA-4905 LATCH Window Detector INTERFACE MEMORY INTERFACE ANALOG INPUTS D/A The high switching speed, low offset current and low offset voltage of the HA-4900 series makes this window detector circuit extremely well suited to applications requiring fast, accurate, decision-making. The circuit above is ideal for industrial process system feedback controllers or “out-oflimit” alarm indicators. +15V MICROPROCESSOR INPUT + HIGH REF - VL+ COMPARATORS HIGH ANALOG INPUT MODULE PROCESSOR Logic Level Translators The HA-4900 series comparators can be used as versatile logic interface devices as shown in the circuits above. Negative logic devices may also be interfaced with appropriate supply connections. If separate supplies are used for V- and VLOGIC-, these logic level translators will tolerate several volts of ground line differential noise. -15V +5.0V IN WINDOW 1/4 HD-74C02 + LOW REF LOW - V+ +5.0V 1/2 HA-4900 +5V TO +15V VL+ +5.0V 4.7kΩ 10kΩ + 1/4 HA-4900 + 1/4 HA-4900 - 10kΩ 1N914s + 1/4 HA-4900 + 1/4 HA-4900 Oscillator/Clock Generator This self-starting fixed frequency oscillator circuit gives excellent frequency stability. R1 and C1 comprise the frequency determining network while R2 provides the regenerative feedback. Diode D1 enhances the stability by compensating for the difference between VOH and VSUPPLY. In applications where a precision clock generator up to 100kHz is required, such as in automatic test equipment, C1 may be replaced by a crystal. - - R2 150kΩ V+ TTL TO CMOS 1N914 CMOS TO TTL RS-232 To CMOS Line Receiver D1 V+ 150kΩ This RS-232 type line receiver to drive CMOS logic uses a Schmitt trigger feedback network to give about 1V input hysteresis for added noise immunity. A possible problem in an interface which connects two equipments, each plugged into a different AC receptacle, is that the power line voltage may appear at the receiver input when the interface connection is made or broken. The two diodes and a 3W input resistor will protect the inputs under these conditions. + 1/4 HA-4900 150kΩ - C1 1 f ≈ -----------------------2.1R 1 C 1 R1 50kΩ +10V 4.7kΩ 3W Schmitt Trigger (Zero Crossing Detector With Hysteresis) 1/4 HA-4900 + 1kΩ 56kΩ 51kΩ 1N4001s 1kΩ 5 This circuit has a 100mV hysteresis which can be used in applications where very fast transition times are required at the output even though the signal input is very slow. The hysteresis loop also reduces false triggering due to noise on the input. The waveforms below show the trip points developed by the hysteresis loop. HA-4900, HA-4902, HA-4905 +15V +5V VOH 1/4 HA-4900 + VOH ≈ 4.2V R2 2kΩ VTRIP+ 0V -15V VTRIP- R3 13kΩ R1 100Ω -15V INPUT TO OUTPUT WAVEFORM SHOWING HYSTERESIS TRIP POINTS Typical Performance Curves TA = 25oC, VS = ±15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified INPUT OFFSET CURRENT (nA) 80 60 40 20 15 10 5 0 0 -55 -25 0 25 50 75 100 -55 125 -25 TEMPERATURE (oC) 0 25 60 40 20 -12 -9 -6 -3 0 +3 +6 +9 +12 +15 COMMON MODE INPUT VOLTAGE FIGURE 4. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE (VDIFF = 0V) 6 75 100 125 FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE 80 0 -15 50 TEMPERATURE (oC) FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (nA) 100 HA-4900, HA-4902, HA-4905 Typical Performance Curves 10 SUPPLY CURRENT (mA) 7 VS = ±15V VLOGIC+ = 5V VLOGIC- = GND IPSL, VOUT = H 6 IPS+, VOUT = L 8 SUPPLY CURRENT (mA) 12 TA = 25oC, VS = ±15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified (Continued) IPS+, VOUT = H 6 IPS-, VOUT = L 4 IPS-, VOUT = H IPSL, VOUT = L 5 IPS+, VOUT = H 4 IPS+, VOUT = L 3 IPSL, VOUT = L 2 2 0 -50 -25 0 V+ = 5V, V- = GND VLOGIC+ = 5V VLOGIC- = GND 1 IPSL, VOUT = H 25 50 75 100 0 125 -50 TEMPERATURE (oC) FIGURE 5. SUPPLY CURRENT vs TEMPERATURE (FOR ±15V SUPPLIES AND +5V LOGIC SUPPLY) 0 25 50 TEMPERATURE (oC) 75 100 125 FIGURE 6. SUPPLY CURRENT vs TEMPERATURE (FOR SINGLE +5V OPERATION) 5 5 OVERDRIVE = 20mV 3 OVERDRIVE = 5mV 4 OVERDRIVE = 2mV 2 OVERDRIVE = 20mV VOUT (V) 4 3 OVERDRIVE = 5mV 2 1 1 0 0 0 +100mV OVERDRIVE = 2mV VIN VIN VOUT (V) -25 0 -100mV 0 100 200 TIME (ns) 300 0 400 100 200 TIME (ns) 300 400 FIGURE 7. RESPONSE TIME FOR VARIOUS INPUT OVERDRIVES 2.0 250 CERDIP POWER DISSIPATION (mW) PACKAGE DISSIPATION (W) 1.75 1.50 1.25 1.0 PDIP 0.75 0.50 SOIC 200 150 V+ 100 V- 50 0.25 VLOGIC+ 0 0 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 8. MAXIMUM PACKAGE DISSIPATION vs AMBIENT TEMPERATURE 7 0 2 4 6 8 10 SUPPLY VOLTAGE (V) 12 14 FIGURE 9. POWER DISSIPATION vs SUPPLY VOLTAGE (NO LOAD CONDITION) HA-4900, HA-4902, HA-4905 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 8