Micro Linear ML4803IP-2 8-pin pfc and pwm controller combo Datasheet

February 1999
PRELIMINARY
ML4803
8-Pin PFC and PWM Controller Combo
GENERAL DESCRIPTION
FEATURES
The ML4803 is a space-saving controller for power factor
corrected, switched mode power supplies that offers very
low start-up and operating currents.
■
Internally synchronized PFC and PWM in one 8-pin IC
■
Patented one-pin voltage error amplifier with advanced
input current shaping technique
■
Peak or average current, continuous boost, leading
edge PFC (Input Current Shaping Technology)
■
High efficiency trailing-edge current mode PWM
■
Low supply currents; start-up: 150µA typ., operating:
2mA typ.
■
Synchronized leading and trailing edge modulation
■
Reduces ripple current in the storage capacitor
between the PFC and PWM sections
■
Overvoltage, UVLO, and brownout protection
■
PFC VCCOVP with PFC Soft Start
Power Factor Correction (PFC) offers the use of smaller,
lower cost bulk capacitors, reduces power line loading
and stress on the switching FETs, and results in a power
supply fully compliant to IEC1000-3-2 specifications. The
ML4803 includes circuits for the implementation of a
leading edge, average current “boost” type PFC and a
trailing edge, PWM.
The ML4803-1’s PFC and PWM operate at the same
frequency, 67kHz. The PFC frequency of the ML4803-2 is
automatically set at half that of the 134kHz PWM. This
higher frequency allows the user to design with smaller
PWM components while maintaining the optimum
operating frequency for the PFC. An overvoltage
comparator shuts down the PFC section in the event of a
sudden decrease in load. The PFC section also includes
peak current limiting for enhanced system reliability.
BLOCK DIAGRAM
7
VEAO
7V
4
+
VCC
PFC OFF
COMP
–
17.5V
16.2V
35µA
REF
+
VCC OVP
VREF
GND
COMP
–
2
M3
–1
M4
M1
PFC
CONTROL
LOGIC
M2
R1
C1
30pF
PFC OUT
1
M7
LEADING
EDGE PFC
ONE PIN ERROR AMPLIFIER
3
ISENSE
+
+
VCC
OSCILLATOR
PFC – 67kHz
PWM – 134kHz
26k
–
TRAILING
EDGE PWM
DUTY CYCLE
LIMIT
PWM COMPARATOR
COMP
40k
+
1.2V
6
SOFT START
PFC/PWM UVLO
VREF
VDC
–
PFC ILIMIT
–
–1V
5
COMP
–4
ILIMIT
PWM
CONTROL
LOGIC
–
COMP
+
PWM OUT
8
M6
1.5V
–
DC ILIMIT
+
1
ML4803
PIN CONFIGURATION
ML4803
8-Pin PDIP (P08)
8-Pin SOIC (S08)
PFC OUT
1
8
PWM OUT
GND
2
7
VCC
ISENSE
3
6
ILIMIT
VEAO
4
5
VDC
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
PFC OUT
PFC driver output
2
GND
3
4
2
PIN
NAME
FUNCTION
5
VDC
PWM voltage feedback input
Ground
6
I LIMIT
PWM current limit comparator input
ISENSE
Current sense input to the PFC current
limit comparator
7
VCC
Positive supply (may require an
external shunt regulator)
VEAO
PFC one-pin error amplifier input
8
PWM OUT PWM driver output
February 1999
ML4803
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
ICC Current (average) ............................................. 40mA
VCC MAX ............................................................... 18.3V
ISENSE Voltage .................................................. -5V to 1V
Voltage on Any Other Pin ...... GND - 0.3V to VCC + 0.3V
Peak PFC OUT Current, Source or Sink ....................... 1A
Peak PWM OUT Current, Source or Sink ..................... 1A
PFC OUT, PWM OUT Energy Per Cycle .................. 1.5µJ
Junction Temperature .............................................. 150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................... 260°C
Thermal Resistance (qJA)
Plastic DIP ..................................................... 110°C/W
Plastic SOIC ................................................... 160°C/W
OPERATING CONDITIONS
Temperature Range
ML4803CX-X ............................................. 0°C to 70°C
ML4803IX-X ............................................-40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 15V, TA = Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
33.5
35.0
36.5
µA
0.1
0.3
µA
15.5
16.0
16.5
V
-0.9
-1
-1.15
V
150
300
ns
1.5
1.6
V
150
300
ns
67
74
kHz
ONE-PIN ERROR AMPLIFIER
VEAO Output Current
TA = 25ºC, VEAO = 6V
Line Regulation
10V < VCC < 15V, VEAO = 6V
VCC OVP COMPARATOR
Threshold Voltage
TA = 0ºC to 70ºC
PFC ILIMIT COMPARATOR
Threshold Voltage
Delay to Output
DC ILIMIT COMPARATOR
Threshold Voltage
1.4
Delay to Output
OSCILLATOR
Initial Accuracy
TA = 25°C
Voltage Stability
10V < VCC < 15V
62
Temperature Stability
1
%
2
%
Total Variation
Over Line and Temp
60
67
74.5
kHz
Dead Time
PFC Only
0.3
0.45
0.65
µs
Minimum Duty Cycle
VEAO > 7.0V,ISENSE = -0.2V
0
%
Maximum Duty Cycle
VEAO < 4.0V,ISENSE = 0V
PFC
95
%
8
15
W
IOUT = -100mA
0.8
1.5
V
IOUT = –10mA, VCC = 8V
0.7
1.5
V
Output Low Impedance
Output Low Voltage
90
February 1999
3
ML4803
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
8
15
W
PFC (Continued)
Output High Impedance
Output High Voltage
IOUT = 100mA, VCC = 15V
13.5
Rise/Fall Time
CL = 1000pF
Duty Cycle Range
TA = 0ºC to 70ºC, ML4803-2
0-43
TA = 0ºC to 70ºC, ML4803-1
0-49.5
14.2
V
50
ns
PWM
0-50
%
0-50
%
8
15
W
IOUT = –100mA
0.8
1.5
V
IOUT = –10mA, VCC = 8V
0.7
1.5
V
8
15
W
Output Low Impedance
Output Low Voltage
Output High Impedance
Output High Voltage
IOUT = 100mA, VCC = 15V
Rise/Fall Time
CL = 1000pF
VCC Clamp Voltage (VCCZ)
ICC = 10mA
Start-up Current
Operating Current
13.5
0-47
14.2
V
50
ns
SUPPLY
Note 1:
4
16.7
17.5
18.3
V
VCC = 11V, CL = 0
0.2
0.4
mA
VCC = 15V, CL = 0
2.5
4
mA
Undervoltage Lockout Threshold
11.5
12
12.5
V
Undervoltage Lockout Hysteresis
2.4
2.9
3.4
V
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
February 1999
ML4803
FUNCTIONAL DESCRIPTION
The ML4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a
synchronized Pulse Width Modulation (PWM) controller. It
is distinguished from earlier combo controllers by its low
pin count, innovative input current shaping technique, and
very low start-up and operating currents. The PWM section
is dedicated to peak current mode operation. It uses
conventional trailing-edge modulation, while the PFC uses
leading-edge modulation. This patented Leading Edge/
Trailing Edge (LETE) modulation technique helps to
minimize ripple current in the PFC DC buss capacitor.
The ML4803 is offered in two versions. The ML4803-1
operates both PFC and PWM sections at 67kHz, while the
ML4803-2 operates the PWM section at twice the
frequency (134kHz) of the PFC. This allows the use of
smaller PWM magnetics and output filter components,
while minimizing switching losses in the PFC stage.
In addition to power factor correction, several protection
features have been built into the ML4803. These include
soft start, redundant PFC over-voltage protection, peak
current limiting, duty cycle limit, and under voltage
lockout (UVLO). See Figure 12 for a typical application.
DETAILED PIN DESCRIPTIONS
VEAO
This pin provides the feedback path which forces the PFC
output to regulate at the programmed value. It connects to
programming resistors tied to the PFC output voltage and
is shunted by the feedback compensation network.
ISENSE
This pin ties to a resistor or current sense transformer
which senses the PFC input current. This signal should be
negative with respect to the IC ground. It internally feeds
the pulse-by-pulse current limit comparator and the
current sense feedback signal. The ILIMIT trip level is –1V.
The ISENSE feedback is internally multiplied by a gain of
four and compared against the internal programmed ramp
to set the PFC duty cycle. The intersection of the boost
inductor current downslope with the internal
programming ramp determines the boost off-time.
is offset internally by 1.2V and then compared against the
opto feedback voltage to set the PWM duty cycle.
PFC OUT and PWM OUT
PFC OUT and PWM OUT are the high-current power
drivers capable of directly driving the gate of a power
MOSFET with peak currents up to ±1A. Both outputs are
actively held low when VCC is below the UVLO threshold
level.
VCC
VCC is the power input connection to the IC. The VCC startup current is 150µA . The no-load ICC current is 2mA. VCC
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the
operating frequency and the MOSFET gate charge (Qg),
average PFC and PWM output currents can be calculated
as IOUT = Qg x F. The average magnetizing current
required for any gate drive transformers must also be
included. The VCC pin is also assumed to be proportional
to the PFC output voltage. Internally it is tied to the
VCCOVP comparator (16.2V) providing redundant highspeed over-voltage protection (OVP) of the PFC stage.
VCC also ties internally to the UVLO circuitry, enabling
the IC at 12V and disabling it at 9.1V. VCC must be
bypassed with a high quality ceramic bypass capacitor
placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
ML4803.
VCC is typically produced by an additional winding off
the boost inductor or PFC Choke, providing a voltage that
is proportional to the PFC output voltage. Since the
VCCOVP max voltage is 16.2V, an internal shunt limits
VCC overvoltage to an acceptable value. An external
clamp, such as shown in Figure 1, is desirable but not
necessary.
VCC is internally clamped to 16.7V minimum, 18.3V
maximum. This limits the maximum VCC that can be
applied to the IC while allowing a VCC which is high
VCC
VDC
This pin is typically tied to the feedback opto-collector. It
is tied to the internal 5V reference through a 26kW resistor
and to GND through a 40kW resistor.
ILIMIT
1N4148
1N4148
1N5246B
This pin is tied to the primary side PWM current sense
resistor or transformer. It provides the internal pulse-by
pulse-current limit for the PWM stage (which occurs at
1.5V) and the peak current mode feedback path for the
current mode control of the PWM stage. The current ramp
February 1999
GND
Figure 1. Optional VCC Clamp
5
ML4803
FUNCTIONAL DESCRIPTION (Continued)
enough to trip the VCCOVP. The max current through this
zener is 10mA. External series resistance is required in
order to limit the current through this Zener in the case
where the VCC voltage exceeds the zener clamp level.
GND
GND is the return point for all circuits associated with
this part. Note: a high-quality, low impedance ground is
critical to the proper operation of the IC. High frequency
grounding techniques should be used.
POWER FACTOR CORRECTION
Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with, and proportional to,
the line voltage. This is defined as a unity power factor is
(one). A common class of nonlinear load is the input of a
most power supplies, which use a bridge rectifier and
capacitive input filter fed from the line. Peak-charging
effect, which occurs on the input filter capacitor in such a
supply, causes brief high-amplitude pulses of current to
flow from the power line, rather than a sinusoidal current
in phase with the line voltage. Such a supply presents a
power factor to the line of less than one (another way to
state this is that it causes significant current harmonics to
appear at its input). If the input current drawn by such a
supply (or any other nonlinear load) can be made to
follow the input voltage in instantaneous amplitude, it
will appear resistive to the AC line and a unity power
factor will be achieved.
To hold the input current draw of a device drawing power
from the AC line in phase with, and proportional to, the
SW2
L1
+
I2
I1
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the
ML4803 uses a boost-mode DC-DC converter to
accomplish this. The input to the converter is the full wave
rectified AC line voltage. No filtering is applied following
the bridge rectifier, so the input voltage to the boost
converter ranges, at twice line frequency, from zero volts
to the peak value of the AC input and back to zero. By
forcing the boost converter to meet two simultaneous
conditions, it is possible to ensure that the current that the
converter draws from the power line matches the
instantaneous line voltage. One of these conditions is that
the output voltage of the boost converter must be set
higher than the peak value of the line voltage. A
commonly used value is 385VDC, to allow for a high line
of 270VACRMS. The other condition is that the current that
the converter is allowed to draw from the line at any given
instant must be proportional to the line voltage.
Since the boost converter topology in the ML4803 PFC is
of the current-averaging type, no slope compensation is
required.
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn ON right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
I3
I4
VIN
RL
SW1
DC
C1
RAMP
VEAO
REF
U3
+
EA
–
TIME
DFF
RAMP
OSC
U4
CLK
+
–
U1
R
Q
D U2
Q
CLK
VSW1
TIME
Figure 2. Typical Trailing Edge Control Scheme.
6
February 1999
ML4803
LEADING/TRAILING MODULATION (Continued)
programming resistor. The nominal voltage at the VEAO
pin is 5V. The VEAO voltage range is 4 to 6V. For a
11.3MW resistor chain to the boost output voltage and 5V
steady state at the VEAO, the boost output voltage would
be 400V.
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 2 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation is
determined during the OFF time of the switch. Figure 3
shows a leading edge control scheme.
PROGRAMMING RESISTOR VALUE
Equation 1 calculates the required programming resistor
value.
Rp =
VBOOST − VEAO 400V − 50
. V
=
= 113
. MΩ
IPGM
35µA
PFC VOLTAGE LOOP COMPENSATION
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns OFF
and Switch 2 (SW2) turns ON at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC’s output ripple
voltage can be reduced by as much as 30% using this
method, substantially reducing dissipation in the highvoltage PFC capacitor.
The voltage-loop bandwidth must be set to less than
120Hz to limit the amount of line current harmonic
distortion. A typical crossover frequency is 30Hz.
Equation 1, for simplicity, assumes that the pole capacitor
dominates the error amplifier gain at the loop unity-gain
frequency. Equation 2 places a pole at the crossover
frequency, providing 45 degrees of phase margin.
Equation 3 places a zero one decade prior to the pole.
Bode plots showing the overall gain and phase are shown
in Figures 5 and 6. Figure 4 displays a simplified model of
the voltage loop.
TYPICAL APPLICATIONS
C COMP =
Pin
C COMP =
The ML4803 utilizes a one pin voltage error amplifier in
the PFC section (VEAO). The error amplifier is in reality a
current sink which forces 35µA through the output
SW2
L1
+
I2
1
Rp × VBOOST × ∆VEAO × C OUT × 2 × π × f
ONE PIN ERROR AMP
I1
(1)
300W
0
6
2
(2)
5
113
. MW ´ 400V ´ 0.5V ´ 220mF ´ 2 ´ p ´ 30Hz
2
C COMP = 16nF
I3
I4
VIN
RL
SW1
DC
C1
RAMP
VEAO
REF
U3
+
–EA
RAMP
OSC
U4
CLK
VEAO
+
–
CMP
U1
TIME
DFF
R
Q
D U2
Q
CLK
VSW1
TIME
Figure 3. Typical Leading Edge Control Scheme.
February 1999
7
ML4803
TYPICAL APPLICATIONS (Continued)
R COMP =
R COMP =
C ZERO =
C ZERO =
1
(3)
2 ´ p ´ f ´ C COMP
1
= 330kW
6.28 ´ 30Hz ´ 16nF
PFC CURRENT SENSE FILTERING
1
2´ p ´
to develop the internal ramp by charging the internal
30pF +12/–10% capacitor. See Figures 10 and 11. The
frequency of the internal programming ramp is set
internally to 67kHz.
f
´ R COMP
10
(4)
1
= 0.16mF
6.28 ´ 3Hz ´ 330kW
INTERNAL VOLTAGE RAMP
The internal ramp current source is programmed by way of
the VEAO pin voltage. Figure 7 displays the internal ramp
current vs. the VEAO voltage. This current source is used
In DCM, the input current wave shaping technique used
by the ML4803 could cause the input current to run away.
In order for this technique to be able to operate properly
under DCM, the programming ramp must meet the boost
inductor current down-slope at zero amps. Assuming the
programming ramp is zero under light load, the OFF-time
will be terminated once the inductor current reaches zero.
Subsequently the PFC gate drive is initiated, eliminating
the necessary dead time needed for the DCM mode. This
forces the output to run away until the VCC OVP shuts
down the PFC. This situation is corrected by adding an
60
Power Stage
Overall Gain
Compensation
Network Gain
40
VO
11.3MΩ
VEAO
IOUT
ML4803
220µF
∆VEAO +
RLOAD
667Ω
ML4803
GAIN (dB)
20
0
–20
330kΩ
IVEAO
35µA
–40
15nF
–
0.15µF
POWER
STAGE
–60
0.1
10
1
COMPENSATION
Figure 4. Voltage Control Loop
0
1000
100
FREQUENCY (Hz)
Figure 5. Voltage Loop Gain
50
Power Stage
Overall
Compensation
Network
FF @ –55ºC
TYP @ –55ºC
40
50
IRAMP (µA)
PHASE (º)
TYP @ ROOM TEMP
100
150
200
0.1
TYP @ 155ºC
30
SS @ 155ºC
20
10
0
1
10
100
1000
0
8
2
3
4
5
6
7
VEAO (V)
FREQUENCY (Hz)
Figure 6. Voltage Loop Phase
1
Figure 7. Internal Ramp Current vs. VEAO
February 1999
ML4803
TYPICAL APPLICATIONS (Continued)
offset voltage to the current sense signal, which forces the
duty cycle to zero at light loads. This offset prevents the
PFC from operating in the DCM and forces pulse-skipping
from CCM to no-duty, avoiding DMC operation. External
filtering to the current sense signal helps to smooth out
the sense signal, expanding the operating range slightly
into the DCM range, but this should be done carefully, as
this filtering also reduces the bandwidth of the signal
feeding the pulse-by-pulse current limit signal. Figure 9
displays a typical circuit for adding offset to ISENSE at
light loads.
VEAO current sink and discharging the VEAO
compensation components until the steady state operating
point is reached. It should be noted that, as shown in
Figure 8, once the VEAO pin exceeds 6.5V, the internal
ramp is defeated. Because of this, an external Zener can
be installed to reduce the maximum voltage to which the
VEAO pin may rise in a shutdown condition. Clamping
the VEAO pin externally to 7.4V will reduce the time
required for the VEAO pin to recover to its steady state
value.
UVLO
PFC Start-Up and Soft Start
During steady state operation VEAO draws 35µA. At startup the internal current mirror which sinks this current is
defeated until VCC reaches 12V. This forces the PFC error
voltage to VCC at the time that the IC is enabled. With
leading edge modulation VCC on the VEAO pin forces
zero duty on the PFC output. When selecting external
compensation components and VCC supply circuits VEAO
must not be prevented from reaching 6V prior to VCC
reaching 12V in the turn-on sequence. This will guarantee
that the PFC stage will enter soft-start. Once VCC reaches
12V the 35µA VEAO current sink is enabled. VEAO
compensation components are then discharged by way of
the 35µA current sink until the steady state operating point
is reached. See Figure 8.
PFC SOFT RECOVERY FOLLOWING VCC OVP
The ML4803 assumes that VCC is generated from a source
that is proportional to the PFC output voltage. Once that
source reaches 16.2V the internal current sink tied to the
VEAO pin is disabled just as in the soft start turn-on
sequence. Once disabled, the VEAO pin charges HIGH
by way of the external components until the PFC duty
cycle goes to zero, disabling the PFC. The VCC OVP resets
once the VCC discharges below 16.2V, enabling the
Once VCC reaches 12V both the PFC and PWM are
enabled. The UVLO threshold is 9.1V providing 2.9V of
hysteresis.
GENERATING VCC
An internal clamp limits overvoltage to VCC. This clamp
circuit ensures that the VCC OVP circuitry of the ML4803
will function properly over tolerance and temperature
while protecting the part from voltage transients. This
circuit allows the ML4803 to deliver 15V nominal gate
drive at PWM OUT and PFC OUT, sufficient to drive lowcost IGBTs.
It is important to limit the current through the Zener to
avoid overheating or destroying it. This can be done with
a single resistor in series with the VCC pin, returned to a
bias supply of typically 14V to 18V. The resistor value
must be chosen to meet the operating current requirement
of the ML4803 itself (4.0mA max) plus the current
required by the two gate driver outputs.
VCC OVP
VCC is assumed to be a voltage proportional to the PFC
output voltage, typically a bootstrap winding off the boost
10V/div.
VCC
C23
0.01µF
0
VEAO
10V/div.
0
VOUT
PFC
GATE
10V/div.
200V/div.
0
CR16
1N4148
R28
20kΩ
C16
1µF
R4
1kΩ
R19
10kΩ
ISENSE
0
VBOOST
R29
20kΩ
C5
0.0082µF
R3
0.015Ω
3W
VCC
RTN
200ms/Div.
Figure 8. PFC Soft Start
Figure 9. ISENSE Offset for Light Load Conditions
February 1999
9
ML4803
TYPICAL APPLICATIONS (Continued)
inductor. The VCC OVP comparator senses when this
voltage exceeds 16V, and terminates the PFC output drive
while disabling the VEAO current sink. Once the VEAO
current sink is disabled, the VEAO voltage will charge
unabated, except for a diode clamp to VCC, reducing the
PFC pulse width. Once the VCC rail has decreased to
below 16.2V the VEAO sink will be enabled, discharging
external VEAO compensation components until the steady
state voltage is reached. Given that 15V on VCC
corresponds to 400V on the PFC output, 16V on VCC
corresponds to an OVP level of 426V.
COMPONENT REDUCTION
Components associated with the VRMS and IRMS pins of a
typical PFC controller such as the ML4824 have been
eliminated. The PFC power limit and bandwidth does vary
with line voltage. Double the power can be delivered from
a 220 V AC line versus a 110 V AC line. Since this is a
combination PFC/PWM, the power to the load is limited
by the PWM stage.
VISENSE
VC1 RAMP
GATE
DRIVE
OUTPUT
Figure 10. Typical Peak Current Mode Waveforms
VOUT = 400V
RP
VC1
VEAO
4
RCOMP
+
C1
30pF
CCOMP
35µA
5V
R1
CZERO
3
ISENSE
–4
VI SENSE
Figure 11. ML4803 PFC Control
10
February 1999
COMP
–
GATE
OUTPUT
ML4803
LINE F1 5A 250V
J1-1
R24
470kΩ
0.5W
C19
4.7nF
250VAC
102T
L2
TH1
10Ω
5A
C4
0.47µF
250VAC
Q5
R1
BR1
600V
4A
36Ω
Q2
NEUTRAL
J1-2
CR1 8A, 600V
1000µH
R2
L3
C20
4.7nF
250VAC
C1
220µF
450V
36Ω
R22
10kΩ
C16
0.01µF
CR5
16V
0.5W
R3 0.15Ω 3W
Q4
CR18 51V
R8 36Ω
CR7
CR3
R30 200Ω
T2
R13
5.62MΩ
3
10
4
C7
0.1µF
R28
20kΩ
1
2
3
CR12
4
R25
390kΩ
7.0V
C8
0.15µF
PFC
GND
ISENSE
VEAO
PWM
VCC
ILIMIT
VDC
C6
1µF
C28
1µF
12VRET
J2-2
4T
CR15
R6 1.2kΩ
5
6
R11 150Ω
5
R32 100Ω
CR11
C27
0.01µF
CR9
R21
10kΩ
U3
1
R37
330Ω
C17
0.1µF
2
4
R10
0.75Ω
3W
C14
4.7µF
R9
1.5kΩ
Q3
R5 36Ω
C10
2.2nF
R14
150Ω
2W
C26
0.01µF
500V
7
C5
8.2nF
C15
0.015µF
C9
1µF
C21
1µF
CR10
8
C2
2200µF
L2
R31
10Ω
ML4803
C3
1µF
CR8
C22
1µF
R19
10kΩ
J2-1
CR2
30A, 60V
L1 25µH
R26
20kΩ
3W
R29 20kΩ
R4 1kΩ
12V
CR2
30A
60V
R27
20kΩ
3W
CR16
IN4148
C25
0.01µF
500V
R36 220Ω
T1
C11
1000µF
R12
5.62MΩ
C18 4.7nF
R23
10kΩ
C29 0.01µF
R7
10Ω
C23
0.01µF
Q1
R38 22Ω
1
R15
9.09kΩ
C13 1nF
R17 3.3kΩ
CR4
R20
510Ω
3
1
U2
C12 0.1µF
2
R18 1kΩ
R16
2.37kΩ
Figure 12. Typical Application Circuit. Universal Input 240W 12V DC Output
February 1999
11
ML4803
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P08
8-Pin PDIP
0.365 - 0.385
(9.27 - 9.77)
0.055 - 0.065
(1.39 - 1.65)
8
0.240 - 0.260 0.299 - 0.335
(6.09 - 6.60) (7.59 - 8.50)
PIN 1 ID
1
0.020 MIN
(0.51 MIN)
(4 PLACES)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.016 - 0.020
(0.40 - 0.51)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
SEATING PLANE
Package: S08
8-Pin SOIC
0.189 - 0.199
(4.80 - 5.06)
8
PIN 1 ID
0.148 - 0.158 0.228 - 0.244
(3.76 - 4.01) (5.79 - 6.20)
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
0º - 8º
0.055 - 0.061
(1.40 - 1.55)
0.012 - 0.020
(0.30 - 0.51)
0.004 - 0.010
(0.10 - 0.26)
0.015 - 0.035
(0.38 - 0.89)
SEATING PLANE
12
February 1999
0.006 - 0.010
(0.15 - 0.26)
ML4803
ORDERING INFORMATION
PART NUMBER
PFC/PWM FREQUENCY
TEMPERATURE RANGE
PACKAGE
ML4803CP-1
ML4803CS-1
67kHz / 67kHz
67kHz / 67kHz
0°C to 70°C
0°C to 70°C
8-Pin PDIP (P08)
8-Pin SOIC (S08)
ML4803IP-1
ML4803IS-1
67kHz / 67kHz
67kHz / 67kHz
-40°C to 85°C
-40°C to 85°C
8-Pin PDIP (P08)
8-Pin SOIC (S08)
ML4803CP-2
ML4803CS-2
67kHz / 134kHz
67kHz / 134kHz
0°C to 70°C
0°C to 70°C
8-Pin PDIP (P08)
8-Pin SOIC (S08)
ML4803IP-2
ML4803IS-2
67kHz / 134kHz
67kHz / 134kHz
-40°C to 85°C
-40°C to 85°C
8-Pin PDIP (P08)
8-Pin SOIC (S08)
Micro Linear Corporation
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
www.microlinear.com
© Micro Linear 1999.
property of their respective owners.
is a registered trademark of Micro Linear Corporation. All other trademarks are the
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property
right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications.
DS4803-01
February 1999
13
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