HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE IDT71342SA/LA Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed access — Commercial: 20/25/35/45/55/70ns (max.) • Low-power operation — IDT71342SA Active: 500mW (typ.) Standby: 5mW (typ.) — IDT71342LA Active: 500mW (typ.) Standby: 1mW (typ.) • Fully asynchronous operation from either port • Full on-chip hardware support of semaphore signalling between ports • Battery backup operation—2V data retention • TTL-compatible; single 5V (±10%) power supply • Available in plastic packages • Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications The IDT71342 is an extremely high-speed 4K x 8 Dual-Port Static RAM with full on-chip hardware support of semaphore signalling between the two ports. The IDT71342 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. To assist in arbitrating between ports, a fully independent semaphore logic block is provided. This block contains unassigned flags which can be accessed by either side; however, only one side can control the flag at any time. An automatic power down feature, controlled by CE and SEM, permits the on-chip circuitry of each port to enter a very low standby power mode (both CE and SEM High). Fabricated using IDT’s CMOS high-performance technology, this device typically operates on only 500mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200µW from a 2V battery. The device is packaged in either a 64-pin TQFP, thin quad plastic flatpack, or a 52-pin PLCC. FUNCTIONAL BLOCK DIAGRAM R/ WL R/ WR CEL CE R OEL OE R I/O0L- I/O 7L COLUMN I/O COLUMN I/O I/O0R - I/O 7R MEMORY ARRAY SEMAPHORE LOGIC SEM R SEML A0L - A11L LEFT SIDE ADDRESS DECODE LOGIC RIGHT SIDE ADDRESS DECODE LOGIC A0R - A 11R 2721 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. OCTOBER 1996 For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. 6.05 DSC-2721/4 1 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATIONS(1,2) 7 6 5 A1L 8 A2L A3L 9 10 11 A11R WR R/ SEMR VCC CER WL R/ CEL A10R 46 OER 45 44 A0R A1R 43 42 A2R A3R A4R A5R A6R 41 40 39 38 16 17 18 19 A7R 37 36 A8R A9R N/C I/O7R I/O6R I/O3R I/O4R I/O5R 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 71342 PN64-1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-PIN TQFP(3) TOP VIEW I/O3L N/C I/O4L I/O5L I/O6L I/O7L N/C N/C GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Rating Com’l. Mil. Unit Terminal Voltage with Respect to Ground –0.5 to +7.0 –0.5 to +7.0 V TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT(3) Power Dissipation 1.5 1.5 W IOUT DC Output Current 50 50 mA CAPACITANCE(1) INDEX OEL (2) NOTES: 2721 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or 10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +0.5V. 2721 drw 02 A11R A10R N/C N/C SEM R WR CER R/ VCC N/C W SEML N/C N/C A10L A11L I/O0R I/O1R I/O2R 35 34 20 21 22 23 24 25 26 27 28 29 30 31 32 33 I/O4L I/O5L I/O2L I/O3L VTERM 52 51 50 49 48 47 PLCC (3) TOP VIEW N/C GND I/O1L 1 IDT71342 J52-1 13 14 15 L A9L I/O0L 12 CEL A7L A8L 2 R/ A5L A6L 4 3 I/O6L I/O7L A4L SEML OEL A0L INDEX A10L A11L Symbol 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R (TA = +25°C, f = 1.0MHz) TQFP Only Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF NOTES: 2721 tbl 02 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V and from 3V to 0V. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE 2721 drw 03 Grade Ambient Temperature GND VCC Commercial 0°C to +70°C 0V 5.0V ± 10% 2721 tbl 03 NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the actual part-marking. RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage GND Ground VIH VIL Input High Voltage Input Low Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 –0.5(1) NOTES: 1. VIL (min.) > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. 6.05 — — (2) 6.0 0.8 V V 2721 tbl 04 2 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = 5V ± 10%) IDT71342SA Symbol Parameter Test Conditions Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to VCC — 10 — 5 µA Output Leakage Current CE = VIH, VOUT = 0V to VCC — 10 — 5 µA Output Low Voltage IOL = 6mA — 0.4 — 0.4 V IOL = 8mA — 0.5 — 0.5 V IOH = –4mA 2.4 — 2.4 — |ILI| Input Leakage Current (1) |ILO| VOL VOH IDT71342LA Output High Voltage V NOTE: 1. At Vcc < 2.0V input leakages are undefined. 2721 tbl 05 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%) 71342X20 Symbol Parameter ICC Dynamic Operating Current (Both Ports Active) ICC1 ISB1 ISB2 Test Conditions CE = VIL Outputs Open SEM = Don't Care f = fMAX(3) Version 71342X25 71342X35 71342X45 71342X55 71342X70 Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit COM’L. S — 280 — 280 — 260 — 240 — 240 — 240 L — 240 — 240 — 220 — 200 — 200 — 200 mA Dynamic Operating CE = VIH COM’L. S — 280 — 200 — 185 — 170 — 170 — 170 Current (Semaphores Both Sides) Standby Current (Both Ports—TTL Level Inputs) Outputs Open L SEM < VIL f = fMAX(3) CEL and CER = VIH COM’L. S SEML = SEMR > VIH L f = fMAX(3) — 240 — 170 — 155 — 140 — 140 — 140 25 25 80 80 25 25 80 50 25 25 75 45 25 25 70 40 25 25 70 40 25 25 70 40 mA — — 180 150 — — 180 150 — — 170 140 — — 160 130 — — 160 130 — — 160 130 mA 1.0 0.2 15 4.5 1.0 0.2 15 4.0 1.0 0.2 15 4.0 1.0 0.2 15 4.0 1.0 0.2 15 4.0 1.0 0.2 15 4.0 mA — — 170 140 — — 170 140 — — 150 130 — — 150 120 — — 150 120 — — 150 120 mA Standby Current (One Port—TTL Level Inputs) ISB3 Full Standby Current (Both Ports—All CMOS Level Inputs) ISB4 Full Standby Current (One Port—All CMOS Level Inputs) CE"A" = VIL and CE"B" = VIH(5) COM’L. S L Active Port Outputs Open, f = fMAX(3) Both Ports CEL and COM’L. S CER > VCC - 0.2V L VIN > VCC - 0.2V or VIN < 0.2V SEML = SEMR > VCC - 0.2V, f = 0(4) One Port CE"A" or COM’L. S CE"B" > VCC - 0.2V L VIN > VCC - 0.2V or VIN < 0.2V SEML = SEMR > VCC - 0.2V Active Port Outputs Open, f = fMAX(3) NOTES: 1. “X” in part number indicates power rating (SA or LA). 2. VCC = 5V, TA = +25°C for typical values, and parameters are not production tested. 3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3. 5. Port "A" may be either left or right port. Port "B" is opposite from port "A". 6.05 mA 2721 tbl 06 3 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE DATA RETENTION CHARACTERISTICS (LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current Test Condition Min. Typ.(1) Max. Unit — 2.0 — — V — 100 1500 µA 0 — — ns — — VCC = 2V, CE ≥ VHC COM’L. SEM ≥ VHC tCDR(3) tR (3) Chip Deselect to Data Retention Time VIN ≥ VHC or ≤ VLC Operation Recovery Time tRC (2) ns 2721 tbl 07 NOTES: 1. VCC = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. DATA RETENTION WAVEFORM DATA RETENTION MODE VDR ≥ 2V 4.5V VCC 4.5V tCDR CE tR VDR VIH VIH 2721 drw 04 AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1 and 2 2721 tbl 08 +5V +5V 1250Ω 1250Ω DATAOUT 775Ω DATAOUT 30pF 775Ω 2721 drw 05 5pF * 2721 drw 06 Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig Figure 1. AC Output Test Load 6.05 4 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4) 71342X20 Symbol Parameter 71342X25 71342X35 Min. Max. Min. Max. Min. Max. Unit 20 — 25 — 35 — ns READ CYCLE tRC Read Cycle Time tAA Address Access Time — 20 — 25 — 35 ns tACE Chip Enable Access Time (3) — 20 — 25 — 35 ns tAOE Output Enable Access Time — 15 — 15 — 20 ns tOH Output Hold from Address Change 0 — 0 — 0 — ns 0 — 0 — 0 — ns — 15 — 15 — 20 ns 0 — 0 — 0 — ns — 50 — 50 — 50 ns — — 10 — 15 — ns tLZ tHZ tPU (1, 2) Output Low-Z Time Output High-Z Time (1, 2) (2) Chip Enable to Power Up Time (2) tPD Chip Disable to Power Down Time tSOP SEM Flag Update Pulse (OE or SEM) (4) tWDD Write Pulse to Data Delay — 40 — 50 — 60 ns tDDD Write Data Valid to Read Data Delay(4) — 30 — 30 — 35 ns tSAA Semaphore Address Access Time — — — 25 — 35 ns 2721 tbl 09 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4) (CONT'D) 71342X45 Symbol Parameter 71342X55 71342X70 Min. Max. Min. Max. Min. Max. Unit 45 — 55 — 70 — ns READ CYCLE tRC Read Cycle Time tAA Address Access Time — 45 — 55 — 70 ns tACE Chip Enable Access Time(3) — 45 — 55 — 70 ns tAOE Output Enable Access Time — 25 — 30 — 40 ns tOH Output Hold from Address Change 0 — 0 — 0 — ns 5 — 5 — 5 — ns — 20 — 25 — 30 ns tLZ tHZ (1, 2) Output Low-Z Time (1, 2) Output High-Z Time (2) tPU Chip Enable to Power Up Time 0 — 0 — 0 — ns tPD Chip Disable to Power Down Time(2) — 50 — 50 — 50 ns tSOP SEM Flag Update Pulse (OE or 15 — 20 — 20 — ns — 70 — 80 — 90 ns tWDD Write Pulse to Data Delay SEM) (4) (4) tDDD Write Data Valid to Read Data Delay — 45 — 55 — 70 ns tSAA Semaphore Address Access Time — 45 — 55 — 70 ns NOTES: 1. Transition is measured ±500mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, and SEM = VIL. 4. “X” in part number indicates power rating (SA or LA). 6.05 2721 tbl 10 5 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1, 2, 4, 6) tRC ADDRESS tAA or tSAA tOH DATAOUT tOH PREVIOUS DATA VALID DATA VALID 2721 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(1, 3) tSOP CE or SEM tACE (5) tAOE tSOP (4) tHZ (2) OE tLZ (1) tHZ VALID DATA DATAOUT tLZ (2) (4) (1) tPU tPD ICC CURRENT 50% 50% ISB 2721 drw 08 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH and address is valid prior to or coincident with CE transition Low. 4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA. 5. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for RAM Address Access and tSAA is for Semaphore Address Access. 6. R/W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1, 2) tWC ADDR "A" MATCH tWP (1) R/W "A" tDH tDW DATAIN "A" VALID ADDR "B" MATCH tWDD VALID DATAOUT "B" tDDD 2721 drw 09 NOTES: 1. Write cycle parameters should be adhered to, in order to ensure proper writing. 2. CEL = CER = VIL. CE"B" = VIL. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.05 6 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5) 71342X20 Symbol Parameter 71342X25 71342X35 Min. Max. Min. Max. Min. Max. Unit 20 — 25 — 35 — ns 15 — 20 — 30 — ns WRITE CYCLE tWC Write Cycle Time (3) tEW Chip Enable to End-of-Write tAW Address Valid to End-of-Write 15 — 20 — 30 — ns tAS Address Set-up Time 0 — 0 — 0 — ns tWP Write Pulse Width 15 — 20 — 25 — ns tWR Write Recovery Time 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 15 — 15 — 20 — ns — 0 — 3 10 10 15 — 15 — — — — 0 — 3 10 10 15 — 15 — — — — 3 — 3 10 10 20 — 20 — — — ns ns ns ns ns ns tHZ tDH tWZ tOW tSWR tSPS (1, 2) Output High-Z Time Data Hold Time(4) Write Enabled to Output in High-Z(1, 2) Output Active from End-of-Write(1, 2, 4) SEM Flag Write to Read Time SEM Flag Contention Window 2721 tbl 11 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)(CONT'D) 71342X45 Symbol Parameter Min. Max. 71342X55 Min. Max. 71342X70 Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 45 — 55 — 70 — ns tEW Chip Enable to End-of-Write(3) 40 — 50 — 60 — ns tAW Address Valid to End-of-Write 40 — 50 — 60 — ns tAS Address Set-up Time 0 — 0 — 0 — ns tWP Write Pulse Width 40 — 50 — 60 — ns tWR Write Recovery Time 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 20 — 25 — 30 — ns tHZ Output High-Z Time(1, 2) — 20 — 25 — 30 ns tDH Data Hold Time(4) 3 — 3 — 3 — ns tWZ Write Enabled to Output in High-Z (1, 2) — 20 — 25 — 30 ns tOW Output Active from End-of-Write(1, 2, 4) 3 — 3 — 3 — ns tSWR SEM Flag Write to Read Time 10 — 10 — 10 — ns tSPS SEM Flag Contention Window 10 — 10 — 10 — ns 2721 tbl 12 NOTES: 1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. “X” in part number indicates power rating (SA or LA). 6.05 7 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1, 5, 8) tWC ADDRESS tAS OE (6) (3) tAW CE or SEM tWR (9) tWP W (2) tHZ (7) R/ tWZ tLZ (7) tHZ tOW (4) (4) DATAOUT (7) tDH tDW DATAIN 2721 drw 10 TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1, 5) tWC ADDRESS tAW CE or SEM (9) (6) tAS tEW (3) (2) tWR W R/ tDW tDH DATAIN 2721 drw 11 NOTES: 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of either CE or SEM = VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going High to the end-of-write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE =V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 6.05 8 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1) tSAA A0 - A2 VALID ADDRESS tAW VALID ADDRESS tWR tACE tEW SEM DATA0 DATAOUT (2) VALID DATAIN VALID tAS tWP tOH tSOP tDW tDH R/ W tSWRD tAOE OE Write Cycle Test Cycle (Read Cycle) 2721 drw 12 NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value. TIMING WAVEFORM OF SEMAPHORE CONTENTION(1, 3, 4) A0"A" - A2"A" SIDE (2) "A" MATCH R/W "A" SEM "A" tSPS A0"B" - A2"B" (2) SIDE "B" MATCH W" " R/ B SEM "B" 2721 drw 13 NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 3. This parameter is measured from the point where R/W "A" or SEM "A" goes High until R/W "B" or SEM "B" goes High. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. 6.05 9 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAMs and can be read from or written to at the same time, with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Table 1 where CE and SEM are both high. Systems which can best use the IDT71342 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT71342’s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT71342 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor had set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT71342 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through the address pins A0–A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other (see Table II). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side’s semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence of WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as a one, a fact which the processor will verify by the subsequent read (see Table II). As an example, assume a 6.05 10 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE processor writes a zero in the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during a subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 3. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first TABLE I — NON-CONTENTION READ/WRITE CONTROL Left or Right Port(1) R/W CE SEM OE X H H X Z H H L L DATAOUT X u X X H Z H L X DATAIN H L H L DATAOUT L L H X DATAIN X L L X — D0-7 Function Port Disabled and in Power Down Mode Data in Semaphore Flag Output on Port Output Disabled Port Data Bit D0 Written Into Semaphore Flag Data in Memory Output on Port Data on Port Written Into Memory Not Allowed 2721 tbl 13 NOTE: 1. AOL = A10L ≠ A0R - A10R. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-impedance, and " " = Low-to-High transition. u TABLE II — EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE(1,2) D0 - D7 Left D0 - D7 Right No Action Function 1 1 Semaphore free Status Left Port Writes “0” to Semaphore 0 1 Left port has semaphore token Right Port Writes “0” to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes “1” to Semaphore 1 0 Right port obtains semaphore token Left Port Writes “0” to Semaphore 1 0 No change. Left side has no write access to semaphore Right Port Writes “1” to Semaphore 0 1 Left port obtains semaphore token Left Port Writes “1” to Semaphore 1 1 Semaphore free Right Port Writes “0” to Semaphore 1 0 Right port has semaphore token Right Port Writes “1” to Semaphore 1 1 Semaphore free Left Port Writes “0” to Semaphore 0 1 Left port has semaphore token Left Port Writes “1” to Semaphore 1 1 Semaphore free 2721 tbl 14 NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2. 6.05 11 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Code integrity is of the utmost importance when semaphores are used instead of slower, more restrictive hardware intensive schemes. Initialization of the semaphores is not automatic and must be handled via the initialization program at power up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORES–Some examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT71342’s Dual-Port RAM. Say the 4K x 8 RAM was to be divided into two 2K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of the memory. To take a resource, in this example the lower 2K of DualPort RAM, the processor on the left port could write and then read a zero into Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 2K. Meanwhile, the right processor would attempt to perform the same function. Since this processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 2K blocks of Dual-Port RAM with each other. The blocks do not have to by any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices had determined which memory area was “off limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D SEMAPHORE REQUEST FLIP FLOP Q Q D D0 WRITE WRITE SEMAPHORE READ SEMAPHORE READ 2721 drw 14 Figure 3. IDT71342 Semaphore Logic 6.05 12 IDT71342SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank Commercial (0°C to +70°C) J PF 52-pin PLCC (J52-1) 64-pin TQFP (PN64-1) 20 25 35 45 55 70 LA SA 71342 Speed in nanoseconds Low Power Standard Power 32K (4K x 8-Bit) Dual-Port RAM w/ Semaphore 2721 drw 15 6.05 13