IXYS CPC5601D Auxiliary programmable driver ic Datasheet

CPC5601 LITELINK™ Family
Auxiliary Programmable Driver IC
INTEGRATED CIRCUITS DIVISION
Features
Description
•
•
•
•
The CPC5601 is a serially-programmed driver IC for
use with IXYS Integrated Circuits Division’s LITELINK
Silicon Data Access Arrangement (DAA) ICs. The
CPC5601 allows host-equipment control of DAA characteristics for worldwide DAA implementations, avoiding multiple implementations with discrete component
changes or “stuff” options. The small, low-profile package makes the CPC5601 ideal for 56K PC Card
(PCMCIA) modems, PC motherboards, and softmodems.
Meets PC Card (PCMCIA) height requirements
Zero standby current
PCB real estate and cost savings
Can be used with LITELINK II and LITELINK III parts
Compliance
•
•
•
•
•
•
•
•
TIA/EIA/IS-968 (FCC part 68)
UL1950
UL60950
EN/IEC 60950-1 compliant
EN55022B
CISPR22B
EN55024
TBR-21
The CPC5601 uses opto-electronics to maintain the
isolation barrier required in the data access arrangement for connection of host devices to the public
switched telephone network (PSTN).
Ordering Information
Part Number
Description
CPC5601D
16-pin, 14-lead SOIC, 0.300” wide package,
50/Tube
CPC5601DTR
16-pin, 14-lead SOIC, 0.300” wide package,
1000/Reel
The one-bit serial input of the CPC5601 recovers
clocking information from the input signal to set bits in
the shift register. The shift register outputs connect to
open-drain FET latches that are used to switch in different external components to set V/I slope, DC termination current limit, gain, and AC termination value in
LITELINK DAA implementations.The CPC5601 does
not need a clock signal for shift register operation, but
relies on internal timing instead.
The CPC5601 also includes an opto-coupler for ring
detection applications where the AC coupled ring
detector of the LITELINK DAA is not used.
Figure 1. CPC5601 Block Diagram
RING
16
1
15
GND
INPUT
NC
2
14
3
13
12
11
10
9
8
7
6
Pb
DS-CPC5601-R04
Shift
Register
Drivers
LEDLED+
VDDLINE
B1
B2
B3
B4
B5
B6
-BR
e3
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1
CPC5601
INTEGRATED CIRCUITS DIVISION
1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. 1 Absolute Minimum and Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. 2 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. 3 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. 4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
4
4
2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. 1 Application Circuit Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. 2 AC Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. 3 LITELINK III Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. 4 Current Limiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. 5 Figure 3. Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2. 6 Figure 4. Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2. 7 Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. 8 Output Current Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. 1 Latch Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. 2 Programming Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. 3 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
11
4 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. 1 Clare Design Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. 2 Third Party Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. 1 Moisture Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. 2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. 3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. 4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. 5 CPC5601D Package 15
6. 6 CPC5601DTR Tape and Reel Specifications 15
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R04
CPC5601
INTEGRATED CIRCUITS DIVISION
1. Specifications
1.1 Absolute Minimum and Maximum Ratings
Parameter
Isolation Voltage
Operating temperature
Minimum
Maximum
Unit
Conditions
1500
-
VRMS
From pins 1, 2, and 3 to
pins 7 through 16
0
+85
°C
Storage temperature
-40
+125
°C
Soldering temperature
-
+220
°C
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings
can cause permanent damage to the
device. Functional operation of the device
at these or any other conditions beyond
those indicated in the operational sections
of this data sheet is not implied. Exposure
of the device to the absolute maximum ratings for an extended period may degrade
the device and affect its reliability.
1.2 Electrical Characteristics
Parameter
Minimum
Typical
Maximum
Unit
Conditions
Data Input
Input high threshold current
-
1
5
mA
Input low threshold current
0.10
0.20
-
mA
Input voltage drop
0.9
1.2
1.4
V
-
-
10
mA
IF = 5 mA
b1 Through b5 Output Driver
Output Current
Output Breakdown Voltage
-
-
6
V
On Resistance
-
10
11

-
-
120
mA
Supply voltage >= 2.8 V
b6 Output Driver
Output Current
Output Breakdown Voltage
-
-
6
V
On Resistance
-
0.5
1.4

Supply voltage >= 2.8 V
6
20
100
mA
IC = 2 mA, VCE = 0.5 V
0.9
1.2
1.4
V
IF = 5 mA
20
50
-
V
IC = 10 mA
Dark Current
-
50
500
nA
IF = 0 mA
Saturation Voltage
-
0.3
0.5
V
IC = 2 mA, IF = 16 mA
33
400
-
%
IF = 6 mA, VCE = 0.5 V
Ring Detect Input
Input Control Current
Input Voltage drop
Ring Detect Output
Blocking Voltage
Current transfer ratio
Power Requirements
Supply Voltage
2.5
3.5
5.5
V
Total supply current (input current low)
-
0.01
1
A
Total supply current (input current high)
-
10
20
A
Specifications subject to change without notice. All performance characteristics based on the use of IXYS Integrated Circuits Division application circuits. Functional operation of the device at conditions beyond those specified here is not implied. Specification conditions: VDD = 5V, temperature = 25
°C, unless otherwise indicated.
R04
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CPC5601
INTEGRATED CIRCUITS DIVISION
1.3 Timing Characteristics
Parameter
Minimum
Typical
Maximum
Unit
Conditions
Setup time
50
-
-
S
logic low before positive timing transition on input (pin 3)
Data hold time
60
-
-
S
hold time after internal 140 S
clock period
Data latch time
-
-
140
S
from positive transition on input
Input hold time for output on
200
-
-
S
Input hold time for output off
-
-
50
S
1.4 Pinout
Pin
Name
Figure 2. CPC5601 Pinout
Function
1
RING
Opto-isolated ring output
2
GND
Analog host system ground
3
INPUT
Serial data input used to program outputs b1
through b6.
4
NC
No connection
5
NC
No connection
6
NC
No connection
7
BR-
Phone line side common
8
B6
Output b6
9
B5
Output b5
10 B4
Output b4
11 B3
Output b3
12 B2
Output b2
13 B1
Output b1
14 VDDLINE
Telephone line side voltage source
15 LED+
Ring LED anode
16 LED-
Ring LED cathode
4
1
16
2
15
3
14
13
12
6
11
7
10
8
9
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R04
CPC5601
INTEGRATED CIRCUITS DIVISION
2. Application
In the application circuits shown below, the CPC5601
is used to switch AC termination and gain. Loop-current limit switching is optional.
Figure 3. CPC5601 Application Circuit Using the LITELINK II and the Optical Snoop Circuit
II
501K
C3 0.1
REFM
R77 499K 1%
0.015
301
¹This design was tested and found to comply with FCC part 68 with this part.
Other compliance requirements may require a different part.
²Higher noise power supplies may require substitution of a 220 H inductor,
Toko 380HB-2215 or similar. See the power quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information. Both application circuits use the same components for setting AC
termination and the telephone line current limit.
R04
3
Addition of this capacitor improves trans-hybrid loss.
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5
CPC5601
INTEGRATED CIRCUITS DIVISION
Figure 4. CPC5601 Application Circuit Using the LITELINK III and the LITELINK Snoop Circuit
3.3 or 5 V
R23²
10
C1
1
FB1
600 
200 mA
C16
10
C9
0.1
A
U1
LITELINK III
A
1
R1 (RTX) 80.6K 1%
2
C13 0.1
3
TX-
C2 0.1
TX+
4
5
6
MODE
7
8
OH
REFL
VDD
TXSM
TXF
TX-
ZTX
TX+
ZNT
TX
TXSL
BR-
MODE
NTS
GND
GAT
OH
9 RING
10 CID
RING
CID
NTF
DCS1
C14 0.1 11
RX12 RX+
C4 0.1
13 SNP+
14 SNP-
RXRX+
DCS2
ZDC
BRRPB
15 RXF
16 RX
RXS
VDDL
32
31
C15
0.01
500V
30
29
28
R22 (RDCS1A)
6.8 M 1%
R21 (RDCS1B)
6.2 M 1%
R14
(RGAT)
47
26
R10 499K 1%
25
BR-
Q1
CPC5602C
R13
(RNTS)
501K
1%
R75 (RNTX)
261K 1%
27
24
C12 (CDCS)
0.027
C21 (CGAT) 100 pF
23
R12 (RNTF) 499K 1%
22
R15 (RDCS2)
1.69M 1%
21
20
R16 (RZDC) 8.2 1%
19
R78 (RHNTF)
200K 1%
18
BR-
R20
(RVDDL)
2
BR-
+ DB1
NOTE: Unless otherwise
noted, all resistors are in
Ohms, 5%. All capacitors
are in microFarads.
17
R2
(RRXF)
130K
1%
A
C10
0.01
500V
BRR5 (RTXF)
60.4K
1%
TIP
R8 (RHTX)
221K 1%
R4
(RPB)
68.1
1%
BR-
SP1¹
-
C18
15 pF³
1
BR2
RING
C7
(CSNP-)
220pF
2000V
R6 (RSNP-2)
1.8M 1/10W 1%
R44 (RSNP-1)
1.8M 1/10W 1%
R7 (RSNP+2)
C8
(CSNP+) 1.8M 1/10W 1%
220pF
2000V
R45 (RSNP+1)
1.8M 1/10W 1%
R3
(RSNPD)
1.5M
1%
U4
CPC5601
1
RING
LED-
2
GND
R65 3
PROG
470 4
NC
5
NC
6
NC
7
BR8
B6
A
PROG
-BR
LED+
VDDLINE
B1
B2
B3
B4
B5
R76
100K
5%
16
15
14
13
12
C34
2.2 F
R67 301 1%
R66 4.99K 1%
C31
0.68 F
11
10
9
R71
165
1%
R72
59
1%
C33
0.024 F
R75
200K
1%
-BR
R73
R18
(RZTX)
10K
1%
-BR
¹This design was tested and found to comply with FCC part 68 with this part.
Other compliance requirements may require a different part.
²Higher noise power supplies may require substitution of a 220 H inductor,
Toko 380HB-2215 or similar. See the power quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information. Both application circuits use the same components for setting AC
termination and the telephone line current limit.
6
3
Addition of this capacitor improves trans-hybrid loss.
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R04
CPC5601
INTEGRATED CIRCUITS DIVISION
2.1 Application Circuit Configurations
Figure 4 shows LITELINK II in circuit designed to use
the optical snoop circuit in the CPC5601 for ring
detection. Figure 5 shows LITELINK III in a circuit that
uses the LITELINK snoop circuit ring detection and
display feature (caller ID) signal processing. Note that
either generation of LITELINK can be used with either
signal monitoring scheme. Using the optical path on
the CPC5601 for ring detect precludes on-hook display feature signal processing.
2.4 Current Limiting
Clare recommends using the default value for RZDC
to set the loop-current limit to 133 mA. You can, if
required, adjust the current limit level by adding R73
and using output b6 to switch this value in parallel with
RZDC. See the appropriate LITELINK datasheet for
more information on setting loop-current limits.
2.2 AC Termination
2.2.1 LITELINK II
The networks connected to outputs b1, b2, b3 and b4
provide selectable telephone line AC termination
depending on which network is switched in place of
RZNT (see the appropriate LITELINK data sheet and the
application note Understanding LITELINK for more information).
In North American applications, turn outputs b1 and
b2 on, and turn outputs b3 and b4 off to switch in the
required 600  AC termination. For European applications, turn outputs b1 and b2 off, and outputs b3 and
b4 on to switch in the complex AC termination network.
2.2.2 LITELINK III
The networks connected to outputs b1 and b3 provide
selectable telephone line AC termination depending
on which network is switched in place of RZNT (see the
appropriate LITELINK data sheet and the application
note Understanding LITELINK for more information). The
resistor connected to output b2 provides the required
bias current for North American applications.
In North American applications, turn outputs b1 and
b2 on, and turn output b3 off to switch in the required
600  AC termination. For European applications, turn
outputs b1 and b2 off, and output b3 on to switch in the
complex AC termination network.
2.3 LITELINK III Gain
Turning output 5 on adds attenuation to the receive
path, which is required for the complex termination.
Asserting the MODE pin on LITELINK III corrects for
the added attenuation.
R04
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7
CPC5601
INTEGRATED CIRCUITS DIVISION
2.5 Figure 3. Part List
Qty.
1
1
1
1
1
1
2
1
1
1
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
Reference
U1
U4
Q1
Q2
DB1
D1
Z1, Z2
SP1
FB1
C1
C2, C3, C4, C9,
C13, C14
C10
C12
C15
C16
C29
C30
C31
C32
C33
C34
R1
R2
R4
R5
R8, R9
R13
R14
R15
R20
R21
R22
R23
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
Value
CPC561x LITELINK II
CPC5601 Auxiliary Programmable Driver
CPC5602C N-Channel Depletion-Mode FET
MMBT4126 PNP bipolar transistor
S1ZB60 or DB104 Bridge Rectifier
1N914
10V Zener Diode
P3100SB Sidactor
600 , 200 mA ferrite bead
1 F, 16 V, ± 10%
Suppliers
IXYS Integrated Circuits Division
Fairchild
Sindengen Co., Diodes, Inc.
Teccor, TI, ST Microelectronics
Murata BLM11A601S or similar
0.1 F, 16 V, ± 10%
0.01 F, 500 V, ± 10%1
0.027 F, 16 V, ± 10%
0.0022 F, 500 V, ± 10%1
10 F, 16 V, ± 10%
1.5 F, 16 V, ± 10%
0.47 F, 300 V, ± 10%
0.68 F, 16 V, ± 10%
0.47 F, 16 V, ± 10%
0.015 F, 16 V, ± 10%
2.2 F, 16 V, ± 10%
80.6 K, 1/16W, ± 1%
127 K, 1/16W, ± 1%
68.1 , 1/16W, ± 1%
42.2 K, 1/16W, ± 1%
200 K, 1/16W, ± 1%
501 K, 1/16W, ± 1%
47 , 1/16W, ± 1%
1.69 M, 1/16W, ± 1%
2 , 1/16W, ± 1%
6.2 M, 1/4W, ± 1%
6.8 M, 1/4W, ± 1%
10 , 1/16W, ± 5% or 220 H inductor
10 k, 1/16W, ± 5%
470 , 1/16W, ± 5%
150 , 1/16W, ± 1%
301 , 1/16W, ± 1%
82.5 , 1/16W, ± 1%
29.4 , 1/16W, ± 1%
8.2 k, 1/4W, ± 5%
165 , 1/16W, ± 1%
59 , 1/16W, ± 1%
optional, see text
10 , 1/16W, ± 1%
402 k, 1/16W, ± 1%
100 k, 1/16W, ± 5%
499 k, 1/16W, ± 1%
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Panasonic, Electro Films, FMI, Vishay, etc.
R04
CPC5601
INTEGRATED CIRCUITS DIVISION
2.6 Figure 4. Part List
Qty.
1
1
1
1
1
1
1
4
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R04
Reference
U1
U4
Q1
DB1
SP1
FB1
C1
C2, C9, C13, C14
C7, C8
C10, C15
C12
C15
C16
C18
C21
C29
C30
C31
C32
C33
C34
R1
R2
R3
R4
R5
R6, R7, R44, R45
R8
R10, R12
R13
R14
R15
R16
R18
R20
R21
R22
R23
R64
R65
R66
R67
R71
R72
R73
R75
R76
R77
R78
Value
CPC562x LITELINK III
CPC5601 Auxiliary Programmable Driver
CPC5602C N-Channel Depletion-Mode FET
S1ZB60 or DB104 Bridge Rectifier
P3100SB Sidactor
600 , 200 mA ferrite bead
1 F, 16 V, ± 10%
0.1 F, 16 V, ± 10%
220 pF, 2 kV, ±5%1
0.01 F, 500 V, ± 10%1
0.027 F, 16 V, ± 10%
0.0022 F, 500 V, ± 10%1
10 F, 16 V, ± 10%
15 pF, 50 V, ± 10%
100 pF, 50 V, ± 10%
1.5 F, 16 V, ± 10%
0.47 F, 300 V, ± 10%
0.68 F, 16 V, ± 10%
0.47 F, 16 V, ± 10%
0.024 F, 16 V, ± 10%
2.2 F, 16 V, ± 10%
80.6 K, 1/16W, ± 1%
130 K, 1/16W, ± 1%
1.5 M, 1/16W, ± 1%
68.1 , 1/16W, ± 1%
60.4 K, 1/16W, ± 1%
1.8 M, 1/10W, ± 1%
221 K, 1/16W, ± 1%
499 K, 1/16W, ± 1%
501 K, 1/16W, ± 1%
47 , 1/16W, ± 1%
1.69 M, 1/16W, ± 1%
8.2 , 1/16W, ± 1%
10 K, 1/16W, ± 1%
2 , 1/16W, ± 1%
6.2 M, 1/4W, ± 1%
6.8 M, 1/4W, ± 1%
10 , 1/16W, ± 5% or 220 H inductor
10 k, 1/16W, ± 5%
470 , 1/16W, ± 5%
150 , 1/16W, ± 1%
301 , 1/16W, ± 1%
165 , 1/16W, ± 1%
59 , 1/16W, ± 1%
optional, see text
402 k, 1/16W, ± 1%
100 k, 1/16W, ± 5%
499 k, 1/16W, ± 1%
200 k, 1/16W, ± 1%
www.ixysic.com
Suppliers
IXYS Integrated Circuits Division
Sindengen Co., Diodes, Inc.
Teccor, TI, ST Microelectronics
Murata BLM11A601S or similar
Panasonic, AVX, Novacap, Murata, SMEC
Panasonic, Electro Films, FMI, Vishay, etc.
9
CPC5601
INTEGRATED CIRCUITS DIVISION
2.7 Operational Sequence
In the application circuits above, the CPC5601 is powered from the telephone line only when the LITELINK
is off-hook. This requires that you set the telephone
line characteristics controlled by the CPC5601 under
host system control immediately after taking the DAA
off-hook or after pulse dialing is complete, using the
following sequence:
1. For incoming calls, validate a ring signal by having the host system poll or read the output of
RING (ring detect via snoop circuit on the LITELINK) or RING (ring detect via opto-isolated ring
circuit in the CPC5601).
2. Assert OH to complete the connection.
3. Set the telephone line characteristics of the DAA
using the CPC5601 via the programming method
(see “Programming” on page 10).
With this circuit, you must program the CPC5601 as
soon as possible after asserting off hook. Leaving the
CPC5601 unprogrammed leaves open the possibility
of LITELINK instability due to lack of AC termination.
2.8 Output Current Ratings
Output b6 is the only output that can be used for the
current limiting function of a DAA. The FET on output
b6 can sink up to 120 mA of current, while the other
outputs can sink up to 10 mA.
The other outputs can be used for any of the other
switchable functions on the telephone line side of a
DAA, as long as the current does not exceed the
10 mA limit.
3. Programming
3.1 Latch Circuit Description
Data applied to the input pin is optically coupled to the
shift register through a pulse generator. Each low-tohigh transition in the pulse generator triggers a clock
pulse. Clock pulses are applied to the CLK input of six
rising-edge-triggered flip-flops. The non-inverted input
data is fed to the flip-flops at all times, but the flip-flops
are only clocked on receipt of a pulse from the pulse
generator. The flip-flops drive six FET switches.
10
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R04
CPC5601
INTEGRATED CIRCUITS DIVISION
3.2 Programming Protocol
Figure 5. Latch Circuit Timing to Turn an Output On
t0
INPUT (pin 3)
140 s
>=50s (tsetup)
200 s
Transition after setup time
initiates clock pulse
CLOCK
thold
reads data
First
at the rising edge of the clock
B1 (pin 13)
B1 output FET
(drain open)
B1 output FET on (sinking current)
A setup pulse on the input of at least 50 S starts the
bit programming sequence. The trailing edge of the
setup pulse starts a timer on the CPC5601 (t0). After
140 S, the value of the input is latched into the shift
register.
To set an output, hold the input high for 200 S from
the leading edge after the setup pulse. This turns on
the corresponding open-drain FET to sink current.
Figure 6. Latch Circuit Timing to Turn an Output Off
>=50 s (tsetup)
t0
50 s
140 s
INPUT (pin 3)
150 s min
Transition after setup time
initiates clock pulse
CLOCK
B1 (pin 13)
First
reads data
at the rising edge of the clock
B1 output FET on (sinking current)
To clear an output, hold the input high for 50 S after
the setup pulse, then take the input low for at least 150
S.
Repeat the sequence of the setup pulse followed by
the appropriate input condition for each successive bit.
B1 output FET
(drain open)
absence of low-to-high transitions on the input, the
internal CPC5601 clock is held high, preventing any
output changes.
• The CPC5601 does not employ a shift register load
function. As new data is shifted into the flip-flops, the
outputs (starting with b1) change throughout the
data input sequence.
Bear the following in mind while programming the
CPC5601:
• All bits must be set in each programming sequence,
even to change just one of the outputs.
• Data is placed in least-significant bit (output 1) first.
• After setting all the bits, take the input low. In the
R04
3.3 Programming Example
This programming example sets the following
CPC5601 output state, suitable for a European DAA:
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11
CPC5601
INTEGRATED CIRCUITS DIVISION
2. Set the input high for 50 S to trigger the timer.
3. Set the input low for 150 S to set output b1 to
off.
4. Repeat the steps as shown in the programming
waveform below to program all six outputs to the
desired pattern.
3.3.1 LITELINK III
b1 (LSB)
b2
b3
b4
b5
b6 (MSB)
off
off
on
off
on
off
3.3.2 LITELINK II
b1 (LSB)
b2
b3
b4
b5
b6 (MSB)
off
off
on
on
on
off
1. Hold the input low for 50 S.
Figure 7. LITELINK III European Programming Sample Input Waveform
t0
timer
trigger
setup
setup
bit 1
set off
timer
trigger
timer
trigger
setup
bit 2
set off
bit 4
set off
bit 3
set on
setup
setup
setup
timer
trigger
timer
trigger
timer
trigger
bit 5
set on
bit 6
set off
timer
trigger
timer
trigger
50S/div.
Figure 8. LITELINK II European Programming Sample Input Waveform
t0
timer
trigger
setup
setup
bit 1
set off
timer
trigger
timer
trigger
setup
bit 2
set off
timer
trigger
bit 3
set on
setup
setup
setup
bit 4
set on
bit 5
set on
bit 6
set off
50S/div.
12
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R04
CPC5601
INTEGRATED CIRCUITS DIVISION
4. Regulatory Information
CPC5601 can be used to build products that comply
with the requirements of TIA/EIA/IS-968 (formerly
FCC part 68), FCC part 15B, TBR-21, EN60950,
UL1950, EN55022B, IEC950/IEC60950, CISPR22B,
EN55024, and many other standards. CPC5601 complies with the requirements of UL1577. CPC5601 provides supplementary isolation. Metallic surge
requirements are met through the inclusion of a Sidactor in the application circuit. Longitudinal surge protection is provided by CPC5601’s optical-across-thebarrier technology and the use of high-voltage components in the application circuit as needed.
The information provided in this document is intended
to inform the equipment designer but it is not sufficient
to assure proper system design or regulatory compliance. Since it is the equipment manufacturer's responsibility to have their equipment properly designed to
conform to all relevant regulations, designers using
CPC5601 are advised to carefully verify that their endproduct design complies with all applicable safety,
EMC, and other relevant standards and regulations.
Semiconductor components are not rated to withstand
electrical overstress or electro-static discharges resulting from inadequate protection measures at the board
or system level.
5. LITELINK Design Resources
5.1 Clare Design Resources
The IXYS Integrated Circuits Division web site has a
wealth of information useful for designing with LITELINK, including application notes and reference
designs that already meet all applicable regulatory
requirements. LITELINK data sheets also contains
additional application and design information. See the
following links:
Application note AN-147, Worldwide Application of LITELINK
Application note AN-149, Increased LITELINK II Transmit
Power
Application note AN-150, Ground-start Supervision Circuit Using IAA110
LITELINK datasheets and reference designs
Application note AN-107 LOCxx Series - Isolated Amplifier Design Principles
5.2 Third Party Design Resources
The following also contain information useful for LITELINK designs. All of the books are available on amazon.com.
Application note AN-114 ITC117P
Application note AN-117 Customize Caller-ID Gain and
Ring Detect Voltage Threshold for CPC5610/11
Understanding Telephone Electronics, Stephen J. Bigelow, et. al., Butterworth-Heinenman; ISBN:
0750671750.
Newton’s Telecom Dictionary, Harry Newton, CMP
Books; ISBN: 1578200695.
Application note AN-140, Understanding LITELINK
Application note AN-141, Enhanced Pulse Dialing with
LITELINK
Application note AN-143, Loop Reversal Detection with
LITELINK
Photodiode Amplifiers: Op Amp Solutions, Jerald
Graeme, McGraw-Hill Professional Publishing; ISBN:
007024247X
Teccor, Inc. Surge Protection Products
Application note AN-146, Guidelines for Effective LITELINK Designs
R04
United States Code of Federal Regulations, CFR 47
Part 68.3.
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13
CPC5601
INTEGRATED CIRCUITS DIVISION
6. Manufacturing Information
6.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC5601D
MSL 3
6.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
6.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC5601D
260°C for 30 seconds
6.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or Fluorinebased solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used.
Pb
14
e3
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R04
CPC5601
INTEGRATED CIRCUITS DIVISION
6.5 CPC5601D Package
10.160±0.051
(0.400±0.002)
PCB Land Pattern
0.254 ±0.0127
(0.010±0.0005)
PIN 16
10.363±0.127
(0.408±0.005)
7.493±0.127
(0.295±0.005)
0.635 X 45°
(0.025 X 45°)
1.016 TYP
(0.040 TYP)
9.30
(0.366)
1.90
(0.075)
PIN 1
1.270 TYP
(0.050 TYP)
2.108 MAX
(0.083 MAX)
See Note 3
0.406 TYP
(0.016 TYP)
8.890 TYP
(0.350 TYP)
0.483±0.102
(0.019±0.004)
1.27
(0.050)
1.981±0.025
(0.078±0.001)
Lead to Package Standoff:
MIN: 0.000
MAX: 0.102 (0.004)
0.60
(0.024)
DIMENSIONS
mm
(inches)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating
(1000 microinch maximum).
3. Sum of package height, standoff, and coplanarity
does not exceed 2.108 (0.083).
6.6 CPC5601DTR Tape and Reel Specifications
330.2 DIA.
(13.00 DIA.)
W=16
(0.630)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
B0=10.70
(0.421)
K0=3.20
(0.126)
A0=10.90
(0.429)
P=12.00
(0.472)
K1=2.70
(0.106)
Embossed Carrier
Embossment
NOTES:
1. All dimensions carry tolerances of EIA Standard 481-2
2. The tape complies with all “Notes” for constant dimensions
listed on page 5 of EIA-481-2
Dimensions
mm
(inches)
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-CPC5601-R04
©Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/22/2012
R04
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15