MOTOROLA MC145740 Dual tone multiple frequency line interface Datasheet

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by MC145740/D
SEMICONDUCTOR TECHNICAL DATA
Product Preview
20
The MC145740 is a silicon gate HCMOS LSI designed for general purpose
Dual Tone Multiple Frequency (DTMF) communications, and contains a DTMF
signal generator and a receiver for all 16 standard digits.
The generator block has a differential line driver which drives a 600 Ω load
with 0 dBm level. The transmit signal level is adjusted in 1 dB steps by the
programmable attenuator.
The receiver block has an Auto Gain Control (AGC) amplifier to demodulate
50 dB (typ) dynamic range of DTMF signals to the hexadecimal codes.
The device also includes a serial control interface that permits a CPU to
exercise the following built–in features.
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F SUFFIX
SOG PACKAGE
CASE 751J
1
ORDERING INFORMATION
MC145740F
SOG Package
PIN ASSIGNMENT
Single Power Supply: 3.6 to 5.5 V
DTMF Generator and Receiver for All 16 Standard Digits
0 dBm Line Driver Into 600 Ω Load
AGC Amplifier
Programmable Transmit Attenuator
Serial Control Interface
Power Down Mode, Less Than 1 µA
TxA1
1
20
DSI
TxA2
2
19
VDD
RxA
3
18
VSS
AGCout
4
17
CLK
Vref
5
16
EN
FC1
6
15
DATA
FC2
7
14
R/W
X1
8
13
TD
X2
9
12
DV
10
11
VDD
VSS
BLOCK DIAGRAM
AGCout
FC1
Rx GAIN
CONTROL
WITH AGC
AMP
RxA
HIGH–BAND
BPF
ANTI–ALIAS
FILTER
FC2
TIMING
CIRCUIT
DTMF
DETECTER
DV
TD
LOW–BAND
BPF
DSI
TxA2
TxA1
SMOOTHING
FILTER AND
Tx GAIN
CONTROL
–
+
DTMF
GENERATOR
–1
CONTROL REGISTER
AND
SERIAL INTERFACE
EN
CLK
DATA
R/W
CLOCK
GENERATOR
X1
X2
VDD
VSS
Vref
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 0
8/96

Motorola, Inc. 1996
MOTOROLA
MC145740
1
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MAXIMUM RATINGS (Voltages Referenced to VSS Unless Otherwise Noted)
Ratings
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin
– 0.5 to VCC + 0.5
V
I
± 20
mA
Power Dissipation
PD
500
mW
Storage Temperature Range
Tstg
– 65 to + 150
°C
DC Supply Voltage
Input Voltage, All Pins
DC Current Per Pin
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
applications of any voltage higher than maximum rated voltages to this high impedance
circuit. For proper operation, it is recommended
that Vin and Vout be constrained to the range
VSS ≤ (Vin or Vout) ≤ VDD.
Reliability of operation is enhanced if unused
logic inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
DC Supply Voltage
Typ
Max
Unit
VCC
3.6
5
5.5
V
Input Voltage, All Pins
Vin
0
—
VCC
V
Input Rise or Fall Time
tr, tf
0
—
500
ns
Crystal Frequency
fosc
—
3.5795
—
MHz
TA
– 20
25
70
°C
Min
Typ
Max
Unit
V
Operating Temperature Range
DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ± 10%, TA = – 20 to 70°C)
Symbol
Parameter
Condition
Input Voltage
H Level
VIH
3.15
—
—
EN, CLK, DATA, R/W
L Level
VIL
—
—
1.1
Output Voltage
H Level
VOH
IOH = 20 µA
VCC – 0.1
VCC – 0.01
—
DV, TD, DATA
L Level
VOL
IOL = – 20 µA
IOL = – 2 mA
—
—
0.01
—
0.1
0.4
Vin = VDD or VSS
—
± 1.0
± 10.0
µA
DTMF Tx Mode
—
5
—
mA
DTMF Rx Mode
—
8
—
Power Down 1
—
—
500
Power Down 2
—
—
1
Input Current
Supply Current
Standby Current
MC145740
2
R/W, DATA, EN, CLK
Iin
IDD
IDD
V
µA
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
DTMF TRANSMIT CHARACTERISTICS (VCC = 5 V ± 10%, TA = – 20 to 70°C)
Parameter
Min
Typ
Max
Unit
—
2.5
—
dBm
—
3.5
—
0
—
3
dB
DIST
—
5
—
%
DTMF Frequency Variation
∆fV
–1
—
1
%
Out–of–Band Energy
(See Figure 1)
VOE
—
—
—
Setup Time
tosc
—
4
—
ms
Min
Typ
Max
Unit
0
—
15
dB
1 dB – 5 dB
– 0.5
—
0.5
dB
6 dB – 9 dB
–1
—
1
10 dB – 15 dB
– 1.7
—
1
Min
Typ
Max
Unit
50
—
—
kΩ
Detect Signal Level (Each Tone)
– 48
—
0
dBm
Twist (High Group/Low Group)
– 10
—
10
dB
± 1.5% ± 2 Hz
—
—
% fc
Transmit Level
Symbol
Low Group
Vfl
High Group
Vfh
High Group Pre–Emphasis
DTMF Distortion
PE
Condition
Attenuator = 0 dB
fosc = 3.579545
3 579545 MHz
VTxA1 – VTxA2
RL = 1.2 kΩ
TRANSMIT ATTENUATOR CHARACTERISTICS (VCC = 5 V ± 10%, TA = – 20 to 70°C)
Symbol
Parameter
Attenuator Range
ARNG
Attenuator Accuracy
AACC
Condition
DTMF RECEIVER CHARACTERISTICS (VCC = 5 V ± 10%, TA = – 20 to 70°C)
Symbol
Parameter
Input Impedance
Condition
RIDTMF
See Figure 3
Frequency Detect Band Width
—
—
± 3.5
CD1 = 0, CD0 = 1
—
20
—
CD1 = 1, CD0 = 0
—
30
—
CD1 = 1, CD0 = 1
—
40
—
CD1 = 0, CD0 = 1
—
20
—
CD1 = 1, CD0 = 0
—
30
—
CD1 = 1, CD0 = 1
—
20
—
Frequency Reject Band Width
DTMF Detect Timing
(See Figure 2)
OFF to ON
ON to OFF
MOTOROLA
TVDON
TVDOFF
ms
MC145740
3
SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, TA = – 20 to 70°C, See Figure 4)
Symbol
Number
Min
Typ
Max
Unit
Pulse Width (H)
Parameter
EN, SCK
twh
1
50
—
—
ns
Pulse Width (L)
EN, SCK
twl
2
50
—
—
ns
Clock Cycle
tc
3
100
—
—
ns
Input Rise Time
tr
4
—
—
2
µs
Input Fall Time
tf
5
—
—
2
µs
EN to SCK
trec
6, 18
50
—
—
ns
DATA to SCK
tsu
7
50
—
—
ns
R/W Low to DATA
9
100
—
—
R/W High to DATA
12
50
—
—
8
50
—
—
EN to R/W
10
50
—
—
DATA to R/W
14
50
—
—
R/W to DATA
15
50
—
—
13
—
—
50
17
—
—
50
Recovery Time
Setup Time
Hold Time
Read Data Delay Time
SCK to DATA
EN to DATA
SCK to DATA
MC145740
4
th
td
ns
ns
MOTOROLA
0
3.4 k 4 k
16 k
f (Hz)
256 k
TRANSMIT LEVEL (dBr)
0
– 25
– 15 dB/OCT.
– 55
Figure 1. Out–of–Band Energy
DTMF TONE CHANGED WITHOUT SILENT PERIOD
“A”
RxA
“B”
“C”
“D”
ton
(NOTE 1)
u 1 u 10 mS
TD
ton
toff
(NOTE 2)
DV
(NOTE 3)
D0 – D3
“A”
“B”
“C”
“D”
NOTES:
1. The high–to–low and low–to–high transition on the TD pin will appear immediately after the valid DTMF
tones are detected. The TD will also output a short H pulse when the device detects the DTMF tones
being changed without a silent period.
2. The high–to–low and low–to–high transition on the DV pin will appear after the programmed guard time
determined by two bits of serial data (CD1, CD0).
3. The device recognizes the DTMF tones changed without a silent period, and the four bits of data can
be read from the status register.
Figure 2. DTMF Detect Timing
NO DETECT
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
– 3.5%
DETECT MINIMUM
WIDTH
– 1.5% – 2 Hz
+ 1.5% + 2 Hz
LO
NO DETECT
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
+ 3.5%
Figure 3. DTMF Frequency Detect Band Width
MOTOROLA
MC145740
5
CONTROL REGISTER
1
(NOTE 1)
EN
(NOTE 6)
6
3
1
CLK
2
3
5
4
6
7
8
9
10
2
7
9
T2
T1
11
12
T0
13
14
(LSB CLOCK)
5
1
8
T3
DATA
7
4
A2
A3
A1
A0
CD0
CD1
SQ
M2
M1
M0
10
R/W
STATUS REGISTER
11
EN
(NOTE 6)
4
(NOTE 5)
1
CLK
2
17
3
0
1
2
1
5
(NOTE 3)
2
13
DATA
5
3
18
12
D0
1
D1
D2
(NOTE 2) 4
D3
D0
D1
D2
D1
D0
15
14
16
HIGH IMPEDANCE
(NOTE 4)
R/W
NOTES:
1. The data in front of the EN signal will be latched.
2. The latched data will be repeated until there is an EN pulse.
3. The detected data will be updated with the next EN pulse.
4. After the R/W pin becomes inactive, the data will be lost.
5. D1 corresponds to CLK1.
6. The EN and CLK signals need to be set at the logic low level when the R/W signal changes.
7. The CLK signal must be held low when the EN signal is high.
Figure 4. Serial Interface Timing
MC145740
6
MOTOROLA
PIN DESCRIPTIONS
TxA1
Non–Inverting Analog Output (Pin 1)
This pin is the line driver non–inverting output. A + 7 dBm
(typ) differential output voltage can be obtained by connecting a 1.2 kΩ load resistor between TxA1 and TxA2. Note that
the DSI input, if used, must be controlled for the output level
not to exceed the above signal level.
TxA2
Inverting Analog Output (Pin 2)
This pin is the driver inverting output. Refer to TxA1.
RxA
DTMF Receive Input (Pin 3)
This pin is the DTMF signal input (AGC input).
AGCout
AGC Output (Pin 4)
This pin is the AGC amplifier output. The signal received
from the RxA pin appears at this pin through the AGC amplifier so that any signal receivers can be connected on this pin
to decode the non–DTMF signals. The AGC amplifier gain is
software programmable as shown in Table 3.
Vref
Reference Analog Ground (Pin 5)
This pin provides the analog ground voltage, VCC/2, which
is internally regulated from V CC . This pin should be
decoupled to GND with 0.1 µF and 100 µF capacitors.
FTLC1, FTLC2
Band–Pass Filter Test (Pins 6, 7)
These pins are high impedance filter outputs. They may be
used for testing the DTMF receive high and low band–pass
filter characteristics, and are reserved for manufacturer’s use
only. In normal operation, each pin is decoupled to Vref with
0.1 µF capacitors.
X1
Crystal Oscillator Output (Pin 8)
A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin
with the other end connected to X2.
X2
Crystal Oscillator Input (Pin 9)
A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin
with the other end connected to X1. X2 may be driven
directly from an appropriate external clock source. In this
case, X1 should be held open.
GND
Ground (Pins 10, 18)
Ground pins are connected to the system ground.
VCC
Power Supply (Pins 11, 19)
The digital supply pins are connected to the positive power
supply (5 V).
DV
DTMF Data Valid (Pin 12)
This pin goes low when valid DTMF tones are detected.
The guard time of DTMF tone detection (ton) and release
MOTOROLA
(toff) is programmed by two bits of serial data (CD1, CD0) as
shown in Table 2. This feature improves the immunity to the
short noise and momentary dropouts. See Figure 2 for the
detailed timing diagram.
TD
Tone Detect (Pin 13)
This pin goes low immediately after valid DTMF tones are
detected, regardless of the guard time set by two bits of
serial data. This pin also outputs the short high pulse when
the device detects the change of DTMF tones without a silent
period. For a detailed description, see Figure 2.
R/W
Read/Write Data Switch (Pin 14)
This pin is used for controlling the input/output direction of
the DATA I/O pin.
DATA
Serial Data Input/Output (Pin 15)
When the R/W pin is at logic low, the DATA pin works as
the 14–bit control register input which determines the function mode, DTMF tones, transmit level (or receiver gain level), detect time, and transmit squelch. When the R/W pin is at
logic high, the DATA pin works as the 4–bit status register
output which provides the hexadecimal codes corresponding
to the detected digit.
EN
Enable Input (Pin 16)
When the R/W pin is held low, high level input to this pin
transfers the 14 bits of control register data to the mode
control logic, then the function mode is immediately
changed. When this pin is at logic low, the control register
and the mode control logic are isolated. Therefore, the
14 bits of data in the control register must not be changed
while EN is at logic high level.
When the R/W pin is held high, the rising edge of the EN
pin loads the DTMF data from the DTMF decoder into the
status register, and shifts out the first bit (LSB = D0) to the
DATA pin.
CLK
SPI Clock Input (Pin 17)
This pin is the SPI clock input for the 14–bit control register
and the 4–bit status register. At the rising edge of CLK, the
14 bits of data are captured into the control register when
R/W is at logic low, and the 4 bits of data are shifted out from
the status register when R/W is at logic high.
DSI
Driver Summing Input (Pin 20)
This pin is the inverting input of the line driver. An external
signal source may be connected to this pin through a series
resistor RDSI, transmitting the signal from the TxA1 and
TxA2. The differential gain GDSI = (VTxA1 – VTxA2)/VDSI
is determined by the following equation:
GDSI = – 2 RF/RDSI, RF – 20 kΩ
Note that the programmable transmit attenuator does not
affect this case.
The DSI pin should be held open when not in use.
MC145740
7
Single Tone Mode (M2 – M0 = 0, 1, 0)
SERIAL DATA INTERFACE
REGISTER MAP DESCRIPTION
The timing diagram of the 14–bit control register input and
the 4–bit status register output is shown in Figure 4. When
the R/W pin is at logic low (write is selected), the control register is enabled. The 14 bits of data are captured into the control register at the rising edge of SCK. The 14 bits of data in
the control register are transferred to the mode control logic
at logic high to the EN pin, and then the function mode is immediately changed.
When the R/W pin is at logic high (read is selected), the
status register is enabled to read out the decoded DTMF
data. At the rising edge of EN, the four bits of data in the
DTMF decoder are loaded into the status register, and the
first bit (D0) is presented on the DATA pin. The next three bits
are shifted out by following rising edges of CLK (see Figure
4).
The transmitter generates one of the eight frequencies of
DTMF tones. The receiver is disabled.
Power Down Mode (Mode 1: M2 – M0 = 0, 1, 1;
Mode 2: M2 – M0 = 1, 0, 0)
In Power Down Mode 1, all internal circuits except for the
oscillator are disabled, so that all output pins except for the
X1 are in high–impedance state. The device current is
decreased to 500 µA (max). In Power Down Mode 2, all internal circuits are disabled, so all output pins are in high impedance state. The device current is decreased to 1 µA (max).
Analog Loopback Mode (M2 – M0 = 1, 0, 1)
The transmitter output is internally connected to the
receiver input.
FUNCTION MODE (M2 – M0)
These three bits (M2 – M0) determine the function mode
shown in Table 1.
Table 1. Function Mode Truth Table
M2
M1
M0
Function Mode
0
0
0
DTMF Receive
0
0
1
DTMF Transmit
0
1
0
Single Tone Transmit
0
1
1
Power Down 1
1
0
0
Power Down 2
1
0
1
Analog Loopback
TRANSMIT SQUELCH (SQ)
When the SQ bit is 1, the DTMF and single tone transmission are disabled (squelch is selected). However, the transmit squelch does not affect the external signal input from
DSI.
DTMF TONE DETECT/REJECT TIME (CD1, CD0)
The CD1 and CD0 bits determine DTMF tones detect time
(ton) and release time (toff) of the DV pin, as shown in
Table 2. The timing diagram is shown in Figure 2.
Table 2. DTMF Detect Time Truth Table
DTMF Receive Mode (M2 – M0 = 0, 0, 0)
The DTMF receiver is enabled. The transmitter is disabled.
DTMF Transmit Mode (M2 – M0 = 0, 0, 1)
The DTMF tone generator is enabled. The receiver is disabled.
CD1
CD0
ton (ms)
toff (ms)
0
0
0
1
20
20
1
0
30
30
1
1
40
20
Reserved
CONTROL REGISTER (R/W = “L”)
FUNCTION MODE
: 3 BITS
M2
M1
M0
TRANSMIT SQUELCH
: 1 BIT
SQ
DTMF DETECT TIME
: 2 BITS
CD1
CD0
TRANSMIT ATTENUATOR/AGC GAIN
: 4 BITS
A3
A2
A1
A0
TRANSMIT FREQUENCY
: 4 BITS
T3
T2
T1
T0
: 4 BITS
D3
D2
D1
D0
STATUS REGISTER (R/W = “H”)
RECEIVED TONE FREQUENCY
MC145740
8
MOTOROLA
TRANSMIT ATTENUATOR/AGC GAIN (A3 – A0)
TRANSMIT TONE FREQUENCY (T3 – T0)
The A3 – A0 bits determine the analog transmit level of
DTMF tones. The transmit attenuator range is controlled
from 0 to 15 dB in 1 dB steps as shown in Table 3. However,
this attenuator does not affect the external signal source
from DSI. These four bits also determine the AGC amplifier
gain in DTMF receive mode. In normal operation, “automatic”
may be selected so that the receiver’s gain is automatically
adjusted, corresponding to the input signal level.
The T3 – T0 bits determine DTMF tone frequencies transmitted from TxA1 and TxA2 in DTMF transmit and analog
loopback mode, and determine the single tone frequency in
single tone mode. Tone frequency assignments for the
T3 – T0 bits are shown in Table 4.
RECEIVED TONE FREQUENCY (D3 – D0)
The D3 – D0 bits provide hexadecimal codes corresponding to detected DTMF tones. Tone frequency assignments
for the D3 – D0 bits are shown in Table 4.
Table 3. Transmit Attenuator/AGC Gain Set Truth Table
MOTOROLA
A3
A2
A1
A0
Tx Attenuation (dB)
Rx AGC Gain (dB)
0
0
0
0
0
– 5.0
0
0
0
1
1
– 2.5
0
0
1
0
2
0.0
0
0
1
1
3
2.5
0
1
0
0
4
5.0
0
1
0
1
5
7.5
0
1
1
0
6
10.0
0
1
1
1
7
12.5
1
0
0
0
8
15.0
1
0
0
1
9
17.5
1
0
1
0
10
20.0
1
0
1
1
11
Clamp
1
1
0
0
12
Automatic
1
1
0
1
13
—
1
1
1
0
14
—
1
1
1
1
15
—
MC145740
9
Table 4. Tone Frequency Truth Table
Tone Frequency (Hz)
DTMF Tx/Rx Mode Frequency
T3/D3
T2/D2
T1/D1
T0/D0
High Group
Low Group
Keyboard
Equivalent
Single
Si
l Tone
T
Mode
0
0
0
1
697
1209
1
697
0
0
1
0
697
1336
2
697
0
0
1
1
697
1477
3
697
0
1
0
0
770
1209
4
770
0
1
0
1
770
1336
5
770
0
1
1
0
770
1477
6
770
0
1
1
1
852
1209
7
852
1
0
0
0
852
1336
8
1336
1
0
0
1
852
1477
9
1477
1
0
1
0
941
1336
0
1336
1
0
1
1
941
1209
*
1209
1
1
0
0
941
1477
#
1477
1
1
0
1
697
1633
A
1633
1
1
1
0
770
1633
B
1633
1
1
1
1
852
1633
C
1633
0
0
0
0
941
1633
D
941
MC145740
10
MOTOROLA
APPLICATION CIRCUIT
600 : 600
TxA1
600 Ω
*
RING
TxA2
RxA
AGCout*
Vref
100 µF
0.1 µF
FC1
0.1 µF
FC2
0.1 µF
X1
3.579545 MHz
X2
GND
* Protection Network
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
Reference Analog Ground
DSI*
RDSI
VCC
100 µF
+5V
GND
CLK
0.1 µF
EN
DATA
R/W
TD
DV
I/O PORT
10 Ω
TIP
MCU
VCC
System Ground
* The external devices (i.e., modem) may be connected on these pins, using the built–in line interface circuit.
MOTOROLA
MC145740
11
PACKAGE DIMENSIONS
F SUFFIX
SOG (SMALL OUTLINE GULL–WING) PACKAGE
CASE 751J–02
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.12 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
20
11
1
10
–B–
G
S 10 PL
0.13 (0.005)
M
B
M
C
D 20 PL
0.13 (0.005)
M
T B
S
K
0.10 (0.004)
L
–T–
A
S
SEATING
PLANE
J
DIM
A
B
C
D
G
J
K
L
M
S
MILLIMETERS
MIN
MAX
12.55
12.80
5.10
5.40
–––
2.00
0.35
0.45
1.27 BSC
0.18
0.23
0.55
0.85
0.05
0.20
0_
7_
7.40
8.20
INCHES
MIN
MAX
0.494
0.504
0.201
0.213
–––
0.079
0.014
0.018
0.050 BSC
0.007
0.009
0.022
0.033
0.002
0.008
0_
7_
0.291
0.323
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
MFAX: [email protected] – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC145740
12
◊
*MC145740/D*
MC145740/D
MOTOROLA