ON MC100LVEL51 Differential clock d flip-flop Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MC100LVEL51 is a differential clock D flip-flop with reset. The
device is functionally equivalent to the EL51 device, but operates from a
low voltage supply. With propagation delays and output transition times
essentially equal to the EL51, the LVEL51 is ideally suited for those
applications which require the ultimate in AC performance at 3.3V VCC.
The reset input is an asynchronous, level triggered signal. Data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs of the LVEL51 allow the device to
be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under
open input conditions. When left open, the CLK input will be pulled down
to VEE and the CLK input will be biased at VCC/2.
8
1
•
•
•
•
•
475ps Propagation Delay
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
2.8GHz Toggle Frequency
Operates from –3.3V (or 3.3V) Supply
75kΩ Internal Input Pulldown Resistors
>2000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
R 1
8
VCC
7
Q
TRUTH TABLE
R
D
2
D
Flip-Flop
CLK
CLK
3
6
4
5
Q
4–1
R
CLK
Q
L
L
Z
L
H
L
Z
H
X
H
X
L
Z = LOW to HIGH Transition
VEE
8/96
 Motorola, Inc. 1996
D
REV 1
MC100LVEL51
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C
Symbol
Characteristic
Min
IEE
Power Supply Current
VEE
Power Supply Voltage
IIH
Input HIGH Current
IIL
Input LOW Current CLK
Other
–3.0
0°C
Typ
Max
30
35
–3.3
–3.8
Min
–3.0
Typ
Max
30
35
–3.3
–3.8
150
–600
0.5
25°C
Min
–3.0
Typ
Max
30
35
–3.3
–3.8
150
–600
0.5
85°C
Min
–3.0
Typ
Max
Unit
32
37
mA
–3.3
–3.8
V
150
µA
150
–600
0.5
µA
–600
0.5
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C
Symbol
Characteristic
Min
Typ
0°C
Max
2.7
Min
Typ
25°C
Max
2.9
Min
Typ
85°C
Max
2.9
Min
Typ
Max
2.9
Unit
fMAX
Maximum Toggle
Frequency
GHz
tPLH
tPHL
Propagation Delay
to Output
tS
Setup Time
150
0
150
0
150
0
150
0
ps
tH
Hold Time
200
100
200
100
200
100
200
100
ps
tRR
Reset Recovery
350
200
350
200
350
200
350
200
ps
tPW
Minimum Pulse
Width
VPP
VCMR
ps
CLK
R
CLK
Reset
330
340
510
540
330
340
510
540
340
350
520
550
370
390
550
590
400
500
400
500
400
500
400
500
ps
Minimum Input Swing1
150
150
150
150
mV
Common Mode Range2
VPP < 500mV
VPP ≥ 500mV
–2.0
–1.8
V
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
tr
Output Rise/Fall Times Q
120
320
120
320
120
320
120
320
ps
tf
(20% – 80%)
1. Minimum input swing for which AC parameters are guaranteed.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V – |VCMR(min)|.
MOTOROLA
4–2
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MC100LVEL51
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–05
ISSUE P
–A–
M
1
4
R
0.25 (0.010)
4X
–B–
X 45 _
B
M
5
P
8
NOTES:
1. DIMENSIONS A AND B ARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. DIMENSIONS ARE IN MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J
M_
C
F
G
–T–
K
SEATING
PLANE
8X
D
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.18
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
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◊
ECLinPS and ECLinPS Lite
DL140 — Rev 3
4–3
*MC100LVEL51/D*
MC100LVEL51/D
MOTOROLA
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