Cypress CY7C136-35JC 2k x 8 dual-port static ram Datasheet

CY7C132/CY7C136
CY7C142/CY7C146
2K x 8 Dual-Port Static RAM
Features
Functional Description
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
The CY7C132/CY7C136/CY7C142 and CY7C146 are
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER
dual-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C132/CY7C136 easily expands data bus
width to 16 or more bits using slave CY7C142/CY7C146
• BUSY output flag on CY7C132/CY7C136; BUSY input
on CY7C142/CY7C146
• INT flag for port-to-port communication (52-pin
PLCC/PQFP versions)
• Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and
52-pin TQFP (CY7C136/146)
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. On the PLCC
version, INT is an interrupt flag indicating that data has been
placed in a unique location (7FF for the left port and 7FE for
the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
• Pb-Free packages available
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
Pin Configuration
R/WL
CEL
R/WR
CER
OEL
OER
I/O7L
I/O
CONTROL
I/O0L
I/O7R
I/O
CONTROL
I/O0R
BUSYL[1]
A 10L
A 0L
DIP
Top View
[1]
BUSYR
MEMORY
ARRAY
ADDRESS
DECODER
CEL
OEL
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
R/WL
A 10R
ADDRESS
DECODER
A 0R
CER
OER
R/WR
INTL[2]
INTR
[2]
CEL
R/WL
BUSYL
A10L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
1
2
3
4
5
6
7
8
9
10
11
12 7C132
13 7C142
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
CER
R/WR
BUSYR
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
Notes:
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.
CY7C142/CY7C146 (Slave): BUSY is input.
2. Open drain outputs; pull-up resistor required.
Cypress Semiconductor Corporation
Document #: 38-06031 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 1, 2005
CY7C132/CY7C136
CY7C142/CY7C146
Pin Configurations
OER
A0R
A1R
A2R
A3R
A4R
A5R
I/O5R
I/O6R
A6R
A7R
A8R
A9R
NC
I/O7R
BUSYR
INTR
A10R
CER
R/WR
INTL
BUSYL
R/W
L
CEL
VCC
52 51 50 49 48 47 46 45 44 43 42 41 40
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O2R
I/O3R
I/O4R
1
2
3
4
5
6
7
8
9
10
11
12
13
OER
A0R
A1R
A2R
A3R
A4R
A5R
39
38
37
36
35
34
33
32
31
30
29
28
27
7C136
7C146
A6R
A7R
A8R
A9R
NC
I/O7R
I/O5R
I/O6R
I/O2R
I/O3R
I/O4R
NC
GND
I/O0R
I/O1R
I/O6L
I/O7L
1415 16 17 18 19 20 21 22 23 24 25 26
I/O4L
I/O5L
I/O0R
I/O1R
NC
GND
A0L
OEL
A10L
BUSYR
INTR
A10R
CER
R/WR
PQFP
Top View
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C136
40
7C146
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
I/O6L
I/O7L
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O4L
I/O5L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
BUSYL
R/W
L
CEL
VCC
A0L
OEL
A10L
INTL
PLCC
Top View
Selection Guide
7C132-25[3]
7C136-25
7C136-15[3] 7C142-25
7C146-15 7C146-25
7C132-30
7C136-30
7C142-30
7C146-30
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
Unit
55
ns
Maximum Access Time
15
25
30
35
45
Maximum Operating Current Com’l/Ind
190
170
170
120
120
110
mA
170
170
120
mA
mA
Maximum Operating Current Military
Maximum Standby Current
Com’l/Ind
75
Military
65
65
45
45
35
65
65
45
Shaded areas contain preliminary information.
Note:
3. 15 and 25-ns version available in PQFP and PLCC packages only.
Document #: 38-06031 Rev. *C
Page 2 of 18
CY7C132/CY7C136
CY7C142/CY7C146
DC Input Voltage ................................................. −3.5V to +7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
Range
Ambient Temperature
VCC
0°C to +70°C
5V ± 10%
Industrial
–40°C to +85–C
5V ± 10%
Military[4]
–55°C to +125°C
5V ± 10%
Commercial
DC Voltage Applied to Outputs
in High-Z State .....................................................−0.5V to +7.0V
Electrical Characteristics Over the Operating Range[5]
7C132-30[3]
7C136-25,30
7C136-15[3] 7C142-30
7C146-15 7C146-25,30
Parameter
Description
Output HIGH voltage VCC = Min., IOH = –4.0 mA
VOL
Output LOW voltage IOL = 4.0 mA
2.4
IOL = 16.0 mA[6]
VIH
Input HIGH voltage
VIL
Input LOW voltage
7C132-55
7C136-55
7C142-55
7C146-55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Test Conditions
VOH
7C132-35,45
7C136-35,45
7C142-35,45
7C146-35,45
2.4
2.4
2.4
V
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
2.2
2.2
0.8
2.2
0.8
2.2
0.8
V
V
0.8
V
IIX
Input load current
GND < VI < VCC
–5
+5
−5
+5
−5
+5
−5
+5
µA
IOZ
Output leakage
current
GND < VO < VCC, Output Disabled
–5
+5
−5
+5
−5
+5
−5
+5
µA
IOS
Output short circuit
current[7]
VCC = Max., VOUT = GND
–350
−350
−350
−350 mA
ICC
VCC Operating
Supply Current
CE = VIL, Outputs Open, f = Com’l
fMAX[8]
Mil
190
170
120
110 mA
170
120
ISB1
Standby current both CEL and CER > VIH,
ports, TTL Inputs
f = fMAX[8]
Com’l
75
65
45
35
65
45
ISB2
Standby Current
One Port,
TTL Inputs
CEL or CER > VIH,
Active Port Outputs Open,
f = fMAX[8]
Com’l
135
115
90
75
115
90
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CER > VCC – 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V, f = 0
Com’l
15
15
15
15
Standby Current
One Port,
CMOS Inputs
One Port CEL or CER > VCC – Com’l
0.2V, VIN > VCC – 0.2V or VIN < Mil
0.2V, Active Port Outputs Open,
f = fMAX[8]
ISB3
ISB4
Mil
Mil
15
15
Mil
125
105
85
70
105
85
mA
mA
mA
mA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
15
pF
10
pF
Shaded areas contain preliminary information.
Notes:
4. TA is the “instant on” case temperature.
5. See the last page of this specification for Group A subgroup testing information.
6. BUSY and INT pins only.
7. Duration of the short circuit should not exceed 30 seconds.
8. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V.
9. This parameter is guaranteed but not tested.
Document #: 38-06031 Rev. *C
Page 3 of 18
CY7C132/CY7C136
CY7C142/CY7C146
AC Test Loads and Waveforms
R1 893Ω
5V
OUTPUT
5V
R1 893Ω
5V
OUTPUT
R2
347Ω
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
347Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
THÉVENIN EQUIVALENT
250Ω
OUTPUT
1.4V
30 pF
BUSY Output Load
(CY7C132/CY7C136 Only)
(b)
ALL INPUT PULSES
3.0V
GND
281Ω
BUSY
OR
INT
10%
90%
10%
90%
< 5 ns
< 5 ns
Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [5, 10]
7C136-15[3]
7C146-15
Parameter
Description
Min.
Max.
7C132-25[3]
7C136-25
7C142-25
7C146-25
Min.
Max.
7C132-30
7C136-30
7C142-30
7C146-30
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
Valid[11]
tAA
Address to Data
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid[11]
tDOE
OE LOW to Data Valid[11]
tLZOE
OE LOW to Low Z[9, 12]
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low
tHZCE
CE HIGH to High Z[9, 12, 13]
tPU
CE LOW to Power-Up[9]
tPD
CE HIGH to
15
0
0
15
3
10
3
5
0
ns
30
ns
20
ns
ns
ns
15
ns
15
ns
5
15
0
15
30
3
15
10
ns
0
25
10
3
Power-Down[9]
30
25
15
Z[9, 12, 13]
Z[9, 12]
25
ns
0
25
ns
25
ns
Write Cycle[14]
tWC
Write Cycle Time
15
25
30
ns
tSCE
CE LOW to Write End
12
20
25
ns
tAW
Address Set-up to Write End
12
20
25
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
R/W Pulse Width
12
15
25
ns
tSD
Data Set-up to Write End
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
ns
Z [9]
tHZWE
R/W LOW to High
tLZWE
R/W HIGH to Low Z [9]
10
0
15
0
15
0
ns
ns
Shaded areas contain preliminary information.
Notes:
10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
IOL/IOH, and 30-pF load capacitance.
11. AC test conditions use VOH = 1.6V and VOL = 1.4V.
12. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
13. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
14. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-06031 Rev. *C
Page 4 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) (continued)[5, 10]
7C136-15[3]
7C146-15
Parameter
Description
Min.
Max.
7C132-25[3]
7C136-25
7C142-25
7C146-25
Min.
Max.
7C132-30
7C136-30
7C142-30
7C146-30
Min.
Max.
Unit
Busy/Interrupt Timing
tBLA
BUSY LOW from Address Match
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch[15]
15
20
20
ns
tBLC
BUSY LOW from CE LOW
15
20
20
ns
20
ns
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set Up for Priority
[15]
15
5
[16]
20
5
5
ns
tWB
R/W LOW after BUSY LOW
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
20
30
ns
tBDD
BUSY HIGH to Valid Data
tDDD
tWDD
Interrupt
15
25
30
ns
Write Data Valid to Read Data Valid
Note 17
Note 17
Note 17
ns
Write Pulse to Data Delay
Note 17
Note 17
Note 17
ns
Timing[18]
tWINS
R/W to INTERRUPT Set Time
15
25
25
ns
tEINS
CE to INTERRUPT Set Time
15
25
25
ns
tINS
Address to INTERRUPT Set Time
15
25
25
ns
tOINR
OE to INTERRUPT Reset Time[15]
15
25
25
ns
tEINR
Time[15]
15
25
25
ns
25
25
ns
tINR
CE to INTERRUPT Reset
Address to INTERRUPT Reset
Time[15]
15
Switching Characteristics Over the Operating Range (Speeds -35, -45, -55)
7C132-35
7C136-35
7C142-35
7C146-35
Parameter
Description
Min.
Max.
[5, 10]
7C132-45
7C136-45
7C142-45
7C146-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7C146-55
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid[11]
35
tOHA
Data Hold from Address Change
45
35
0
55
45
0
ns
55
ns
0
ns
tACE
CE LOW to Data
Valid[11]
35
45
55
ns
tDOE
OE LOW to Data Valid[11]
20
25
25
ns
25
ns
[9, 12]
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[9, 12, 13]
tLZCE
CE LOW to Low Z[9, 12]
CE HIGH to High Z
tPU
CE LOW to Power-Up[9]
CE HIGH to
Power-Down[9]
3
20
5
[9, 12, 13]
tHZCE
tPD
3
3
20
5
20
0
5
20
0
35
ns
ns
25
ns
0
35
ns
35
ns
Notes:
15. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
16. CY7C142/CY7C146 only.
17. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
18. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *C
Page 5 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) (continued)[5, 10]
7C132-35
7C136-35
7C142-35
7C146-35
Parameter
Description
Min.
Max.
7C132-45
7C136-45
7C142-45
7C146-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7C146-55
Min.
Max.
Unit
[14]
Write Cycle
tWC
Write Cycle Time
35
45
55
ns
tSCE
CE LOW to Write End
30
35
40
ns
tAW
Address Set-up to Write End
30
35
40
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
R/W Pulse Width
25
30
30
ns
tSD
Data Set-up to Write End
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
ns
Z [9]
tHZWE
R/W LOW to High
tLZWE
R/W HIGH to Low Z [9]
20
0
20
0
25
ns
0
ns
Busy/Interrupt Timing
tBLA
BUSY LOW from Address Match
20
25
30
ns
tBHA
BUSY HIGH from Address Mismatch[15]
20
25
30
ns
tBLC
BUSY LOW from CE LOW
20
25
30
ns
tBHC
BUSY HIGH from CE HIGH[15]
20
25
30
ns
tPS
Port Set Up for Priority
5
LOW[16]
5
tWB
R/W LOW after BUSY
tWH
R/W HIGH after BUSY HIGH
tBDD
BUSY HIGH to Valid Data
tDDD
Write Data Valid to Read Data Valid
Note 17
tWDD
Write Pulse to Data Delay
Note 17
5
ns
0
0
0
ns
30
35
35
ns
35
45
45
ns
Note 17
Note 17
ns
Note 17
Note 17
ns
[18]
Interrupt Timing
tWINS
R/W to INTERRUPT Set Time
25
35
45
ns
tEINS
CE to INTERRUPT Set Time
25
35
45
ns
tINS
Address to INTERRUPT Set Time
25
35
45
ns
tOINR
OE to INTERRUPT Reset Time[15]
25
35
45
ns
tEINR
[15]
25
35
45
ns
Time[15]
25
35
45
ns
tINR
CE to INTERRUPT Reset Time
Address to INTERRUPT Reset
Document #: 38-06031 Rev. *C
Page 6 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[19, 20]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (Either Port-CE/OE)[19, 21]
CE
tHZCE
tACE
OE
tLZOE
tHZOE
tDOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
tRC
ADDRESSR
ADDRESS MATCH
R/WR
tPWE
DINR
VALID
tPS
ADDRESS MATCH
ADDRESSL
tBHA
BUSYL
tBLA
tBDD
DOUTL
VALID
tWDD
tDDD
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
21. Address valid prior to or coincident with CE transition LOW.
Document #: 38-06031 Rev. *C
Page 7 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)[14, 22]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
OE
tHZOE
HIGH IMPEDANCE
DOUT
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[14, 23]
tWC
ADDRESS
tSCE
tHA
CE
tSA
tAW
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
tHZWE
tLZWE
HIGH IMPEDANCE
DOUT
Notes:
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Document #: 38-06031 Rev. *C
Page 8 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
tRC or tWC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSYR
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
Document #: 38-06031 Rev. *C
Page 9 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
CE
tPWE
R/W
tWB
tWH
BUSY
Interrupt Timing Diagrams[18]
Left Side Sets INTR:
tWC
ADDRESSL
WRITE 7FF
tHA
tINS
CEL
tEINS
R/WL
tSA
tWINS
INTR
Right Side Clears INTR:
tRC
ADDRESSR
READ 7FF
tHA
CER
tINR
tEINR
R/WR
OER
tOINR
INTR
Right Side Sets INTL:
tWC
ADDRESSR
WRITE 7FE
tINS
CER
tEINS
R/WR
INTL
Document #: 38-06031 Rev. *C
tHA
tSA
tWINS
Page 10 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Interrupt Timing Diagrams[18] (continued)
Right Side Clears INTL:
tRC
ADDRESSL
READ 7FE
tHA
CEL
tINR
tEINR
R/WL
OEL
tOINR
INTL
Typical DC and AC Characteristics
1.0
0.8
0.6
0.4
0.0
4.0
4.5
5.0
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
0.2
ISB3
0.2
1.0
5.5
ISB3
0.6
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.1
TA = 25°C
1.2
1.0
VCC = 5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
0.6
–55
6.0
25
30.0
2.5
25.0
20.0
2.0
15.0
1.5
0.5
4.0
SUPPLY VOLTAGE (V)
Document #: 38-06031 Rev. *C
40
20
0
0
5.0
0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
40
VCC = 5.0V
TA = 25°C
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
1.25
NORMALIZED ICC vs. CYCLE TIME
VCC = 5.0V
TA = 25°C
VIN = 0.5V
1.0
VCC = 4.5V
TA = 25°C
5.0
3.0
VCC = 5.0V
TA = 25°C
0.75
10.0
1.0
2.0
60
NORMALIZED ICC
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
1.0
80
125
DELTA tAA (ns)
NORMALIZED tPC
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
0
100
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.0
125
120
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.0
25
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
OUTPUT SOURCE CURRENT (mA)
ICC
ICC
OUTPUT SINK CURRENT (mA)
1.2
1.2
NORMALIZED ICC, ISB
NORMALIZED ICC, ISB
1.4
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0
200 400 600 800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 11 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Ordering Information
Speed
(ns)
30
35
45
55
15
25
30
35
45
55
30
35
Ordering Code
CY7C132-30PC
Package
Name
P25
Package Type
48-Lead (600-Mil) Molded DIP
Operating
Range
Commercial
CY7C132-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C132-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C132-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C132-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C132-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C132-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C136-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C136-15NC
N52
52-Pin Plastic Quad Flatpack
CY7C136-25JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C136-25JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C136-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C136-25NXC
N52
52-Pin Pb-Free Plastic Quad Flatpack
CY7C136-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C136-30NC
N52
52-Pin Plastic Quad Flatpack
Commercial
Commercial
CY7C136-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C136-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C136-35NC
N52
52-Pin Plastic Quad Flatpack
CY7C136-35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C136-35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C136-45JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C136-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C136-45JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C136-45LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C136-55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C136-55JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C136-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C136-55NXC
N52
52-Pin Pb-Free Plastic Quad Flatpack
CY7C136-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C136-55JXI
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C136-55NI
N52
52-Pin Plastic Quad Flatpack
CY7C136-55NXI
N52
52-Pin Pb-Free Plastic Quad Flatpack
CY7C136-55LMB
L69
52-Square Leadless Chip Carrier
Military
Industrial
CY7C142-30PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C142-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C142-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C142-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C142-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Document #: 38-06031 Rev. *C
Page 12 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Ordering Information (continued)
Speed
(ns)
45
55
15
25
30
35
45
55
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C142-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C142-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C142-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C142-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C142-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C142-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C146-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-15NC
N52
52-Pin Plastic Quad Flatpack
CY7C146-25JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C146-25JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
Commercial
CY7C146-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C146-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C146-30NC
N52
52-Pin Plastic Quad Flatpack
CY7C146-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-35NC
N52
52-Pin Plastic Quad Flatpack
CY7C146-35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C146-45JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C146-45JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-45LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C146-55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-55JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C146-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C146-55JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-55LMB
L69
52-Square Leadless Chip Carrier
Military
Document #: 38-06031 Rev. *C
Commercial
Page 13 of 18
CY7C132/CY7C136
CY7C142/CY7C146
MILITARY SPECIFICATIONS
Group A Subgroup Testing—DC Characteristics
Parameter
VOH
VOL
VIH
VIL Max.
IIX
IOZ
ICC
ISB1
ISB2
ISB3
ISB4
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Switching Characteristics
Parameter
Read Cycle
tRC
tAA
tACE
tDOE
Write Cycle
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
Busy/Interrupt Timing
tBLA
tBHA
tBLC
tBHC
tPS
tWINS
tEINS
tINS
tOINR
tEINR
tINR
BUSY TIMING
tWB[24]
tWH
tBDD
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Note:
24. CY7C142/CY7C146 only.
Document #: 38-06031 Rev. *C
Page 14 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
MIL-STD-1835 D-14 Config. C
51-80044-**
52-Lead Plastic Leaded Chip Carrier J69
52-Lead Pb-Free Plastic Leaded Chip Carrier J69
51-85004-*A
Document #: 38-06031 Rev. *C
Page 15 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams (continued)
52-Square Leadless Chip Carrier L69
51-80054-**
52-Lead Plastic Quad Flatpack N52
52-Lead Pb-Free Plastic Quad Flatpack N52
51-85042-**
Document #: 38-06031 Rev. *C
Page 16 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
51-85020-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06031 Rev. *C
Page 17 of 18
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C132/CY7C136
CY7C142/CY7C146
Document History Page
Document Title: CY7C132/CY7C136/CY7C142/CY7C146 2K x 8 Dual Port Static RAM
Document Number: 38-06031
REV.
ECN NO.
Orig. of
Issue Date Change
Description of Change
**
110171
10/21/01
SZV
Change from Spec number: 38-06031
*A
128959
09/03/03
JFU
Added CY7C136-55NI to Order Information
*B
236748
See ECN
YDT
Removed cross information from features section
*C
393184
See ECN
YIM
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC,
CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC
Document #: 38-06031 Rev. *C
Page 18 of 18
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