HD74HC165 Parallel-load 8-bit Shift Register REJ03D0581-0300 Rev.3.00 Jan 31, 2006 Description This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock. Features • • • • • • High Speed Operation: tpd (Clock to QH) = 21 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC165P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74HC165FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Shift/Load Clock Inhibit Clock Serial Parallel Internal outputs A ······ H QA L X X X a ······h a H L L X X QA0 H X H H L L X L H L H H X X X QA0 QAo to QHo = Outputs remain unchanged. QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input. H: High level L: Low level X: Irrelevant Rev.3.00, Jan 31, 2006 page 1 of 7 QB b QB0 QAn QAn QB0 Output QH h QH0 QGn QGn QH0 HD74HC165 Pin Arrangement Shift/ Load Clock 2 Parallel Inputs 16 VCC 1 Clock 15 Inhibit CK E 3 E D 14 D F 4 F C 13 C G 5 G B 12 B H 6 H A 11 A QH 7 QH Parallel Inputs 10 Serial-In QH 9 QH GND 8 (Top view) Timing Diagram Clock Clock Inhibit Serial Input Shift/Load Data A B H L C D H L E F H L G H H H Output QH Output QH Inhibit Load Rev.3.00, Jan 31, 2006 page 2 of 7 H H L H L H L H L L H L H L H L Serial Shift HD74HC165 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Symbol VCC VIN, VOUT Ta Input rise / fall time*1 Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 tr, tf Unit V V °C ns 0 to 400 Note: Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Iin Quiescent supply current ICC Min 2.0 1.5 4.5 6.0 Ta = 25°C Typ Max Ta = –40 to+85°C Unit Min Max — — 1.5 — 3.15 — — 3.15 — 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — 6.0 5.68 — — 5.63 — 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 6.0 6.0 6.0 — — — — — — 0.26 ±0.1 4.0 — — — 0.33 ±1.0 40 Rev.3.00, Jan 31, 2006 page 3 of 7 Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC165 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Maximum clock frequency Propagation delay time Setup time Removal time Hold time Pulse width Output rise/fall time Input capacitance Symbol VCC (V) fmax tPLH, tPHL tsu trem th tw tTLH, tTHL Cin Ta = 25°C Ta = –40 to +85°C Unit Min Typ Max Min Max 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — — — — — — — — — — — — 100 20 17 100 20 17 100 20 17 100 20 17 5 5 5 5 5 5 5 5 5 80 16 14 — — — — 21 — — 23 — — 21 — — –3 — — 3 — — — — — 6 — — –3 — — 3 — — — — — 6 — 5 27 32 150 30 26 160 32 27 150 30 26 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 125 25 21 125 25 21 125 25 21 125 25 21 5 5 5 5 5 5 5 5 5 100 20 17 4 21 25 190 38 33 200 40 34 190 38 33 — — — — — — — — — — — — — — — — — — — — — — — — MHz 2.0 4.5 6.0 — — — — — — 5 — 5 75 15 13 10 — — — — 95 19 16 10 ns Rev.3.00, Jan 31, 2006 page 4 of 7 Test Conditions ns Clock to QH or QH ns Shift/Load to QH or QH ns H to QH or QH ns Parallel data inputs to Shift/Load ns Serial input to Clock ns Shift/load to Clock ns Clock to Clock inhibit or Clock inhibit to Clock ns Shift/Load to parallel data input ns Clock to Serial input ns Clock to Shift/Load ns Clock, Shift/Load pF HD74HC165 Test Circuit Measurement point CL* Note: CL includes the probe and fig capacitance. Waveforms 6ns V 90% 50% Shift / Load 10% GND t rem 6ns 6ns 90% Serial Input 50% 10% th 90% VCC 90% 50% 50% t su Clock CC 10% th t su 50% 10% 10% Notes 1. 6ns The eight data inputs and the clock-inhibit input are low. Results are monitored at output QH at tn+7. 2. Input pulse : PRR ≤ 1MHz, duty cycle 50% Rev.3.00, Jan 31, 2006 page 5 of 7 GND VCC 90% 50% 6ns 50% GND HD74HC165 V CC (See notes 3) Clock Inhibit (Clock) 50% GND t rem V CC Clock (Clock Inhibit) 50% 50% 50% GND t su t w (clock) V CC F, H (See notes 1 and 2) 50% 50% 50% t su GND th t w (load) 90% 50% 10% 6ns t PHL V CC 50% 50% 50% 10% GND t PLH t PHL t PHL t PLH t PLH VOH 90% 50% 10% t THL t PLH 90% QH t w (load) 6ns 90% QH th 90% 50% Shift / Load 50% 50% 50% 10% t TLH t PHL VOL t PLH t PLH t PHL t PHL VOH 90% 50% 10% 50% 50% 50% 50% 10% VOL t TLH t THL Notes 1. The remaining six data inputs and the serial input are low. 2. Prior to test, high-level data is loaded into H input. 3. Disable while clock is high. 4. Input pulse : PRR ≤ 1MHz, duty cycle 50% Rev.3.00, Jan 31, 2006 page 6 of 7 HD74HC165 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jan 31, 2006 page 7 of 7 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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