Revised May 2005 MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description Features The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. ■ Typical propagation delay: 18 ns ■ Wide operating voltage range: 2V–6V ■ Low input current: 1 PA maximum ■ Low quiescent current: 80 PA maximum ■ Compatible with bus-oriented systems ■ Output drive capability: 15 LS-TTL loads These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Ordering Code: Order Number Package Number MM74HC574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC574SJ MM74HC574MTC MM74HC574N MTC20 N20A Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Output Clock Data Output H Control L n H L n L L L L X Q0 H X X Z H HIGH Level L LOW Level X Don't Care n Transition from LOW-to-HIGH Z High Impedance State Q0 The level of the output before steady state input conditions were established Top View © 2005 Fairchild Semiconductor Corporation DS005213 www.fairchildsemi.com MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop September 1983 MM74HC574 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC Min Max Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V 40 85 qC (VIN,VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Symbol VIH VIL VOH Parameter IOZ ICC 'ICC ns 500 ns VCC 6.0V 400 ns Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. VCC TA 25qC Typ TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 Voltage 4.5V 3.15 3.15 3.15 6.0V 4.2 4.2 4.2 Maximum LOW Level Input 2.0V 0.5 0.5 0.5 Voltage 4.5V 1.35 1.35 1.35 6.0V 1.8 1.8 1.8 Minimum HIGH Level Output VIN Voltage |IOUT | d 20 PA Units V V VIH or VIL 2.0V 2.0 1.9 1.9 1.9 4.5V 4.5 4.4 4.4 4.4 6.0V 6.0 5.9 5.9 5.9 |IOUT | d 6.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT | d 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V VIH or VIL Maximum LOW Level Output VIN Voltage |IOUT | d 20 PA V VIH or VIL 2.0V 0 0.1 0.1 0.1 4.5V 0 0.1 0.1 0.1 6.0V 0 0.1 0.1 0.1 |IOUT | d 6.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT | d 7.8 mA 6.0V 0.2 0.26 0.33 0.4 Maximum Input Current VIN 6.0V r0.1 r1.0 r1.0 PA 6.0V r0.5 r5.0 r10 PA 8.0 80 160 PA 1.5 1.8 2.0 VIN IIN 1000 4.5V (Note 4) Conditions VIN VOL 2.0V VCC Note 2: Unless otherwise specified all voltages are referenced to ground. 260qC DC Electrical Characteristics VCC Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units VIH or VIL VCC or GND Maximum 3-STATE VOUT Output Leakage Current OC VIH Maximum Quiescent Supply VIN VCC or GND Current IOUT 0 PA 6.0V Quiescent Supply Current VCC 5.5V OE per Input Pin VIN V V VCC or GND 1.0 2.4V CLK 0.6 0.8 1.0 1.1 or 0.4V (Note 4) DATA 0.4 0.5 0.6 0.7 mA Note 4: For a power supply of 5V r10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 VCC 25qC, tr 5V, TA tf 6 ns Symbol Parameter Conditions Guaranteed Typ Limit Units fMAX Maximum Operating Frequency 60 33 MHz tPHL, tPLH Maximum Propagation Delay, Clock to Q CL 45 pF 17 27 ns tPZH, tPZL Maximum Output Enable Time RL 1 k: 19 28 ns CL 45 pF RL 1 k: 14 25 ns CL 5 pF ns tPHZ, tPLZ Maximum Output Disable Time tS Minimum Setup Time, Data to Clock 10 12 tH Minimum Hold Time, Clock to Data 3 5 ns tW Minimum Pulse Clock Width 8 15 ns AC Electrical Characteristics VCC 2.0 6.0V, CL Symbol fMAX tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tS tH tTHL, tTLH 50 pF, tr tf 6 ns (unless otherwise specified) Parameter Maximum Operating Frequency Conditions CL 50 pF tr,tf CPD CIN TA 25qC Typ TA 40 to 85qC TA 55 to 125qC Guaranteed Limits 2.0V 33 28 23 4.5V 30 24 20 6.0V 35 28 23 Maximum Propagation CL 50 pF 2.0V 18 30 38 45 Delay, Clock to Q CL 150 pF 2.0V 51 155 194 233 CL 50 pF 4.5V 13 23 29 35 CL 150 pF 4.5V 19 31 47 47 CL 50 pF 6.0V 12 20 25 30 CL 150 pF 6.0V 18 27 34 41 Maximum Output Enable RL 1 k: Time CL 50 pF 2.0V 22 30 38 45 CL 150 pF 2.0V 59 180 225 270 CL 50 pF 4.5V 14 28 35 42 CL 150 pF 4.5V 20 36 45 54 CL 50 pF 6.0V 12 24 30 36 CL 150 pF 6.0V 18 31 39 47 RL 1 k: 2.0V 15 30 38 45 CL 50 pF 4.5V 12 25 31 38 6.0V 10 21 27 32 Minimum Setup Time 2.0V 6 12 15 18 Data to Clock 4.5V 20 25 30 6.0V 17 21 25 Maximum Output Disable Time 1 Minimum Hold Time 2.0V 5 6 8 Clock to Data 4.5V 0 0 0 6.0V 0 0 0 18 Maximum Output Rise CL 50 pF and Fall Time tW VCC Minimum Clock Pulse Width 2.0V 6 12 15 4.5V 7 12 15 18 6.0V 6 10 13 15 2.0V 30 15 20 24 4.5V 9 16 20 24 6.0V 8 14 18 20 1000 Maximum Clock Input Rise 2.0V 1000 1000 and Fall Time 4.5V 500 500 500 6.0V 400 400 400 Power Dissipation Capacitance OC VCC 5 (Note 5) (per latch) OC GND 58 Maximum Input Capacitance 5 3 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns pF 10 10 10 pF www.fairchildsemi.com MM74HC574 AC Electrical Characteristics MM74HC574 AC Electrical Characteristics Symbol COUT Parameter (Continued) Conditions VCC Maximum Output TA 25qC Typ 15 TA 40 to 85qC TA 55 to 125qC 20 20 20 Capacitance Note 5: CPD determines the no load dynamic power consumption, PD IS CPD V CC f ICC. www.fairchildsemi.com CPD VCC2 f ICC VCC, and the no load dynamic current consumption, 4 Units Guaranteed Limits pF MM74HC574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8