Fujitsu MB8998X 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
Revision 3.0
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89980 Series
MB89983/P985/PV980
■ DESCRIPTION
The MB89980 series is a line of the general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers contain a variety of peripheral functions such as an LCD controller/driver,
an A/D converter, timers, remote control transmission output, buzzer output, PWM timers, and external interrupts.
■ FEATURES
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F2MC-8L family CPU core
Dual-clock control system
Maximum memory size: 8-Kbyte ROM, 256-byte RAM (max.)
Minimum execution time: 0.95 µs/4.2 MHz
I/O ports: max. 47 channels (max. 13 high-current type)
21-bit time-base counter
8/16-bit timer/counter: 8bit x 2 channels or 16-bit x 1 channels
External interrupts (wake-up function): Four channels with edge selection plus eight level-interrupt channels
8-bit A/D converter: 4 channels
8-bit PWM timers: 2 channels
Watch prescaler (15 bits)
LCD controller/driver: 14 segments × 4 commons (max. 56 pixels)
LCD driving reference voltage generator
Remote control transmission output
Buzzer output
Power-on reset function (option)
Low-power consumption modes (stop, sleep, and watch mode)
CMOS technology
■ PACKAGE
64-pin Ceramic MQFP
(MQP-64C-P01)
(MQP-64C-P01)
64-pin Plastic LQFP
(FPT-64P-M03)
(FPT-64P-M03)
64-pin Plastic QFP
(FPT-64P-M09)
(FPT-64P-M09)
MB89980 Series
■ PRODUCT LINEUP
Part number
MB89983
MB89P985
MB89PV980
Mass production products
(mask ROM products)
One-time PROM product (OTP)
Piggyback/evaluation
product (for development)
ROM size
8 K x 8 bits
(internal mask ROM)
16K x 8 bits
(Internal PROM)
32K x 8 bits
(External ROM)
RAM size
256 × 8 bits
Parameter
Classification
512 x 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8,16 bits
0.95 µs/4.2 MHz
9 µs/4.2 MHz
Ports
General-purpose I/O ports (N-ch open-drain): 8 (4 ports also serve as peripherals,
3 ports are heavy-current drive type.)
Output-only ports (N-ch open-drain):
20 (4 ports also serve as A/D, 14 ports
serve as segment pins and 2 ports serve
as common pins, 10 ports are heavycurrent drive type .)
General-purpose I/O ports (CMOS):
16 (12 ports also serve as an external
interrupt, )
Input-only ports (CMOS)
2 (serve with sub-clock pins)
Output-only ports (CMOS)
1 (serves as peripherials
Total:
47 (max.)
Timer/counter
8-bit timer operation (toggled output capable, operating clock cycle 1.9 µs to 486 µs)
16-bit timer operation (toggled output capable, operating clock cycle 1.9 µs to 486 µs)
LCD controller/driver
Common output:
Segment output:
Bias power supply pins:
LCD display RAM size:
Dividing resistor for LCD driving:
A/D converter
8-bit resolution × 4 channels
A/D conversion mode (conversion time 43 µs/4.2 MHz (44 instruction cycles))
Sense mode (conversion time 11.9 µs/4.2 MHz)
Continuous activation by an internal timer capable
Reference voltage input
PWM timer 1,
PWM timer 2
8 bits × 2 channels
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.95 µs to 124
ms)
8-bit resolution PWM operation (conversion cycle: 243 µs to 32 s)
4 (max.)
14 (max.) *2
4
14 × 4 bits
Built-in (an external resistor
selectability)
(Continued)
2
MB89980 Series
(Continued)
Part number
MB89983
Parameter
MB89P985
External interrupt 1
(wake-up function)
4 independent channels (edge selectability)
Rising edge/falling edge selectability
Used also for wake-up from stop/sleep mode.
(Edge detection is also permitted in stop mode.)
External interrupt 2
“L” level interrupts × 8 channels
Buzzer output
1 (7 frequencies are selectable by the software.)
Remote control
transmission
output
1 (Pulse width and cycle are software selectable.)
Standby modes
MB89PV980
Subclock mode, sleep mode, stop mode, and watch mode
Process
CMOS
Operating voltage*1
2.2 V to 6.0 V
2.7 V to 6.0 V
*1: Varies with conditions such as the operating frequency. (The operating voltage of the A/D converter is assured
separately. See section “■ Electrical Characteristics.”)
*2: See section “■ Mask Options.”
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89P985
MB89PV980
FPT-64P-M09
×
FPT-64P-M03
×
MQP-64C-P01
: Available
MB89983
×
×
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
3
MB89980 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV980, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in the sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-up resistor is not selectable for P40 to P47 and P60 to P65 if they are used as LCD pins.
• A pull-up resistor is not selectable for P50 to P53 if they are used as analog input.
4. Pull-up resistor
Pull-up resisitors of MB89P985 and MB89PV980 are selected by pull-up control registor (Port 0, 1, 5), but there
are no pull-up resistor for Port 2, 4 and 6 in MB89P985 and MB89PV980.
ALL pull-up resistor of MB89983 are selected by mask option (Port 0, 1, 2, 4, 5, 6)
5. Segment/Common port
The Segment/Port , Common/Port output in MB89P985 and MB89PV980 are selected by control register, LCR2.
The Segment/Port , Common/Port output in MB89983 are selected by mask option.
4
MB89980 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P47/SEG7*1 *4
P46/SEG6*1 *4
P45/SEG5*1 *4
P44/SEG4*1 *4
P43/SEG3*1 *5
P42/SEG2*1 *5
P41/SEG1*1 *5
P40/SEG0*1 *5
Vcc
P71/COM3*3
P70/COM2*3
COM1
COM0
V3
V2
Vss
■ PIN ASSIGNMENT
TOP VIEW
QFP-64
(FPT-64P-M09)
(FPT-64P-M03)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V1
V0
P27/PWM2*1
P26*1
P25
P24/RCO
P23
P22/TO
P21*1
P20/EC
P17
P16
P15
P14
P13/INT13
P12/INT12
P31/X0A*2
P32/X1A*2
RST
MOD0
MOD1
X0
X1
Vss
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
P60/SEG8*1 *3
P61/SEG9*1 *3
P62/SEG10*6
P63/SEG11*6
P64/SEG12*6
P65/SEG13*6
P50/AN0
P51/AN1
P52/AN2
P53/AN3
AVcc
AVR
AVss
P00/INT20
P01/INT21
P30/PWM1/BZ
*1: Heavy-current drive type
*2: When the dual clock system is selected
*3, *4, *5, *6: Selected using mask option in MB89983, but selected by software in MB89P985 and MB89PV980.
5
MB89980 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
P46/SEG6*1*4
P45/SEG5*1*4
P44/SEG4*1*4
P43/SEG3*1*5
P42/SEG2*1*5
P41/SEG1*1*5
P40/SEG0*1*5
VCC
P71/COM3*3
P70/COM2*3
COM1
COM0
V3
(Top view)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
84
83
82
81
80
79
78
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
77
76
75
74
73
72
71
70
69
94
95
96
65
66
67
68
85
86
87
88
89
90
91
92
93
V2
VSS
V1
V0
P27/PWM2*1
P26*1
P25
P24/RCO
P23
P22/TO
P21*1
P20/EC
P17
P16
P15
P14
P13/INT13
P12/INT12
P11/INT11
RST
MOD0
MOD1
X0
X1
VSS
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
20
21
22
23
24
25
26
27
28
29
30
31
32
P47/SEG7*1*4
P60/SEG8*1*3
P61/SEG9*1*3
P62/SEG10*6
P63/SEG11*6
P64/SEG12*6
P65/SEG13*6
P50/AN0
P51/AN1
P52/AN2
P53/AN3
AVCC
AVR
AVSS
P00/INT20
P01/INT21
P30/PWM1/BZ
P31/X0A*2
P32/X1A*2
(MQP-64C-P01)
*1: Heavy-current drive type
*2: When the dual clock system is selected
*3, *4,*5, *6: Selected using mask option in MB89983, but selected by software in MB89P985 and MB89PV980.
•
Pin assignment on package top (MB89PV980 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
65
N.C.
73
A2
81
N.C.
89
OE
66
VPP
74
A1
82
O4
90
N.C.
67
A12
75
A0
83
O5
91
A11
68
A7
76
N.C.
84
O6
92
A9
69
A6
77
O1
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
71
A4
79
O3
87
CE
95
A14
72
A3
80
VSS
88
A10
96
VCC
N.C.: Internally connected. Do not use.
6
MB89980 Series
■ PIN DESCRIPTION
Pin no.
LQFP*1
MQFP*3
QFP*2
22
23
I/O circuit type
Pin name
MB89983
24
X1
20
21
MOD0
19
22
20
A
C
A hysteresis input type
Memory access mode setting pins
Connect directly to VSS.
D
Reset I/O pin
This pin is an N-ch open-drain output type with a pullup resistor, and a hysteresis input type. “L” is output
from this pin by an internal reset request (optional).
The internal circuit is initialized by the input of “L”.
MOD1
RST
Function
Crystal or other resonator connector pins for the main
clock
The external clock can be connected to X0. When this
is done, be sure to leave X1 open.
CR oscillation selectability in model with a mask ROM
only.
X0
23
21
MB89P985
MB89PV980
14 to 15 15 to 16
P00/INT20 to
P01/INT21
E
F
General-purpose I/O ports
Also serve as an external interrupt 2 input (wake-up
function). External interrupt 2 input is hysteresis input.
25 to 30 26 to 31
P02/INT22 to
P07/INT27
E
F
General-purpose I/O ports
Also serve as an external interrupt 2 input (wake-up
function). External interrupt 2 input is hysteresis input.
31 to 34 32 to 35
P10/INT10 to
P13/INT13
E
F
General-purpose I/O ports
Also serve as input for external interrupt 1 input
(wake-up function). External interrupt 1 input is hysteresis input.
35 to 38 36 to 39
P14 to P17
G
H
General-purpose I/O ports
39
40
P20/EC
J
K
N-ch open-drain general-purpose I/O port
Also serve as the external clock input for the 8/16-bit
timer/counter.
The peripheral is a hysteresis input.
40
41
P21
L
M
N-ch open-drain general-purpose I/O port
41
42
P22/TO
L
M
N-ch open-drain general-purpose I/O port
Also serves as an 8/16-bit timer/counter output.
42
43
P23
L
M
N-ch open-drain general-purpose I/O port
43
44
P24/RCO
L
M
N-ch open-drain general-purpose I/O port
Also serves as Remote control output.
P25 to P26
L
M
N-ch open-drain general-purpose I/O port
P27/PWM2
L
M
N-ch open-drain general-purpose I/O port
Also serves as the square wave or PWM wave output
for the 8-bit PWM timer 2.
44 to 45 45 to 46
46
47
(Continued)
*1: FPT-64P-M03
*2: FPT-64P-M09
*3: MQP-64C-P01
7
MB89980 Series
(Continued)
Pin no.
LQFP*1
QFP*2
MQFP*3
16
17
17
18
I/O circuit type
Pin name
MB89983
MB89P985
MB89PV980
Function
P30/PWM1/
BZ
I
General-purpose CMOS Output port
Also serves as the square wave or PWM wave
output for the 8-bit PWM timer 1, or buzzer output..
P31
S
General-purpose CMOS Input port (Hysteresis
input type)
X0A
B
Crystal or other resonator connector pins for the
subclock
(Subclock: 32.768 kHz)
The external clock can be connected to X0A.
When this is done, Be sure to leave X1A open.
P32
S
General-purpose CMOS Input port (Hysteresis
input type)
18
19
X1A
B
7 to 10
8 to 11
P50/AN0 to
P53/AN3
P
Q
57 to 64
58 to 64
and 1
P40/SEG0 to
P47/SEG7
N/O
T/O
1 to 2
2 to 3
P60/SEG8
to
P61/SEG9
N/O
T/O
3 to 6
4 to 7
P62/SEG10
to
P65/SEG13
N/O
T/O
54, 55
55, 56
P70/COM2,
P71/COM3
N/O
T/O
52, 53
53, 54
COM0,
COM1
O
Crystal or other resonator connector pins for the
subclock
(Subclock: 32.768 kHz)
The external clock can be connected to X0A.
When this is done, Be sure to leave X1A open.
N-ch open-drain general-purpose output ports
Also serve as the analog input for the A/D
converter.
N-ch open-drain general-purpose output ports
(High current type)
Also serve as an LCD controller/driver segment
output.
N-ch open-drain general-purpose output ports
(High-current type)
Also serve as an LCD controller/driver segment
output.
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver segment
output.
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver common
output.
LCD controller/driver common output
(Continued)
*1: FPT-64P-M03
*2: FPT-64P-M09
*3: MQP-64C-P01
8
MB89980 Series
(Continued)
Pin no.
I/O circuit type
Pin name
Function
MB89983
MB89P985
MB89PV980
V0 to V3
—
—
LCD driving power supply pins.
57
Vcc
—
—
Power supply pin
24, 49
25, 50
Vss
—
—
Power supply (GND) pin
11
12
AVcc
—
—
A/D converter power supply pin
12
13
AVR
—
—
A/D converter reference voltage input pin
13
14
AVss
—
—
A/D converter power supply pin
Use this pin at the same voltage as VSS.
1
LQFP*
QFP2*2
MQFP*3
47, 48,
50, 51
48, 49
51, 52
56
*1: FPT-64P-M03
*2: FPT-64P-M09
*3: MQP-64C-P01
9
MB89980 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Main clock (main clock crystal
oscillator)
• At an oscillation feedback
resistor of approximately 1
MΩ/5.0 V
• CR oscillation is selectable for
MB89983 only
X1
N-ch P-ch
A
P-ch
X0
N-ch
X1A
N-ch P-ch
B
P-ch
X0A
N-ch
N-ch
Subclock (subclock crystal
oscillator)
• At an oscillation feedback
resistor of approximately 4.5
MΩ/5.0 V
• Hysteresis input
• At a pull-down resistor (P-ch)
of approximately 50 kΩ/5.0 V
C
R
• At an output pull-up resistor
(P-ch) of approximately 50
kΩ/5.0 V
• Hysteresis input
P-ch
D
N-ch
R
P-ch
P-ch
E
N-ch
Port
Peripheral
R
P-ch
Pull-up control register
P-ch
F
N-ch
Port
Peripheral
• CMOS output
• CMOS input
• The peripheral is a hysteresis
input type.
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resistor is selected by
mask option.
• CMOS output
• CMOS input
• The peripheral is a hysteresis
input type.
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resisitor is selected by
pull-up control register
(Continued)
10
MB89980 Series
(Continued)
Type
Circuit
R
Remarks
P-ch
• CMOS output
• CMOS input
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resistor is selected by
mask option.
P-ch
G
N-ch
Port
R
P-ch
Pull-up control register
P-ch
H
N-ch
• CMOS output
• CMOS input
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resisitor is selected
by pull-up control register
Port
P-ch
I
• CMOS output
N-ch
R
P-ch
J
N-ch
Port
• N-ch open-drain output
• CMOS input
• The peripheral is a hysteresis
input type.
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resistor is selected by
mask option.
Peripheral
N-ch
K
Port
• N-ch open-drain output
• CMOS input
• The peripheral is a hysteresis
input type.
Peripheral
R
P-ch
L
N-ch
Port
• N-ch open-drain output
• CMOS input
• P21, P26, and P27 are a
heavy-current drive type.
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resistor is selected by
mask option.
(Continued)
11
MB89980 Series
(Continued)
Type
Circuit
M
Remarks
N-ch
Port
R
P-ch
• N-ch open-drain output
• CMOS input
• P21, P26, and P27 are a
heavy-current drive type.
• N-ch open-drain output
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resistor is selected by
mask option.
N
N-ch
P-ch
N-ch
• LCD controller/driver
common/segment output
O
P-ch
N-ch
R
P-ch
P
• N-ch open-drain output
• Analog input (A/D converter)
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resistor is selected by
mask option.
P-ch
N-ch
Analog input
R
Q
P-ch
Pull-up control register
P-ch
N-ch
• N-ch open-drain output
• Analog input (A/D converter)
• Pull-up resistor is
approximately 50 kΩ/5.0 V
• Pull-up resisitor is selected
by pull-up control register
Analog input
S
• Hysteresis input
T
• N-ch open-drain output
N-ch
12
MB89980 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “ 1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC to VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AV CC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D Converters
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
7. Treatment of two Vss pins
Two Vss pins should be connected together externally.
8. Treatment of input port pins in standby mode
To avoid current leakage, it is recommended to remain a known logic level of input port pins during the standby
mode.
13
MB89980 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P985
The MB89P985 is an OTPROM version of the MB89980 series.
1. Features
• 16-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address in normal mode
0000H
I/O
0080H
RAM
0100H
0200H
Generalpurpose
registers
0280H
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000H
8000H
Vacant area
read FFH
Prohibited
C000H
4000H
ROM
FFFFH
7FFFH
Prog. area
(PROM)
3. Programming to the EPROM
In EPROM mode, the MB89P985 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH
(note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM
mode).
(3) Program with the EPROM programmer.
14
MB89980 Series
■ HANDLING THE MB89P985
1. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
2. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
3. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
FPT-64P-M03
TBD
FPT-64P-M09
TBD
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
15
MB89980 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
LCC-32 (Rectangle)
Adapter socket part number
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address
Single chip
Corresponding addresses on the EPROM programmer
0000H
I/O
0080H
RAM
0280H
Not available
8000H
0000H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
16
MB89980 Series
■ BLOCK DIAGRAM
Main clock
Oscillator
(max. 4.2 MHz)
X0
X1
21-bit timebase
timer
N-ch open-drain I/O port
Clock controller
P31/X0A*2
Sub-clock
Oscillator
P32/X1A*2
8-bit PWM timer 2
P26*1
Port 3
8
(Timer 2)
timer/counter 2
8-bit
P23
P21*1
(Timer 1)
timer/counter 1
8-bit
P20/EC
4
LCD controller/driver
8
External interrupt 2
(wake-up function)
4
P14 to P17
Port 1
4
2
4
External interrupt 1
(wake-up function)
14 × 4-bit display
RAM (7 bytes)
2
Port 6, 7
6
CMOS I/O port
P10/INT10 to
P13/INT13
P22/TO
Port 4
P00/INT20 to
P07/INT27
8
Port 0
RST
Internal data bus
Buzzer output
Reset circuit
(Watchdog timer)
CMOS I/O port
N-ch open-drain output ports
RAM
V0 to V3
COM0 to COM1
4
P40/SEG0
to P43/SEG3*1 *4
4
P44/SEG4
to P47/SEG7*1 *5
2
P60/SEG8
to P61/SEG9*1 *3
2
P62/SEG10
to P63/SEG11*6
2
P64/SEG12
to P65/SEG13*6
2
P70/COM2
to P71/COM3*3
N-ch open-drain
output port
4
8-bit A/D converter
Port 5
F2MC-8L
CPU
P24/RCO
P25
8-bit PWM timer 1
CMOS Input port
(P30 is CMOS output port)
Port 2
Remote control
output
Watch Prescaler
timer
P30/PWM1/BZ
P27/PWM2*1
4
P50/AN0
to P53/AN3
AVCC
ROM
AVR
AVSS
Other pins
MOD0, MOD1, VCC, VSS x 2
*1: Heavy-current drive type
*2: When the dual clock system is selected
*3, *4, *5, *6: Selected using mask option in MB89983, but selected by software in MB89P985 and MB89PV980.
17
MB89980 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89980 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89980 series is structured as illustrated below.
MB89P985
MB89983
0000H
0000H
I/O
I/O
0080H
0080H
0100H
RAM
0100H
I/O
0080H
RAM
0100H
Registers
Registers
0180H
MB89PV980
0000H
0200H
0280H
Registers
0200H
0280H
Access
prohibited
Access
prohibited
Access
prohibited
RAM
8000H
C000H
E000H
ROM
ROM
FFC0H
FFFFH
FFC0H
FFFFH
ROM
FFC0H
FFFFH
Vector table
(reset, interrupt, vector call instruction)
18
MB89980 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 18-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
: Program counter
FFFDH
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divide into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
11
10
9
8
Vacancy Vacancy Vacancy
RP
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
19
MB89980 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set the shift-out value in the case of a shift instruction.
20
MB89980 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 16 banks can be used on the MB89983 (RAM 256 × 8 bits). Up to a total of 32
banks can be used on the MB89P985 and MB89PV980 (RAM 512 × 8 bits). The bank currently in use is indicated
by the register bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuraiton
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
16banks
banks(MB89163)
(MB89983)
16
32banks
banks(MB89165)
(MB89P985 and MB89PV980)
32
Memory area
21
MB89980 Series
■ I/O MAP
Register
name
Address
Read/write
00H
R/W
PDR0
Port 0 data register
01H
W
DDR0
Port 0 data direction register
02H
R/W
PDR1
Port 1 data register
03H
W
DDR1
Port 1 data direction register
04H
R/W
PDR2
Port 2 data register
05H
W
DDR2
Port 2 data direction register
06H
Register description
(Vacancy)
07H
R/W
SYCC
08H
R/W
STBC
Standby control register
09H
R/W
WDTC
Watchdog timer control register
0AH
R/W
TBTC
Timebase timer control register
0BH
R/W
WPCR
Watch prescaler control register
0CH
R/W
PDR3
Port 3 data register
0DH
System clock control register
(Vacancy)
0EH
R/W
PDR4
Port 4 data register
0FH
R/W
PDR5
Port 5 data register
10H
R/W
BZCR
Buzzer register
11H
(Vacancy)
12H
R/W
PDR6
Port 6 data register
13H
R/W
PDR7
Port 7 data register
14H
R/W
RCR1
Remote control transmission register 1
15H
R/W
RCR2
Remote control transmission register 2
18H
R/W
T2CR
Timer 2 control register
19H
R/W
T1CR
Timer 1 control register
1AH
R/W
T2DR
Timer 2 data register
1BH
R/W
T1DR
Timer 1 data register
16H to 17H
(Vacancy)
1CH - 1DH
(Vacancy)
1EH
R/W
CNTR1
PWM 1 control register
1FH
W
COMR1
PWM 1 compare register
20H
R/W
CNTR2
PWM 2 control register
21H
W
COMR2
PWM 2 compare register
22H to 2CH
(Vacancy)
2DH
R/W
ADC1
A/D control register 1
2EH
R/W
ADC2
A/D control register 2
2FH
R/W
ADCD
A/D data register
30H
R/W
EIE1
External interrupt 1 control register
31H
R/W
EIF1
External interrupt 1 flag register
(Continued)
22
MB89980 Series
(Continued)
Address
Read/write
Register
name
32H
R/W
EIE2
External interrupt 2 control register
33H
R/W
EIF2
External interrupt 2 flag register
34H to 3FH
Register description
(Vacancy)
40H
R/W
PURR0
Pull-up control register 0 (For MB89P985/PV980 only)
41H
R/W
PURR1
Pull-up control register 1 (For MB89P985/PV980 only)
42H
R/W
PURR5
Pull-up control register 5 (For MB89P985/PV980 only)
43H to 5FH
60H to 66H
(Vacancy)
R/W
VRAM
67H to 71H
Display RAM
(Vacancy)
72H
R/W
LCR1
LCD control register 1
73H
R/W
LCR2
LCD control register 2 (For MB89P985/PV980 only)
7CH
W
ILR1
Interrupt level setting register 1
7DH
W
ILR2
Interrupt level setting register 2
7EH
W
ILR3
Interrupt level setting register 3
7FH
Access
prohibited
ITR
Interrupt test register
74H to 7BH
(Vacancy)
Notes: Do not use vacancies.
Notes: Read/write access symbols :
R/W : Readable and writable
R : Read-only
W : Write-only
23
MB89980 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
LCD power supply voltage
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
AVCC
VSS – 0.3
VSS + 7.0
V
AVCC must not exceed VCC + 0.3 V.
AVR
VSS – 0.3
VSS + 7.0
V
AVR must not exceed AVCC + 0.3 V.
V0 to V3
VSS – 0.3
VSS + 7.0
V
V0 to V3 must not exceed VCC.
VI1
VSS – 0.3
VCC + 0.3
V
VI1 must not exceed VSS + 7.0 V.
All pins except P20 to P27 without
a pull-up resistor
VI2
VSS – 0.3
VSS + 7.0
V
P20 to P27 without a pull-up
resistor
Input voltage
VO1
VSS – 0.3
VCC + 0.3
V
VO1 must not exceed VSS + 7.0 V.
All pins except P20 to P27, P40 to
P47, P60 to P65, P70 and P71
without a pull-up resistor
VO2
VSS – 0.3
VSS + 7.0
V
P20 to P27, P40 to P47, P60 to
P65, P70 and P71 without a pull-up
resistor
IOL1

10
mA
All pins except P21, P26, P27,
P40 to P47, P60 and P61
IOL2

20
mA
P21, P26, P27, P40 to P47, P60
and P61
mA
All pins except P21, P26, P27,
P40 to P47, P60, P61 and power
supply pins
Average value (operating current ×
operating rate)
Output voltage
“L” level maximum output current
IOLAV1

4
“L” level average output current
IOLAV2

8
mA
P21, P26, P27, P40 to P47, P60
and P61
Average value (operating current ×
operating rate)
“L” level total maximum output current
∑IOL

100
mA
Peak value
“L” level total average output current
∑IOLAV

40
mA
Average value (operating current ×
operating rate)
IOH1

–5
mA
All pins except P30 and power
supply pins
IOH2

–10
mA
P30
“H” level maximum output current
(Continued)
24
MB89980 Series
(Continued)
(AVSS = VSS = 0.0 V)
Value
Symbol
Parameter
Min.
Max.
Unit
Remarks
IOHAV1
—
–2
mA
All pins except P30 and power
supply pins
Average value (operating current ×
operating rate)
IOHAV2
—
–4
mA
P30
Average value (operating current ×
operating rate)
“H” level total maximum output current
∑IOH
—
–50
mA
Peak value
“H” level total average output current
∑IOHAV
—
–10
mA
Average value (operating current ×
operating rate)
Power consumption
PD
—
300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
“H” level average output current
Precautions: Parmanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Symbol
VCC
AVCC
AVR
Value
Unit
Remarks
Min.
Max.
2.2*1
6.0*1
V
Normal operation assurance range*1
2.2*1
4.0
V
Dual-clock mask ROM products
1.5
6.0
V
Retains the RAM state in stop mode
2.0
AVCC
V
Normal operation assurance range
V0 to V3 pins
LCD power supply range
(The optimum value dependent on the
LCD element in use.)
LCD power supply voltage
V0 to V3
VSS
VCC
V
Operating temperature
TA
–40
+85
°C
*1: The minimum operating power supply voltage varies with the execution time (instruction cycle time) setting for
the operating frequency.
A/D converter assurance accuracy varies with the operating power supply voltage.
25
MB89980 Series
6
Analog accurancy
assured in the AVCC
= VCC = 3.5 V to 6.0 V
range
Operating voltage (V)
5
Operation assurance range
4
3
2
1
1
2
3
4
(MHz)
1.0
(µs)
Main clock operating frequency
4.0
2.0
Minimum execution time (instruction cycle)
Note: The shaded area is assured only for the MB89983.
Figure 1
Operating Voltage vs. Main Clock Operating Frequency
Figures 1 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
Warning: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely reliability and could result in device failure.
No warranty is made with respect to uses, operating condition, or combination not represented on the
datasheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
26
MB89980 Series
2. DC Characteristics
(1) Pin DC characteristics (VCC = +5.0 V)
Parameter
Symbol
“L” level output
voltage
Min.
P00 to P07,
P10 to P17,
P20 to P27
0.7 VCC

VCC + 0.3
V
VIHS
RST,
MOD0, MOD1, EC,
INT10 to INT13,
INT20 to INT27
0.8 VCC

VCC + 0.3
V
VIL
P00 to P07,
P10 to P17,
P20 to P27
VSS − 0.3

0.3 VCC
V
VILS
RST,
MOD0, MOD1, EC,
INT10 to INT13,
INT20 to INT27
VSS − 0.3

0.2 VCC
V
VD1
P20 to P27
P40 to P47,
P60 to P65
VSS − 0.3

VSS + 6.0
V
VD2
P50 to P53
VSS − 0.3

VCC + 0.3
V
VOH1
P00 to P07,
P10 to P17
IOH = –2.0 mA
2.4


V
VOH2
P30
IOH = –6.0 mA
4.0


V
VOL1
P00 to P07,
P10 to P17,
P30
IOL = 1.8 mA


0.4
V
VOL2
P20, P22 to P25,
P50 to P53,
P62 to P65,
P70 to P71
IOL = 4.0 mA


0.4
V
VOL3
P21, P26, P27,
P40 to P47,
P60, P61
IOL = 8.0 mA


0.4
V
VOL4
RST
IOL = 4.0 mA


0.4
V


±5
µA
“L” level input voltage
“H” level output
voltage
Condition
VIH
“H” level input voltage
Open-drain output
pin application
voltage
Pin
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Typ.
Max.
Input leakage current
(Hi-z output leakage ILI
current)

P00 to P07,
P10 to P17,
0.45 V < VI < VCC
MOD0, MOD1, P30
P20 to P27 , P40
to P47, and P60 to
P65 without pullup resistor only
Without pull-up
resistor
(Continued)
27
MB89980 Series
(Continued)
Parameter
Symbol
Pin
Condition
Min.
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Typ.
Max.
ILO1
P20 to P27,
P40 to P47,
P60 to P65,
P70, P71
0.45 V < VI < 6.0 V
—
—
±5
µA
Without pull-up
resistor
ILO2
P50 to P53
0.45 V < VI < VCC
—
—
±5
µA
Without pull-up
resistor
Pull-up resistance
RPULL
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P53,
P60 to P65,
RST
VI = 0.0 V
25
50
100
kΩ
With pull-up
resistor
Common output
impedance
RVCOM
COM0 to COM3
—
—
2.5
kΩ
Segment output
impedance
RVSEG
SEG0 to SEG13
—
—
15
kΩ
LCD divided
resistance
RLCD
Between VCC and V0
300
500
750
kΩ
—
—
—
±1
µA
—
10
—
pF
Open-drain output
leakage current
V1 to V3 = +5.0 V
—
LCD controller/driver
ILCDL
leakage current
V0 to V3,
COM0 to COM3,
SEG0 to SEG13
Input capacitance
Other than
VCC, VSS
CIN
f = 1 MHz
Note: For pins which serve as the segment (SEG0 to SEG13) and ports (P40 to P47, P50 to P53, and P60 to P65),
see the port parameter when these pins are used as ports and the segment parameter when they are used
as segments.
28
MB89980 Series
(2) Pin DC Characteristics (VCC = +3.0 V)
Parameter
“H” level output
voltage
Symbol
Condition
VOH1
P00 to P07,
P10 to P17
IOH = –1.0 mA
2.4
—
—
V
VOH2
P30
IOH = –3.0 mA
2.4
—
—
V
VOL1
P00 to P07,
P10 to P17,
P20 to P27,
P30,
P50 to P53,
P62 to P65,
P70 to P71
IOL = 1.8 mA
—
—
0.4
V
VOL2
RST
IOL = 1.8 mA
—
—
0.4
V
VOL3
P21, P26, P27
P40 to P47,
P60, P61
IOL = 3.6 mA
—
—
0.4
V
RPULL
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P53,
P60 to P65,
P70 to P71
RST
VI = 0.0 V
50
100
150
kΩ
“L” level output
voltage
Pull-up resistance
Pin
(VCC = 3.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Typ.
Max.
With pull-up
resistor
29
MB89980 Series
(3)
Power Supply Current Characteristics (MB89983)
Parameter
Power supply
current*1
Symbol
Pin
Condition
Min.
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Typ.
Max.
ICC1
FCH = 4.2 MHz, VCC = 5.0 V
tinst*2 = 4/FCH
Main clock operation mode
—
5.0
10.0
mA
ICC2
FCH = 4.2 MHz, VCC = 3.0 V
tinst*2 = 64/FCH
Main clock operation mode
—
1.5
2.0
mA
ICCL
FCL = 32.768 kHz, VCC = 3.0 V
tinst*2 = 2/FCL
Subclock operation mode
—
0.05
0.1
mA
ICCS1
FCH = 4.2 MHz, VCC = 5.0 V
tinst*2 = 4/FCH
Main clock sleep mode
—
2.5
5.0
mA
ICCS2
FCH = 4.2 MHz, VCC = 3.0 V
tinst*2 = 64/FCH
Main clock sleep mode
—
1.0
1.5
mA
ICCSL
FCL = 32.768 kHz, VCC = 3.0 V
tinst*2 = 2/FCL
Subclock sleep mode
—
25
50
µA
ICCT
FCL = 32.768 kHz, VCC = 3.0 V
Watch mode
—
10
15
µA
ICCH
TA = +25×C, VCC = 5.0 V
Stop mode
—
0.1
1.0
µA
FCH = 4.2 MHz, VCC = 5.0 V
—
1.0
3.0
mA
IA
VCC
AVCC
MB89983
When A/D
conversion is
activated
*1: The power supply current is measured at the external clock, open output pins, and the external LCD dividing
resistor (or external input for the reference voltage).
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
30
MB89980 Series
4. AC Characteristics
(1) Reset Timing
Parameter
(VCC = +5.0 V ±10 %, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
RST “L” pulse width
tZLZH
RST “H” pulse width
tZHZL
—
48 tXCYL
—
ns
24 tXCYL
—
ns
tZLZH
tZHZL
RST
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
(2) Power-on Reset
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Condition
Value
Min.
Max.
Unit
Remarks
Power supply rising time
tR
—
—
50
ms
Power-on reset
function only
Power supply cut-off time
tOFF
—
1
—
ms
Due to repeated
operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage
needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
2.0 V
VCC
0.2 V
0.2 V
0.2 V
31
MB89980 Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Value
Pin
Min.
Typ.
Max.
Unit
Remarks
FCH
X0, X1
1
—
4.2
MHz
Main clock
FCL
X0A, X1A
—
32.768
—
kHz
Subclock
tHCYL
X0, X1
238
—
1000
ns
Main clock
tLCYL
X0A, X1A
—
30.5
—
µs
Subclock
Input clock pulse width
PWH
PWL
X0
20
—
—
ns
Input clock rising/falling
time
tCR
tCF
X0
—
—
24
ns
Clock frequency
Clock cycle time
External clock
Main Clock Timing and Conditions
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCR
tCF
Main Clock Conditions
When a crystal
or
ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
When the CR
oscillation option is used
X0
X1
Open
FCH
FCH
R
FCH
C0
32
C1
C
MB89980 Series
Subclock Timing and Conditions
tLCYL
0.8 VCC
X0A
Subclock Conditions
When a crystal
or
ceramic oscillator is used
X0A
When the single-clock option is used
X 0A
X1A
FCL
C0
Rd
X 1A
Open
C1
(4) Instruction Cycle
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Instruction cycle
(minimum execution time)
Symbol
tinst
Value (typical)
4/FCH, 8/FCH, 16/FCH,
64/FCH
2/FCL
Unit
Remarks
µs
(4/FCH) tinst = 1.0 µs at FCH = 4 MHz
µs
tinst = 62 µs at FCL = 32.768 kHz
33
MB89980 Series
(5) Peripheral Input Timing
Parameter
(VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Unit
Remarks
Min.
Max.
Symbol
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
Peripheral input “H” pulse width 2
tILIH2
Peripheral input “L” pulse width 2
tIHIL2
INT10 to INT13, EC
INT20 to INT27
1 tinst*
—
µs
1 tinst*
—
µs
2 tinst*
—
µs
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
t IHIL1
INT10 to 13,
EC
t ILIH1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t IHIL2
t ILIH2
INT20 to 27
0.8 VCC
0.2 VCC
34
0.2 VCC
0.8 VCC
MB89980 Series
5. A/D Converter Electrical Characteristics
(3 MHz, AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Resolution
Condition
—
Total error
—
Linearity error
Differential linearity error
Zero transition voltage
VOT
Full-scale transition
voltage
VFST
AVR = AVCC
Value
Unit
Min.
Typ.
Max.
—
—
8
bit
—
—
±1.5
LSB
—
—
±1.0
LSB
—
—
±0.9
LSB
AVSS – 1.0 LSB AVSS + 0.5 LSB AVSS + 2.0 LSB
mV
AVR – 3.0 LSB AVR – 1.5 LSB
AVR
mV
Remarks
—
Interchannel disparity
A/D mode conversion time
—
—
0.5
LSB
—
44 tinst
—
ms
—
12 tinst
—
ms
—
—
10
µA
0.0
—
AVR
V
2.0
—
AVCC
V
AVR = 5.0 V,
when A/D
conversion is
activated
—
100
—
µA
AVR = 5.0 V,
when A/D
conversion is
stopped
—
—
1
µA
—
Sense mode conversion
time
—
Analog port input current IAI
Analog input voltage
—
Reference voltage
—
AN0 to
AN3
IR
AVR
Reference voltage supply
current
IRH
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 8, analog voltage can be divided into 28=256.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
35
MB89980 Series
Digital output
1111
1111
.
.
.
.
.
.
.
.
.
.
.
0000
0000
0000
1111
1110
Actual conversion value
1 LSB =
AVR
256
Theoretical conversion value
VNT - (1 LSB x N + VOT)
Linearity error =
(1 LSB x N + VOT)
1 LSB
V(N+1)T - VNT
Defferential linearity error =
Total error =
1 LSB
-1
VNT - (1 LSB x N + 1 LSB)
1 LSB
Linearity error
0010
0001
0000
VOT
VNT V(N + 1)T
VFST
Analog input
(2) Precautions
• Input impedance of analog input pins
The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the
sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Analog Input Equivalent Circuit
Sample hold circuit
.
C =. 33 pF
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R =. 6 kΩ
Close for 8 instruction cycles after
activating A/D conversion.
Analog channel selector
• Error
The smaller the |AVR – AV SS|, the greater the error would become relatively.
36
MB89980 Series
■ EXAMPLE CHARACTERISTICS
1. “L” Level Output Voltage
VOL1 vs. IOL
VOL1 (V)
VOL2 vs. IOL
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.0 V
0.6
VCC = 4.0 V
TA = +25°C
0.5
VCC = 5.0 V
VCC = 6.0 V
0.4
VOL2 (V)
VCC = 2.0 V
1.0
TA = +25°C
0.9
VCC = 2.5 V VCC = 3.0 V
0.8
0.7
VCC = 4.0 V
0.6
VCC = 5.0 V
VCC = 6.0 V
0.5
0.3
0.4
0.2
0.3
0.2
0.1
0.1
0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
0
0
2
4
6
8
10
12 14
16 18
20
IOL (mA)
2. “H” Level Output Voltage
VCC – VOH1 vs. IOH
VCC – VOH1 (V)
VCC = 2.0 V VCC = 2.5 V VCC = 3.0 V
1.0
TA = +25°C
0.9
0.8
0.7
0.6
VCC – VOH2 vs. IOH
VCC – VOH2 (V)
VCC = 2.0 V VCC = 2.5 V
1.0
TA = +25°C
0.9
VCC = 4.0 V
0.8
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.7
VCC = 5.0 V
VCC = 6.0 V
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
0
–1
–2
–3
–4
VCC = 3.0 V
–5
IOH (mA)
0
–1
–2
–3
–4 –5
–6
–7
–8
–9 –10
IOH (mA)
37
MB89980 Series
3. “H” Level Input Voltage/“L” level Input Voltage
CMOS input
CMOS hysteresis input
VIN (V)
5.0
TA = +25°C
4.5
VIN (V)
5.0
TA = +25°C
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
VIHS
VILS
0
1
2
3
4
5
6
7
VCC (V)
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
4. Power Supply Current (External Clock)
ICC1 vs VCC (Mask ROM products)
ICC2 vs VCC (Mask ROM products)
ICC1 (mA)
ICC2 (mA)
5
1
o
TA = +25 C
o
TA = +25 C
4
0.8
FCH = 4.2 MHz
3
0.6
FCH = 4.2 MHz
FCH = 3 MHz
2
0.4
FCH = 3 MHz
1
FCH = 1MHz
0
1
2
3
4
5
6
7
VCC (V)
0.2
FCH = 1 MHz
0
1
2
3
4
5
6
7
VCC (V)
(Continued)
38
MB89980 Series
(Continued)
ICC1S vs VCC (Mask ROM products)
ICC2S vs VCC (Mask ROM products)
ICC2S (mA)
ICC1S (mA)
1
FCH = 4.2 MHz
o
0.5
o
TA = +25 C
TA = + 25 C
0.4
0.8
FCH = 3 MHz
0.6
FCH = 4.2 MHz
0.3
FCH = 3 MHz
0.2
0.4
FCH = 1 MHz
0.2
FCH = 1 MHz
0.1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
VCC (V)
ICCL vs VCC (Mask ROM products)
7
VCC (V)
ICCT vs VCC
ICCL (mA)
ICCT (mA)
100
4
o
TA = + 25 C
3.6
o
TA = + 25 C
80
3.2
2.8
60
2.4
FCL = 32.768 kHz
40
FCL = 32.768kHz
2
1.6
1.2
0.8
20
0.4
0
1
2
3
4
5
6
7
VCC (V)
0
1
2
3
4
5
6
7
VCC (V)
(Continued)
39
MB89980 Series
(Continued)
ICCSL vs. VCC
ICCSL (mA)
200
TA = +25˚C
180
160
140
120
100
FCL = 32.768 kHz
80
60
40
20
0
1
2
3
4
5
6
7
VCC (V)
IA vs AVCC
IR vs. AVR
IA (mA)
IR (uA)
4
120
o
3.5
TA = + 25 C
o
TA = + 25 C
FCH = 4 MHz
3
100
2.5
80
2
60
1.5
40
1
20
0.5
0
1.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
1.5
2
2.5
3
3.5
AVCC(V)
4
4.5
5
5.5
6
6.5
AVR (V)
(Continued)
5. Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
TA = +85°C
TA = +25°C
50
TA = –40°C
10
1
40
2
3
4
5
6
7
VCC (V)
MB89980 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation for instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
41
MB89980 Series
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
Number of instructions
#:
Number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
42
MB89980 Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F 2MC-8 family)
43
MB89980 Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
44
MB89980 Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
45
46
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0
R0,#d8
R0,#d8
dir: 0 dir: 0,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1
R1,#d8
R1,#d8
dir: 1 dir: 1,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2
R2,#d8
R2,#d8
dir: 2 dir: 2,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3
R3,#d8
R3,#d8
dir: 3 dir: 3,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4
R4,#d8
R4,#d8
dir: 4 dir: 4,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5
R5,#d8
R5,#d8
dir: 5 dir: 5,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6
R6,#d8
R6,#d8
dir: 6 dir: 6,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7
R7,#d8
R7,#d8
dir: 7 dir: 7,rel
8
9
A
B
C
D
E
F
A
A
A
SUBC
A
XCH
A, T
XOR
A
AND
A
OR
A
MOV
MOV
CLRB
BBC
INCW
DECW
MOVW
MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
ADDC
A,@IX
+d
SUBC
A,@IX
+d
MOV
@IX
+d,A
AND
XOR
@A,IX A,@IX
+d +d
OR
A,@IX
+d
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
CMP
@EP,#d
8
DAS
R7
R6
R5
R4
R3
R2
R1
R0
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
R7
R6
R5
R4
R3
R2
R1
R0
rel
rel
rel
rel
rel
CALLV
BLT
#7
rel
CALLV
BGE
#6
rel
CALLV
BZ
#5
CALLV
BNZ
#4
CALLV
BN
#3
CALLV
BP
#2
CALLV
BC
#1
CALLV
BNC
#0
rel
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 7 dir: 7,rel
A,@EP
@EP,A EP,#d16
A,EP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 4 dir: 4,rel
A,ext
ext,A
A,#d16
A,PC
ADDCW SUBCW XCHW
XORW
ANDW
ORW
MOVW
MOVW
CLRB
BBC
INCW
DECW
MOVW
MOVW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
ADDC
CLRB
BBC
INCW
DECW
MOVW
MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
A,@EP
A,@EP
A,@EP
A,@EP
@EP,A
A,@EP
A,@EP
A,@EP @EP,#d
8
CMP
A,@IX
+d
CMPW
CMP
SETC
7
F
MOVW
XCHW
MOVW
CLRB
BBC
MOVW
CMP
MOV
IX,#d16
A,IX
@IX
dir: 6 dir: 6,rel
A,@IX
@IX
@IX
+d,A
+d
+d,#d8
+d,#d8
E
MOV
A,@IX
+d
D
6
C
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir
dir,#d8
dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
B
CLRB
BBC
INCW
DECW
JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
5
A
A
JMP
CALL
PUSHW POPW
MOV
MOVW
CLRC
addr16
addr16
IX
IX
ext,A
PS,A
SETI
9
MOV
CMP
ADDC
SUBC
A,#d8
A,#d8
A,#d8
A,#d8
8
4
7
RORC
6
3
A
5
PUSHW POPW
MOV
MOVW
CLRI
A
A
A,ext
A,PS
4
ROLC
DIVU
RETI
3
2
A
RET
2
MULU
SWAP
1
1
0
NOP
H
0
L
MB89980 Series
■ INSTRUCTION MAP
MB89980 Series
■ MASK OPTIONS
No.
Part number
MB89983
MB89P985
MB89PV980
Specifying procedure
Specify when
ordering masking
Setting with
software
Setting with
software
Slectable per pin
(The pull-up
resistors for P40 to
P47 and P60 to P65
are only selectable
when these pins are
not set as segment/
common outputs.
When the A/D is
used, P50 to P53 are
must not selected.)
Selectable per pin
by pull-up control
registers.
(Pull-up resistors are
not available for P20
to P27, P40 to P47
and P60 to P65.
Furthermore, P50 to
P53 must be set to
without a pull-up
resistor when an A/D
converter is used.)
Selectable per pin
by pull-up control
registers.
(Pull-up resistors are
not available for P20
to P27, P40 to P47
and P60 to P65.
Furthermore, P50 to
P53 must be set to
without a pull-up
resistor when an A/D
converter is used.)
Fixed with power-on
reset
Fixed with power-on
reset
1
Pull-up resistors (SEG)
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P53,
P60 to P65
2
Power-on reset (POR)
With power-on reset
Without power-on reset
Selectable
Selection of oscillation stabilization
time (OSC)
• The initial value of the oscillation
stabilization time for the main
clock can be set by selecting the
values of the WT1 and WT0 bits
on the right.
Selectable
OSC
0
: 22/FCH
1
: 212/FCH
2
: 216/FCH
3
: 218/FCH
Fixed to oscillation
stabilization time of
218/FCH (Approx.
62.4 ms).
Fixed to oscillation
stabilization time of
218/FCH (Approx.
62.4 ms).
Main clock oscillation type (XSL)
Crystal or ceramic resonator
CR
Selectable
Crystal or ceramic
resonator only
Crystal or ceramic
resonator only
Reset pin output (RST)
With reset output
Without reset output
Selectable
Fixed with reset
output
Selectable
Selection by version
number
101 : Single clock
201 : Dual clock
3
4
5
6
Clock mode selection (CLK)
Dual-clock mode
Single-clock mode
Fixed with reset
output
Selection by version
number
101 : Single clock
201 : Dual clock
47
MB89980 Series
• Segment Options
No.
7
Part number
MB89983
Specifying procedure
Specify when
ordering masking
LCD output pin configuration
choices
Specify by the option combinations
listed below
SEG = 3:
P40 to P47 segment output
P60 to P65 segment output
P70, P71 common output
Specify as SEG = 3
SEG = 2:
P40 to P43 port output
P44 to P47 segment output
P60 to P65 segment output
P70, P71 common output
Specify as SEG = 2
SEG = 1:
P40 to P47 port output
P60 to P65 segment output
P70, P71 common output
Specify as SEG = 1
SEG = 0:
P40 to P47 port output
P60 to P65 port output
P70, P71 port output
Specify as SEG = 0
■ VERSIONS
Version
Mass production
product
48
One-time
PROM product
Features
Piggyback
product
Clock mode
MB89983
MB89P985-101
MB89PV980-101
Single clock
MB89983
MB89P985-201
MB89PV980-201
Dual clock
MB89980 Series
■ ORDERING INFORMATION
Part Number
Package
MB89983-xxx-PFV
64-pin Plastic LQFP
(FPT-64P-M03)
MB89983-xxx-PFM
64-pin Plastic QFP
(FPT-64P-M09)
MB89P985PFV-101
64-pin Plastic LQFP
(FPT-64P-M03)
MB89P985-PFM-101
64-pin Plastic QFP
(FPT-64P-M09)
MB89P985PFV-201
MB89P985-PFM-201
64-pin Plastic LQFP
(FPT-64P-M03)
64-pin Plastic QFP
(FPT-64P-M09)
Remarks
Single Clock
Dual Clock
MB89PV980-101
64-pin Ceramic MQFP
(MQP-64C-P01)
Single Clock
MB89PV980-201
64-pin Ceramic MQFP
(MQP-64C-P01)
Dual Clock
49
MB89980 Series
■ PACKAGE DIMENSIONS
64-pin Plastic LQFP
(FPT-64P-M03)
+0.20
1.50 –0.10
12.00±0.20(.472±.008)SQ
+.008
.059 –.004
10.00±0.10(.394±.004)SQ
48
(Mounting height)
33
49
32
7.50
(.295)
REF
11.00
(.433)
NOM
INDEX
64
Details of "A" part
17
LEAD No.
1
16
0.50±0.08
(.0197±.0031)
"A"
+0.08
0.10±0.10
(STAND OFF)
(.004±.004)
+0.05
0.18 –0.03
0.127 –0.02
+.003
.007 –.001
.005
+.002
–.001
0.50±0.20
(.020±.008)
0.10(.004)
C
0
10˚
Dimension in mm (inches)
1995 FUJITSU LIMITED F64009S-2C-5
64-pin Plastic QFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
48
33
12.00±0.10(.472±.004)SQ
49
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
32
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
LEAD No.
17
1
0.65(.0256)TYP
Details of "A" part
16
0.30±0.10
(.012±.004)
"A"
0.13(.005)
M
+0.05
0.127 –0.02
+.002
.005 –.001
0.10±0.10 (STAND OFF)
(.004±.004)
0.10(.004)
0
C
50
1994 FUJITSU LIMITED F64018S-1C-2
10˚
0.50±0.20
(.020±.008)
Dimension in mm (inches)
MB89980 Series
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
INDEX AREA
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
+0.40
1.20 –0.20
+.016
.047 –.008
1.00±0.25
(.039±.010)
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.40±0.10
(.016±.004)
18.00(.709)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
51
1994 FUJITSU LIMITED M64004SC-1-3
10.82(.426)
0.15±0.05 MAX
(.006±.002)
Dimension in mm (inches)
MB89980 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9902
 FUJITSU LIMITED Printed in Japan
52
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