PD-95025A
IRFR5305PbF
IRFU5305PbF
l
l
l
l
l
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Ultra Low On-Resistance
Surface Mount (IRFR5305)
Straight Lead (IRFU5305)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Lead-Free
HEXFET® Power MOSFET
D
VDSS = -55V
RDS(on) = 0.065Ω
G
ID = -31A
S
Description
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
HEXFET® Power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable device
for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
D-Pak
IRFR5305
I-Pak
IRFU5305
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew
Max.
Units
-31
-22
-110
110
0.71
± 20
280
-16
11
-5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient**
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Typ.
Max.
Units
–––
–––
–––
1.4
50
110
°C/W
1
12/13/04
IRFR/U5305PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
IGSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
Conditions
-55
––– –––
V
VGS = 0V, ID = -250µA
––– -0.034 ––– V/°C Reference to 25°C, I D = -1mA
–––
––– 0.065
Ω
VGS = -10V, ID = -16A
-2.0
––– -4.0
V
VDS = VGS, ID = -250µA
8.0
––– –––
S
VDS = -25V, ID = -16A
–––
––– -25
VDS = -55V, VGS = 0V
µA
–––
––– -250
VDS = -44V, VGS = 0V, TJ = 150°C
–––
––– 100
VGS = 20V
nA
–––
––– -100
VGS = -20V
–––
–––
63
ID = -16A
–––
–––
13
nC
VDS = -44V
–––
–––
29
VGS = -10V, See Fig. 6 and 13
–––
14
–––
VDD = -28V
–––
66
–––
ID = -16A
ns
–––
39
–––
RG = 6.8Ω
–––
63
–––
RD = 1.6Ω, See Fig. 10
D
Between lead,
4.5 –––
–––
6mm (0.25in.)
nH
G
from package
–––
7.5 –––
and center of die contact
S
––– 1200 –––
VGS = 0V
–––
520 –––
pF
VDS = -25V
–––
250 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
-31
-110
–––
–––
–––
–––
71
170
-1.3
110
250
A
V
ns
nC
Conditions
D
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
S
TJ = 25°C, IS = -16A, VGS = 0V
TJ = 25°C, IF = -16A
di/dt = -100A/µs
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
VDD = -25V, starting TJ = 25°C, L = 2.1mH
RG = 25Ω, IAS = -16A. (See Figure 12)
ISD ≤ -16A, di/dt ≤ -280A/µs, VDD ≤ V(BR)DSS,
Pulse width ≤ 300µs; duty cycle ≤ 2%.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact.
Uses IRF5305 data and test conditions.
T J ≤ 175°C
2
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IRFR/U5305PbF
1000
1000
VGS
- 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
-ID , Drain-to-Source Current (A)
-ID , Drain-to-Source Current (A)
100
10
-4.5V
100
20µs PULSE WIDTH
Tc
J = 25°C
A
1
0.1
1
10
10
-4.5V
R DS(on) , Drain-to-Source On Resistance
(Normalized)
-ID , Drain-to-Source Current (A)
2.0
TJ = 25°C
TJ = 175°C
10
V DS = -25V
20µs PULSE WIDTH
6
7
8
9
-VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
A
100
Fig 2. Typical Output Characteristics
100
5
1
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1
20µs PULSE WIDTH
TCJ = 175°C
1
0.1
100
-VDS , Drain-to-Source Voltage (V)
4
VGS
- 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
TOP
TOP
10
A
I D = -27A
1.5
1.0
0.5
V GS = -10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U5305PbF
C, Capacitance (pF)
2000
Ciss
20
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
-VGS , Gate-to-Source Voltage (V)
2500
Coss
1500
1000
Crss
500
0
10
V DS = -44V
V DS = -28V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
1
I D = -16A
100
0
-VDS , Drain-to-Source Voltage (V)
30
40
50
A
60
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
-ID , Drain Current (A)
-ISD , Reverse Drain Current (A)
20
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
TJ = 175°C
TJ = 25°C
VGS = 0V
10
0.4
0.8
1.2
1.6
-VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
A
2.0
100
100µs
10
1ms
10ms
TC = 25°C
TJ = 175°C
Single Pulse
1
1
A
10
100
-VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U5305PbF
RD
VDS
35
VGS
30
D.U.T.
RG
-
-ID , Drain Current (A)
+
VDD
25
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
15
Fig 10a. Switching Time Test Circuit
10
td(on)
tr
t d(off)
tf
VGS
5
10%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
90%
VDS
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
PDM
0.05
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U5305PbF
+
-
D.U.T
RG
IAS
-20V
tp
VDD
A
DRIVER
0.01Ω
15V
Fig 12a. Unclamped Inductive Test
Circuit
I AS
E AS , Single Pulse Avalanche Energy (mJ)
L
VDS
700
TOP
600
BOTTOM
ID
-6.6A
-11A
-16A
500
400
300
200
100
0
VDD = -25V
25
50
A
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
tp
V(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
-10V
QGS
QGD
D.U.T.
+VDS
VGS
VG
-3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFR/U5305PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
**
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS *
+
-
*
VDD
*
Reverse Polarity for P-Channel
** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
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7
IRFR/U5305PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
PART NUMBER
INTERNAT IONAL
RECTIF IER
LOGO
Note: "P" in ass embly line pos ition
indicates "Lead-Free"
IRFU120
12
916A
34
ASSEMBLY
LOT CODE
DATE CODE
YEAR 9 = 1999
WE EK 16
LINE A
OR
PART NUMBER
INT ERNATIONAL
RECTIFIER
LOGO
IRFU120
12
ASSEMBLY
LOT CODE
8
34
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 16
A = ASSEMBLY S IT E CODE
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IRFR/U5305PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE : T HIS IS AN IRF U120
WIT H ASS EMB LY
LOT CODE 5678
AS SE MBLED ON WW 19, 1999
IN T HE ASS EMBLY LINE "A"
INT ERNATIONAL
RE CT IFIE R
LOGO
PART NUMBER
IRF U120
919A
56
78
ASS EMBLY
LOT CODE
Note: "P" in as s embly line
pos ition indicates "Lead-F ree"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMB ER
IRF U120
56
AS SEMBLY
LOT CODE
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78
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 19
A = AS SEMBLY SIT E CODE
9
IRFR/U5305PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
10
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