IC62LV25616L IC62LV25616LL Document Title 256Kx16 bit Low Voltage and Ultra Low Power CMOS Static RAM Revision History Revision No History Draft Date Remark 0A Initial Draft May 1,2001 Preliminary 0B 1. Change for tPWE: 45 to 40 ns for 55 ns product August 21,2001 : 60 to 40 ns for 70 ns product 2. Change for VCC: 2.2-3.6V to 2.7-3.6V 3.1 Change for ICC test conditiomn: VCC=Max. to 3V 3.2 Change for ICC: 35 to 40mA for 55 ns commercial product 30 to 35mA for 70 ns commercial porduct 25 to 30 mA for 100 ns commercial product 4. Change for ISB1 test conditions: with CE controlled only 5.1 Change for VDR Min. : 1.2 to 1.5V 5.2 Change for IDR test condition: VCC=1.2 to 1.5V 0C January 29,2002 1.Change for ICC: 40 mA to 25 mA for 55 ns 35 mA to 20 mA for 70 ns 30 mA to 15mA for 100 ns 2.Change for IDR: 4µA to 5 µA for commercial/LL product 6µA to 9 µA for Industrial/LL Product October 9,2002 Change for VOH: 2.0V to 2.4V 0D The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 1 IC62LV25616L IC62LV25616LL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES DESCRIPTION The ICSI IC62LV25616L and IC62LV25616LL are low-power, • High-speed access times: 55, 70, 100 ns • CMOS low power operation -- 60 mW (typical) operating -- 3 µW (typical) CMOS standby • TTL compatible interface levels • Single 2.7V-3.6V Vcc power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Available in the 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA 4.194,304 bit static RAMs organized as 262,144 words by 16 bits. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected) or both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC62LV25616L and IC62LV25616LL are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 IC62LV25616L IC62LV25616LL PIN CONFIGURATIONS 48-Pin TF-BGA(TOP View) 44-Pin TSOP-2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A17 1 2 3 4 5 6 A LB OE A0 A1 A2 N/C B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 Vcc E Vcc I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A17 Address Inputs LB Lower-byte Control (l/O0-I/O7) I/O0-I/O15 Data Input/Output UB Upper-byte Control (l/O8-I/O15) CE Chip Enable Input NC No Connection OE Output Enable Input Vcc Power WE Write Enable Input GND Ground TRUTH TABLE Mode Not Selected Output Disab X Read Write WE CE X X X X H H H L L L H L L L L L L L L OE X X High-Z X L L L X X X Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 LB X H H L H L L H L UB X H High-Z H H L L H L L I/O0/-I/O7 High-Z High-Z Active High-Z DOUT High-Z DOUT DIN High-Z DIN I/O PIN I/O8-I/O15 Power High-Z High-Z Stand by Stand by High-Z High-Z DOUT DOUT High-Z DIN DIN Stand by Active Active 3 IC62LV25616L IC62LV25616LL OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C VCC 2.7V- 3.6V –40°C to +85°C 2.7V - 3.6V Industrial ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc related to GND Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –40 to +85 –0.3 to +4.0 –65 to +150 1.0 Unit V °C V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage VIH(1) VIL(2) ILI ILO Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Min. Max. Unit IOH = –1 mA 2.4 — V IOL = 2.1 mA — 0.4 V 2.2 –0.2 –1 –1 VCC + 0.2 0.4 1 1 V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED Notes: 1. VIH(max.) = VCC+2.0V for pulse width less than 10 ns. 2. VIL(min.) = –2.0V for pulse width less than 10 ns. CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 4 Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 IC62LV25616L IC62LV25616LL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V 1.5V See Figures 1 AC TEST LOADS 1 TTL OUTPUT 100 pF Including jig and scope Figure 1 IC62LV25616L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -55 Min. Max. -70 Min. Max. -100 Min. Max. Symbol Parameter Test Conditions ICC Vcc Dynamic Operating Supply Current VCC = 3V, IOUT = 0 mA, f = fMAX Com. Ind. — — 25 25 — — 20 20 — — 15 15 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL, CE ≥ VIH, f = 0 Com. Ind. — — 0.2 0.3 — — 0.2 0.3 — — 0.2 0.3 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0 Com. Ind. — — 35 50 — — 35 50 — — 35 50 µA OR ULB Control Unit VCC = Max., VIN≥VCC-0.2V or VIN ≤ 0.2V, f = 0, UB / LB ≥ VCC – 0.2V Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 5 IC62LV25616L IC62LV25616LL IC62LV25616LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -55 Min. Max. -70 Min. Max. -100 Min. Max. Symbol Parameter Test Conditions ICC Vcc Dynamic Operating Supply Current VCC = 3V, IOUT = 0 mA, f = fMAX Com. Ind. — — 25 25 — — 20 20 — — 15 15 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL, CE ≥ VIH, f = 0 Com. Ind. — — 0.2 0.3 — — 0.2 0.3 — — 0.2 0.3 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., f = 0 CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0 Com. Ind. — — 15 20 — — 15 20 — — 15 20 µA OR ULB Control Unit VCC = Max., VIN≥VCC-0.2V or VIN ≤ 0.2V, f = 0, UB / LB ≥ VCC – 0.2V Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -55 Symbol -70 -100 Min. Max. Parameter Min. Max. Min. Max. tRC Read Cycle Time 55 — 70 — 100 — ns tAA Address Access Time — 55 — 70 — 100 ns tOHA Output Hold Time 10 — 10 — 15 — ns tACE CE Access Time — 55 — 70 — 100 ns tDOE OE Access Time — 30 — 38 — 50 ns tHZOE(2) OE to High-Z Output — 20 — 25 — 30 ns tLZOE(2) OE to Low-Z Output 5 — 5 — 5 — ns (2) CE to High-Z Output 0 20 0 25 0 30 ns (2) CE to Low-Z Output 10 — 10 — 10 — ns tBA LB, UB Access Time — 55 — 70 — 100 ns tHZB LB, UB o High-Z Output 0 25 0 25 0 35 ns tLZB LB. UB to Low-Z Output 0 — 0 — 0 — ns tHZCE tLZCE Unit Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 6 Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 IC62LV25616L IC62LV25616LL AC TEST LOADS READ CYCLE NO.1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CE, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE tACE tHZCE tBA tHZB tLZCE LB, UB DOUT HIGH-Z tLZB DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 7 IC62LV25616L IC62LV25616LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -55 Symbol Parameter -70 Min. Max. Min. Max. -100 Min. Max Unit tWC Write Cycle Time 55 — 70 — 100 — ns tSCE CE to Write End 50 — 65 — 80 — ns tAW Address Setup Time to Write End 50 — 65 — 80 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 45 — 60 — 80 — ns tPWE WE Pulse Width 40 — 40 — 80 — ns tSD Data Setup to Write End 25 — 30 — 40 — ns Data Hold from Write End 0 — 0 — 0 — ns WE LOW to High-Z Output — 30 — 30 — 40 ns tLZWE(3) WE HIGH to Low-Z Output 5 — 5 — 5 — ns tHD tHZWE (3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled) t WC VALID ADDRESS ADDRESS t SA t SCS t HA CE t AW t PWE WE t PBW UB, LB t LZWE t HZWE DOUT DATA UNDEFINED HIGH-Z t SD DIN t HD DATAIN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). 8 Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 IC62LV25616L IC62LV25616LL WRITE CYCLE NO. 2 (WE Controlled) t WC ADDRESS VALID ADDRESS t HA CE LOW t AW t PWE WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 3 (UB / LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 t SA CE LOW t HA t HA t SA WE UB, LB t PBW t PBW WORD 1 WORD 2 t LZWE t HZWE DOUT HIGH-Z DATA UNDEFINED t HD t SD DIN Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 DATAIN VALID t HD t SD DATAIN VALID 9 IC62LV25616L IC62LV25616LL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.6 V IDR Data Retention Current Vcc = 1.5V, CE ≥ Vcc – 0.2V — — — — 10 5 15 9 µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform 5 — ns Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) DATA RETENTION WAVEFORM (CE or LB/UB Controlled) tSDR Data Retention Mode tRDR VCC 2.7V 2.2V VDR CE ≥ VCC - 0.2V CE, LB/UB GND 10 Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 IC62LV25616L IC62LV25616LL ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 55 IC62LV25616L-55T IC62LV25616L-55B TSOP-2 6*8mm TF-BGA 55 IC62LV25616L-55TI IC62LV25616L-55BI TSOP-2 6*8mm TF-BGA 70 IC62LV25616L-70T IC62LV25616L-70B TSOP-2 6*8mm TF-BGA 70 IC62LV25616L-70TI IC62LV25616L-70BI TSOP-2 6*8mm TF-BGA 100 IC62LV25616L-100T IC62LV25616L-100B TSOP-2 6*8mm TF-BGA 100 IC62LV25616L-100TI IC62LV25616L-100BI TSOP-2 6*8mm TF-BGA ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 55 IC62LV25616LL-55T IC62LV25616LL-55B TSOP-2 6*8mm TF-BGA 55 IC62LV25616LL-55TI IC62LV25616LL-55BI TSOP-2 6*8mm TF-BGA 70 IC62LV25616LL-70T IC62LV25616LL-70B TSOP-2 6*8mm TF-BGA 70 IC62LV25616LL-70TI IC62LV25616LL-70BI TSOP-2 6*8mm TF-BGA 100 IC62LV25616LL-100T IC62LV25616LL-100B TSOP-2 6*8mm TF-BGA 100 IC62LV25616LL-100TI IC62LV25616LL-100BI TSOP-2 6*8mm TF-BGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. LPSR013-0D 10/11/2002 11