ISL6545, ISL6545A ® Data Sheet April 29, 2010 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller The ISL6545 makes simple work out of implementing a complete control and protection scheme for a DC/DC stepdown converter driving N-Channel MOSFETs in a synchronous buck topology. Since it can work with either 5V or 12V supplies, this one IC can be used in a wide variety of applications within a system. The ISL6545 integrates the control, gate drivers, output adjustment, monitoring and protection functions into a single 8 Ld SOIC or 10 Ld DFN package. The ISL6545 provides single feedback loop, voltage-mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.6V, with a maximum tolerance of ±1.0% over-temperature and line voltage variations. A selectable fixed frequency oscillator (ISL6545 for 300kHz; ISL6545A for 600kHz) reduces design complexity, while balancing typical application cost and efficiency. The error amplifier features a 20MHz gain-bandwidth product and 9V/µs slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. Protection from overcurrent conditions is provided by monitoring the rDS(ON) of the lower MOSFET to inhibit PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. FN6305.5 Features • Operates from +5V or +12V Supply Voltage (for bias) - 1.0V to 12V VIN Input Range (up to 20V possible with restrictions; see Input Voltage Considerations) - 0.6V to VIN Output Range - Integrated Gate Drivers use VCC (5V to 12V) - 0.6V Internal Reference; ±1.0% tolerance • Simple Single-Loop Control Design - Voltage-Mode PWM Control - Drives N-Channel MOSFETs - Traditional Dual Edge Modulator • Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle • Lossless, Programmable Overcurrent Protection - Uses Lower MOSFET’s rDS(ON) • Small Converter Size in 8 Ld SOIC or 10 Ld DFN - 300kHz or 600kHz Fixed Frequency Oscillator - Fixed Internal Soft-Start, Capable into a Pre-biased Load - Integrated Boot Diode - Enable/Shutdown Function on COMP/SD Pin - Output Current Sourcing and Sinking • Pb-Free (RoHS Compliant) Applications Pinout • Power Supplies for Microprocessors or Peripherals - PCs, Embedded Controllers, Memory Supplies - DSP and Core Communications Processor Supplies ISL6545 (8 LD SOIC) TOP VIEW 8 PHASE BOOT 1 7 COMP/SD UGATE 2 6 FB GND 3 5 VCC LGATE/OCSET 4 • Subsystem Power Supplies - PCI, AGP; Graphics Cards; Digital TV - SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus Termination Supply • Cable Modems, Set Top Boxes, and DSL Modems ISL6545 (10 LD 3x3 DFN) TOP VIEW 1 BOOT UGATE 2 N/C 3 GND 4 LGATE/OCSET 5 • Industrial Power Supplies; General Purpose Supplies • 5V or 12V-Input DC/DC Regulators 10 PHASE 9 COMP/SD GND 8 • Low-Voltage Distributed Power Supplies FB 7 N/C 6 VCC 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006, 2007, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6545, ISL6545A Ordering Information * PART NUMBER (Note) PART MARKING FIXED FREQUENCY OSCILLATOR (kHz) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL6545CBZ* 6545 CBZ 300 0 to +70 8 Ld SOIC M8.15 ISL6545ACBZ* 6545 ACBZ 600 0 to +70 8 Ld SOIC M8.15 ISL6545IBZ* 6545 IBZ 300 -40 to +85 8 Ld SOIC M8.15 ISL6545AIBZ* 6545 AIBZ 600 -40 to +85 8 Ld SOIC M8.15 ISL6545CRZ* 545Z 300 0 to +70 10 Ld DFN L10.3x3C ISL6545ACRZ* 45AZ 600 0 to +70 10 Ld DFN L10.3x3C ISL6545IRZ* 45IZ 300 -40 to +85 10 Ld DFN L10.3x3C ISL6545AIRZ* 5ARZ 600 -40 to +85 10 Ld DFN L10.3x3C *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6305.5 April 29, 2010 ISL6545, ISL6545A Block Diagram VCC DBOOT + - SAMPLE AND HOLD INTERNAL REGULATOR POR AND SOFT-START OC COMPARATOR BOOT UGATE 5V int. 21.5µA 20kΩ ERROR AMP TO LGATE/OCSET 0.6V PWM COMPARATOR + - PHASE INHIBIT GATE CONTROL PWM LOGIC + - FB VCC DIS 5V int. 0.4V LGATE/OCSET DIS + - OSCILLATOR 20μA COMP/SD FIXED 300 (or 600)kHz GND Typical Application VCC 5V or 12V VIN 1V TO 12V CHF VCC CDCPL COMP/SD 5 1 ISL6545 2 CI ROFFSET 3 8 7 RF CF CBULK BOOT CBOOT PHASE UGATE LOUT +VO LGATE/OCSET 6 FB Type II compensation shown 4 3 GND COUT ROCSET RS FN6305.5 April 29, 2010 ISL6545, ISL6545A Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V BOOT Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 36V UGATE Voltage VUGATE . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V LGATE/OCSET Voltage, VLGATE/OCSET GND - 0.3V to VCC + 0.3V PHASE Voltage, VPHASE . . . . . . . . . .GND - 0.3V to VBOOT + 0.3V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . .15V Clamp Voltage, VBOOT - VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .24V FB, COMP/SD Voltage. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV Thermal Resistance θJA (°C/W) θJC (°C/W) SOIC Package (Note 1) . . . . . . . . . . . . 95 N/A DFN Package (Notes 2, 3) . . . . . . . . . . 44 5.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Supply Voltage, VCC . . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V Ambient Temperature Range ISL6545C, ISL6545AC . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6545I, ISL6545AI . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air, with “direct attach” features. See Tech Brief TB379 for details. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 4. Limits should be considered typical and are not production tested. Electrical Specifications Test Conditions: VCC = 12V, TJ = 0 to +85°C, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 4 5.2 7 mA 3.9 4.1 4.3 V 0.30 0.35 0.40 V ISL6545C 270 300 330 kHz ISL6545I 240 300 330 kHz ISL6545AC 540 600 660 kHz ISL6545AI 510 600 660 kHz VCC SUPPLY CURRENT Input Bias Supply Current IVCC VCC = 12V; disabled POWER-ON RESET Rising VCC POR Threshold VPOR VCC POR Threshold Hysteresis OSCILLATOR Switching Frequency fOSC fOSC ΔVOSC Ramp Amplitude (Note 4) 1.5 VP-P REFERENCE Reference Voltage Tolerance Nominal Reference Voltage ISL6545C -1.0 - +1.0 % ISL6545I -1.5 - +1.5 % 0.600 VREF V ERROR AMPLIFIER DC Gain (Note 4) Gain-Bandwidth Product (Note 4) Slew Rate (Note 4) GAIN 96 dB GBWP 20 MHz SR 9 V/µs 3.0 Ω GATE DRIVERS Upper Gate Source Impedance RUG-SRCh 4 VCC = 14.5V; I = 50mA FN6305.5 April 29, 2010 ISL6545, ISL6545A Electrical Specifications Test Conditions: VCC = 12V, TJ = 0 to +85°C, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Upper Gate Sink Impedance RUG-SNKh VCC = 14.5V; I = 50mA 2.7 Ω Lower Gate Source Impedance RLG-SRCh VCC = 14.5V; I = 50mA 2.4 Ω Lower Gate Sink Impedance RLG-SNKh VCC = 14.5V; I = 50mA 2.0 Ω Upper Gate Source Impedance RUG-SRCl VCC = 4.25V; I = 50mA 3.5 Ω Upper Gate Sink Impedance RUG-SNKl VCC = 4.25V; I = 50mA 2.7 Ω Lower Gate Source Impedance RLG-SRCl VCC = 4.25V; I = 50mA 2.75 Ω Lower Gate Sink Impedance RLG-SNKl VCC = 4.25V; I = 50mA 2.1 Ω PROTECTION/DISABLE OCSET Current Source IOCSET ISL6545C; LGATE/OCSET = 0V ISL6545I; LGATE/OCSET = 0V Disable Threshold (COMP/SD pin) VDISABLE Functional Pin Description (SOIC, DFN) VCC (SOIC Pin 5, DFN Pin 6) This pin provides the bias supply for the ISL6545, as well as the lower MOSFET’s gate, and the BOOT voltage for the upper MOSFET’s gate. An internal 5V regulator will supply bias if VCC rises above 6.5V (but the LGATE/OCSET and BOOT will still be sourced by VCC). Connect a welldecoupled 5V or 12V supply to this pin. FB (SOIC Pin 6, DFN Pin 8) This pin is the inverting input of the internal error amplifier. Use FB, in combination with the COMP/SD pin, to compensate the voltage-control feedback loop of the converter. A resistor divider from the output to GND is used to set the regulation voltage. GND (SOIC Pin 3, DFN Pin 4) This pin represents the signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available. For the DFN package, Pin 4 MUST be connected for electrical GND; the metal pad under the package should also be connected to the GND plane for thermal conductivity. PHASE (SOIC Pin 8, DFN Pin 10) Connect this pin to the source of the upper MOSFET, and the drain of the lower MOSFET. It is used as the sink for the UGATE driver, and to monitor the voltage drop across the lower MOSFET for overcurrent protection. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. UGATE (SOIC Pin 2, DFN Pin 2) Connect this pin to the gate of upper MOSFET; it provides the PWM-controlled gate drive. It is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. 5 19.5 21.5 23.5 µA 18.0 21.5 23.5 µA 0.375 0.400 0.425 V BOOT (SOIC Pin 1, DFN Pin 1) This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive an N-channel MOSFET (equal to VCC minus the on-chip BOOT diode voltage drop), with respect to PHASE. COMP/SD (SOIC Pin 7, DFN Pin 9) This is a multiplexed pin. During soft-start and normal converter operation, this pin represents the output of the error amplifier. Use COMP/SD, in combination with the FB pin, to compensate the voltage-control feedback loop of the converter. Pulling COMP/SD low (VDISABLE = 0.4V nominal) will shut-down (disable) the controller, which causes the oscillator to stop, the LGATE and UGATE outputs to be held low, and the soft-start circuitry to re-arm. The external pull-down device will initially need to overcome up to 5mA of COMP/SD output current. However, once the IC is disabled, the COMP output will also be disabled, so only a 20µA current source will continue to draw current. When the pull-down device is released, the COMP/SD pin will start to rise, at a rate determined by the 20µA charging up the capacitance on the COMP/SD pin. When the COMP/SD pin rises above the VDISABLE trip point, the ISL6545 will begin a new Initialization and soft-start cycle. LGATE/OCSET (SOIC Pin 4, DFN Pin 5) Connect this pin to the gate of the lower MOSFET; it provides the PWM-controlled gate drive (from VCC). This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. During a short period of time following Power-On Reset (POR) or shut-down release, this pin is also used to determine the overcurrent threshold of the converter. Connect a resistor (ROCSET) from this pin to GND. See “Overcurrent Protection (OCP)” on page 7 for equations. An overcurrent trip cycles the soft-start function, after two dummy soft-start time-outs. Some of the text describing the FN6305.5 April 29, 2010 ISL6545, ISL6545A LGATE function may leave off the OCSET part of the name, when it is not relevant to the discussion. N/C (DFN only; Pin 3, Pin 7) These two pins in the DFN package are No Connect. Functional Description the higher overcurrent setting). The sample and hold uses a digital counter and DAC to save the voltage, so the stored value does not degrade, for as long as the VCC is above VPOR. See “Overcurrent Protection (OCP)” on page 7 for more details on the equations and variables. Upon the completion of sample and hold at t3, the soft-start operation is initiated, and the output voltage ramps up between t4 and t5. Initialization (POR and OCP sampling) Figure 1 shows a simplified timing diagram. The Power-On-Reset (POR) function continually monitors the bias voltage at the VCC pin. Once the rising POR threshold is exceeded (VPOR ~4V nominal), the POR function initiates the Overcurrent Protection (OCP) sample and hold operation (while COMP/SD is ~1V). When the sampling is complete, VOUT begins the soft-start ramp. LGATE STARTS SWITCHING COMP/SD (0.25V/DIV) 0.4V If the COMP/SD pin is held low during power-up, that will just delay the initialization until it is released, and the COMP/SD voltage is above the VDISABLE trip point. (0.5V/DIV) GND> VCC (2V/DIV) VOUT LGATE/OCSET (0.25V/DIV) 3.4ms t0 t1 3.4ms 0 - 3.4ms t2 6.8ms t3 t4 t5 FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION Soft-Start and Pre-Biased Outputs ~4V POR VOUT (1V/DIV) COMP/SD (1V/DIV) GND> FIGURE 1. POR AND SOFT-START OPERATION Figure 2 shows a typical power-up sequence in more detail. The initialization starts at T0, when either VCC rises above VPOR, or the COMP/SD pin is released (after POR). The COMP/SD will be pulled up by an internal 20µA current source, but the timing will not begin until the COMP/SD exceeds the VDISABLE trip point (at t1). The external capacitance of the disabling device, as well as the compensation capacitors, will determine how quickly the 20µA current source will charge the COMP/SD pin. With typical values, it should add a small delay compared to the soft-start times. The COMP/SD will continue to ramp to ~1V. From t1, there is a nominal 6.8ms delay, which allows the VCC pin to exceed 6.5V (if rising up towards 12V), so that the internal bias regulator can turn on cleanly. At the same time, the LGATE/OCSET pin is initialized, by disabling the LGATE driver and drawing IOCSET (nominal 21.5µA) through ROCSET. This sets up a voltage that will represent the OCSET trip point. At t2, there is a variable time period for the OCP sample and hold operation (0ms to 3.4ms nominal; the longer time occurs with 6 Functionally, the soft-start internally ramps the reference on the non-inverting terminal of the error amp from 0V to 0.6V in a nominal 6.8ms The output voltage will thus follow the ramp, from zero to final value, in the same 6.8ms (the actual ramp seen on the VOUT will be less than the nominal time, due to some initialization timing, between t3 and t4). The ramp is created digitally, so there will be 64 small discrete steps. There is no simple way to change this ramp rate externally, and it is the same for either frequency version of the IC (300kHz or 600kHz). After an initialization period (t3 to t4), the error amplifier (COMP/SD pin) is enabled, and begins to regulate the converter’s output voltage during soft-start. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitors. When the internally generated soft-start voltage exceeds the reference voltage (0.6V), the soft-start is complete, and the output should be in regulation at the expected voltage. This method provides a rapid and controlled output voltage rise; there is no large inrush current charging the output capacitors. The entire start-up sequence from POR typically takes up to 17ms; up to 10.2ms for the delay and OCP sample, and 6.8ms for the soft-start ramp. Figure 3 shows the normal curve in blue; initialization begins at t0, and the output ramps between t1 and t2. If the output is pre-biased to a voltage less than the expected value, as shown by the magenta curve, the ISL6545 will detect that condition. Neither MOSFET will turn on until the soft-start FN6305.5 April 29, 2010 ISL6545, ISL6545A ramp voltage exceeds the output; VOUT starts seamlessly ramping from there. If the output is pre-biased to a voltage above the expected value, as in the red curve, neither MOSFET will turn on until the end of the soft-start, at which time it will pull the output voltage down to the final value. Any resistive load connected to the output will help pull down the voltage (at the RC rate of the R of the load and the C of the output capacitance). VOUT OVERCHARGED VOUT NORMAL t0 Following POR (and 6.8ms delay), the ISL6545 initiates the Overcurrent Protection sample and hold operation. The LGATE driver is disabled to allow an internal 21.5µA current source to develop a voltage across ROCSET. The ISL6545 samples this voltage (which is referenced to the GND pin) at the LGATE/OCSET pin, and holds it in a counter and DAC combination. This sampled voltage is held internally as the Overcurrent Set Point, for as long as power is applied, or until a new sample is taken after coming out of a shut-down. The actual monitoring of the lower MOSFET’s on-resistance starts 200ns (nominal) after the edge of the internal PWM logic signal (that creates the rising external LGATE signal). This is done to allow the gate transition noise and ringing on the PHASE pin to settle out before monitoring. The monitoring ends when the internal PWM edge (and thus LGATE) goes low. The OCP can be detected anywhere within the above window. VOUT PRE-BIASED GND> time-outs, then up to one real one) to provide fault protection. If the shorted condition is not removed, this cycle will continue indefinitely. t1 t2 FIGURE 3. SOFT-START WITH PRE-BIAS If the VIN to the upper MOSFET drain is from a different supply that comes up after VCC, the soft-start would go through its cycle, but with no output voltage ramp. When VIN turns on, the output would follow the ramp of the VIN (at close to 100% duty cycle, with COMP/SD pin >4V), from zero up to the final expected voltage. If VIN is too fast, there may be excessive inrush current charging the output capacitors (only the beginning of the ramp, from zero to VOUT matters here). If this is not acceptable, then consider changing the sequencing of the power supplies, or sharing the same supply, or adding sequencing logic to the COMP/SD pin to delay the soft-start until the VIN supply is ready (see “Input Voltage Considerations” on page 9). If the IC is disabled after soft-start (by pulling COMP/SD pin low), and then enabled (by releasing the COMP/SD pin), then the full initialization (including OCP sample) will take place. However, that there is no new OCP sampling during overcurrent retries. If the regulator is running at high UGATE duty cycles (around 75% for 600kHz or 87% for 300kHz operation), then the LGATE pulse width may not be wide enough for the OCP to properly sample the rDS(ON). For those cases, if the LGATE is too narrow (or not there at all) for 3 consecutive pulses, then the third pulse will be stretched and/or inserted to the 425ns minimum width. This allows for OCP monitoring every third pulse under this condition. This can introduce a small pulse-width error on the output voltage, which will be corrected on the next pulse; and the output ripple voltage will have an unusual 3-clock pattern, which may look like jitter. This is not necessarily a problem; it is more of a compromise to maintain OCP at the higher duty cycles. If the OCP is disabled (by choosing a too-high value of ROCSET, or no resistor at all), then the pulse stretching feature is also disabled. Figure 4 illustrates the LGATE pulse width stretching, as the width gets smaller. > 425 ns = 425 ns If the output is shorted to GND during soft-start, the OCP will handle it, as described in the next section. Overcurrent Protection (OCP) The overcurrent function protects the converter from a shorted output by using the lower MOSFET’s on-resistance, rDS(ON), to monitor the current. A resistor (ROCSET) programs the overcurrent trip level (see “Typical Application” on page 3). This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. If overcurrent is detected, the output immediately shuts off, it cycles the soft-start function in a hiccup mode (2 dummy soft-start 7 < 425 ns << 425 ns FIGURE 4. LGATE PULSE STRETCHING FN6305.5 April 29, 2010 ISL6545, ISL6545A The overcurrent function will trip at a peak inductor current (IPEAK) determined by Equation 1: 2 × I OCSET xR OCSET I PEAK = ---------------------------------------------------------r DS ( ON ) (EQ. 1) where IOCSET is the internal OCSET current source (21.5µA typical). The scale factor of 2 doubles the trip point of the MOSFET voltage drop, compared to the setting on the ROCSET resistor. The OC trip point varies in a system mainly due to the MOSFET’s rDS(ON) variations (over process, current and temperature). To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from Equation 1 with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. ( ΔI ) 3. Determine IPEAK for I PEAK > I OUT ( MAX ) + ---------- , 2 where ΔI is the output inductor ripple current. For an equation for the ripple current see “Output Inductor Selection” on page 12. The range of allowable voltages detected (2*IOCSET*ROCSET) is 0mV to 475mV; but the practical range for typical MOSFETs is typically in the 20mV to 120mV ballpark (500Ω to 3000Ω). If the voltage drop across ROCSET is set too low, that can cause almost continuous OCP tripping and retry. It would also be very sensitive to system noise and inrush current spikes, so it should be avoided. The maximum usable setting is around 0.2V across ROCSET (0.4V across the MOSFET); values above that might disable the protection. Any voltage drop across ROCSET that is greater than 0.3V (0.6V MOSFET trip point) will disable the OCP. The preferred method to disable OCP is simply to remove the resistor; that will be detected that as no OCP. INTERNAL SOFT-START RAMP VOUT (0.5V/DIV) GND> 6.8ms t0 6.8ms t1 0ms to 6.8m t2 6.8ms t0 t1 FIGURE 5. OVERCURRENT RETRY OPERATION Figure 5 shows the output response during a retry of an output shorted to GND. At time t0, the output has been turned off, due to sensing an overcurrent condition. There are two internal soft-start delay cycles (t1 and t2) to allow the MOSFETs to cool down, to keep the average power dissipation in retry at an acceptable level. At time t2, the output starts a normal soft-start cycle, and the output tries to ramp. If the short is still applied, and the current reaches the OCSET trip point any time during soft-start ramp period, the output will shut off, and return to time t0 for another delay cycle. The retry period is thus two dummy soft-start cycles plus one variable one (which depends on how long it takes to trip the sensor each time). Figure 5 shows an example where the output gets about half-way up before shutting down; therefore, the retry (or hiccup) time will be around 17ms. The minimum should be nominally 13.6ms and the maximum 20.4ms. If the short condition is finally removed, the output should ramp up normally on the next t2 cycle. Note that conditions during power-up or during a retry may look different than normal operation. During power-up in a 12V system, the IC starts operation just above 4V; if the supply ramp is slow, the soft-start ramp might be over well before 12V is reached. So with lower gate drive voltages, the rDS(ON) of the MOSFETs will be higher during power-up, effectively lowering the OCP trip. In addition, the ripple current will likely be different at lower input voltage. Starting up into a shorted load looks the same as a retry into that same shorted load. In both cases, OCP is always enabled during soft-start; once it trips, it will go into retry (hiccup) mode. The retry cycle will always have two dummy time-outs, plus whatever fraction of the real soft-start time passes before the detection and shutoff; at that point, the logic immediately starts a new two dummy cycle time-out. Another factor is the digital nature of the soft-start ramp. On each discrete voltage step, there is in effect a small load transient, and a current spike to charge the output capacitors. The height of the current spike is not controlled; it is affected by the step size of the output, the value of the output capacitors, as well as the IC error amp compensation. So it is possible to trip the overcurrent with inrush current, in addition to the normal load and ripple considerations. The output voltage can be programmed to any level between the 0.6V internal reference, up to the VIN supply. The ISL6545 can run at near 100% duty cycle at zero load, but the rDS(ON) of the upper MOSFET will effectively limit it to something less as the load current increases. In addition, the OCP (if enabled) will also limit the maximum effective duty cycle. 8 Output Voltage Selection An external resistor divider is used to scale the output voltage relative to the internal reference voltage, and feed it back to the inverting input of the error amp. See “Typical FN6305.5 April 29, 2010 ISL6545, ISL6545A Application” on page 3 for more detail; RS is the upper resistor; ROFFSET (shortened to RO below) is the lower one. The recommended value for RS is 1kΩ to 5kΩ (±1% for accuracy) and then ROFFSET is chosen according to the equation below. Since RS is part of the compensation circuit (see Feedback Compensation section), it is often easier to change ROFFSET to change the output voltage; that way the compensation calculations do not need to be repeated. If VOUT = 0.6V, then ROFFSET can be left open. Output voltages less than 0.6V are not available as shown in Equation 2. ( RS + RO ) V OUT = 0.6V • --------------------------RO R S • 0.6V R O = ---------------------------------V OUT – 0.6V (EQ. 2) Input Voltage Considerations The Typical Application diagram on page 3 shows a standard configuration where VCC is either 5V (±10%) or 12V (±20%); in each case, the gate drivers use the VCC voltage for LGATE and BOOT/UGATE. In addition, VCC is allowed to work anywhere from 6.5V up to the 14.4V maximum. The VCC range between 5.5V and 6.5V is NOT allowed for long-term reliability reasons, but transitions through it to voltages above 6.5V are acceptable. There is an internal 5V regulator for bias; it turns on between 5.5V and 6.5V; some of the delay after POR is there to allow a typical power supply to ramp up past 6.5V before the soft-start ramps begins. This prevents a disturbance on the output, due to the internal regulator turning on or off. If the transition is slow (not a step change), the disturbance should be minimal. So while the recommendation is to not have the output enabled during the transition through this region, it may be acceptable. The user should monitor the output for their application, to see if there is any problem. The VIN to the upper MOSFET can share the same supply as VCC, but can also run off a separate supply or other sources, such as outputs of other regulators. If VCC powers up first, and the VIN is not present by the time the initialization is done, then the soft-start will not be able to ramp the output, and the output will later follow part of the VIN ramp when it is applied. If this is not desired, then change the sequencing of the supplies, or use the COMP/SD pin to disable VOUT until both supplies are ready. Figure 6 shows a simple sequencer for this situation. If VCC powers up first, Q1 will be off, and R3 pulling to VCC will turn Q2 on, keeping the ISL6545 in shut-down. When VIN turns on, the resistor divider R1 and R2 determines when Q1 turns on, which will turn off Q2, and release the shut-down. If VIN powers up first, Q1 will be on, turning Q2 off; so the ISL6545 will start-up as soon as VCC comes up. The VDISABLE trip point is 0.4V nominal, so a wide variety of NFET’s or NPN’s or even some logic IC’s can be used as Q1 or Q2; but Q2 must be low leakage when off (open-drain or open-collector) 9 so as not to interfere with the COMP output. Q2 should also be placed near the COMP/SD pin. VIN R1 VCC R3 R2 to COMP/SD Q1 Q2 FIGURE 6. SEQUENCER CIRCUIT The VIN range can be as low as ~1V (for VOUT as low as the 0.6V reference). It can be as high as 20V (for VOUT just below VIN). There are some restrictions for running high VIN voltage. The first consideration for high VIN is the maximum BOOT voltage of 36V. The VIN (as seen on PHASE) plus VCC (boot voltage - minus the diode drop), plus any ringing (or other transients) on the BOOT pin must be less than 36V. If VIN is 20V, that limits VCC plus ringing to 16V. The second consideration for high VIN is the maximum (BOOT - VCC) voltage; this must be less than 24V. Since BOOT = VIN + VCC + ringing, that reduces to (VIN + ringing) must be <24V. So based on typical circuits, a 20V maximum VIN is a good starting assumption; the user should verify the ringing in their particular application. Another consideration for high VIN is duty cycle. Very low duty cycles (such as 20V in to 1.0V out, for 5% duty cycle) require component selection compatible with that choice (such as low rDS(ON) lower MOSFET, and a good LC output filter). At the other extreme (for example, 20V in to 12V out), the upper MOSFET needs to be low rDS(ON). In addition, if the duty cycle gets too high, it can affect the overcurrent sample time. In all cases, the input and output capacitors and both MOSFETs must be rated for the voltages present. Switching Frequency The switching frequency is either a fixed 300kHz or 600kHz, depending on the part number chosen (ISL6545 is 300kHz; ISL6545A is 600kHz; the generic name “ISL6545” may apply to either in the rest of this document, except when choosing the frequency). However, all of the other timing mentioned (POR delay, OCP sample, soft-start, etc.) is independent of the clock frequency (unless otherwise noted). BOOT Refresh In the event that the UGATE is on for an extended period of time, the charge on the boot capacitor can start to sag, raising the rDS(ON) of the upper MOSFET. The ISL6545 has a circuit that detects a long UGATE on-time (nominal 100µs), and forces the LGATE to go high for one clock cycle, which will allow the boot capacitor some time to recharge. Separately, the OCP circuit has an LGATE pulse stretcher (to be sure the sample time is long enough), which can also FN6305.5 April 29, 2010 ISL6545, ISL6545A The ISL6545 incorporates a MOSFET shoot-through protection method which allows a converter to sink current as well as source current. Care should be exercised when designing a converter with the ISL6545 when it is known that the converter may sink current. When the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. This means that the converter is boosting current into the VCC rail, which supplies the bias voltage to the ISL6545. If there is nowhere for this current to go, such as to other distributed loads on the VCC rail, through a voltage limiting protection device, or other methods, the capacitance on the VCC bus will absorb the current. This situation will allow voltage level of the VCC rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the ISL6545, then the IC will experience an irreversible failure and the converter will no longer be operational. Ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. VIN ISL6545 Q1 LGATE/OCSET Q2 LO CIN VOUT CO LOAD UGATE PHASE +VIN BOOT Q1 CBOOT ISL6545 LO VOUT PHASE VCC +VCC LGATE/OCSET Q2 LOAD Current Sinking be located as close together as possible. Please note that the capacitors CIN and CO may each represent numerous physical capacitors. For best results, locate the ISL6545 within 1 inch of the MOSFETs, Q1 and Q2 . The circuit traces for the MOSFET gate and source connections from the ISL6545 must be sized to handle up to 1A peak current. ROCSET help refresh the boot. But if OCP is disabled (no current sense resistor), the regular boot refresh circuit will still be active. CO CVCC GND FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES Figure 8 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/SD pin and locate the resistor, ROSCET close to the COMP/SD pin because the internal current source is only 20µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation (not shown) should be located as close to the IC as practical. Feedback Compensation This section highlights the design consideration for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended, as shown in the top part of Figure 9. Figure 9 also highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the ISL6545 circuit. The output voltage (VOUT) is regulated to the reference voltage, VREF. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) modified sawtooth wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank’s equivalent series resistance is represented by the series resistor E. RETURN FIGURE 7. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS Figure 7 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown should 10 FN6305.5 April 29, 2010 ISL6545, ISL6545A V OSC ⋅ R1 ⋅ F 0 R2 = --------------------------------------------d MAX ⋅ V IN ⋅ F LC C2 COMP R2 C3 R3 C1 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC). E/A R1 FB + Ro 1 C1 = ----------------------------------------------2π ⋅ R2 ⋅ 0.5 ⋅ F LC VREF VOUT OSCILLATOR VIN PWM CIRCUIT VOSC UGATE HALF-BRIDGE DRIVE L D PHASE LGATE ISL6545 C E The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis, L and D represent the channel inductance and its DCR, while C and E represent the total output capacitance and its equivalent series resistance. 1 F CE = -----------------------2π ⋅ C ⋅ E (EQ. 3) The compensation network consists of the error amplifier (internal to the ISL6545) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45°). Phase margin is the difference between the closed loop phase at F0dB and 180°. The equations that follow relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 9. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate value for R2 for desired converter bandwidth (F0). If setting the output voltage via an offset resistor connected to the FB pin, Ro in Figure 9, the design procedure can be followed as presented. 11 (EQ. 5) 3. Calculate C2 such that FP1 is placed at FCE. C1 C2 = --------------------------------------------------------2π ⋅ R2 ⋅ C1 ⋅ F CE – 1 (EQ. 6) 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. R1 R3 = ---------------------F SW ------------ – 1 F LC EXTERNAL CIRCUIT FIGURE 9. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN 1 F LC = --------------------------2π ⋅ L ⋅ C (EQ. 4) 1 C3 = ------------------------------------------------2π ⋅ R3 ⋅ 0.7 ⋅ F SW (EQ. 7) It is recommended a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The equations shown in Equations 8 and 9 describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): d MAX ⋅ V IN 1 + s(f) ⋅ E ⋅ C G MOD ( f ) = ----------------------------- ⋅ ---------------------------------------------------------------------------------------2 V OSC 1 + s(f) ⋅ (E + D) ⋅ C + s (f) ⋅ L ⋅ C 1 + s ( f ) ⋅ R2 ⋅ C1 G FB ( f ) = ----------------------------------------------------- ⋅ s ( f ) ⋅ R1 ⋅ ( C1 + C2 ) (EQ. 8) 1 + s ( f ) ⋅ ( R1 + R3 ) ⋅ C3 ⋅ ---------------------------------------------------------------------------------------------------------------------------C1 ⋅ C2 ( 1 + s ( f ) ⋅ R3 ⋅ C3 ) ⋅ ⎛ 1 + s ( f ) ⋅ R2 ⋅ ⎛ ----------------------⎞ ⎞ ⎝ ⎝ C1 + C2⎠ ⎠ G CL ( f ) = G MOD ( f ) ⋅ G FB ( f ) where, s ( f ) = 2π ⋅ f ⋅ j COMPENSATION BREAK FREQUENCY EQUATIONS 1 F Z1 = -------------------------------2π ⋅ R2 ⋅ C1 1 F Z2 = --------------------------------------------------2π ⋅ ( R1 + R3 ) ⋅ C3 1 F P1 = ---------------------------------------------C1 ⋅ C2 2π ⋅ R2 ⋅ ---------------------C1 + C2 (EQ. 9) 1 F P2 = ------------------------------2π ⋅ R3 ⋅ C3 FN6305.5 April 29, 2010 ISL6545, ISL6545A Figure 10 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the loglog graph of Figure 10 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. FP1 FP2 GAIN FZ1 FZ2 R2 20 log ⎛ -------⎞ ⎝ R1⎠ MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN d MAX ⋅ V IN 20 log --------------------------------V OSC 0 GFB LOG GCL GMOD LOG FLC FCE F0 FREQUENCY FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, FSW. This is just one method to calculate compensation components; there are variations of the above equations. The error amp is similar to that on other Intersil regulators, so existing tools can be used here as well. Special consideration is needed if the size of a ceramic output capacitance in parallel with bulk capacitors gets too large; the calculation needs to model them both separately (attempting to combine two different capacitors types into one composite component model may not work properly; a special tool may be needed; contact your local Intersil person for assistance). Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. 12 The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the equations shown in Equation 10: ΔI = VIN - VOUT Fsw x L x VOUT VIN ΔVOUT = ΔI x ESR (EQ. 10) Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6545 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. FN6305.5 April 29, 2010 ISL6545, ISL6545A Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The equations in Equation 11 give the approximate response time interval for application and removal of a transient load: tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT (EQ. 11) where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2 . The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25x greater than the maximum input voltage and a voltage rating of 1.5x is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. MOSFET Selection/Considerations The ISL6545 requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the 13 switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see the equations in Equation 12). These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower MOSFET’s body diode. The gate-charge losses are dissipated by the ISL6545 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Losses while Sourcing Current 2 1 P UPPER = Io × r DS ( ON ) × D + -- ⋅ Io × V IN × t SW × F S 2 PLOWER = Io2 x rDS(ON) x (1 - D) Losses while Sinking Current (EQ. 12) PUPPER = Io2 x rDS(ON) x D 2 1 P LOWER = Io × r DS ( ON ) × ( 1 – D ) + --- ⋅ Io × V IN × t SW × F S 2 Where: D is the duty cycle = VOUT / VIN , tSW is the combined switch ON and OFF time, and FSW is the switching frequency. When operating with a 12V power supply for VCC (or down to a minimum supply voltage of 6.5V), a wide variety of N-MOSFETs can be used. Check the absolute maximum VGS rating for both MOSFETs; it needs to be above the highest VCC voltage allowed in the system; that usually means a 20V VGS rating (which typically correlates with a 30V VDS maximum rating). Low threshold transistors (around 1V or below) are not recommended, for the reasons explained in the next paragraph. For 5V only operation, given the reduced available gate bias voltage (5V), logic-level transistors should be used for both N-MOSFETs. Look for rDS(ON) ratings at 4.5V. Caution should be exercised with devices exhibiting very low VGS(ON) characteristics. The shoot-through protection present aboard the ISL6545 may be circumvented by these MOSFETs if they have large parasitic impedences and/or capacitances that would inhibit the gate of the MOSFET from being discharged below its threshold level before the complementary MOSFET is turned on. Also avoid MOSFETs with excessive switching times; the circuitry is expecting transitions to occur in under 50ns or so. FN6305.5 April 29, 2010 ISL6545, ISL6545A +VIN +VCC VCC + VD - BOOT CBOOT ISL6545 UGATE Q1 PHASE VG-S ≈ VCC - VD VCC Q2 - + LGATE/OCSET VG-S ≈ VCC GND FIGURE 11. UPPER GATE DRIVE BOOTSTRAP BOOTSTRAP Considerations Figure 11 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC . The boot capacitor, CBOOT, develops a floating supply voltage referenced to the PHASE pin. The supply is refreshed to a voltage of VCC less the boot diode drop (VD) each time the lower MOSFET, Q2 , turns on. Check that the voltage rating of the capacitor is above the maximum VCC voltage in the system; a 16V rating should be sufficient for a 12V system. A value of 0.1µF is typical for many systems driving single MOSFETs. If VCC is 12V, but VIN is lower (such as 5V), then another option is to connect the BOOT pin to 12V, and remove the BOOT cap (although, you may want to add a local cap from BOOT to GND). This will make the UGATE VGS voltage equal to (12V - 5V = 7V). That should be high enough to drive most MOSFETs, and low enough to improve the efficiency slightly. Do NOT leave the BOOT pin open, and try to get the same effect by driving BOOT through VCC and the internal diode; this path is not designed for the high current pulses that will result. For low VCC voltage applications where efficiency is very important, an external BOOT diode (in parallel with the internal one) may be considered. The external diode drop has to be lower than the internal one; the resulting higher VG-S of the upper FET will lower its rDS(ON). The modest gain in efficiency should be balanced against the extra cost and area of the external diode. 14 FN6305.5 April 29, 2010 ISL6545, ISL6545A Dual Flat No-Lead Plastic Package (DFN) L10.3x3C 2X 0.10 C A A 10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.10 C B E MAX NOTES A 0.85 0.90 0.95 - A1 - - 0.05 - A C SEATING PLANE D2 0.10 C D2 0.08 C 7 8 D2/2 1 0.20 0.25 0.30 5, 8 3.00 BSC 2.33 E E2 A3 SIDE VIEW (DATUM B) 0.20 REF D B // 2.38 2.43 7, 8 1.69 7, 8 3.00 BSC 1.59 e 1.64 - 0.50 BSC - k 0.20 - - - L 0.35 0.40 0.45 8 N 10 2 Nd 5 3 Rev. 1 4/06 2 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. NX k 2. N is the number of terminals. (DATUM A) 3. Nd refers to the number of terminals on D. E2 E2/2 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. NX L N N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B (A1) 9 L 5 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. CL NX (b) NOMINAL b TOP VIEW 8 MIN A3 6 INDEX AREA 6 INDEX AREA SYMBOL 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE 15 FN6305.5 April 29, 2010 ISL6545, ISL6545A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N a NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6305.5 April 29, 2010