Cypress CY2XP306BVXIT High-frequency programmable pecl clock generation module Datasheet

PRELIMINARY
CY2XP306
High-frequency Programmable PECL Clock Generation Module
Features
• 1–133 MHz Input Frequency Range
• 62.5–500 MHz Output Frequency Range
• 60 ps typical Cycle-to-Cycle Jitter
• 36-pin VFBGA, 6 × 8 × 1 mm
• 30 ps typical Output-Output Skew
• 3.3V operation
• Phase-locked loop (PLL) multiplier select
• Serially Configurable Multiply Ratios
• LVTTL or XO Input; Six LVPECL Outputs
• Selectable Output Divider (/2)
Block Diagram
QA1
FSELA
QA1#
QA2
0
PLL_MULT
QA2#
1
XIN/REF
XTAL
OSCILLATOR
XOUT
PLL
xM
QA3
/1
QA3#
/2
QB1
SER CLK
QB1#
0
QB2
SER DATA
MR
QB2#
1
QB3
QB3#
FSELB
Pin Configuration (Top View)
C Y 2 X P 3 0 6 3 6 V F B G A P IN C O N F IG U R A T IO N
QA1
Q A1#
Q A2
6
5
4
3
2
1
VDDA
GND
GND
SER_
DATA
XO UT
SER_
C LK
X IN
GND
VDDB
VDDB
A
B
Cypress Semiconductor Corporation
Document #: 38-07725 Rev. *A
T O P V IE W
Q A2#
Q A3
Q A3#
VDDA
QB3
VDDB
VDDA
Q B3#
VDDB
GND
GND
PLL_
M ULT
MR
FSELA
C
D
E
F
•
3901 North First Street
Q B1#
GND
Q B2
Q B2#
Q B1
•
FSELB
G
NC
VDDA
VDDA
H
San Jose, CA 95134
•
408-943-2600
Revised April 8, 2005
PRELIMINARY
CY2XP306
Pin Definitions
Pin #
Pin Name
Pin Description
A2
XIN/REF
A3
XOUT
Reference Crystal Feedback
Reference Crystal Input or LVTTL
B2,B5,C1,G2,G5,A4
GND
Ground
A5,H1,H2,H4,H5
VDDA
3.3V Power Supply
A1,B1,G3,G4
VDDB
3.3V Power Supply
A6
QA1
B6
QA1#
LVPECL Clock Output (Complement)
C6
QA2
LVPECL Clock Output
D6
QA2#
LVPECL Clock Output (Complement)
E6
QA3
LVPECL Clock Output
F6
QA3#
LVPECL Clock Output (Complement)
G6
QB1
LVPECL Clock Output
H6
QB1#
LVPECL Clock Output (Complement)
C4
QB2
LVPECL Clock Output
C3
QB2#
LVPECL Clock Output (Complement)
F4
QB3
LVPECL Clock Output
QB3#
LVPECL Clock Output (Complement)
F3
D1
LVPECL Clock Output
PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table
E1
MR
F1
FSELA
G1
FSELB
H3
NC
LVPECL Reset; Internal Pull-Down, see Function Table
LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table
LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table
No Connect
B4
SER_DATA Serial Interface Data
B3
SER_CLK Serial Interface Clock
Table 1. Frequency Table
PLL_Mult
M (PLL Multiplier)
0
x16
1
x8
Example Input Frequency
Example PLL Output Frequency
19.44 MHz
311.04 MHz
19.53 MHz
312.5 MHz
19.44 MHz
155.52 MHz
19.53 MHz
156.25 MHz
38.88 MHz
311.04 MHz
Table 2. Output Frequency Table
Control Pin
0
1
FSELA
QAx = PLL Output Frequency
QAx = PLL Output Frequency/2
FSELB
QBx = PLL Output Frequency
QBx = PLL Output Frequency/2
Control Pin
0
1
MR (Asynchronous)
Active
Reset (QX = Low, QX# = High)
Table 3. Function Table
Document #: 38-07725 Rev. *A
Page 2 of 9
PRELIMINARY
Two-Wire Serial Interface
Introduction
The CY2XP306 has a two-wire serial interface designed for
data transfer operations, and is used for programming the P
and Q values for frequency generation. Sclk is the serial clock
line controlled by the master device. Sdata is a serial bidirectional data line. The CY2XP306 is a slave device and can
either read or write information on the dataline upon request
from the master device.
Figure 1 shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled high by a pull-up resistor.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the Sdata from HIGH to LOW while the Sclk is at
HIGH. Similarly, stop (P) is defined as switching the Sdata from
LOW to HIGH while holding the Sclk HIGH. Between these two
signals, data on Sdata is synchronous with the clock on the Sclk.
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the Sdata LOW before the Sclk rising edge and hold it
LOW until the Sclk falling edge.
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is one byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2 shows the serial interface transfer format used with
the CY2XP306. Two dummy bytes must be transferred before
the first data byte. The CY2XP306 has only three bytes of
latches to store information, and the third byte of data is
reserved. Extra data will be ignored.
V DD
Rp
Rp
S d a ta
S clk
CY2XP306
S d ata _ C
S d ata _ C
S c lk _ C
S d ata _ in
S clk _ in
S d ata _ in
S clk _ in
M a s te r D e vic e
S lav e D ev ice
Figure 1. Device Connections
S clk
S data
Start (S)
valid data
Stop (P)
Acknowledge
Figure 2. Serial Interface Specifications
1 bit
7 bits
S
Slave Address
Data 1
8 bits
Ack
1 bit
R/W
1 bit
Ack
8 bits
Dummy Byte 0
1 bit
8 bits
1 bit
Ack Dummy Byte 1 Ack
8 bits
Data 0
1 bit
Ack
P
1 bit
Figure 3. CY2XP306 Transfer Format
Document #: 38-07725 Rev. *A
Page 3 of 9
PRELIMINARY
CY2XP306
Serial Interface Address for the CY2XP306
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
0
1
0
1
0
Serial Interface Programming for the CY2XP306
Data0
b7
b6
b5
b4
b3
b2
b1
b0
QCNTBYP
SELPQ
Q<5>
Q<4>
Q<3>
Q<2>
Q<1>
Q<0>
Data1
P<7>
P<6>
P<5>
P<4>
P<3>
P<2>
P<1>
P<0>
Data2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
To program the CY2XP306 using the two-wire serial interface,
set the SELPQ bit HIGH. The default setting of this bit is LOW.
The P and Q values are determined by the following formulas:
Pfinal = (P7..0 + 3) * 2
Qfinal = Q5..0 + 2.
If the SELPQ bit is set LOW, the PLL multipliers will be set
using the values in the Select Function Table.
CyberClocks™ has been developed to generate P and Q
values for stable PLL operation. This software is downloadable
from www.cypress.com.
PLL Frequency = Reference x P/Q = Output
If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value
of 1. The default setting of this bit is LOW.
Reference
Q
Φ
Output
VCO
P
PLL
Figure 4. PLL Block Diagram
Functional Specifications
the PLL. The PLL_MULT pin has an internal pull-up resistor.
The multiplier selection is given on Table 1, Frequency Table.
Crystal Input
The MR pin is a reset control pin. It has an internal pull-down
resistor. Please see Table 3 for detailed function.
The CY2XP306 receives its reference from an external
reference input or external crystal. Pin XIN is the reference
crystal input, and pin XOUT is the reference crystal feedback.
The oscillator circuit requires external capacitors. Please refer
to the application note entitled Crystal Oscillator Topics for
details.
Select Input
There are four select input pins, the PLL_MULT, MR, FSELA
and FSELB. PLL_MULT pin selects the frequency multiplier in
The FSELA and FSELB pins are output dividers select pins,
see Table 2 for Output Frequency Table.
All of these four select pins are standard LVCMOS inputs.
State Transition Characteristics
Specifies the maximum settling time of the QA and QB bank
outputs from device power-up. For VDD, any sequences are
allowed to power-up and power-down the CY2XP306.
Table 4. State Transition Characteristics Table
From
VDD On
Transition
Latency
To
QA/QB Outputs Normal
3 ms
Description
Time from VDD is applied and settled to outputs settled.
Table 5. Operating Ambient Temperature
Parameter
TA
Description
Commercial Temperature
Industrial Temperature
Document #: 38-07725 Rev. *A
Min.
Max.
Unit
0
70
°C
–40
85
°C
Page 4 of 9
PRELIMINARY
CY2XP306
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Supply Voltage
Non-functional
–0.3
4.6
V
VDD
Operating Voltage
Functional
3.135
3.465
V
VTT
Output Termination Voltage
Relative to VDD[1]
VIN
Input Voltage
Relative to VDD[1]
–0.3
VDD + 0.3
V
VOUT
Output Voltage
Relative to VDD[1]
–0.3
LUI
Latch Up Immunity
Functional
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Non-functional
ØJc
Dissipation, Junction to Case
Functional
ØJa
Dissipation, Junction to Ambient
Functional
ESDh
ESD Protection (Human Body Model)
MSL
Moisture Sensitivity Level
Crystal Requirements
Requirements to use parallel mode fundamental xtal. External
capacitors are required in the crystal oscillator circuit. Please
VDD – 2
V
VDD + 0.3
V
100
–
mA
150
°C
11.48
°C/W
85.8
°C/W
2000
V
3
N.A.
refer to the application note entitled Crystal Oscillator Topics
for details.
Crystal Requirements
Parameter
XF
Description
Frequency
Min.
Max.
Unit
10
31.25
MHz
Min.
Max.
Unit
DC Specifications (VDD = 3.3 V ± 5%, Commercial and Industrial Temperature)
Parameter
Description
VDD
Supply voltage
3.135
3.465
V
VIL1
Input signal low voltage at pin PLL_MULT
–
0.35
VDD
VIH1
Input signal high voltage at pin PLL_MULT
0.65
–
VDD
VIL2
Input signal low voltage at pins REF
–
0.8
V
VIH2
Input signal high voltage at pins REF
2.0
–
VIL3
LVPECL input signal low voltage at pins MR, FSELA, FSELB
VIH3
VDD – 1.945 VDD – 1.625[3]
LVPECL input signal high voltage at pins MR, FSELA, FSELB VDD – 1.165[3] VDD – 0.88
RPUP
Internal pull-up resistance
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
IEE
Maximum Quiescent Supply Current without Output Termination Current
VOL
LVPECL Output Low Voltage
VDD = 3.3V ± 5%
VOH
LVPECL Output High Voltage
V
V
V
10
100
kΩ
0.05
500
ms
–
150
mA
IOL = –5 mA[2]
VDD – 1.995
VDD – 1.5
V
IOH = –30 mA[2]
VDD – 1.25
VDD – 0.7
V
Note:
1. Where VDD is 3.3V±5%
2. Equivalent to a termination of 50Ω to VTT.
3. VIL3 will operate down to GND; VIH3 will operate up to VDD.
Document #: 38-07725 Rev. *A
Page 5 of 9
PRELIMINARY
CY2XP306
AC Specifications (VDD = 3.3 V ± 5%, Commercial and Industrial Temperature)
Parameter
Description
Conditions
Min.
Limited by Max PLL Frequency
Typ.
Max.
Unit
133
MHz
fIN
Input frequency
1
–
fXTALIN
Crystal Input frequency
10
–
CIN,CMOS
Input capacitance at PLL_MULT
pin[4]
–
–
10
pF
fO
Output Frequency
125
–
500
MHz
Vo(P-P)
Differential output voltage
(peak-to-peak)
0.5
–
–
V
VCMRO
Output Common Voltage Range Typical
tsk(O)
Output-to-output skew
311 MHz 50% duty cycle Standard load Differential
Operation
tsk(PP)
Part-to-part output skew
311 MHz 50% duty cycle Standard load Differential
Operation
TR,TF
Output Rise / Fall time
311 MHz 50% duty cycle Differential (20% to 80%)
DC
Long-term average output duty
cycle
JC2C
Cycle-to-cycle Jitter (Peak)
peak; 311 MHz; Jitter Defined by JESD65B
tr, tf,
2 0 -8 0 %
31.25 MHz
VDD – 1.425
V
–
30
TBD
ps
–
–
150
ps
–
–
0.3
ns
45
–
55
%
–
60
TBD
ps
VO
Figure 5. LVPECL Output
Notes:
4. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
Document #: 38-07725 Rev. *A
Page 6 of 9
PRELIMINARY
CY2XP306
Test Configurations
Standard test load using a differential pulse generator and
differential measurement instrument.
DUT
VTT
RT = 50 ohm
Pulse
Generator
Z = 50 ohm
5"
PLL
Zo = 50 ohm
5"
RT = 50 ohm
VTT
Figure 6. CY2XP306 AC Test Reference. One output LVPECL pair is shown for clarity.
Applications Information
Termination Example
Vdd - 2V
Vdd
R T = 50 ohm
Zo = 50 ohm
REF
R T = 50 ohm
Vdd - 2 V
GND
Figure 7. Standard LVPECL–PECL Output Termination. One output is shown for clarity.
Ordering Information
Ordering Code
Package Type
Operating Range
Operating Voltage
CY2XP306BVXI
36-lead VFBGA
Industrial Temp
3.3V
CY2XP306BVXIT
36-lead VFBGA - Tape and Reel
Industrial Temp
3.3V
Lead Free
Document #: 38-07725 Rev. *A
Page 7 of 9
PRELIMINARY
CY2XP306
Package Drawing and Dimensions
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
2
3
4
5
6
6
5
4
3
2
1
A
B
C
C
E
F
G
D
E
F
2.625
8.00±0.10
D
0.75
A
B
5.25
8.00±0.10
1
Ø0.30±0.05(36X)
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.15 C
0.21±0.05
0.25 C
0.55 MAX.
B
0.15(4X)
51-85149-*B
1.00 MAX
0.26 MAX.
SEATING PLANE
C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07725 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY2XP306
Document History Page
Document Title: CY2XP306 High-frequency Programmable PECL Clock Generation Module
Document Number: 38-07725
REV. ECN NO. Issue Date
Orig. of
Change
Description of Change
**
312633
See ECN
RGL
New Data Sheet
*A
349137
See ECN
RGL
Data sheet re-write
Document #: 38-07725 Rev. *A
Page 9 of 9
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