Am79C961A
PCnet™-ISA II Jumperless, Full Duplex Single-Chip
Ethernet Controller for ISA
DISTINCTIVE CHARACTERISTICS
■ Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
■ Look Ahead Packet Processing (LAPP)
allows protocol analysis to begin before
end of receive frame
■ Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
■ Supports 4 DMA channels on chip
■ Supports full duplex operation on the
10BASE-T, AUI, and GPSI ports
■ Supports 16 boot PROM locations
■ Direct interface to the ISA or EISA bus
■ Pin compatible to Am79C961 PCnet-ISA+
Jumperless Single-Chip Ethernet Controller
■ Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
■ Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
■ Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
■ Supports 16 I/O locations
■ Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 2 modes of
port selection:
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
■ Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
■ Supports bus-master, programmed I/O, and
shared-memory architectures to fit in any PC
application
■ Supports edge and level-sensitive interrupts
— Automatic retransmission with no FIFO
reload
■ DMA Buffer Management Unit for reduced CPU
intervention which allows higher throughput by
by-passing the platform DMA
— Automatic receive stripping and transmit
padding (individually programmable)
■ JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
— Automatic runt packet rejection
■ Integrated Manchester Encoder/Decoder
— Automatic deletion of received collision
frames
■ Supports the following types of network
interfaces:
■ Dynamic transmit FCS generation
programmable on a frame-by-frame basis
■ Single +5 V power supply
■ Internal/external loopback capabilities
■ Supports 8K, 16K, 32K, and 64K Boot PROMs or
Flash for diskless node applications
■ Supports Microsoft’s Plug and Play System
configuration for jumperless designs
■ Supports staggered AT bus drive for reduced
noise and ground bounce
■ Integrated Magic Packet™ support for remote
wake up of Green PCs
■ Supports 8 interrupts on chip
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
■ Supports LANCE General Purpose Serial
Interface (GPSI)
■ 132-pin PQFP and 144-pin TQFP packages
■ Supports Shared Memory and PIO modes
■ Supports PCMCIA mode (144-TQFP version
only)
■ Support for operation in industrial temperature
range (–40°C to +85°C) available in both
packages
Publication# 19364 Rev: D Amendment/0
Issue Date: March 2000
GENERAL DESCRIPTION
The PCnet-ISA II controller, a single-chip Ethernet controller, is a highly integrated system solution for the
PC-AT Industry Standard Architecture (ISA) architecture. It is designed to provide flexibility and compatibility with any existing PC application. This highly
integrated VLSI device is specifically designed to reduce parts count and cost, and addresses applications
where higher system throughput is desired. The PCnet-ISA II controller is fabricated with AMD’s advanced
low-power CMOS process to provide low standby current for power sensitive applications.
The PCnet-ISA II controller can be configured into one
of three different architecture modes to suit a particular
PC application. In the Bus Master mode, all transfers
are performed using the integrated DMA controller.
This configuration enhances system performance by
allowing the PCnet-ISA II controller to bypass the platform DMA controller and directly address the full 24-bit
memory space. The implementation of Bus Master
mode allows minimum parts count for the majority of
PC applications. The PCnet-ISA II can also be configured as a Bus Slave with either a Shared Memory or
Programmed I/O architecture for compatibility with
low-end machines, such as PC/XTs that do not support
Bus Masters, and high-end machines that require local
packet buffering for increased system latency.
The PCnet-ISA II controller is designed to directly interface with the ISA or EISA system bus. It contains an
ISA Plug and Play bus interface unit, DMA Buffer Management Unit, 802.3 Media Access Control function,
individual 136-byte transmit and 128-byte receive
FIFOs, IEEE 802.3 defined Attachment Unit Interface
(AUI), and a Twisted Pair Transceiver Media Attachment Unit. Full duplex network operation can be
enabled on any of the device’s network ports. The PCnet-ISA II controller is also register compatible with the
LANCE (Am7990) Ethernet controller and PCnet-ISA
(Am79C960). The DMA Buffer Management Unit supports the LANCE descriptor software model. External
2
remote boot and Ethernet physical address PROMs
and Electrically Erasable Proms are also supported.
This advanced Ethernet controller has the built-in
capability of automatically selecting either the AUI port
or the Twisted Pair transceiver. Only one interface is
active at any one time. The individual 136-byte transmit
and 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission and reception, and minimizing intervention
during normal network error recovery. The integrated
Manchester encoder/decoder eliminates the need for
an external Serial Interface Adapter (SIA) in the node
system. If support for an external encoding/decoding
scheme is desired, the embedded General Purpose
Serial Interface (GPSI) allows direct access to/from the
MAC. In addition, the device provides programmable
on-chip LED drivers for transmit, receive, collision,
receive polarity, link integrity and activity, or jabber
status. The PCnet-ISA II controller also provides an
External Address Detection InterfaceTM (EADITM) to
allow external hardware address filtering in internetworking applications.
For power sensitive applications where low stand-by
current is desired, the device incorporates a sleep
function to reduce over-all system power consumption,
excellent for notebooks and Green PCs. In conjunction
with this low power mode, the PCnet-ISA II controller
also has integrated functions to support Magic Packet,
an inexpensive technology that allows remote wake up
of Green PCs.
With the rise of embedded networking applications
operating in harsh environments where temperatures
may exceed the normal commercial temperature (0°C
to +70°C) window, an industrial temperature (–40°C to
+85°C) version is available in all two packages; 132-pin
PQFP and 144-pin TQFP. The industrial temperature
version of the PCnet-ISA II Ethernet controller is
characterized across the industrial temperature range
(–40°C to +85°C) within the published power supply
specification (4.75 V to 5.25 V; i.e., ±5% VCC).
Am79C961A
BLOCK DIAGRAM: BUS MASTER MODE
AEN
DACK[3, 5–7]
DRQ[3, 5–7]
RCV
FIFO
IOCHRDY
IOCS16
IOR
IOW
IRQ[3, 4, 5, 9,
10, 11, 12]
MASTER
MEMR
ISA Bus
Interface
Unit
802.3
MAC
Core
CI+/–
Encoder/
Decoder
(PLS) &
AUI Port
XMT
FIFO
MEMW
DXCVR/EAR
DI+/–
XTAL1
XTAL2
DO+/–
REF
RXD+/–
RESET
10BASE-T
MAU
SBHE
BALE
FIFO
Control
SD[0-15]
LA[17-23]
SA[0-19]
SLEEP
SHFBUSY
EEDO
EEDI
EESK
EECS
IRQ15/APCS
Private
Bus
Control
Buffer
Management
Unit
TXD+/–
TXPD+/–
BPCS
LED[0–3]
PRDB[0–7]
TDO
JTAG
Port
Control
EEPROM
Interface
Unit
TMS
TDI
TCK
DVDD[1-7]
DVSS[1-13]
AVDD[1-4]
AVSS[1-2]
19364B-1
Am79C961A
3
TABLE OF CONTENTS
Am79C961A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
BLOCK DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CONNECTION DIAGRAMS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PQFP 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PIN DESCRIPTION: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IEEE P996 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
BALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DACK 3, 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DRQ 3, 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IOCHRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IOCS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IRQ 3, 4, 5, 9, 10, 11, 12, 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
LA17-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MEMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MEMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SA0-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SBHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SD0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
IRQ12/FlashWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
IRQ15/APCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
BPCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DXCVR/EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
LEDO-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PRDB3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PRDB2/EEDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PRDB1/EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PRDB0/EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SHFBUSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
EECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CONNECTION DIAGRAMS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PQFP 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
BLOCK DIAGRAM: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4
Am79C961A
LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PIN DESCRIPTION: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IOCHRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IOCS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IRQ3, 4, 5, 9, 10, 11, 12, 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MEMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MEMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
SA0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
SBHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SD0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
APCS/IRQ15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
BPAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
BPCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
DXCVR/EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
LED0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PRAB0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PRDB3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PRDB2/EEDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PRDB1/EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PRDB0/EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SHFBUSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
EECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SMAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SROE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SRCS/IRQ12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SRWE/WE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PIN DESCRIPTION: NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DI+, DI– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
RXD+, RXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
TXD+, TXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
TXP+, TXP– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PIN DESCRIPTION: IEEE 1149.1 (JTAG) TEST ACCESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . .31
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PIN DESCRIPTION: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
AVDD1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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AVSS1–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DVDD1–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DVSS1–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
TQFP 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . .35
Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . .36
Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
BLOCK DIAGRAM: PCMCIA MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
PIN DESCRIPTION: PCMCIA MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
PCMCIA vs. ISA Pinout Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PCMCIA Pin Specification Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PCMCIA MODE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
PCMCIA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Serial EEPROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Flash Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Shared Memory vs. Programmed I/O Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
FLASH MEMORY MAP AND CARD REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Important Note About The EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Bus Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Auto-Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ADDRESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
WRITE_DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
READ_DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Initiation Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Isolation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Hardware Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Software Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Plug and Play Card Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Plug and Play Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . .54
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Important Note About The EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Basic EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
AMD Device Driver Compatible EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Plug and Play Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
PCnet–ISA II’s Legacy Bit Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Plug & Play Register Locations Detailed Description
(Refer to the Plug & Play Register Map above) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
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Vendor Defined Byte (PnP 0xF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Checksum Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Use Without EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
External Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Optional IEEE Address PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
EISA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
1. Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2. Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3. FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Buffer Management Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Descriptor Ring Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Transmit Descriptor Table Entry (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Receive Descriptor Table Entry (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Differential Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Twisted Pair Transceiver (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Full Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
EADI (External Address Detection Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
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Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Access Operations (Software) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
I/O Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
IEEE Address Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Boot PROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Static RAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Bus Cycles (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Address PROM Cycles External PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Address PROM Cycles Using EEPROM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Ethernet Controller Register Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
MAGIC PACKET OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Magic Packet Mode Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Magic Packet Receive Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
PCNET-ISA II CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
RAP: Register Address Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR0: PCnet-ISA II Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR1: IADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR2: IADR[23:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
CSR5: Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
CSR6: RCV/XMT Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR8: Logical Address Filter, LADRF[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR9: Logical Address Filter, LADRF[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR10: Logical Address Filter, LADRF[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR11: Logical Address Filter, LADRF[63:48] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR12: Physical Address Register, PADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
CSR13: Physical Address Register, PADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
CSR14: Physical Address Register, PADR[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
CSR15: Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
CSR18-19: Current Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
CSR20-21: Current Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
CSR22-23: Next Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR24-25: Base Address of Receive Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR26-27: Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR28-29: Current Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR30-31: Base Address of Transmit Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
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CSR32-33: Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR34-35: Current Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR36-37: Next Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR38-39: Next Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR40-41: Current Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
CSR42-43: Current Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
CSR44-45: Next Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
CSR46: Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
CSR47: Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
CSR48-49: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
CSR50-51: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
CSR52-53: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR54-55: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR56-57: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR58-59: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR60-61: Previous Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR62-63: Previous Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR64-65: Next Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR66-67: Next Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
CSR70-71: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
CSR72: Receive Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
CSR80: Burst and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
CSR82: Bus Activity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
CSR84-85: DMA Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
CSR88-89: Chip ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
CSR92: Ring Length Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
CSR94: Transmit Time Domain Reflectometry Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
CSR96-97: Bus Interface Scratch Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR98-99: Bus Interface Scratch Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR104-105: SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR108-109: Buffer Management Scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR124: Buffer Management Unit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
ISACSR0: Master Mode Read Active/SRAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
ISACSR1: Master Mode Write Active/SRAM Address Pointer . . . . . . . . . . . . . . . . . . . . . . . .114
ISACSR2: Miscellaneous Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
ISACSR3: EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
ISACSR4: LED0 Status (Link Integrity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
ISACSR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
ISACSR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
ISACSR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
ISACSR8: Software Configuration Register (Read-Only Register) . . . . . . . . . . . . . . . . . . . . .120
ISACSR9: Miscellaneous Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
RMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
RMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
RMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Am79C961A
9
RMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
TMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
TMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
TMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
TMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Ethernet Controller Registers (Accessed via RDP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port) . . . . . . . . . . . . . . . . . .128
SYSTEM APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Compatibility Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Optional Address PROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Boot PROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Static RAM Interface (for Shared Memory Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
SWITCHING CHARACTERISTICS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE . . . . . . . . . . 140
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH WRITE CYCLE . . . . . . . . . .140
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . 141
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE . . . . . .144
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH WRITE CYCLE . . . . . .144
SWITCHING CHARACTERISTICS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . .145
SWITCHING CHARACTERISTICS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
SWITCHING CHARACTERISTICS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . .148
SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
SWITCHING WAVEFORMS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
SWITCHING WAVEFORMS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
SWITCHING WAVEFORMS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
SWITCHING WAVEFORMS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .173
SWITCHING WAVEFORMS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
SWITCHING WAVEFORMS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
PQB132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
PQB132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
PCnet-ISA II Compatible Media Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . .183
PCNET-ISA II COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS . . . . . . . . . . . . . . . . .183
PCNET-ISA II COMPATIBLE AUI ISOLATION TRANSFORMERS . . . . . . . . . . . . . . . . . . . . . . . . .183
PCNET-ISA II COMPATIBLE DC/DC CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
MANUFACTURER CONTACT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
10
Am79C961A
Layout Recommendations for Reducing Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
DECOUPLING LOW-PASS R/C FILTER DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Digital Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Analog Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
AVSS1 and AVDD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
AVSS2 and AVDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
AVSS2 and AVDD2/AVDD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
Sample Plug and Play Configuration Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
SAMPLE CONFIGURATION FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Alternative Method for Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Introduction of the Look-Ahead Packet Processing (LAPP) Concept . . . . . . . . . .191
Outline of the LAPP Flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
SETUP: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
FLOW: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
LAPP Enable Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
LAPP Enable Rules for Parsing of Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Some Characteristics of the XXC56 Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . .201
SWITCHING CHARACTERISTICS OF A TYPICAL XXC56 SERIAL EEPROM INTERFACE . . . .201
INSTRUCTION SET FOR THE XXC56 SERIES OF EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Am79C961A PCnet-ISA II Silicon Errata Report . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
AM79C961A REV FD SILICON STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Am79C961A
11
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM79C961A
K
C
\W
ALTERNATE PACKAGING OPTION
\W=Trimmed and Formed (PQB132)
OPTIONAL PROCESSING
Blank=Standard Processing
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I =Industrial (–40°C to +85°C)
PACKAGE TYPE (per Prod. Nomenclature/16-038)
K=132-pin Plastic Quad Flat Pack (PQR132)
V=144-pin Thin Quad Flat Package (PQT144)
SPEED
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C961A
PCnet-ISA II Jumperless Single-Chip Ethernet Controller for ISA
Valid Combinations
Valid Combinations
KC, KC\W
AM79C961A
VC, VC\W
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
KI, KI\W
AM79C961A
VI, VI\W
12
Am79C961A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
DVSS3
MASTER
DRQ7
DRQ6
DRQ5
DVSS10
DACK7
DACK6
DACK5
LA17
LA18
LA19
LA20
DVSS4
LA21
LA22
LA23
SBHE
DVDD3
SA0
SA1
SA2
DVSS5
SA3
SA4
SA5
SA6
SA7
SA8
SA9
DVSS6
SA10
SA11
DVDD4
SA12
SA13
SA14
SA15
DVSS7
SA16
SA17
SA18
SA19
AEN
IOCHRDY
MEMW
MEMR
DVSS11
IRQ15/APCS
IRQ12/FLASHWE
IRQ11
DVDD5
IRQ10
IOCS16
BALE
IRQ3
IRQ4
IRQ5
REF
DVSS12
DRQ3
DACK3
IOR
IOW
IRQ9
RESET
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
DVDD2
TCK
TMS
TDO
TDI
EECS
BPCS
SHFBUSY
PRDB0/EESK
PRDB1/EEDI
PRDB2/EEDO
PRDB3
DVSS2
PRDB4
PRDB5
PRDB6
PRDB7
DVDD1
LED0
LED1
DVSS1
LED2
LED3
DXCVR/EAR
AVDD2
CI+
CI–
DI+
DI–
AVDD1
DO+
DO–
AVSS1
CONNECTION DIAGRAMS: BUS MASTER MODE
PQFP 132
Am79C961AKC
Am79C961A
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXPD+
TXD–
TXPD–
AVDD4
RXD+
RXD–
DVSS13
SD15
SD7
SD14
SD6
DVSS9
SD13
SD5
SD12
SD4
DVDD7
SD11
SD3
SD10
SD2
DVSS8
SD9
SD1
SD8
SD0
SLEEP
DVDD6
19364B-2
13
PIN DESIGNATIONS: BUS MASTER MODE
Listed by Pin Number
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
DVSS3
34
DVDD4
67
DVDD6
100
AVSS1
2
MASTER
35
SA12
68
SLEEP
101
DO–
3
DRQ7
36
SA13
69
SD0
102
DO+
4
DRQ6
37
SA14
70
SD8
103
AVDD1
5
DRQ5
38
SA15
71
SD1
104
DI–
6
DVSS10
39
DVSS7
72
SD9
105
DI+
7
DACK7
40
SA16
73
DVSS8
106
CI–
8
DACK6
41
SA17
74
SD2
107
CI+
9
DACK5
42
SA18
75
SD10
108
AVDD2
10
LA17
43
SA19
76
SD3
109
DXCVR/EAR
11
LA18
44
AEN
77
SD11
110
LED3
12
LA19
45
IOCHRDY
78
DVDD7
111
LED2
13
LA20
46
MEMW
79
SD4
112
DVSS1
14
DVSS4
47
MEMR
80
SD12
113
LED1
15
LA21
48
DVSS11
81
SD5
114
LED0
16
LA22
49
IRQ15/APCS
82
SD13
115
DVDD1
17
LA23
50
IRQ12/FlashWE
83
DVSS9
116
PRDB7
18
SBHE
51
IRQ11
84
SD6
117
PRDB6
19
DVDD3
52
DVDD5
85
SD14
118
PRDB5
20
SA0
53
IRQ10
86
SD7
119
PRDB4
21
SA1
54
IOCS16
87
SD15
120
DVSS2
22
SA2
55
BALE
88
DVSS13
121
PRDB3
23
DVSS5
56
IRQ3
89
RXD–
122
PRDB2/EEDO
24
SA3
57
IRQ4
90
RXD+
123
PRDB1/EEDI
25
SA4
58
IRQ5
91
AVDD4
124
PRDB0/EESK
26
SA5
59
REF
92
TXPD–
125
SHFBUSY
27
SA6
60
DVSS12
93
TXD–
126
BPCS
28
SA7
61
DRQ3
94
TXPD+
127
EECS
29
SA8
62
DACK3
95
TXD+
128
TDI
30
SA9
63
IOR
96
AVDD3
129
TDO
31
DVSS6
64
IOW
97
XTAL1
130
TMS
32
SA10
65
IRQ9
98
AVSS2
131
TCK
33
SA11
66
RESET
99
XTAL2
132
DVDD2
14
Am79C961A
PIN DESIGNATIONS: BUS MASTER MODE
Listed by Pin Name
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
AEN
44
DVSS12
60
LED2
111
SA6
27
AVDD1
103
DVSS13
88
LED3
110
SA7
28
AVDD2
108
DVSS2
120
MASTER
2
SA8
29
AVDD3
96
DVSS3
1
MEMR
47
SA9
30
AVDD4
91
DVSS4
14
MEMW
46
SBHE
18
AVSS1
100
DVSS5
23
PRDB0/EESK
124
SD0
69
AVSS2
98
DVSS6
31
PRDB1/EEDI
123
SD1
71
BALE
55
DVSS7
39
PRDB2/EEDO
122
SD10
75
BPCS
126
DVSS8
73
PRDB3
121
SD11
77
CI–
106
DVSS9
83
PRDB4
119
SD12
80
CI+
107
DXCVR/EAR
109
PRDB5
118
SD13
82
DACK3
62
EECS
127
PRDB6
117
SD14
85
DACK5
9
IOCHRDY
45
PRDB7
116
SD15
87
DACK6
8
IOCS16
54
REF
59
SD2
74
DACK7
7
IOR
63
RESET
66
SD3
76
DI–
104
IOW
64
RXD–
89
SD4
79
DI+
105
IRQ10
53
RXD+
90
SD5
81
DO–
101
IRQ11
51
SA0
20
SD6
84
DO+
102
IRQ12/FlashWE
50
SA1
21
SD7
86
DRQ3
61
IRQ15/APCS
49
SA10
32
SD8
70
DRQ5
5
IRQ3
56
SA11
33
SD9
72
DRQ6
4
IRQ4
57
SA12
35
SHFBUSY
125
DRQ7
3
IRQ5
58
SA13
36
SLEEP
68
DVDD1
115
IRQ9
65
SA14
37
TCK
131
DVDD2
132
LA17
10
SA15
38
TDI
128
DVDD3
19
LA18
11
SA16
40
TDO
129
DVDD4
34
LA19
12
SA17
41
TMS
130
DVDD5
52
LA20
13
SA18
42
TXD–
93
DVDD6
67
LA21
15
SA19
43
TXD+
95
DVDD7
78
LA22
16
SA2
22
TXPD–
92
DVSS1
112
LA23
17
SA3
24
TXPD+
94
DVSS10
6
LED0
114
SA4
25
XTAL1
97
DVSS11
48
LED1
113
SA5
26
XTAL2
99
Am79C961A
15
PIN DESIGNATIONS: BUS MASTER MODE
Listed by Group
Pin Name
Pin Function
I/O
Driver
ISA Bus Interface
AEN
Address Enable
I
BALE
Bus Address Latch Enable
I
DACK[3, 5–7]
DMA Acknowledge
I
DRQ[3, 5–7]
DMA Request
I/O
TS3
IOCHRDY
I/O Channel Ready
I/O
OD3
IOCS16
I/O Chip Select 16
O
OD3
IOR
I/O Read Select
I
IOW
I/O Write Select
I
IRQ[3, 4, 5, 9, 10, 11, 12, 15]
Interrupt Request
O
LA[17-23]
Unlatched Address Bus
I/O
TS3
MASTER
Master Transfer in Progress
O
OD3
MEMR
Memory Read Select
O
TS3
MEMW
Memory Write Select
O
TS3
REF
Memory Refresh Active
I
RESET
System Reset
I
SA[0 –19]
System Address Bus
I/O
TS3
SBHE
System Byte High Enable
I/O
TS3
SD[0 –15]
System Data Bus
I/O
TS3
O
TS1
O
TS1
I/O
TS1
O
TS2
O
TS2
O
TS2
O
TS2
I/O
TS1
TS3/OD3
Board Interfaces
IRQ15/APCS
IRQ15 or Address PROM Chip Select
BPCS
Boot PROM Chip Select
DXCVR/EAR
Disable Transceiver
LED0
LED0/LNKST
LED1
LED1/SFBD/RCVACT
LED2
LED2/SRD/RXDATPOL
LED3
LED3/SRDCLK/XMTACT
PRDB[3–7]
PROM Data Bus
SLEEP
Sleep Mode
XTAL1
Crystal Input
XTAL2
Crystal Output
SHFBUSY
Read access from EEPROM in process
PRDB(0)/EESK
Serial Shift Clock
PRDB(1)/EEDI
Serial Shift Data In
PRDB(2)/EEDO
Serial Shift Data Out
EECS
EEPROM Chip Select
16
I
I
Am79C961A
O
I/O
I/O
I/O
O
PIN DESIGNATIONS: BUS MASTER MODE (continued)
Listed by Group
Pin Name
Pin Function
I/O
Collision Inputs
I
Driver
Attachment Unit Interface (AUI)
CI±
DI±
Receive Data
I
DO±
Transmit Data
O
10BASE-T Receive Data
I
10BASE-T Transmit Data
O
10BASE-T Predistortion Control
O
Twisted Pair Transceiver Interface (10BASE-T)
RXD±
TXD±
TXPD±
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK
Test Clock
I
TDI
Test Data Input
I
TDO
Test Data Output
O
TMS
Test Mode Select
I
TS2
Power Supplies
AVDD
Analog Power [1-4]
AVSS
Analog Ground [1-2]
DVDD
Digital Power [1-7]
DVSS
Digital Ground [1-13]
Output Driver Types
Name
Type
IOL (mA)
IOH (mA)
pF
TS1
Tri-State
4
–1
50
TS2
Tri-State
12
–4
50
TS3
Tri-State
24
–3
120
OD3
Open Drain
24
–3
120
Am79C961A
17
PIN DESCRIPTION: BUS MASTER MODE
These pins are part of the bus master mode. In order to
understand the pin descriptions, definition of some
terms from a draft of IEEE P996 are included.
IEEE P996 Terminology
Alternate Master: Any device that can take control of
the bus through assertion of the MASTER signal. It has
the ability to generate addresses and bus control signals in order to perform bus operations. All Alternate
Masters must be 16 bit devices and drive SBHE.
Bus Ownership: The Current Master possesses bus
ownership and can assert any bus control, address and
data lines.
Current Master: The Permanent Master, Temporary
Master or Alternate Master which currently has ownership of the bus.
between back-to-back DMA requests. See the
Back-to-Back DMA Requests section for details.
Because of the operation of the Plug and Play registers, the DMA Channels on the PCnet-ISA II must be
attached to the specific DRQ and DACK signals on the
PC/AT bus as indicated by the pin names.
IOCHRDY
I/O Channel Ready
Input/Output
When the PCnet-ISA II controller is being accessed,
IOCHRDY HIGH indicates that valid data exists on the
data bus for reads and that data has been latched for
writes. When the PCnet-ISA II controller is the Current
Master on the ISA bus, it extends the bus cycle as long
as IOCHRDY is LOW.
IOCS16
I/O Chip Select 16
Output
Permanent Master: Each P996 bus will have a device
known as the Permanent Master that provides certain
signals and bus control functions as described in Section 3.5 (of the IEEE P996 spec.), “Permanent Master”.
The Permanent Master function can reside on a Bus
Adapter or on the backplane itself.
When an I/O read or write operation is performed, the
PCnet-ISA II controller will drive the IOCS16 pin LOW
to indicate that the chip supports a 16-bit operation at
this address. (If the motherboard does not receive this
signal, then the motherboard will convert a 16-bit
access to two 8-bit accesses).
Temporary Master: A device that is capable of generating a DMA request to obtain control of the bus and
directly asserting only the memory and I/O strobes
during bus transfer. Addresses are generated by the
DMA device on the Permanent Master.
The PCnet-ISA II controller follows the IEEE P996 specification that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no dependency on IOR, or IOW; however, some PC/AT clone systems are not compatible with this approach. For this
reason, the PCnet-ISA II controller is recommended to
be configured to run 8-bit I/O on all machines. Since data
is moved by memory cycles there is virtually no performance loss incurred by running 8-bit I/O and compatibility problems are virtually eliminated. The PCnet-ISA II
controller can be configured to run 8-bit-only I/O by
clearing Bit 0 in Plug and Play register F0.
ISA Interface
AEN
Address Enable
Input
This signal must be driven LOW when the bus performs
an I/O access to the device.
BALE
IOR
Used to latch the LA20–23 address lines.
I/O Read
DACK 3, 5-7
DMA Acknowledge
Input
Asserted LOW when the Permanent Master acknowledges a DMA request. When DACK is asserted the
PCnet-ISA II controller becomes the Current Master by
asserting the MASTER signal.
I/O Write
Input/Output
When the PCnet-ISA II controller needs to perform a
DMA transfer, it asserts DRQ. The Permanent Master
acknowledges DRQ with the assertion of DACK. When
the PCnet-ISA II does not need the bus it desserts
DRQ. The PCnet-ISA II provides for fair bus bandwidth
sharing between two bus mastering devices on the ISA
bus through an adaptive delay which is inserted
18
IOR is driven LOW by the host to indicate that an Input/
Output Read operation is taking place. IOR is only valid
if the AEN signal is LOW and the external address
matches the PCnet-ISA II controller’s predefined I/O
address location. If valid, IOR indicates that a slave
read operation is to be performed.
IOW
DRQ 3, 5-7
DMA Request
Input
Input
IOW is driven LOW by the host to indicate that an Input/
Output Write operation is taking place. IOW is only valid
if AEN signal is LOW and the external address matches
the PCnet-ISA II controller’s predefined I/O address
location. If valid, IOW indicates that a slave write operation is to be performed.
Am79C961A
IRQ 3, 4, 5, 9, 10, 11, 12, 15
Interrupt Request
(DRQ), the Ethernet controller asserts the MASTER
signal to indicate to the Permanent Master that the PCnet-ISA II controller is becoming the Current Master.
Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.
All status flags have a mask bit which allows for suppression of IRQ asser tion. These flags have the
following meaning:
MEMR
Memory Read
Input/Output
MEMR goes LOW to perform a memory read operation.
MEMW
Memory Write
Input/Output
MEMW goes LOW to perfor m a memor y wr ite
operation.
BABL
Babble
RCVCCO
Receive Collision Count Overflow
JAB
Jabber
REF
MISS
Missed Frame
MERR
Memory Error
MPCO
Missed Packet Count Overflow
RINT
Receive Interrupt
IDON
Initialization Done
TXDATSTRT
Transmit Start
Memory Refresh
Input
When REF is asserted, a memory refresh is active. The
PCnet-ISA II controller uses this signal to mask inadvertent DMA Acknowledge assertion during memory
refresh periods. If DACK is asserted when REF is
active, DACK assertion is ignored. REF is monitored to
eliminate a bus arbitration problem observed on some
ISA platforms.
Because of the operation of the Plug and Play registers, the interrupts on the PCnet-ISA II must be
attached to specific IRQ signals on the PC/AT bus.
LA17-23
Unlatched Address Bus
Input/Output
The unlatched address bus is driven by the PCnet-ISA
II controller during bus master cycle.
The functions of these unlatched address pins will
change when GPSI mode is invoked. The following
table shows the pin configuration in GPSI mode. Please
refer to the section on General Purpose Serial Interface
for detailed information on accessing this mode.
Pin
Number
Pin Function in Bus
Master Mode
Pin Function in
GPSI Mode
10
LA17
RXDAT
11
LA18
SRDCLK
12
LA19
RXCRS
13
LA20
CLSN
15
LA21
STDCLK
16
LA22
TXEN
17
LA23
TXDAT
RESET
Reset
Input
When RESET is asserted HIGH the PCnet-ISA II controller performs an internal system reset. RESET must
be held for a minimum of 10 XTAL1 periods before
being deasserted. While in a reset state, the PCnet-ISA
II controller will tristate or deassert all outputs to predefined reset levels. The PCnet-ISA II controller resets
itself upon power-up.
SA0-19
System Address Bus
Input/Output
This bus contains address information, which is stable
during a bus operation, regardless of the source.
SA17-19 contain the same values as the unlatched
address LA17-19. When the PCnet-ISA II controller is
the Current Master, SA0-19 will be driven actively.
When the PCnet-ISA II controller is not the Current
Master, the SA0-19 lines are continuously monitored to
determine if an address match exists for I/O slave
transfers or Boot PROM accesses.
SBHE
System Byte High Enable
Input/Output
This signal indicates the high byte of the system data
bus is to be used. SBHE is driven by the PCnet-ISA II
controller when performing bus mastering operations.
MASTER
Master Mode
Input/Output
This signal indicates that the PCnet-ISA II controller
has become the Current Master of the ISA bus. After
the PCnet-ISA II controller has received a DMA
Acknowledge (DACK) in response to a DMA Request
SD0-15
System Data Bus
Input/Output
These pins are used to transfer data to and from the
PCnet-ISA II controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA II control-
Am79C961A
19
ler when performing bus master writes and slave read
operations. Likewise, the data on SD0-15 is latched by
the PCnet-ISA II controller when performing bus
master reads and slave write operations.
Board Interface
IRQ12/FlashWE
Flash Write Enable
Output
Optional interface to the Flash memory boot PROM
Write Enable.
IRQ15/APCS
Address PROM Chip Select
Output
When programmed as APCS in Plug and Play Register
F0, this signal is asserted when the external Address
PROM is read. When an I/O read operation is
performed on the first 16 bytes in the PCnet-ISA II controller’s I/O space, APCS is asserted. The outputs of
the external Address PROM drive the PROM Data Bus.
The PCnet-ISA II controller buffers the contents of the
PROM data bus and drives them on the lower eight bits
of the System Data Bus.
If EADI mode is selected, this pin becomes the EAR
input.
The incoming frame will be checked against the internally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and
timing of this signal).
LEDO-3
LED Drivers
Output
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section The ISA
Bus Configuration Registers) and they are active LOW.
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0
continues to indicate 10BASE-T Link Status.
When programmed to IRQ15 (default), this pin has the
same function as IRQ 3, 4, 5, 9, 10, 11, or 12.
Boot PROM Chip Select
Output
This signal is asserted when the Boot PROM is read. If
SA0-19 lines match a predefined address block and
MEMR is active and REF inactive, the BPCS signal will
be asserted. The outputs of the external Boot PROM
drive the PROM Data Bus. The PCnet-ISA II controller
buffers the contents of the PROM data bus and drives
them on the lower eight bits of the System Data Bus.
DXCVR/EAR
1
SF/BD
2
SRD
3
SRDCLK
Private Data Bus
Input/Output
This is the data bus for the Boot PROM and the
Address PROM.
PRDB2/EEDO
Private data bus bit 2/Data Out
Input/Output
A multifunction pin which serves as PRDB2 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA OUT from the EEPROM.
PRDB1/EEDI
Input/Output
This pin can be used to disable external transceiver
circuitry attached to the AUI interface when the internal
10BASE-T port is active. The polarity of this pin is set
by the DXCVRP bit (PnP register 0xF0, bit 5). When
DXCVRP is cleared (default), the DXCVR pin is driven
HIGH when the Twisted Pair port is active or SLEEP
mode has been entered and driven LOW when the AUI
port is active. When DXCVRP is set, the DXCVR pin is
driven LOW when the Twisted Pair port is active or
SLEEP mode has been entered and driven HIGH when
the AUI port is active.
20
EADI Function
PRDB3-7
BPCS
Disable Transceiver/
External Address Reject
LED
Private data bus bit 1/Data In Input/Output
A multifunction pin which serves as PRDB1 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA In to the EEPROM.
PRDB0/EESK
Private data bus bit 0/
Serial Clock
Input/Output
A multifunction pin which serves as PRDB0 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become Serial Clock to the EEPROM.
Am79C961A
SHFBUSY
Shift Busy
Input/Output
This pin indicates that a read from the external
EEPROM is in progress. It is active only when data is
being shifted out of the EEPROM due to a hardware
RESET or assertion of the EE_LOAD bit (ISACSR3, bit
14). If this pin is left unconnected or pulled low with a
pull-down resistor, an EEPROM checksum error is
forced. Normally, this pin should be connected to VCC
through a 10K Ω pull-up resistor.
EECS
EEPROM CHIP SELECT
Output
This signal is asserted when read or write accesses
are being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
SLEEP
Sleep
Input
When SLEEP pin is asserted (active LOW), the PCnet-ISA II controller performs an internal system reset
and proceeds into a power savings mode. All outputs
will be placed in their normal reset condition. All PCnet-ISA II controller inputs will be ignored except for the
SLEEP pin itself. Deassertion of SLEEP results in the
device waking up. The system must delay the starting
of the network controller by 0.5 seconds to allow internal analog circuits to stabilize.
XTAL1
Crystal Connection
Input
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
XTAL2
Crystal Connection
Output
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
Am79C961A
21
DVDD4
PRAB12
PRAB13
PRAB14
PRAB15
DVSS7
SA13
SA14
SA15
SRWE
AEN
IOCHRDY
MEMW
MEMR
DVSS11
APCS/IRQ15
SRCS/IRQ12
IRQ11
DVDD5
IRQ10
IOCS16
BPAM
IRQ3
IRQ4
IRQ5
REF
DVSS12
SROE
SMAM
IOR
IOW
IRQ9
RESET
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
DVDD2
TCK
TMS
TDO
TDI
EECS
BPCS
SHFBUSY
PRDB0/EESK
PRDB1/EEDI
PRDB2/EEDO
PRDB3
DVSS2
PRDB4
PRDB5
PRDB6
PRDB7
DVDD1
LED0
LED1
DVSS1
LED2
LED3
DXCVR/EAR
AVDD2
CI+
CI–
DI+
DI–
AVDD1
DO+
DO–
AVSS1
CONNECTION DIAGRAMS: BUS SLAVE MODE
PQFP 132
DVSS3
SMA
SA0
SA1
SA2
DVSS10
SA3
SA4
SA5
SA6
SA7
SA8
SA9
DVSS4
SA10
SA11
SA12
SBHE
DVDD3
PRAB0
PRAB1
PRAB2
DVSS5
PRAB3
PRAB4
PRAB5
PRAB6
PRAB7
PRAB8
PRAB9
DVSS6
PRAB10
PRAB11
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Am79C961AKC
Am79C961A
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXPD+
TXD–
TXPD–
AVDD4
RXD+
RXD–
DVSS13
SD15
SD7
SD14
SD6
DVSS9
SD13
SD5
SD12
SD4
DVDD7
SD11
SD3
SD10
SD2
DVSS8
SD9
SD1
SD8
SD0
SLEEP
DVDD6
19364B-3
BLOCK DIAGRAM: BUS SLAVE MODE
AEN
RCV
FIFO
IOCHRDY
802.3
MAC
Core
IOR
IOW
IRQ[3, 4, 5, 9,
10, 11, 12]
IOCS16
MEMR
DXCVR/EAR
CI+/ISA Bus
Interface
Unit
Encoder/
Decoder
(PLS) &
AUI Port
XMT
FIFO
MEMW
DI+/XTAL1
XTAL2
DO+/-
REF
RXD+/-
RESET
10BASE-T
MAU
SA[0-15]
SBHE
FIFO
Control
SD[0-15]
Private
Bus
Control
Buffer
Management
Unit
SMA
SLEEP
BPAM
SMAM
SHFBUSY
EEDO
EEDI
EESK
EECS
TXD+/TXPD+/-
IRQ15/APCS
BPCS
LED[0-3]
PRAB[0-15]
PRDB[0-7]
SROE
SRWE
TDO
JTAG
Port
Control
EEPROM
Interface
Unit
TMS
TDI
TCK
DVDD[1-7]
19364B-4
DVSS[1-13]
AVDD[1-4]
AVSS[1-2]
Am79C961A
23
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Pin Number
24
Pin #
Name
Pin #
Name
Pin #
Name
1
DVSS3
45
IOCHRDY
89
RXD-
2
SMA
46
MEMW
90
RXD+
3
SA0
47
MEMR
91
AVDD4
4
SA1
48
DVSS11
92
TXPD-
5
SA2
49
IRQ15
93
TXD-
6
DVSS10
50
IRQ12
94
TXPD+
7
SA3
51
IRQ11
95
TXD+
8
SA4
52
DVDD5
96
AVDD3
9
SA5
53
IRQ10
97
XTAL1
10
SA6
54
IOCS16
98
AVSS2
11
SA7
55
BPAM
99
XTAL2
12
SA8
56
IRQ3
100
AVSS1
13
SA9
57
IRQ4
101
DO-
14
DVSS4
58
IRQ5
102
DO+
15
SA10
59
REF
103
AVDD1
16
SA11
60
DVSS12
104
DI-
17
SA12
61
SROE
105
DI+
18
SBHE
62
SMAM
106
CI-
19
DVDD3
63
IOR
107
CI+
20
PRAB0
64
IOW
108
AVDD2
21
PRAB1
65
IRQ9
109
DXCVR/EAR
22
PRAB2
66
RESET
110
LED3
23
DVSS5
67
DVDD6
111
LED2
24
PRAB3
68
SLEEP
112
DVSS1
25
PRAB4
69
SD0
113
LED1
26
PRAB5
70
SD8
114
LED0
27
PRAB6
71
SD1
115
DVDD1
28
PRAB7
72
SD9
116
PRDB7
29
PRAB8
73
DVSS8
117
PRDB6
30
PRAB9
74
SD2
118
PRDB5
31
DVSS6
75
SD10
119
PRDB4
32
PRAB10
76
SD3
120
DVSS2
33
PRAB11
77
SD11
121
PRDB3
34
DVDD4
78
DVDD7
122
PRDB2/EEDO
35
PRAB12
79
SD4
123
PRDB1/EEDI
36
PRAB13
80
SD12
124
PRDB0/EESK
37
PRAB14
81
SD5
125
SHFBUSY
38
PRAB15
82
SD13
126
BPCS
39
DVSS7
83
DVSS9
127
EECS
40
SA13
84
SD6
128
TDI
41
SA14
85
SD14
129
TDO
42
SA15
86
SD7
130
TMS
43
SRWE
87
SD15
131
TCK
44
AEN
88
DVSS13
132
DVDD2
Am79C961A
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Pin Name
Name
Pin#
Name
Pin#
Name
Pin#
AEN
44
IRQ15
49
SA13
40
AVDD1
103
IRQ3
56
SA14
41
AVDD2
108
IRQ4
57
SA15
42
AVDD3
96
IRQ5
58
SA2
5
AVDD4
91
IRQ9
65
SA3
7
AVSS1
100
LED0
114
SA4
8
AVSS2
98
LED1
113
SA5
9
BPAM
55
LED2
111
SA6
10
BPCS
126
LED3
110
SA7
11
CI-
106
MEMR
47
SA8
12
CI+
107
MEMW
46
SA9
13
DI-
104
PRAB0
20
SBHE
18
DI+
105
PRAB1
21
SD0
69
DO-
101
PRAB10
32
SD1
71
DO+
102
PRAB11
33
SD10
75
DVDD1
115
PRAB12
35
SD11
77
DVDD2
132
PRAB13
36
SD12
80
DVDD3
19
PRAB14
37
SD13
82
DVDD4
34
PRAB15
38
SD14
85
DVDD5
52
PRAB2
22
SD15
87
DVDD6
67
PRAB3
24
SD2
74
DVDD7
78
PRAB4
25
SD3
76
DVSS1
112
PRAB5
26
SD4
79
DVSS10
6
PRAB6
27
SD5
81
DVSS11
48
PRAB7
28
SD6
84
DVSS12
60
PRAB8
29
SD7
86
DVSS13
88
PRAB9
30
SD8
70
DVSS2
120
PRDB0/DO
124
SD9
72
DVSS3
1
PRDB0/D1
123
SHFBUSY
125
DVSS4
14
PRDB0/SCLK
122
SLEEP
68
DVSS5
23
PRDB3
121
SMA
2
DVSS6
31
PRDB4
119
SMAM
62
DVSS7
39
PRDB5
118
SROE
61
DVSS8
73
PRDB6
117
SRWE
43
DVSS9
83
PRDB7
116
TCK
131
DXCVR/EAR
109
REF
59
TDI
128
EECS
127
RESET
66
TDO
129
IOCHRDY
45
RXD-
89
TMS
130
IOCS16
54
RXD+
90
TXD-
93
IOR
63
SA0
3
TXD+
95
IOW
64
SA1
4
TXPD-
92
IRQ10
53
SA10
15
TXPD+
94
IRQ11
51
SA11
16
XTAL1
97
IRQ12
50
SA12
17
XTAL2
99
Am79C961A
25
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Group
Pin Name
Pin Function
I/O
Driver
ISA Bus Interface
AEN
Address Enable
I
IOCHRDY
I/O Channel Ready
O
OD3
IOCS16
I/O Chip Select 16
O
OD3
IOR
I/O Read Select
I
IOW
I/O Write Select
I
IRQ[3, 4, 5, 9, 10, 11, 12, 15]
Interrupt Request
O
MEMR
Memory Read Select
I
MEMW
Memory Write Select
I
REF
Memory Refresh Active
I
RESET
System Reset
I
SA[0–15]
System Address Bus
I
TS3/OD3
SBHE
System Byte High Enable
SD[0–15]
System Data Bus
I/O
I
TS3
IRQ15/APCS
IRQ15 or Address PROM Chip Select
O
TS1
BPCS
Boot PROM Chip Select
O
TS1
BPAM
Boot PROM Address Match
I
DXCVR/EAR
Disable Transceiver
I/O
TS1
LED0
LED0/LNKST
O
TS2
LED1
LED1/SFBD/RCVACT
O
TS2
LED2
LED2/SRD/RXDATD01
O
TS2
LED3
LED3/SRDCLK/XMTACT
O
TS2
PRAB[0–15]
PRivate Address Bus
I/O
TS3
PRDB[3–7]
PRivate Data Bus
I/O
TS1
SLEEP
Sleep Mode
I
SMA
Slave Mode Architecture
I
SMAM
Shared Memory Address Match
I
SROE
Static RAM Output Enable
O
TS3
SRWE
Static RAM Write Enable
O
TS1
XTAL1
Crystal Oscillator Input
I
XTAL2
Crystal Oscillator OUTPUT
O
Board Interfaces
SHFBUSY
Read access from EEPROM in process
O
PRDB(0)/EESK
Serial Shift Clock
I/O
PRDB(1)/EEDI
Serial Shift Data In
I/O
PRDB(2)/EEDO
Serial Shift Data Out
I/O
EECS
EEPROM Chip Select
O
26
Am79C961A
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Group
Pin Name
Pin Function
I/O
Collision Inputs
I
Driver
Attachment Unit Interface (AUI)
CI±
DI±
Receive Data
I
DO±
Transmit Data
O
10BASE-T Receive Data
I
10BASE-T Transmit Data
O
10BASE-T Predistortion Control
O
Twisted Pair Transceiver Interface (10BASE-T)
RXD±
TXD±
TXPD±
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK
Test Clock
I
TDI
Test Data Input
I
TDO
Test Data Output
O
TMS
Test Mode Select
I
TS2
Power Supplies
AVDD
Analog Power [1-4]
AVSS
Analog Ground [1-2]
DVDD
Digital Power [1-7]
DVSS
Digital Ground [1-13]
Output Driver Types
Name
Type
IOL (mA)
IOH (mA)
pF
TS1
Tri-State
4
–1
50
TS2
Tri-State
12
–4
50
TS3
Tri-State
24
–3
120
OD3
Open Drain
24
–3
120
Am79C961A
27
PIN DESCRIPTION: BUS SLAVE MODE
ISA Interface
AEN
Address Enable
Input
This signal must be driven LOW when the bus performs
an I/O access to the device.
IOCHRDY
I/O Channel Ready
Output
When the PCnet-ISA II controller is being accessed, a
HIGH on IOCHRDY indicates that valid data exists on
the data bus for reads and that data has been latched
for writes.
IOCS16
I/O Chip Select 16
Input/Output
When an I/O read or write operation is performed, the
PCnet-ISA II controller will drive this pin LOW to indicate that the chip supports a 16-bit operation at this
address. (If the motherboard does not receive this
signal, then the motherboard will convert a 16-bit
access to two 8-bit accesses).
The PCnet-ISA II controller follows the IEEE P996 specification that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no dependency on IOR, or IOW; however, some PC/AT clone
systems are not compatible with this approach. For this
reason, the PCnet-ISA II controller is recommended to
be configured to run 8-bit I/O on all machines. Since data
is moved by memory cycles there is vir tually no
performance loss incurred by running 8-bit I/O and
compatibility problems are virtually eliminated. The PCnet-ISA II controller can be configured to run 8-bit-only I/
O by clearing Bit 0 in Plug and Play Register F0.
IOR
I/O Read
Input
To perform an Input/Output Read operation on the
device IOR must be asserted. IOR is only valid if the
AEN signal is LOW and the external address matches
the PCnet-ISA II controller’s predefined I/O address
location. If valid, IOR indicates that a slave read operation is to be performed.
IOW
I/O Write
Input
To perform an Input/Output write operation on the
device IOW must be asserted. IOW is only valid if AEN
signal is LOW and the external address matches the
PCnet-ISA II controller’s predefined I/O address location. If valid, IOW indicates that a slave write operation
is to be performed.
28
IRQ3, 4, 5, 9, 10, 11, 12, 15
Interrupt Request
Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON or TXSTRT. All status flags have a mask
bit which allows for suppression of IRQ assertion.
These flags have the following meaning:
BABL
Babble
RCVCCO
Receive Collision Count Overflow
JAB
Jabber
MISS
Missed Frame
MERR
Memory Error
MPCO
Missed Packet Count Overflow
RINT
Receive Interrupt
IDON
Initialization Done
TXSTRT
Transmit Start
MEMR
Memory Read
Input
ME M R go es L OW to pe rfo r m a me mo r y r ea d
operation.
MEMW
Memory Write
Input
MEMW goes LOW to perform a memory write operation.
REF
Memory Refresh
Input
When REF is asserted, a memory refresh cycle is in
progress. During a refresh cycle, MEMR assertion
is ignored.
RESET
Reset
Input
When RESET is asserted HIGH, the PCnet-ISA II
controller performs an internal system reset. RESET
must be held for a minimum of 10 XTAL1 periods before
being deasserted. While in a reset state, the PCnet-ISA
II controller will tristate or deassert all outputs to
predefined reset levels. The PCnet-ISA II controller
resets itself upon power-up.
SA0-15
System Address Bus
Input
This bus carries the address inputs from the system
address bus. Address data is stable during command
active cycle.
Am79C961A
SBHE
DXCVR/EAR
System Bus High Enable
Input
This signal indicates the HIGH byte of the system data
bus is to be used. There is a weak pull-up resistor on
this pin. If the PCnet-ISA II controller is installed in an
8-bit only system like the PC/XT, SBHE will always be
HIGH and the PCnet-ISA II controller will perform only
8-bit operations. There must be at least one LOW going
edge on this signal before the PCnet-ISA II controller
will perform 16-bit operations.
Disable Transceiver/
External Address Reject
Input/Output
This pin disables the transceiver. The DXCVR output is
configured in the initialization sequence. A high level
indicates the Twisted Pair Interface is active and the
AUI is inactive, or SLEEP mode has been entered. A
low level indicates the AUI is active and the Twisted Pair
interface is inactive.
SD0-15
If EADI mode is selected, this pin becomes the EAR
input.
System Data Bus
Input/Output
This bus is used to transfer data to and from the PCnet-ISA II controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA II
controller when performing slave read operations.
The incoming frame will be checked against the internally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and timing of this signal).
Likewise, the data on SD0-15 is latched by the PCnet-ISA II controller when performing slave write
operations.
LED0-3
Board Interface
APCS/IRQ15
Address PROM Chip Select
Output
This signal is asserted when the external Address
PROM is read. When an I/O read operation is performed on the first 16 bytes in the PCnet-ISA II
controller’s I/O space, APCS is asserted. The outputs
of the external Address PROM drive the PROM Data
Bus. The PCnet-ISA II controller buffers the contents of
the PROM data bus and drives them on the lower eight
bits of the System Data Bus. IOCS16 is not asserted
during this cycle.
BPAM
Boot PROM Address Match
Input
This pin indicates a Boot PROM access cycle. If no
Boot PROM is installed, this pin has a default value of
HIGH and thus may be left connected to VDD.
BPCS
Boot PROM Chip Select
Output
This signal is asserted when the Boot PROM is read. If
BPAM is active and MEMR is active, the BPCS signal
will be asserted. The outputs of the external Boot
PROM drive the PROM Data Bus. The PCnet-ISA II
controller buffers the contents of the PROM data bus
and drives them on the System Data Bus. IOCS16 is
not asserted during this cycle. If 16-bit cycles are
performed, it is the responsibility of external logic to
assert MEMCS16 signal.
LED Drivers
Output
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section The ISA
Bus Configuration Registers) and they are active LOW.
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0
continues to indicate 10BASE-T Link Status. The
DXCVR input becomes the EAR input.
LED
EADI Function
1
SF/BD
2
SRD
3
SRDCLK
PRAB0-15
Private Address Bus
Input/Output
The Private Address Bus is the address bus used to
drive the Address PROM, Remote Boot PROM, and
SRAM.
PRDB3-7
Private Data Bus
Input/Output
This is the data bus for the static RAM, the Boot PROM,
and the Address PROM.
PRDB2/EEDO
Private Data Bus Bit 2/Data Out Input/Output
A multifunction pin which serves as PRDB2 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA OUT from the EEPROM.
Am79C961A
29
PRDB1/EEDI
Private Data Bus Bit 1/Data In Input/Output
A multifunction pin which serves as PRDB1 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA In to the EEPROM.
PRDB0/EESK
Private Data Bus Bit 0/
Serial Clock
Input/Output
A multifunction pin which serves as PRDB0 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become Serial Clock to the EEPROM.
cess or Programmed I/O access through the PIOSEL
bit (ISACSR2, bit 13).
SMAM
Shared Memory
Address Match
Input
When the Shared Memory architecture is selected
(ISACSR2, bit 13), this pin is an input that indicates an
access to shared memory when asserted. The type of
access is decided by MEMR or MEMW.
When the Programmed I/O architecture is selected,
this pin should be permanently tied HIGH.
SHFBUSY
SROE
Shift Busy
Input/Output
This pin indicates that a read from the external
EEPROM is in progress. It is active only when data is
being shifted out of the EEPROM due to a hardware
RESET or assertion of the EE_LOAD bit (ISACSR3, bit
14). If this pin is left unconnected or pulled low with a
pull-down resistor, an EEPROM checksum error is
forced. Normally, this pin should be connected to VCC
through a 10K Ω pull-up resistor.
Static RAM Output Enable
Output
This pin directly controls the external SRAM’s OE pin.
EECS
EEPROM CHIP SELECT
Output
This signal is asserted when read or write accesses
are being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
SLEEP
Sleep
Input
When SLEEP input is asserted (active LOW), the PCnet-ISA II controller performs an internal system reset
and proceeds into a power savings mode. All outputs
will be placed in their normal reset condition. All PCnet-ISA II controller inputs will be ignored except for the
SLEEP pin itself. Deassertion of SLEEP results in the
device waking up. The system must delay the starting
of the network controller by 0.5 seconds to allow internal analog circuits to stabilize.
SMA
Slave Mode Architecture
Input
This pin must be permanently pulled LOW for operation
in the Bus Slave mode. It is sampled after the hardware
RESET sequence. In the Bus Slave mode, the PCnet-ISA II can be programmed for Shared Memory ac-
30
SRCS/IRQ12
Static RAM Chip Select
Output
This pin directly controls the external SRAM’s chip
select (CS) pin when the Flash boot ROM option is
selected.
When Flash boot ROM option is not selected, this pin
becomes IRQ12.
SRWE/WE
Static RAM Write Enable/
Write Enable
Output
This pin (SRWE) directly controls the external SRAM’s
W E p i n w h e n a F l a s h m e m o r y d ev i c e i s n o t
implemented.
When a Flash memory device is implemented, this pin
becomes a global write enable (WE) pin.
XTAL1
Crystal Connection
Input
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
XTAL2
Crystal Connection
Output
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
Am79C961A
PIN DESCRIPTION:
NETWORK INTERFACES
AUI
TDO
Test Data Output
Output
This is the test data output path from the PCnet-ISA II
controller. TDO is tri-stated when JTAG port is inactive.
CI+, CI–
Control Input
Input
This is a differential input pair used to detect Collision
(Signal Quality Error Signal).
DI+, DI–
Data In
Input
This is a differential receive data input pair to the PCnet-ISA II controller.
DO+, DO–
Data Out
Output
This is a differential transmit data output pair from the
PCnet-ISA II controller.
Twisted Pair Interface
RXD+, RXD–
Receive Data
Input
This is the 10BASE-T port differential receive input
pair.
TXD+, TXD–
Transmit Data
Output
These are the 10BASE-T port differential transmit
drivers.
TXP+, TXP–
Transmit Predistortion Control
Output
These are 10BASE-T transmit waveform pre-distortion
control differential outputs.
PIN DESCRIPTION:
IEEE 1149.1 (JTAG) TEST ACCESS PORT
TCK
Test Clock
Input
This is the clock input for the boundary scan test mode
operation. TCK can operate up to 10 MHz. TCK does
not have an internal pull-up resistor and must be connected to a valid TTL level of high or low. TCK must not
be left unconnected.
TDI
Test Data Input
Input
This is the test data input path to the PCnet-ISA II controller. If left unconnected, this pin has a default value
of HIGH.
TMS
Test Mode Select
Input
This is a serial input bit stream used to define the specific boundary scan test to be executed. If left unconnected, this pin has a default value of HIGH.
PIN DESCRIPTION:
POWER SUPPLIES
All power pins with a “D” prefix are digital pins connected to the digital circuitry and digital I/O buffers. All
power pins with an “A” prefix are analog power pins
connected to the analog circuitry. Not all analog pins
are quiet and special precaution must be taken when
doing board layout. Some analog pins are more noisy
than others and must be separated from the other
analog pins.
AVDD1–4
Analog Power (4 Pins)
Power
Supplies power to analog portions of the PCnet-ISA II
controller. Special attention should be paid to the
printed circuit board layout to avoid excessive noise on
these lines.
AVSS1–2
Analog Ground (2 Pins)
Power
Supplies ground reference to analog portions of PCnet-ISA II controller. Special attention should be paid to
the printed circuit board layout to avoid excessive noise
on these lines.
DVDD1–7
Digital Power (7 Pins)
Power
Supplies power to digital portions of PCnet-ISA II controller. Four pins are used by Input/Output buffer drivers
and two are used by the internal digital circuitry.
DVSS1–13
Digital Ground (13 Pins)
Power
Supplies ground reference to digital portions of PCnet-ISA II controller. Ten pins are used by Input/Output
buffer drivers and two are used by the internal digital
circuitry.
Am79C961A
31
CONNECTION DIAGRAM
Am79C961AVC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
TQFP 144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
19364B-5
32
Am79C961A
PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144)
Listed by Pin Number
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
NC
37
NC
73
NC
109
NC
2
DVSS3
38
DVDD4
74
DVDD6
110
AVSS1
3
MASTER
39
SA12
75
SLEEP
111
DO–
4
DRQ7
40
SA13
76
SD0
112
DO+
5
DRQ6
41
SA14
77
SD8
113
AVDD1
6
DRQ5
42
SA15
78
SD1
114
DI–
7
DVSS10
43
DVSS7
79
SD9
115
DI+
8
DACK7
44
SA16
80
DVSS8
116
CI–
9
DACK6
45
SA17
81
SD2
117
CI+
10
DACK5
46
SA18
82
SD10
118
AVDD2
11
LA17
47
SA19
83
SD3
119
DXCVR/EAR
12
LA18
48
AEN
84
SD11
120
LED3
13
LA19
49
IOCHRDY
85
DVDD7
121
LED2
14
LA20
50
MEMW
86
SD4
122
DVSS1
15
DVSS4
51
MEMR
87
SD12
123
LED1
16
LA21
52
DVSS11
88
SD5
124
LED0
17
LA22
53
IRQ15/APCS
89
SD13
125
DVDD1
18
LA23
54
IRQ12/FlashWE
90
DVSS9
126
PRDB7
19
SBHE
55
IRQ11
91
SD6
127
PRDB6
20
DVDD3
56
DVDD5
92
SD14
128
PRDB5
21
SA0
57
IRQ10
93
SD7
129
PRDB4
22
SA1
58
IOCS16
94
SD15
130
DVSS2
23
SA2
59
BALE
95
DVSS13
131
PRDB3
24
DVSS5
60
IRQ3
96
RXD–
132
PRDB2/EEDO
25
SA3
61
IRQ4
97
RXD+
133
PRDB1/EEDI
26
SA4
62
IRQ5
98
AVDD4
134
PRDB0/EESK
27
SA5
63
REF
99
TXPD–
135
SHFBUSY
28
SA6
64
DVSS12
100
TXD–
136
BPCS
29
SA7
65
DRQ3
101
TXPD+
137
EECS
30
SA8
66
DACK3
102
TXD+
138
TDI
31
SA9
67
IOR
103
AVDD3
139
TDO
32
DVSS6
68
IOW
104
XTAL1
140
TMS
33
SA10
69
IRQ9
105
AVSS2
141
TCK
34
SA11
70
RESET
106
XTAL2
142
DVDD2
35
NC
71
NC
107
NC
143
NC
36
NC
72
NC
108
NC
144
NC
Am79C961A
33
PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144)
Listed by Pin Name
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
AEN
48
DVSS3
2
NC
37
SA3
25
AVDD1
113
DVSS4
15
NC
71
SA4
26
AVDD2
118
DVSS5
24
NC
72
SA5
27
AVDD3
103
DVSS6
32
NC
73
SA6
28
34
AVDD4
98
DVSS7
43
NC
107
SA7
29
AVSS1
110
DVSS8
80
NC
108
SA8
30
AVSS2
105
DVSS9
90
NC
109
SA9
31
BALE
59
DXCVR/EAR
119
NC
143
SBHE
19
BPCS
136
EECS
137
NC
144
SD0
76
CI+
117
IOCHRDY
49
PRDB0/EESK
134
SD1
78
CI–
116
IOCS16
58
PRDB1/EEDI
133
SD10
82
DACK3
66
IOR
67
PRDB2/EEDO
132
SD11
84
DACK5
10
IOW
68
PRDB3
131
SD12
87
DACK6
9
IRQ10
57
PRDB4
129
SD13
89
DACK7
8
IRQ11
55
PRDB5
128
SD14
92
DI+
115
IRQ12/FlashWE
54
PRDB6
127
SD15
94
DI–
114
IRQ15/APCS
53
PRDB7
126
SD2
81
DO+
112
IRQ3
60
REF
63
SD3
83
DO–
111
IRQ4
61
RESET
70
SD4
86
DRQ3
65
IRQ5
62
RXD+
97
SD5
88
DRQ5
6
IRQ9
69
RXD–
96
SD6
91
DRQ6
5
LA17
11
SA0
21
SD7
93
DRQ7
4
LA18
12
SA1
22
SD8
77
DVDD1
125
LA19
13
SA10
33
SD9
79
DVDD2
142
LA20
14
SA11
34
SHFBUSY
135
DVDD3
20
LA21
16
SA12
39
SLEEP
75
DVDD4
38
LED0
124
SA13
40
TCK
141
DVDD5
56
LED1
123
SA14
41
TDI
138
DVDD6
74
LED2
121
SA15
42
TDO
139
DVDD7
85
LED3
120
SA16
44
TMS
140
DVSS1
122
MASTER
3
SA17
45
TXD+
102
DVSS10
7
MEMR
51
SA18
46
TXD–
100
DVSS11
52
MEMW
50
SA19
47
TXPD+
101
DVSS12
64
NC
1
SA2
23
TXPD–
99
DVSS13
95
NC
35
SA22
17
XTAL1
104
DVSS2
130
NC
36
SA23
18
XTAL2
106
Am79C961A
PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144)
Listed by Pin Number
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
NC
37
NC
73
NC
109
NC
2
DVSS3
38
DVDD4
74
DVDD6
110
AVSS1
3
SMA
39
PRAB12
75
SLEEP
111
DO-
4
SA0
40
PRAB13
76
SD0
112
DO+
5
SA1
41
PRAB14
77
SD8
113
AVDD1
6
SA2
42
PRAB15
78
SD1
114
DI-
7
DVSS10
43
DVSS7
79
SD9
115
DI+
8
SA3
44
SA13
80
DVSS8
116
CI-
9
SA4
45
SA14
81
SD2
117
CI+
10
SA5
46
SA15
82
SD10
118
AVDD2
11
SA6
47
SRWE
83
SD3
119
DXCVR/EAR
12
SA7
48
AEN
84
SD11
120
LED3
13
SA8
49
IOCHRDY
85
DVDD7
121
LED2
14
SA9
50
MEMW
86
SD4
122
DVSS1
15
DVSS4
51
MEMR
87
SD12
123
LED1
16
SA10
52
DVSS11
88
SD5
124
LED0
17
SA11
53
IRQ15
89
SD13
125
DVDD1
18
SA12
54
IRQ12
90
DVSS9
126
PRDB7
19
SBHE
55
IRQ11
91
SD6
127
PRDB6
20
DVDD3
56
DVDD5
92
SD14
128
PRDB5
21
PRAB0
57
IRQ10
93
SD7
129
PRDB4
22
PRAB1
58
IOCS16
94
SD15
130
DVSS2
23
PRAB2
59
BPAM
95
DVSS13
131
PRDB3
24
DVSS5
60
IRQ3
96
RXD-
132
PRDB2/
EEDO
25
PRAB3
61
IRQ4
97
RXD+
133
PRDB1/EEDI
26
PRAB4
62
IRQ5
98
AVDD4
134
PRDB0/EESK
27
PRAB5
63
REF
99
TXPD-
135
SHFBUSY
28
PRAB6
64
DVSS12
100
TXD-
136
BPCS
29
PRAB7
65
SROE
101
TXPD+
137
EECS
30
PRAB8
66
SMAM
102
TXD+
138
TDI
31
PRAB9
67
IOR
103
AVDD3
139
TDO
32
DVSS6
68
IOW
104
XTAL1
140
TMS
33
PRAB10
69
IRQ9
105
AVSS2
141
TCK
34
PRAB11
70
RESET
106
XTAL2
142
DVDD2
35
NC
71
PCMCIA_MODE
107
NC
143
NC
36
NC
72
NC
108
NC
144
NC
Am79C961A
35
PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144)
Listed by Pin Name
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
AEN
48
EECS
137
PRAB13
40
SA7
12
AVDD1
113
IOCHRDY
49
PRAB14
41
SA8
13
AVDD2
118
IOCS16
58
PRAB15
42
SA9
14
AVDD3
103
IOR
67
PRAB2
23
SBHE
19
AVDD4
98
IOW
68
PRAB3
25
SD0
76
AVSS1
110
IRQ10
57
PRAB4
26
SD1
78
AVSS2
105
IRQ11
55
PRAB5
27
SD10
82
BPAM
59
IRQ12
54
PRAB6
28
SD11
84
BPCS
136
IRQ15
53
PRAB7
29
SD12
87
CI+
117
IRQ3
60
PRAB8
30
SD13
89
CI–
116
IRQ4
61
PRAB9
31
SD14
92
DI+
115
IRQ5
62
PRDB0/EESK
134
SD15
94
DI–
114
IRQ9
69
PRDB1/EEDI
133
SD2
81
DO+
112
LED0
124
PRDB2/EEDO
132
SD3
83
DO–
111
LED1
123
PRDB3
131
SD4
86
DVDD1
125
LED2
121
PRDB4
129
SD5
88
DVDD2
142
LED3
120
PRDB5
128
SD6
91
DVDD3
20
MEMR
51
PRDB6
127
SD7
93
DVDD4
38
MEMW
50
PRDB7
126
SD8
77
DVDD5
56
NC
1
REF
63
SD9
79
DVDD6
74
NC
35
RESET
70
SHFBUSY
135
DVDD7
85
NC
36
RXD+
97
SLEEP
75
DVSS1
122
NC
37
RXD–
96
SMAM
66
DVSS10
7
NC
72
SA0
4
SMA
3
DVSS11
52
NC
73
SA1
5
SROE
65
DVSS12
64
NC
107
SA10
16
SRWE
47
DVSS13
95
NC
108
SA11
17
TCK
141
DVSS2
130
NC
109
SA12
18
TDI
138
DVSS3
2
NC
143
SA13
44
TDO
139
DVSS4
15
NC
144
SA14
45
TMS
140
DVSS5
24
PCMCIA_MODE
71
SA15
46
TXD+
102
DVSS6
32
PRAB0
21
SA2
6
TXD–
100
DVSS7
43
PRAB1
22
SA3
8
TXPD+
101
DVSS8
80
PRAB10
33
SA4
9
TXPD–
99
DVSS9
90
PRAB11
34
SA5
10
XTAL1
104
DXCVR/EAR
119
PRAB12
39
SA6
11
XTAL2
106
36
Am79C961A
BLOCK DIAGRAM: PCMCIA MODE
REG
CE2
CE1
RCV
FIFO
WAIT
INPACK
STSCHG
IORD
IOWR
PCMCIA Bus
Interface
Unit
IREQ
IOIS16
802.3
MAC
Core
CI±
Encoder/
Decoder
(PLS) &
AUI Port
XMT
FIFO
OE
DXCVR/EAR
DI±
XTAL1
XTAL2
DO±
WE
RXD±
VCC
10BASE-T
MAU
RESET
A[0-15]
FIFO
Control
D[0-15]
PCMCIA_MODE
SMA
SLEEP
Optional
SMAM
SHFBUSY
EEDO
EEDI
EESK
EECS
Private
Bus
Control
Buffer
Management
Unit
TXD±
TXPD±
FLCS
LED[0-3]
PRAB[0-15]
PRDB[0–7]
SROE
SRWE
SRCS
TDO
JTAG
Port
Control
EEPROM
Interface
Unit
TMS
TDI
TCK
DVDD[1-7]
DVSS[1-13]
AVDD[1-4]
AVSS[1-2]
19364B-6
Am79C961A
37
PIN DESIGNATIONS: PCMCIA MODE (TQFP 144)
Listed by Pin Number
38
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
NC
37
NC
73
NC
109
NC
2
DVSS3
38
DVDD4
74
DVDD6
110
AVSS1
3
SMA
39
PRAB12
75
SLEEP
111
DO–
4
SA0
40
PRAB13
76
SD0
112
DO+
5
SA1
41
PRAB14
77
SD8
113
AVDD1
6
SA2
42
PRAB15
78
SD1
114
DI–
7
DVSS10
43
DVSS7
79
SD9
115
DI+
8
SA3
44
SA13
80
DVSS8
116
CI–
9
SA4
45
SA14
81
SD2
117
CI+
10
SA5
46
SA15
82
SD10
118
AVDD2
11
SA6
47
SRWE
83
SD3
119
DXCVR/EAR
12
SA7
48
REG
84
SD11
120
LED3
13
SA8
49
WAIT
85
DVDD7
121
LED2
14
SA9
50
WE
86
SD4
122
DVSS1
15
DVSS4
51
OE
87
SD12
123
LED1
16
SA10
52
DVSS11
88
SD5
124
LED0
17
SA11
53
NC
89
SD13
125
DVDD1
18
SA12
54
SRCS
90
DVSS9
126
PRDB7
19
CE2
55
INPACK
91
SD6
127
PRDB6
20
DVDD3
56
DVDD5
92
SD14
128
PRDB5
21
PRAB0
57
STSCHG
93
SD7
129
PRDB4
22
PRAB1
58
IOIS16
94
SD15
130
DVSS2
23
PRAB2
59
CE1
95
DVSS13
131
PRDB3
24
DVSS5
60
IREQ
96
RXD–
132
PRDB2/EEDO
25
PRAB3
61
NC
97
RXD+
133
PRDB1/EEDI
26
PRAB4
62
NC
98
AVDD4
134
PRDB0/EESK
27
PRAB5
63
REF
99
TXPD–
135
SHFBUSY
28
PRAB6
64
DVSS12
100
TXD–
136
FLCS
29
PRAB7
65
SROE
101
TXPD+
137
EECS
30
PRAB8
66
SMAM
102
TXD+
138
TDI
31
PRAB9
67
IORD
103
AVDD3
139
TDO
32
DVSS6
68
IOWR
104
XTAL1
140
TMS
33
PRAB10
69
NC
105
AVSS2
141
TCK
34
PRAB11
70
RESET
106
XTAL2
142
DVDD2
35
NC
71
PCMCIA_MODE
107
NC
143
NC
36
NC
72
NC
108
NC
144
NC
Am79C961A
PIN DESIGNATIONS: PCMCIA MODE (TQFP 144)
Listed by Pin Name
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
AVDD1
113
INPACK
55
PRAB4
26
SD1
78
AVDD2
118
IOIS16
58
PRAB5
27
SD10
82
AVDD3
103
IORD
67
PRAB6
28
SD11
84
AVDD4
98
IOWR
68
PRAB7
29
SD12
87
AVSS1
110
IREQ
60
PRAB8
30
SD13
89
AVSS2
105
LED0
124
PRAB9
31
SD14
92
CE1
59
LED1
123
PRDB0/EESK
134
SD15
94
CE2
19
LED2
121
PRDB1/EEDI
133
SD2
81
CI+
117
LED3
120
PRDB2/EEDO
132
SD3
83
CI–
116
NC
1
PRDB3
131
SD4
86
DI+
115
NC
35
PRDB4
129
SD5
88
DI–
114
NC
36
PRDB5
128
SD6
91
DO+
112
NC
37
PRDB6
127
SD7
93
DO–
111
NC
53
PRDB7
126
SD8
77
DVDD1
125
NC
61
REF
63
SD9
79
DVDD2
142
NC
62
REG
48
SHFBUSY
135
DVDD3
20
NC
69
RESET
70
SLEEP
75
DVDD4
38
NC
72
RXD+
97
SMAM
64
DVDD5
56
NC
73
RXD–
96
SMAM
66
DVDD6
74
NC
107
SA0
4
SRCS
54
DVDD7
85
NC
108
SA1
5
SROE
65
DVSS1
122
NC
109
SA10
16
SRWE
47
DVSS10
7
NC
143
SA11
17
STSCHG
57
DVSS11
52
NC
144
SA12
18
TCK
141
DVSS13
95
OE
51
SA13
44
TDI
138
DVSS2
130
PCMCIA_MODE
71
SA14
45
TDO
139
DVSS3
2
PRAB0
21
SA15
46
TMS
140
DVSS4
15
PRAB1
22
SA2
6
TXD+
102
DVSS5
24
PRAB10
33
SA3
8
TXD–
100
DVSS6
32
PRAB11
34
SA4
9
TXPD+
101
DVSS7
43
PRAB12
39
SA5
10
TXPD–
99
DVSS8
80
PRAB13
40
SA6
11
VSS
3
DVSS9
90
PRAB14
41
SA7
12
WAIT
49
DXCVR/EAR
119
PRAB15
42
SA8
13
WE
50
EECS
137
PRAB2
23
SA9
14
XTAL1
104
FLCS
136
PRAB3
25
SD0
76
XTAL2
106
Am79C961A
39
PIN DESCRIPTION: PCMCIA MODE
The PCMCIA pins function as described in the
PCMCIA Specification Revision 2.1. Please refer to it
for more details.
The non-PCMCIA pins used by the 144-pin TQFP
package have the same functions as described by “Pin
Description: Bus Slave Mode” for ISA operation beginning on page 26 of the Am79C961A PCnet-ISA II data
sheet (PID #19364A) with the exception of pin 71,
PCMCIA_MODE.
PCMCIA_MODE
Input
Sets the device for PCMCIA operation when tied high.
This pin is not available in the 132-pin PQFP package
option.
40
Am79C961A
PCMCIA vs. ISA Pinout Comparison
The pins listed below are pin definition changes specific to PCMCIA mode: In PCMCIA mode, a number of
the input pins have internal resistors turned on with a
resistance greater than 100 KΩ. These resistors are either connected to V CC or V SS. The diagram below
shows the pin connections for the ISA slave mode and
PCMCIA mode.
Pin Number
TQFP144
ISA
Slave Mode
PCMCIA
Mode
PCMCIA
Input Pin Resistance
> 100 KΩ
19
SBHE
CE2
to VCC
48
AEN
REG
to VCC
49
IOCHRDY
WAIT
50
MEMW
WE
to VCC
51
MEMR
OE
to VCC
53
IRQ15
NC
54
IRQ12
SRCS
55
IRQ11
INPACK
57
IRQ10
STSCHG
58
IOCS16
IOIS16
59
BPAM
CE1
60
IRQ3
IREQ
61
IRQ4
NC
62
IRQ5
NC
67
IOR
IORD
to VCC
68
IOW
IOWR
to VCC
69
IRQ9
NC
70
RESET
to VCC
RESET
1
to VCC
2
71
PCMCIA_MODE
PCMCIA_MODE
75
SLEEP
SLEEP3
SD0–SD15
D0–D15
to GND
SA0–SA15
A0–A15
to GND
PCMCIA Pin Specification Changes
In ISA mode, the IOCHRDY and IOCS16 signals are
defined as Open Drain outputs. In PCMCIA mode,
the WAIT and IOIS16 signals are full CMOS drivers. In
PCMCIA mode, the Max values for t IOR8, t MR8 and
tSFR10 change from 10 ns to –40 ns.
— PCMCIA-MODE1 should be tied to VSS in ISA
slave mode
— PCMCIA-MODE2 should be tied to VCC in
PCMCIA mode
— SLEEP3 pin remains functional in PCMCIA
mode, it is recommended to tie it to VCC
Am79C961A
41
PCMCIA MODE BLOCK DIAGRAM
[0]
PRDB[0–7]
SA[0–15]
System Address
Bus
FLCS
PCMCIA
Bus
PCnet-ISA II
Controller
PCMCIA Control
A[1–19]
D[0–7]
A[0]
WE
Flash/EPROM
120 ns
OE
CS
SROE
PRAB[0–15]
D[0–7]
A[0–15]
SRWE
16-Bit System
Data
SD[0–15]
SRCS
SMAM
WE
CS
SRAM
70 ns
OE
(Upper Address pin)
19364B-7
Note:
SMAM shown only for Shared Memory architecture designs. SMAM should be tied HIGH on the PCnet-ISA II for Programmed
I/O architecture designs in order to access the flash memory at common memory location zero.
Plug and Play Compatible with Flash Memory Support
42
Am79C961A
FUNCTIONAL DESCRIPTION
PCMCIA Operation
EEPROM. For cost purposes, it is recommended to
place the IEEE address in the CIS (Card Information
Structure) Attribute Memory.
When a PCMCIA card is first plugged into a PCMCIA
host, all PCMCIA cards respond as a memory only
device. In the PCMCIA standard there are two memory
spaces, common memory and attribute memory. The
REG pin determines which memory space is selected.
After the host detects that the PCMCIA card is inserted,
the host reads a section of the attribute memory called the
CIS (Card Information Structure) which provides
configuration information about the inserted card. The
attribute memory is a byte wide memory which is only
addressable on even bytes. Consequently, odd byte
accesses are not defined for attribute memory. Mapped in
the CIS area are four Card Configuration Registers which
are physically located inside the PCnet-ISA II device. In
the PCnet-ISA II device there are four registers which are
located at decimal byte address 1008, 1010, 1012 and
1014, respectively. Inside the CIS data structure, there is
information which provides the base address of the Card
Configuration Registers.
Inside first Card Configuration Register is a configuration index region which allows programming the device
to support I/O accesses. The PCnet-ISA II supports
PCMCIA’s Independent I/O address window mechanism. When I/O Enable is set in the CCR 0 register the
PCnet-ISA II controller will respond to I/O commands.
The lower 5 address bits decode register accesses.
The PCMCIA host is expected to decode I/O address
bits 6 and above and only assert CE1 and/or CE2 if the
upper I/O address lines match. After the host has
mapped the PCMCIA’s card resources to the system,
the card should be visible by the system and the driver
may be loaded.
Flash Memory Map
The PCnet-ISA II device supports either a single Flash or
EPROM device. The external flash device contains the
CIS area as well as an area located in common memory
used to hold software drivers. The attribute memory origin is located at byte 0. The common memory region is
accessed when REG is deasserted and an access to
common memory occurs. SMAM is normally connected
to an upper address line on the PCMCIA card. When a
high order address is asserted the Flash Memory will be
selected. Accesses to common memory when SMAM is
low will access the Shared RAM when Shared Memory
mode is selected. If Programmed I/O mode is used, the
SMAM can be tied high which will result in the Flash’s
base address being mapped to location zero.
Flash Memory Programming
The Flash Memory device can be read at anytime. In
order to program the flash device, the APWEN bit must
be set in ISACSR2 register to allow write operations to
the Flash or non-volatile EEPROM device.
Shared Memory vs. Programmed I/O
Implications
The PCnet-ISA II controller in PCMCIA modes allows for
the local packet buffer memory to be mapped into common memory or indirectly accessed through I/O accesses. If shared memory is chosen, the local SRAM will
be mapped as a memory resource. Consequently, the
CIS will have to indicate this requirement to the system.
If Programmed I/O is used no additional memory resources will be required to be allocated by the system.
Serial EEPROM Support
The Serial EEPROM is not required in PCMCIA mode
but can be used to hold the contents of the IEEE address
Am79C961A
43
FLASH MEMORY MAP AND CARD REGISTERS
131070 Byte (1FFFEh)
FLASH
Common
Memory
Common Memory
1024 Byte (400h)
1022 Byte (3FEh)
Reserved
1016 Byte (3F8h)
Attribute Memory
CCR 3
1014 Byte (3F6h)
CCR 2
1012 Byte (3F4h)
CCR 1
1010 Byte (3F2h)
CCR 0
1008 Byte (3F0h)
1006 Byte (3EEh)
(Not Available)
CIS
Data
(Unused)
0 Byte (0h)
19364B-8
44
Am79C961A
FUNCTIONAL DESCRIPTION
The PCnet-ISA II controller is a highly integrated system
solution for the PC-AT ISA architecture. It provides a Full
Duplex Ethernet controller, AUI port, and 10BASE-T
transceiver. The PCnet-ISA II controller can be directly interfaced to an ISA system bus. The PCnet-ISA II controller contains an ISA bus interface unit, DMA Buffer
Management Unit, 802.3 Media Access Control function,
separate 136-byte transmit and 128-byte receive FIFOs,
IEEE defined Attachment Unit Interface (AUI), and
Twisted-Pair Transceiver Media Attachment Unit. In addition, a Sleep function has been incorporated which provides low standby current for power sensitive applications.
The PCnet-ISA II controller is register compatible with
the LANCE (Am7990) Ethernet controller and PCnet-ISA (Am79C960). The DMA Buffer Management
Unit supports the LANCE descriptor software model
and the PCnet-ISA II controller is software compatible
with the Novell NE2100 and NE1500T add-in cards.
External remote boot PROMs and Ethernet physical
address PROMs are supported. The location of the I/O
registers, Ethernet address PROM, and the boot PROM
are determined by the programming of the registers internal to PCnet-ISA II. These registers are loaded at
RESET from the EEPROM, if an EEPROM is utilized.
Normally, the Ethernet physical address will be stored in
the EEPROM with the other configuration data. This
reduces the parts count, board space requirements,
and power consumption. The option to use a standard
parallel 8 bit PROM is provided to manufactures who
are concer ned about the non-volatile nature of
EEPROMs.
The PCnet-ISA II controller’s bus master architecture
brings to system manufacturers (adapter card and
motherboard makers alike) something they have not
been able to enjoy with other architectures—a low-cost
system solution that provides the lowest parts count
and highest performance. As a bus-mastering device,
costly and power-hungry external SRAMs are not
needed for packet buffering. This results in lower system cost due to fewer components, less real-estate and
less power. The PCnet-ISA II controller’s advanced bus
mastering architecture also provides high data throughput and low CPU utilization for even better performance.
To offer greater flexibility, the PCnet-ISA II controller has
a Bus Slave mode to meet varying application needs.
The bus slave mode utilizes a local SRAM memory to
store the descriptors and buffers that are located in system memory when in Bus Master mode. The SRAM can
be slave accessed on the ISA bus through memory
cycles in Shared Memory mode or I/O cycles in Programmed I/O mode. The Shared Memory and Programmed I/O architectures offer maximum compatibility
with low-end machines, such as PC/XTs that do not
support bus mastering, and very high end machines
which require local packet buffering for increased
system latency.
The network interface provides an Attachment Unit
Interface and Twisted-Pair Transceiver functions. Only
one interface is active at any particular time. The AUI
allows for connection via isolation transformer to
10BASE5 and 10BASE2, thick and thin based coaxial
cables. The Twisted-Pair Transceiver interface allows
for connection of unshielded twisted-pair cables as
specified by the Section 14 supplement to IEEE 802.3
Standard (Type 10BASE-T).
Important Note About The EEPROM
Byte Map
The user is cautioned that while the Am79C961A (PCnet-ISA II) and its associated EEPROM are pin compatible
to their predecessors the Am79C961 (PCnet-ISA+) and its
associated EEPROM, the byte map structure in each of
the EEPROMs are different from each other.
The EEPROM byte map structure used for the
Am79C961A PCnet-ISA II has the addition of “MISC Config 2, ISACSR9" at word location 10Hex. The EEPROM
byte map structure used for the Am79C961 PCnet-ISA+
does not have this.
Therefore, should the user intend to replace the PCnet-ISA+ with the PCnet-ISA II, care MUST be taken to reprogram the EEPROM to reflect the new byte map
structure needed and used by the PCnet-ISA II. For additional information, refer to the section in this data sheet
under EEPROM and the Am79C961 PCnet-ISA+ data
sheet (PID #18183) under the sections entitled EEPROM
and Serial EEPROM Byte Map.
Bus Master Mode
System Interface
The PCnet-ISA II controller has two fundamental operating modes, Bus Master and Bus Slave. Within the Bus
Slave mode, the PCnet-ISA II can be programmed for a
Shared Memory or Programmed I/O architecture. The
selection of either the Bus Master mode or the Bus
Slave mode must be done through hard wiring; it is not
software configurable. When in the Bus Slave mode, the
selection of the Shared Memory or Programmed I/O
architecture is done through software with the PIOSEL
bit (ISACSR2, bit 13).
The optional Boot PROM is in memory address space
and is expected to be 8–64K. On-chip address comparators control device selection is based on the value in
the EEPROM.
The address PROM, board configuration registers, and
the Ethernet controller occupy 24 bytes of I/O space
and can be located at 16 different starting addresses.
Am79C961A
45
CE
BPCS
16-Bit
System Data
PRDB[0-7]
D[0-7]
SD[0-15]
ISA
Bus
PRDB[2]/EEDO
PCnet-ISA II PRDB[1]/EEDI
Controller PRDB[0]/EESK
DO
DI
SK
CS
EECS
SHFBUSY
Boot
PROM
(Optional)
A[0-15]
24-Bit System
Address
SA[0-19]
LA[17-23]
OE
EEPROM
(Optional,
Common)
VCC
ORG
VCC
19364B-9
Bus Master Block Diagram Plug and Play Compatible
BPCS
PRDB[0-7]
SD[0-15]
16-Bit
System
Data
PCnet-ISA II
Controller
24-Bit
System
Address
ISA
Bus
IEEE
Address
PROM
(Optional)
G
PRDB[0]/EESK
PRDB[1]/EEDI
PRDB[2]/EEDO
SA[0-19]
LA[17-23]
A[0-4]
D[0-7]
EECS
A[0-15]
D[0-7]
Flash
(Optional)
IRQ15/APCS IRQ12/FlashWE SHFBUSY
VCC
WE
OE
CS
SK
DI
DO
CS
EEPROM
(Optional,
Common)
VCC
ORG
19364B-10
Bus Master Block Diagram Plug and Play Compatible
with Flash and parallel Address PROM Support
46
Am79C961A
Bus Slave Mode
System Interface
The Bus Slave mode is the other fundamental operating mode available on the PCnet-ISA II controller.
Within the Bus Slave mode, the PCnet-ISA II can be
programmed for a Shared Memory or Programmed I/O
architecture. In the Bus Slave mode the PCnet-ISA II
controller uses the same descriptor and buffer architecture as in the Bus Master mode, but these data structures are stored in a static RAM controlled by the
PCnet-ISA II controller. When operating with the
Shared Memory architecture, the local SRAM is visible
as a memory resource on the PC which can be
accessed through memory cycles on the ISA bus interface. When operating with the Programmed I/O architecture, the local SRAM is accessible through I/O
cycles on the ISA bus. Specifically, the SRAM is accessible using the RAP and IDP I/O ports to access the
ISACSR0 and ISACSR1 registers, which serve as the
SRAM Data port and SRAM Address Pointer port,
respectively.
In the Bus Slave mode, the PCnet-ISA II registers and
optional Ethernet physical address PROM look the
same and are accessed in the same way as in the Bus
Master mode.
The Boot PROM is selected by an external device
which drives the Boot PROM Address Match (BPAM)
input to the PCnet-ISA II controller. The PCnet-ISA II
controller can perform two 8-bit accesses from the 8-bit
Boot PROM and present 16-bits of data to accommodate 16 bit read accesses on the ISA bus.
When using the Shared Memory architecture mode,
access to the local SRAM works the same way as
access to the Boot PROM, with an external device generating the Shared Memory Address Match (SMAM)
signal and the PCnet-ISA II controller performing the
SRAM read or write and the 8/16 bit data conversion.
The Programmed I/O architecture mode uses the RAP
and IDP ports to allow access to the local SRAM
hence, external address decoding is not necessary and
the SMAM pin is not used in Programmed I/O architecture mode (SMAM should be tied HIGH in the Programmed I/O architecture mode). Similar to the Shared
Memory architecture mode, in the Programmed I/O architecture mode, 8/16 bit conversion occurs when 16
bit reads and writes are performed on the SRAM Data
Port (ISACSR1).
Converting the local SRAM accesses from 8-bit cycles
to 16-bit cycles allows use of the much faster 16-bit
cycle timing while cutting the number of bus cycles in
half. This raises performance to more than 400% of
what could be achieved with 8-bit cycles. When the
Shared Memory architecture mode is used, converting
boot PROM accesses to 16-bit cycles allows the two
memory resources to be in the same 128 Kbyte block
of memory without a clash between two devices with
different data widths.
The PCnet-ISA II prefetches data from the SRAM to
allow fast, minimum wait-state read accesses of consecutive SRAM addresses. In both the Shared Memory
architecture and the Programmed I/O architecture,
prefetch data is read from a speculated address that
assumes that successive reads in time will be from
adjacent ascending addresses in the SRAM. At the
beginning of each SRAM read cycle, the PCnet-ISA II
determines whether the prefetched data can be
assumed to be valid. If the prefetched data can be
assumed to be valid, it is driven onto the ISA bus
without inserting any wait states. If the prefetched data
cannot be assumed to be valid, the PCnet-ISA II will insert wait states into the ISA bus read cycle until the
correct word is read from the SRAM.
External logic must also drive MEMCS16 appropriately
for the 128Kbyte segment decoded from the LA[23:17]
signals.
Am79C961A
47
A[0–15]
PRAB[0-15]
16-Bit
System Data
PRDB[0]
WE
BPCS
SROE
CS
PRDB[2]/EEDO
DO
PRDB[1]/EEDI
DI
PRDB[0]/EESK
SK
EECS
SRWE
SHFBUSY SMAM BPAM IRQ12/SRCS
CS
SD[0]
PCnet-ISA II
Controller
24-Bit System
Address
SA[0]
ISA
Bus
D[0–7]
Flash
(Optional)
OE
EEPROM
VCC
ORG
OE
A[0-15]
SRAM
WE
CS
SIN
D[0-7]
MEMCS16
CLK
VCC
External
Glue
Logic
SMAM
BPAM
SHFBUSY
SA[16] LA[17-23]
19364B-11
Note:
SMAM shown only for Shared Memory architecture designs. SMAM should be tied HIGH on the PCnet-ISA II for Programmed
I/O architecture designs.
Bus Slave Block Diagram
Plug and Play Compatible with Flash Memory Support
48
Am79C961A
PLUG AND PLAY
Plug and Play is a standardized method of configuring
jumperless adapter cards in a system. Plug and Play is
a Microsoft standard and is based on a central software
configuration program, either in the operating system
or elsewhere, which is responsible for configuring all
Plug and Play cards in a system. Plug and Play is fully
supported by the PCnet-ISA II ethernet controller.
For a copy of the Microsoft Plug and Play specification
contact Microsoft Inc. This specification should be
referenced in addition to PCnet-ISA II Technical
Reference Manual and this data sheet.
Operation
If the PCnet-ISA II ethernet controller is used to boot off
the network, the device will come up active at RESET,
otherwise it will come up inactive. Information stored in
the serial EEPROM is used to identify the card and to
describe the system resources required by the card,
such as I/O space, Memory space, IRQs and DMA
channels. This information is stored in a standardized
Read Only format. Operation of the Plug and Play
system is shown as follows:
■ Isolate the Plug and Play card
■ Read the cards resource data
Port Name
Location
Type
ADDRESS
0X279 (Printer Status Port)
Write-only
WRITE-DATA
0xA79 (Printer status port +
0x0800)
Write-only
READ-DATA
Relocatable in range
0x0203-0x03FF
Read-only
The address and Write_DATA ports are located at
fixed, predefined I/O addresses. The Write_Data port is
located at an alias of the Address port. All three
auto-configuration ports use a 12-bit ISA address
decode.
The READ_DATA port is relocatable within the range
0 x 2 0 3 – 0 x 3 F F by a c o m m a n d w r i t t e n t o t h e
WRITE_DATA port.
ADDRESS PORT
The internal Plug and Play registers are accessed by
writing the address to the ADDRESS PORT and then
either reading the READ_DATA PORT or writing to the
WRITE_DATA PORT. Once the ADDRESS PORT has
been written, any number of reads or writes can occur
without having to rewrite the ADDRESS PORT.
■ Identify the card
The ADDRESS PORT is also the address to which the
initiation key is written to, which is described later.
■ Configure its resources
WRITE_DATA PORT
The Plug and Play mode of operation allows the following benefits to the end user.
The WRITE_DATA PORT is the address to which all
writes to the internal Plug and Play registers occur. The
destination of the data written to the WRITE_DATA
PORT is determined by the last value written to the
ADDRESS PORT.
■ Eliminates all jumpers or dip switches from the
adapter card
■ Ease of use is greatly enhanced
READ_DATA PORT
■ Allows the ability to uniquely address identical cards
in a system, without conflict
■ Allows the software configuration program or OS to
read out the system resource requirements
required by the card
The READ_DATA PORT is used to read information
from the internal Plug and Play registers. The register
to be read is determined by the last value of the
ADDRESS PORT.
■ Maintain backward compatibility with other ISA bus
adapters
The I/O address of the READ_DATA PORT is set by
writing the chosen I/O location to Plug and Play Register 0. The isolation protocol can determine that the
address chosen is free from conflict with other devices
I/O ports.
Auto-Configuration Ports
Initiation Key
Three 8 bit I/O ports are used by the Plug and Play configuration software on each Plug and Play device to
communicate with the Plug and Play registers. The
ports are listed in the table below. The software configuration space is defined as a set of 8 bit registers.
These registers are used by the Plug and Play software
configuration to issue commands, access the resource
information, check status, and configure the PCnet-ISA
II controller hardware.
The PCnet-ISA II controller is disabled at reset when
operating in Plug and Play mode. It will not respond to
any memory or I/O accesses, nor will the PCnet-ISA II
controller drive any interrupts or DMA channels.
■ Defines a mechanism to set or modify the current
configuration of each card
The initiation key places the PCnet-ISA II device into
the configuration mode. This is done by writing a predefined pattern to the ADDRESS PORT. If the proper
sequence of I/O writes are detected by the PCnet-ISA
II device, the Plug and Play auto-configuration ports
Am79C961A
49
are enabled. This pattern must be sequential, i.e., any
other I/O access to this I/O port will reset the state
machine which is checking the pattern. Interrupts
should be disabled during this time to eliminate any
extraneous I/O cycles.
The exact sequence for the initiation key is listed below
in hexadecimal.
6A, B5, DA, ED, F6, FB, 7D, BE
DF, 6F, 37, 1B, 0D, 86, C3, 61
The key element of this mechanism is that each card
contains a unique number, referred to as the serial
identifier for the rest of the discussion. The serial identifier is a 72-bit unique, non-zero, number composed of
two, 32-bit fields and an 8-bit checksum. The first 32-bit
field is a vendor identifier. The other 32 bits can be any
value, for example, a serial number, part of a LAN
address, or a static number, as long as there will never
be two cards in a single system with the same 64 bit
number. The serial identifier is accessed bit-serially by
the isolation logic and is used to differentiate the cards.
B0, 58, 2C, 16, 8B, 45, A2, D1
E8, 74, 3A, 9D, CE, E7, 73, 39
Isolation Protocol
Checksum
A simple algorithm is used to isolate each Plug and
Play card. This algorithm uses the signals on the ISA
bus and requires lock-step operation between the Plug
and Play hardware and the isolation software.
Serial
Vendor
Number
ID
Byte Byte Byte Byte Byte Byte Byte Byte Byte
0
3
2
1
0
3
2
1
0
Shift
19364B-13
Shifting of Serial Identifier
State
Isolation
Read from serial
isolation register
Yes
Get one bit from
serial identifier
Hardware Protocol
ID bit = “1H”
Drive “55H”
on SD[7:0]
The shift order for all Plug and Play serial isolation and
resource data is defined as bit[0], bit[1], and so on
through bit[7].
No
The isolation protocol can be invoked by the Plug and
Play software at any time. The initiation key, described
earlier, puts all cards into configuration mode. The
hardware on each card expects 72 pairs of I/O read
accesses to the READ_DATA por t. The card’s
response to these reads depends on the value of each
bit of the serial identifier which is being examined one
bit at a time in the sequence shown above.
Leave SD in
high-impedance
No
SD[1:0] = “01"
Yes
Wait for next read from serial isolation register
Drive “AAH”
on SD[7:0]
Leave SD in
high-impedance
No
After I/O read
completes, fetch
next ID bit from
serial identifier
No
Read all 72 bits
from serial
identifier
SD[1:0] = “10"
Yes
ID = 0;
other card
ID = 1
If a high impedance card sensed another card driving
the data bus with the appropriate data during both
cycles, then that card ceases to participate in the current iteration of card isolation. Such cards, which lose
out, will participate in future iterations of the isolation
protocol.
State
Sleep
Yes
One
Card
Isolated
Plug and Play ISA Card
Isolation Algorithm
50
If the current bit of the serial identifier is a “1", then the
card will drive the data bus to 0x55 to complete the first
I/O read cycle. If the bit is “0", then the card puts its data
bus driver into high impedance. All cards in high impedance will check the data bus during the I/O read cycle
to sense if another card is driving D[1:0] to “01". During
the second I/O read, the card(s) that drove the 0x55,
will now drive a 0xAA. All high impedance cards will
check the data bus to sense if another card is driving
D[1:0] to “10". Between pairs of Reads, the software
should wait at least 30 µs.
19364B-12
Note: During each read cycle, the Plug and Play hardware drives the entire 8-bit databus, but only checks
the lower 2 bits.
Am79C961A
If a card was driving the bus or if the card was in high
impedance and did not sense another card driving the
bus, then it should prepare for the next pair of I/O
reads. The card shifts the serial identifier by one bit and
uses the shifted bit to decide its response. The above
sequence is repeated for the entire 72-bit serial
identifier.
At the end of this process, one card remains. This card
is assigned a handle referred to as the Card Select
Number (CSN) that will be used later to select the card.
Cards which have been assigned a CSN will not participate in subsequent iterations of the isolation protocol.
Cards must be assigned a CSN before they will
respond to the other commands defined in the
specification.
It should be noted that the protocol permits the 8-bit
checksum to be stored in non-volatile memory on the
card or generated by the on-card logic in real-time. The
same LFSR algorithm described in the initiation key
section of the Plug and Play specification is used in the
checksum generation.
Software Protocol
The Plug and Play software sends the initiation key to
all Plug and Play cards to place them into configuration
mode. The software is then ready to perform the isolation protocol.
The Plug and Play software generates 72 pairs of l/O
read cycles from the READ_DATA port. The software
checks the data returned from each pair of I/O reads for
the 0x55 and 0xAA driven by the hardware. If both 0x55
and 0xAA are read back, then the software assumes
that the hardware had a “1" bit in that position. All other
results are assumed to be a “0.”
During the first 64 bits, software generates a checksum
using the received data. The checksum is compared
with the checksum read back in the last 8 bits of the
sequence.
There are two other special considerations for the software protocol. During an iteration, it is possible that the
0x55 and 0xAA combination is never detected. It is also
possible that the checksum does not match If either of
these cases occur on the first iteration, it must be
assumed that the READ_DATA port is in conflict. If a
conflict is detected, then the READ_DATA port is
relocated. The above process is repeated until a nonconflicting location for the READ_DATA port is found.
The entire range between 0x203 and 0x3FF is available, however in practice it is expected that only a few
locations will be tried before software determines that
no Plug and Play cards are present.
During subsequent iterations, the occurrence of either
of these two special cases should be interpreted as the
absence of any further Plug and Play cards (i.e. the last
card was found in the previous iteration). This
terminates the isolation protocol.
Note: The software must delay 1 ms prior to starting
the first pair of isolation reads, and must wait 250 µsec
between each subsequent pair of isolation reads. This
delay gives the ISA card time to access information
from possibly very slow storage devices.
Plug and Play Card Control Registers
The state transitions and card control commands for
the PCnet-ISA II controller are shown in the following
figure.
Am79C961A
51
Power up
RESET_DRV
Set CSN = 0
State
Active Commands
Wait for Key
no active commands
Initiation Key
State
Active Commands
Reset
Wait for Key
Wake[CSN]
Sleep
Lose serial location OR WAKE <> CSN
(WAKE <> CSN)
State
Isolation
Active Commands
Reset
Wait for Key
Set RD_DATA Port
Serial Isolation
Wake[CSN]
State
Set CSN
Config
Active Commands
Reset
Wait for Key
Wake[CSN]
Resource Data
Status
Logical Device
I/O Range Check
Activate
Configuration Registers
Notes:
1. CSN = Card Select Number.
2. RESET_DRV causes a state transition from the current state to Wait for Key and sets all CSNs to
zero. All logical devices are set to their power-up configuration values.
3. The Wait for Key command causes a state transition from the current state to Wait for Key.
19364B-13
Plug and Play ISA Card State Transitions
Plug and Play Registers
The PCnet-ISA II controller supports all of the defined
Plug and Play card control registers. Refer to the tables
on the following pages for detailed information.
52
Am79C961A
Plug and Play Standard Registers
Name
Set RD_DATA Port
Address
Port Value
0x00
Definition
Writing to this location modifies the address of the port used for reading from the
Plug and Play ISA cards. Bits[7:0] become I/O read port address bits [9:2].
Reads from this register are ignored. I/O Address bits 11:10 should = 00, and 1:0 = 11.
Serial Isolation
0x01
A read to this register causes a Plug and Play card in the Isolation state to
compare one bit of the board’s ID. This process is fully described above. This
register is read only.
Config Control
0x02
Bit[0] - Reset all logical devices and restore configuration registers to their
power-up values.
Bit[1] - Return to the Wait for Key state
Bit[2] - Reset CSN to 0
A write to bit[0] of this register performs a reset function on all logical devices.
This resets the contents of configuration registers to their default state. All card’s
logical devices enter their default state and the CSN is preserved.
A write to bit[1] of this register causes all cards to enter the Wait for Key state but
all CSNs are preserved and logical devices are not affected.
A write to bit[2] of this register causes all cards to reset their CSN to zero.
This register is write-only. The values are not sticky, that is, hardware will
automatically clear them and there is no need for software to clear the bits.
Wake[CSN]
0x03
A write to this port will cause all cards that have a CSN that matches the write
data[7:0] to go from the Sleep state to either the Isolation state if the write data
for this command is zero or the Config state if the write data is not zero. This
register is write-only. Writing to this register resets the EEPROM pointer to the
beginning of the Plug and Play Data Structure.
Resource Data
0x04
A read from this address reads the next byte of resource information. The Status
register must be polled until bit[0] is set before this register may be read. This
register is read-only.
Status
0x05
Bit[0] when set indicates it is okay to read the next data byte from the Resource
Data register. This register is read-only.
Card Select Number
0x06
A write to this port sets a card’s CSN. The CSN is a value uniquely assigned to
each ISA card after the serial identification process so that each card may be
individually selected during a Wake [CSN] command. This register is read/write.
Logical Device Number
0x07
Selects the current logical device. This register is read only. The PCnet-ISA II
controller has only 1 logical device, and this register contains a value of 0x00
Am79C961A
53
PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS
The PCnet-ISA II controller supports a subset of the
defined Plug and Play logical device control registers.
The reason for only supporting a subset of the registers
is that the PCnet-ISA II controller does not require as
many system resources as Plug and Play allows. For
instance, Memory Descriptor 2 is not used, as the PCnet-ISA II controller only requires two memor y
descriptors, one for the Boot PROM/Flash, and one for
the SRAM in Shared Memory Mode.
Plug and Play Logical Device Control Registers
Name
Address
Port Value
Definition
Activate
0x30
For each logical device there is one activate register that controls whether or
not the logical device is active on the ISA bus. Bit[0], if set, activates the logical
device. Bits[7:1] are reserved and must be zero. This is a read/write register.
Before a logical device is activated, I/O range check must be disabled.
I/O Range Check
0x31
This register is used to perform a conflict check on the I/O port range
programmed for use by a logical device.
Bit[7:2] Reserved
Bit 1[1] Enable I/O Range check, if set then I/O Range Check is enabled. I/O
range check is only valid when the logical device is inactive.
Bit[0], if set, forces the logical device to respond to I/O reads of the logical
device’s assigned I/O range with a 0x55 when I/O range check is in operation.
If clear, the logical device drives 0xAA. This register is read/write.
Memory Space Configuration
Name
Register
Index
Definition
Memory base address
bits[23:16] descriptor 0
0x40
Read/write value indicating the selected memory base address bits[23:16] for
memory descriptor 0. This is the Boot Prom Space.
Memory base address
bits [15:08] descriptor 0
0x41
Read/write value indicating the selected memory base address bits[15:08] for
memory descriptor 0.
Memory control
0x42
Bit[1] specifies 8/16-bit control. The encoding relates to memory control
(bits[4:3]) of the information field in the memory descriptor.
Bit[0], =0, indicates the next field is used as a range length for decode
(implies range length and base alignment of memory descriptor are equal).
Bit[0] is read-only.
Memory upper limit
address;
bits [23:16] or range
length;
bits [15:08] for
descriptor 0
0x43
Memory upper limit
bits [15:08] or range
length;
bits [15:08] for
descriptor 0
0x44
Memory descriptor 1
0x48-0x4C
Read/write value indicating the selected memory high address bits[23:16] for
memory descriptor 0.
If bit[0] of memory control is 0, this is the range length.
If bit[0] of memory control is 1, this is considered invalid.
Read/write value indicating the selected memory high address bits[15:08] for
memory descriptor 0, either a memory address or a range length as described
above.
Memory descriptor 1. This is the SRAM Space for Shared Memory.
I/O Space Configuration
Name
Register
Index
Definition
I/O port base address
bits[15:08] descriptor 0
0x60
Read/write value indicating the selected I/O lower limit address bits[15:08] for
I/O descriptor 0. If a logical device indicates it only uses 10 bit encoding, then
bits[15:10] do not need to be supported.
I/O port base address
bits[07:00] descriptor 0
0x61
Read/write value indicating the selected I/O lower limit address bits[07:00] for
I/O descriptor 0.
54
Am79C961A
I/O Interrupt Configuration
Name
Interrupt request level
select 0
Register
Index
0x70
Definition
Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt
level used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is
not a valid interrupt selection and represents no interrupt selection.
Read/write value indicating which type of interrupt is used for the Request Level
selected above.
Interrupt request type
select 0
0x71
Bit[1] : Level,
1 = high, 0 = low
Bit[0] : Type,
1 = level, 0 = edge
The PCnet-ISA II controller only supports Edge High and Level Low Interrupts.
DMA Channel Configuration
Name
Register
Index
Definition
DMA channel select 0
0x74
Read/write value indicating selected DMA channels. Bits[2:0] select which DMA
channel is in use for DMA 0. Zero selects DMA channel 0, seven selects DMA
channel 7. DMA channel 4, the cascade channel is used to indicate no DMA channel
is active.
DMA channel select 1
0x75
Read only with a value of 0x04.
DETAILED FUNCTIONS
EEPROM
Interface
The EEPROM supported by the PCnet-ISA II controller
is an industry standard 93C56 2-Kbit EEPROM device
which uses a 4-wire interface. This device directly interfaces to the PCnet-ISA II controller through a 4-wire
interface which uses 3 of the private data bus pins for
Data In, Data Out, and Serial Clock. The Chip Select
pin is a dedicated pin from the PCnet-ISA II controller.
Note: All data stored in the EEPROM is stored in bit-reversal format. Each word (16 bits) must be written into
the EEPROM with bit 15 swapped with bit 0, bit 14
swapped with bit 1, etc.
This is a 2-Kbit device organized as 128 x 16 bit words.
A map of the device as used in the PCnet-ISA II controller is below. The information stored in the EEPROM
is as follows:
IEEE address 6 bytes
Reserved10 bytes
EISA ID4 bytes
ISACSRs14 bytes
Plug and Play Defaults19 bytes
8-Bit Checksum1 byte
External Shift Chain2 bytes
Plug and Play Config Info192 bytes
Important Note About The EEPROM
Byte Map
The user is cautioned that while the Am79C961A (PCnet-ISA II) and its associated EEPROM are pin comp at i bl e t o th e i r p r e d ec es s o r s th e A m 7 9 C9 6 1
(PCnet-ISA+) and its associated EEPROM, the byte
map structure in each of the EEPROMs are different
from each other.
The EEPROM byte map structure used for the
Am79C961A PCnet-ISA II has the addition of “MISC
Config 2, ISACSR9" at word location 10Hex. The
EEPROM byte map structure used for the Am79C961
PCnet-ISA+ does not have this.
Therefore, should the user intend to replace the PCnet-ISA+ with the PCnet-ISA II, care MUST be taken to
reprogram the EEPROM to reflect the new byte map
structure needed and used by the PCnet-ISA II. For
additional information, refer to the Am79C961 PCnet-ISA+ data sheet (PID #18183) under the sections
entitled EEPROM and Serial EEPROM Byte Map.
Am79C961A
55
Basic EEPROM Byte Map
The following is a byte map of the XXC56 series of
EEPROMs used by the PCnet-ISA II Ether net
Controller. This byte map is for the case where a
non-PCnet Family compatible software driver is
implemented.
Byte 1
Byte 0
Word
Location
0
Byte 3
Byte 2
1
Byte 5
Byte 4
2
Byte 7
Byte 6
3
Byte 9
Byte 8
4
Byte 11
Byte 10
5
Byte 13
Byte 12
6
Byte 15
Byte 14
7
(8h)
EISA Byte 1
EISA Byte 0
8
EISA Config Reg.
EISA Byte 3
EISA Byte 2
9
IEEE Address (0h)
(Bytes 0 – 5)
(Ah)
MSRDA, ISACSR0
A
MSWRA, ISACSR1
B
MISC Config 1, ISACSR2
C
LED1 Config, ISACSR5
D
LED2 Config, ISACSR6
E
LED3 Config, ISACSR7
F
MISC Config 2, ISACSR9
10
Internal Registers
(11h)
Plug and Play Reg.
(1Ah)
PnP 0x61
PnP 0x60
11
I/O Ports
Pnp 0x71
PnP 0x70
12
Interrupts
Unused
PnP 0x74
13
DMA Channels
PnP 0x41
PnP 0x40
14
ROM Memory
PnP 0x43
PnP 0x42
15
Unused
PnP 0x44
16
PnP 0x49
PnP 0x48
17
PnP 0x4B
PnP 0x4A
18
Unused
PnP 0x4C
19
8–Bit Checksum
PnP 0xF0
56
Vendor Byte
(1Bh)
External Shift Chain
1B
(1Ch)
Unused Locations
1C
(20h)
Plug and Play Starting Location
1F
20
Note:
Checksum is calculated on words 0 through 0x1Bh (first 56 bytes).
Am79C961A
RAM Memory
..
AMD Device Driver Compatible
EEPROM Byte Map
PCnet Family compatible software driver is implemented.
The following is a byte map of the XXC56 series
of EEPROMs used by the PCnet-ISA II Ethernet
Controller. This byte map is for the case where a
(This byte map is an application reference for use in
developing AMD software devices.)
Word
Location
0
Byte 1
Byte 0
1
Byte 3
Byte 2
2
Byte 5
Byte 4
3
Reserved
Reserved
4
HWID (01H)
Reserved
EISA Config Reg.
Internal Registers
Plug and Play Reg.
5
User Space 1
6
16-Bit Checksum 1
7
ASCII W (0 x 57H)
ASCII W (0 x 57H)
8
EISA Byte 1
EISA Byte 0
9
EISA Byte 3
EISA Byte 2
A
MSRDA, ISACSR0
B
MSWRA, ISACSR1
C
MISC Config, ISACR2
D
LED1 Config, ISACSR5
E
LED2 Config, ISACSR6
F
LED3 Config, ISACSR7
10
MISC Config 2, ISACSR9
11
PnP 0x61
PnP 0x60
I/O Ports
12
Pnp 0x71
PnP 0x70
Interrupts
13
Unused
PnP 0x74
DMA Channels
14
PnP 0x41
PnP 0x40
ROM Memory
15
PnP 0x43
PnP 0x42
16
Unused
PnP 0x44
17
PnP 0x49
PnP 0x48
18
PnP 0x4B
PnP 0x4A
19
Unused
PnP 0x4C
1A
8-Bit Checksum
PnP 0xF0
1B
..
See Appendix C
IEEE Address
(Bytes 0–5)
RAM Memory
Vendor Byte
External Shift Chain
1C
Unused Locations
1F
20
Plug and Play Starting Location
See Appendix C
Note:
Checksum 1 is calculated on words 0 through 5 plus word 7.
Checksum 2 is calculated on words 0 through 0x1Bh (first 56 bytes).
Am79C961A
57
Plug and Play Register Map
Plug and Play operation. These registers control the
configuration of the PCnet-ISA II controller.
The following chart and its bit descriptions show the
internal configuration registers associated with the
Plug and
Play Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x00
READ_DATA
0x01
SERIAL ISOLATION
0x02
0
0
0
0
0
0x03
WAKE [CSN]
0x04
RESOURCE_DATA
0x05
0
0
0
0
0
0x06
CSN
0x07
LOGICAL DEVICE NUMBER
Bit 2
Bit 1
Bit 0
RST
CSN
WAIT
KEY
RST
ALL
0
0
READ
STATUS
ACTIVATE
0x30
0
0
0
0
0
0
0
0x31
0
0
0
0
0
0
IORNG
58
READ_DATA
Address of Plug and Play READ_DATA Port.
SERIAL_ISOLATION
Used in the Serial Isolation process.
RST_CSN
Resets CSN register to zero.
WAIT_KEY
Resets Wait for Key State.
RST_ALL
Resets all logical devices.
WAKE [CSN]
Will wake up if write data matches CSN Register.
READ_STATUS
Read Status of RESOURCE DATA.
RESOURCE_DATA
Next pending byte read from EEPROM.
CSN
Plug and Play CSN Value.
ACTIVATE
Indicates that the PCnet-ISA II device should be activated.
IORNG
Bits used to enable the I/O Range Check Command.
Am79C961A
IORNG
The following chart and its bit descriptions show the
internal command registers associated with the Plug
Plug and
Play Register
and Play operation. These registers control the PCnet-ISA II controller Plug and Play operation.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x60
0
0
0
0
0
0
1
IOAM3
0x61
IOAM2
IOAM1
IOAM0
0
0
0
0
0
0x70
0
0
0
0
IRQ3
IRQ2
IRQ1
IRQ0
0x71
0
0
0
0
0
0
IRQ_LVL
IRQ_TYPE
0x74
0
0
0
0
0
DMA2
DMA1
0x40
0
0
0
0
1
1
0
BPAM3
0x41
BPAM2
BPAM1
BPAM0
0
0
0
0
0
0x42
0
0
0
0
0
0
BP_16B
0
0x43
1
1
1
1
1
1
1
BPSZ3
0x44
BPSZ2
BPSZ1
BPSZ0
0
0
0
0
0
0x48
0
0
0
0
1
1
SRAM4
SRAM3
0x49
SRAM2
SRAM1
SRAM0
0
0
0
0
0
0x4A
0
0
0
0
0
0
SR16B
0
0x4B
1
1
1
1
1
1
1
SRSZ3
0x4c
SRSZ2
SRSZ1
SRSZ0
0
0
0
0
0
0xF0
0
LGCY_EN
DXCVRP
FL_SEL
BP_CS
APROM_EN
AEN_CS
IO_MODE
PCnet–ISA II’s Legacy Bit Feature
Description
The current PCnet-ISA II chip is designed such that it
always responds to Plug and Play configuration software. There are situations where this response to the
Plug and Play software is undesirable. An example of
this is when a fixed configuration is required, or when
the only possible resource available for the PCnet-ISA
II conflicts with a present but not used resource such as
IRQ, or when the chip is used in a system with a buggy
PnP BIOS.
To function in the situations above, a new feature has
been added to the PCnet-ISA II chip. This new feature
DMA0
makes the chip ignore the PnP software’s special initiation key sequence (6A). This will effectively turn the
chip into the “Legacy” mode operation, where it will be
visible in the I/O space, and only special setup programs will be able to reconfigure it. In case the
EEPROM is missing, empty, or corrupted, the chip will
still recognize AMD’s special initiation key sequence
(6B).
To enable this feature, a one has to be written into the
LGCY_EN bit, which is bit 6 of the Plug and Play register 0xF0. A preferred method would be set this bit in
the Vendor Byte (PnP 0xF0) field of the EEPROM
located in word offset 0x1A.
Am79C961A
59
Plug & Play Register Locations Detailed
Description (Refer to the Plug & Play
Register Map above)
IOAM[3:0]
I/O Address Match to bits [8:5] of SA
bus (PnP 0x60–0x61). Controls the
base address of PCnet-ISA II. The
IOAM will be written with a value
from the EEPROM.
IOAM[3:0]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IRQ[3:0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Base Address (Hex)
200
220
240
260
280
2A0
2C0
2E0
300
320
340
360
380
3A0
3C0
3E0
IRQ[3:0]
ISA IRQ Pin
0
1
1
IRQ3 (Default)
0
1
0
0
IRQ4
0
1
0
1
IRQ5
1
0
0
1
IRQ9
1
0
1
0
IRQ10
1
0
1
1
IRQ11
1
1
0
1
IRQ12
1
1
1
0
IRQ15
IRQ Type
IRQ_LVL
DMA[2:0]
60
DMA[2:0]
DMA Channel (DRQ/DACK Pair)
0
1
1
Channel 3
1
0
1
Channel 5
1
1
0
Channel 6
1
1
1
Channel 7
1
0
0
No DMA Channel
BPAM[3:0]
IRQ selection on the ISA bus (PnP
0x70). Controls which interrupt will
be asserted. ISA Edge sensitive or
EISA level mode is controlled by
IRQ_TYPE bit in PnP 0x71. Default
is ISA Edge Sensitive. The IRQ signals will not be driven unless PnP
activate register bit is set.
0
register will be written with a value
from the EEPROM. {For Bus Master
Mode Only} The DRQ signals will
not be driven unless Plug and Play
activate register bit is set.
IRQ Type(PnP 0x71). Indicates the
type of interrupt setting; Level is 1,
Edge is 0.
IRQ Level (PnP 0x71). A read-only register bit that indicates the type of setting, active high or low. Always complement of
IRQ_TYPE. See ISA CSR2 (EISA_LVL).
DMA Channel Select (PnP 0x74).
Controls the DRQ and DMA selection of PCnet-ISA II. The DMA[2:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Boot PROM Address Match to bits
[16:13] of SA bus (PnP 0x40–0x41).
Selects the location where the Boot
PROM Address match decode is
started. The BPAM will be written
with a value from the EEPROM.
BPAM[3:0]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address
Location (Hex)
C0000
C2000
C4000
C6000
C8000
CA000
CC000
CE000
D0000
D2000
D4000
D6000
D8000
DA000
DC000
DE000
Size Supported
(K bytes)
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8
BP_16B
Boot PROM 16-bit access (PnP
0x42). Is asserted if Boot PROM
cycles should respond as an 16-bit
device. In Bus Master mode, all boot
PROM cycles will only be 8 bits in
width.
BPSZ[3:0]
Boot PROM Size (PnP 0x43–0x44).
Selects the size of the boot PROM
selected.
BPSZ[3:0]
Boot PROM Size
0
1
x
1
x
1
x
1
No Boot PROM Selected
8K
1
1
1
1
1
0
0
0
16 K
32 K
1
0
0
0
64 K
SRAM[4:0]
Am79C961A
Static RAM Address Match to bits
[17:13] of SA bus (PnP 0x48-0x49).
Selects the starting location of the
Shared Memory when using the
Shared Memory architecture mode.
The SRAM[2:0] bits are used for performing address decoding on the
SA[15:13] address bits as shown in
the table below. S RAM[4] an d
SRAM[3] must reflect the external
address match logic for SA[17] and
SA[16], respectively. The SRAM[4:0]
bits are ignored when in the Bus
Master mode or in the Programmed
I/O Architecture mode.
SRAM[2:0]
0
0
0
0
0
0
8, 16, 32, 64
0
0
1
0
0
1
8
0
1
0
0
1
0
8, 16
0
1
1
0
1
1
8
1
0
0
1
0
0
8, 16, 32
1
0
1
1
0
1
8
1
1
0
1
1
0
8, 16
1
1
1
1
1
1
8
Static RAM 16-bit access (PnP
0x4A). If asserted, the PCnet-ISA II
will respond to SRAM cycles as a
16-bit device. This bit should be set
if external logic is designed to assert
the MEMCS16 signal when
accesses to the shared memory are
decoded. This bit is ignored when in
the Bus Master mode or in the Programmed I/O Architecture mode.
SRSZ[3:0]
DXCVRP
SRAM Size
(K bytes)
SA[15:13]
SR_16B
PCnet-ISA II will respond to the 6A
key sequence if the EEPROM read
was successful, otherwise it will respond to the 6B key sequence.
The DXCVRP should generally be
left cleared when the PCnet-ISA II is
being used with an external DC-DC
conver ter that has an active low
enable pin. The DXCVRP should
generally be set when the PCnet-ISA II is being used with an external DC-DC converter that has an
active high enable pin.
IO_MODE
I/O Mode. When set to one, the
internal selection will respond as a
16-bit port, (i.e. drive IOCS16 pin).
When IO_MODE is set to zero,
(Default), the internal I/O selection
will respond as an 8-bit port.
AEN_CS
External Decode Logic for I/O Registers. When written with a one, the
PCnet-ISA II will use the AEN pin as
I/O chip select bar, to allow for external decode logic for the upper address bit of SA [9:5]. The purpose of
this pin is to allow I/O locations, not
suppor ted with the IOAM[3:0],
selection, to be defined outside the
range 0x200–0x3F7. When set to a
zero, (Default), I/O Selection will use
IOAM[3:0].
APROM_EN
External Parallel IEEE Address
PROM. When set, the IRQ15 pin is
reconfigured to be an Address Chip
Select low, similar to APCS pin in the
existing PCnet-ISA (Am79C960)
device. The purpose of this bit is to
allow for both a serial EEPROM and
parallel PROM to coexist. When
APROM_EN is set, the IEEE
address located in the serial EEPROM will be ignored and parallel
access will occur over the PRDB
Static RAM size (PnP 0x4B-0x4C).
Selects the size of the static RAM.
The SRSZ[3:0] bits are ignored
when in the Bus Master mode or in
the Programmed I/O Architecture
mode.
SRSZ[3:0]
Shared Memory Size
0
x
x
x
No Static RAM Selected
1
1
1
1
8K
1
1
1
0
16 K
1
1
0
0
32 K
1
0
0
0
64 K
Vendor Defined Byte (PnP 0xF0)
LGCY_EN
DXCVR Polarity. The DXCVRP bit
sets the polarity of the DXCVR pin.
When DXCVRP is cleared (default),
the DXCVR pin is driven HIGH when
the Twisted Pair port is active or
SLEEP mode has been entered and
driven LOW when the AUI port is
active. When DXCVRP is set, the
DXCVR pin is driven LOW when the
Twisted Pair port is active or SLEEP
mode has been entered and driven
HIGH when the AUI port is active.
Legacy mode enable. When written
with a one, the PCnet-ISA II will not
respond to the Plug and Play initiation key sequence (6A) but will
respond to the AMD key sequence
(6B). Therefore, it cannot be reconfigured by the Plug and Play software. When set to zero (default), the
Am79C961A
61
bus. When APROM_EN is cleared,
default state, the IEEE address will
be read in from the serial device and
written to an internal RAM. When
the I/O space of the IEEE PROM is
selected, PCnet-ISA II, will access
the contents of this RAM for I/O read
cycles. I/O wr ite cycles will be
ignored.
BP_CS
FL_SEL
Boot PROM Chip Select. When
BP_CS is set to one, BALE will act
as an external chip select (active
low) above bit 15 of the address bus.
BALE = 0, will select the boot PROM
when MEMR is asserted low if the
BP_CS bit is set and BPAM[2:0]
match SA[15:13] and BPSZ[3:0]
matches the selected size. When
BP_CS is set to zero. BALE will act
as the normal address latch strobe
to capture the upper address bits for
memory access to the boot PROM.
BP_CS is by default low. The primary purpose of this bit is to allow
non-ISA bus applications to support
larger Boot PROMS or non-standard
Boot PROM/Flash locations.
Flash Memory Device Selected.
W h e n s e t , t h e B o o t P RO M i s
replaced with an external Flash
memor y device. In Bus Master
M o d e, B P CS i s r e p l a c e d w i t h
Flash_OE. IRQ12 becomes
Flash_WE. The Flash’s CS pin is
grounded. In shared memory mode,
BPCS is replaced with Flash_CS.
IRQ12 becomes Static_RAM_CS
pin. The SROE and SRWE signals
are connected to both the SRAM
and Flash memory devices. FL_SEL
is cleared by a reset, which is the
default.
Checksum Failure
After RESET, the PCnet-ISA II controller begins
reading the EEPROM and storing the information in
registers inside PCnet-ISA II controller. PCnet-ISA II
controller does a checksum on word locations 0-1Bh
inclusive and if the byte checksum = FFh, then the
data read from the EEPROM is considered good. If
the checksum is not equal to FFh, then the PCnet-ISA II controller enters what is called software relocatable mode.
In software relocatable mode, the device functions the
same as in Plug and Play mode, except that it does not
62
respond to the same initiation key as Plug and Play
supports. Instead, a different key is used to bring PCnet-ISA II controller out of the Wait For Key state. This
key is as follows:
6B, 35, 9A, CD, E6, F3, 79, BC
5E, AF, 57, 2B, 15, 8A, C5, E2
F1, F8, 7C, 3E, 9F, 4F, 27, 13
09, 84, 42, A1, D0, 68, 34, 1A
Use Without EEPROM
In some designs, especially PC motherboard applicat i o n s , i t m ay b e d e s i r a b l e t o e l i m i n a t e t h e
EEPROM altogether. This would save money, space,
and power consumption.
The operation of this mode is similar to when the PCnet-ISA II controller encounters a checksum error, except that to enter this mode the SHFBUSY pin is left
unconnected. The device will enter software relocatable mode, and the BIOS on the motherboard can
wake up the device, configure it, load the IEEE address
(possibly stored in Flash ROM) into the PCnet-ISA II
controller, and activate the device.
External Scan Chain
The External Scan Chain is a set of bits stored in the
EEPROM which are not used in the PCnet-ISA II controller but which can be used with external hardware to
allow jumperless configuration of external devices.
A f t e r R E S E T, t h e P C n e t -I S A I I c o n t r o l l e r
begins reading the EEPROM and storing the informat i o n i n r e g i s t e r s i n s i d e t h e P C n e t -I S A I I
controller. SHFBUSY is held high during the read of the
EEPROM. If external circuitry is added, such as a shift
register, which is clocked from SCLK and is attached to
DO from the EEPROM, data read out of the EEPROM
will be shifted into the shift register. After reading the
EEPROM to the end of the External Shift Chain, and if
there is a correct checksum, SHFBUSY will go low.
This will be used to latch the infor mation from
the EEPROM into the shift register. If the checksum is
invalid, SHFBUSY will not go low, indicating that the
EEPROM may be bad.
Flash PROM
Use
Instead of using a PROM or EPROM for the Boot
PROM, it may be desirable to use a Flash or EEPROM
type of device for storing the Boot code. This would
allow for in-system updates and changes to the information in the Boot ROM without opening up the PC. It
may also be desirable to store statistics or drivers in the
Flash device.
Am79C961A
Interface
To use a Flash-type device with the PCnet-ISA
II controller, Flash Select is set in register 0F0h of the
Plug and Play registers. Flash Select is cleared
by RESET (default).
In bus master mode, BPCS becomes Flash_OE and
IRQ12 becomes Flash_WE. The Flash ROM devices
CS pin is connected to ground.
are received. IOCHRDY is asynchronously driven
LOW if the PCnet-ISA II controller needs a wait state. It
is released synchronously when the PCnet-ISA II controller is ready.
When the PCnet-ISA II controller is the Current Master,
all the signals it generates are synchronous to the
on-chip 20 MHz clock.
DMA Transfers
In shared memory mode, BPCS becomes Flash_CS
and IRQ12 becomes the static RAM Chip Select, and
the SROE and SRWE signals are connected to both
the SRAM and Flash devices.
The BIU will initiate DMA transfers according to the
type of operation being performed. There are three primary types of DMA transfers:
Optional IEEE Address PROM
During initialization, the PCnet-ISA II transfers 12
words from the initialization block in memory to internal
registers. These 12 words are transferred through different bus mastership period sequences, depending on
whether the TIMER bit (CSR4, bit 13) is set and, if
TIMER is set, on the value in the Bus Activity Timer
register (CSR82).
Normally, the Ethernet physical address will be stored
in the EEPROM with the other configuration data. This
reduces the parts count, board space requirements,
and power consumption. The option to use a standard
parallel 8 bit PROM is provided to manufacturers who
a r e c o n c e r n e d a b o u t t h e n o n -vo l a t i l e n a t u r e
of EEPROMs.
To use a 8 bit parallel PROM to store the IEEE address
data instead of stor ing it in the EEPROM, the
APROM_EN bit is set in the Plug and Play registers by
the EEPROM upon RESET. IRQ15 is redefined by the
setting of this bit to be APCS, or ADDRESS PROM
CHIP SELECT. This pin is connected to an external 8
bit PROM, such as a 27LS19. The address pins of the
PROM are connected to the lower address pins of the
ISA bus, and the data lines are connected to the private
data bus.
In this mode, any accesses to the IEEE address will be
passed to the external PROM and the data will be
passed through the PCnet-ISA II controller to
the system data bus.
EISA Configuration Registers
The PCnet-ISA II controller has support for the 4-byte
EISA Configuration Registers. These are used in EISA
systems to identify the card and load the appropriate
configuration file for that card. This feature is enabled
using bit 10 of ISACSR2. When set to 1, the EISA
Configuration registers will be enabled and will be
read at I/O location 0xC80–0xC83. The contents of
these 4 registers are stored in the EEPROM and are
automatically read in at RESET.
Bus Interface Unit (BIU)
The bus interface unit is a mixture of a 20 MHz state
machine and asynchronous logic. It handles two types
of accesses; accesses where the PCnet-ISA II controller is a slave and accesses where the PCnet-ISA II controller is the Current Master.
In slave mode, signals like IOCS16 are asserted and
deasser ted as soon as the appropr iate inputs
1. Initialization Block DMA Transfers
If the TIMER bit is reset (default), the 12 words are
always transferred during three separate bus mastership periods. During each bus mastership period, four
words (8 bytes) will be read from contiguous memory
addresses.
If the TIMER bit is set, the 12 words may be transferred
using anywhere from 1 to 3 bus mastership periods,
depending on the value of the Bus Activity Timer register (CSR82). During each bus mastership period, a
minimum of four words (8 bytes) will be read from contiguous memory addresses. If the TIMER bit is set and
the value in the Bus Activity Timer register allows it, 8
or all 12 words of the initialization block are read during
a single bus mastership period.
2. Descriptor DMA Transfers
Descriptor DMA transfers are performed to read or
write to transmit or receive descriptors. All transmit and
receive descriptor READ accesses require 3 word
reads (TMD1, TMD0, then TMD2 for transmit descriptors and RMD1, RMD0, then RMD2 for receive descriptors). Transmit and receive descr iptor WRITE
accesses to unchained descriptors or the last descriptor in a chain (ENP set) require 2 word writes (TMD1
then TMD3 for transmit and RMD1 then RMD3 for receive). Transmit and receive descriptor WRITE accesses to chained descriptors that do not have ENP set
require 1 word write (TMD1 for transmit and RMD1 for
receive). During descriptor write accesses, only the
bytes which need to be written are written, as controlled by the SA0 and SBHE pins.
If the TIMER bit is reset (default), all accesses during a
single bus mastership period will be either all read or all
write and will be to only one descriptor. Hence, when
the TIMER bit is reset, the bus mastership periods for
Am79C961A
63
descriptor accesses are always either 3, 2, or 1 cycles
long, depending on which descriptor operation is being
performed.
If the TIMER bit is set, the 3, 2, or 1 cycles required in
a descriptor access may be performed as a part of a
bus mastership period in which any combination of
descriptor reads and writes and buffer reads and writes
are performed. When the TIMER bit is set, the Bus
Activity Timer (CSR82) and the bus access requirements of the PCnet-ISA II govern the operations performed during a single bus mastership period.
3. FIFO DMA Transfers
FIFO DMA transfers occur when the PCnet-ISA II
microcode determines that transfers to and/or from the
FIFOs are required. Once the PCnet-ISA II BIU has
been granted bus mastership, it will perform a series of
consecutive transfer cycles before relinquishing the
bus.
When the Bus Activity Timer is disabled by clearing the
TIMER (CSR4, bit 13) bit, all FIFO DMA transfers
within a bus mastership period will be either read or
write cycles, and all transfers will be to adjacent,
ascending addresses. When the Bus Activity Timer is
enabled by setting the TIMER bit, DMA transfers within
a bus mastership period may consist of any mixture of
read and write cycles, without restriction on the
address ordering. This mode of operation allows the
PCnet-ISA II to accomplish more during each bus
ownership period.
The number of data transfer cycles contained within a
single bus mastership period is in general dependent
on the programming of the DMAPLUS (CSR4, bit 14)
and the TIMER (CSR4, bit 13) options. Several other
factors will also affect the length of the bus mastership
period. The possibilities are as follows:
If DMAPLUS = 0 and TIMER = 0, a maximum of 16
transfers to or from the FIFO will be performed by
default. This default value may be changed by writing
to the DMA Burst Register (CSR80, bits 7:0). Since
TIMER = 0, all FIFO DMA transfers within a bus mastership period will be either read or write cycles, and all
transfers will be to adjacent, ascending addresses.
Note that DMAPLUS = 0 merely sets a maximum value
for the number of FIFO transfers that may occur during
one bus mastership period. The minimum number of
transfers in the bus mastership period will be determined by the settings of the FIFO watermarks and the
conditions of the FIFOs, and the value of the Bus Activity Timer (CSR82) if the TIMER bit is set.
If DMAPLUS = 1 and TIMER = 0, the bus mastership
period will continue until the transmit FIFO is filled to its
high threshold (read transfers) or the receive FIFO is
emptied to its low threshold (write transfers). Other
variables may also affect the end point of the bus mas-
64
tership period in this mode, including the particular conditions existing within the FIFOs, and receive and
transmit status conditions. Since TIMER = 0, all FIFO
DMA transfers within a bus mastership period will be
either read or write cycles, and all transfers will be to
adjacent, ascending addresses.
If TIMER = 1, the bus mastership period will continue
until all “pending bus operations” are completed or until
the Bus Activity Timer value (CSR82) has expired.
These bus operations may consist of any mixture of
descriptor and buffer read and write accesses. If DMAPLUS = 1, “pending bus operations” includes any descriptor accesses and buffer accesses that need to be
performed. If DMAPLUS = 0, “pending bus operations”
include any descriptor accesses that need to be performed and any buffer accesses that need to be performed up to the limit specified by the DMA Burst
Register (CSR80, bits 7:0).
Note that when TIMER=1, following a last bus transaction during a bus mastership period, the PCnet-ISA II
may keep ownership of the bus for up to approximately
1 µs. The PCnet-ISA II determines whether there are
further pending bus operations by waiting approximately 1 µs after the completion of every bus operation
(e.g. a descriptor or FIFO access). If, during the 1 µs
period, no further bus operations are requested by the
internal Buffer Management Unit, the PCnet-ISA II
determines that there are no further pending operations and gives up bus ownership. This 1 µs of unused
bus ownership time is more than made up for by the
efficiency gained by being able to perform any mixture
of descriptor and buffer read and write accesses during
a single bus ownership period.
The FIFO thresholds are programmable (see description of CSR80), as are the DMA Burst Register and Bus
Activity Timer values. The exact number of transfer
cycles in the case of DMAPLUS = 1 will be dependent
on the latency of the system bus to the PCnet-ISA II
controller’s DMA request and the speed of bus operation, but will be limited by the value in the Bus Activity
Timer register (if the TIMER bit is set), the FIFO condition, and receive and transmit status. Barring a
time-out by either of these registers, or exceptional receive and transmit events, or an end of packet signal
from the FIFO, the FIFO watermark settings and the
extent of Bus Grant latency will be the major factors determining the number of accesses performed during
any given arbitration cycle when DMAPLUS = 1.
The IOCHRDY response of the memory device will
a l s o a f fe c t t h e n u m b e r o f t r a n s fe r s w h e n
DMAPLUS = 1, since the speed of the accesses will affect the state of the FIFO. During accesses, the FIFO
may be filling or emptying on the network end. A slower
memory response will allow additional data to accumulate inside of the FIFO (during write transfers from the
receive FIFO). If the accesses are slow enough, a com-
Am79C961A
plete word may become available before the end of the
arbitration cycle and thereby increase the number of
transfers in that cycle. The general rule is that the
longer the Bus Grant latency or the slower the bus
transfer operations (or clock speed) or the higher the
transmit watermark or the lower the receive watermark
or any combination thereof, the longer will be the average bus mastership period.
Buffer Management Unit (BMU)
The buffer management unit is a microcoded 20 MHz
state machine which implements the initialization block
and the descriptor architecture.
Initialization
PCnet-ISA II controller initialization includes the reading of the initialization block in memory to obtain the
operating parameters. The initialization block is read
when the INIT bit in CSR0 is set. The INIT bit should be
set before or concurrent with the STRT bit to insure correct operation. See previous section “1. Initialization
Block DMA Transfer.” Once the initialization block has
been read in and processed, the BMU knows where the
receive and transmit descriptor rings are. On completion of the read operation and after internal registers
have been updated, IDON will be set in CSR0, and an
interrupt generated if IENA is set.
The Initialization Block is vectored by the contents of
CSR1 (least significant 16 bits of address) and CSR2
(most significant 8 bits of address). The block contains
the user defined conditions for PCnet-ISA II controller
operation, together with the address and length information to allow linkage of the transmit and receive
descriptor rings.
There is an alternative method to initialize the PCnet-ISA II controller. Instead of initialization via the initialization block in memory, data can be written directly
into the appropriate registers. Either method may be
used at the discretion of the programmer. If the registers are written to directly, the INIT bit must not be set,
or the initialization block will be read in, thus overwriting
the previously written information. Please refer to
Appendix D for details on this alternative method.
Reinitialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same
in the PCnet-ISA II controller as in the LANCE. In particular, the PCnet-ISA II controller reloads the transmit
and receive descriptor pointers (working registers) with
their respective base addresses. This means that the
software must clear the descriptor’s own bits and reset
its descriptor ring pointers before the restart of the PCnet-ISA controller. The reload of descriptor base
addresses is performed in the LANCE only after initialization, so a restart of the LANCE without initialization
leaves the LANCE pointing at the same descriptor
locations as before the restart.
Suspend
The PCnet-ISA II controller offers a suspend mode that
allows easy updating of the CSR registers without
going through a full reinitialization of the device. The
suspend mode also allows stopping the device with
orderly termination of all network activity.
The host requests the PCnet-ISA II controller to enter
the suspend mode by setting SPND (CSR5, bit 0) to
ONE. The host must poll SPND until it reads back ONE
to determine that the PCnet-ISA II controller has entered the suspend mode. When the host sets SPND to
ONE, the PCnet-ISA II controller first finishes all on-going transmit activity and updates the corresponding
transmit descriptor entries. It then finishes all on-going
receive activity and updates the corresponding receive
descriptor entries. It then sets the read-version of
SPND to ONE and enters the suspend mode. In suspend mode, all of the CSR registers are accessible. As
long as the PCnet-ISA II controller is not reset while in
suspend mode (by asserting the RESET pin, reading
the RESET register, or by setting the STOP bit), no
reinitialization of the device is required after the device
comes out of suspend mode. When SPND is set to
ZERO, the PCnet-ISA II controller will leave the suspend mode and will continue at the transmit and receive descriptor ring locations where it had left when it
entered the suspend mode.
Buffer Management
Reinitialization
The transmitter and receiver section of the PCnet-ISA
II controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
state of the transmitter and receiver are monitored
through CSR0 (RXON, TXON bits). The PCnet-ISA II
controller should be reinitialized if the transmitter and/
or the receiver were not turned on during the original
initialization and it was subsequently required to activate them, or if either section shut off due to the detection of an error condition (MERR, UFLO, TX BUFF
error).
Buffer management is accomplished through message
descriptor entries organized as ring structures in memory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4 words
(8 bytes).
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT
bit in CSR0), the PCnet-ISA II controller reads the
user-defined base address for the transmit and receive
descriptor rings, which must be on an 8-byte boundary,
as well as the number of entries contained in the
Am79C961A
65
descriptor rings. By default, a maximum of 128 ring
entries is permitted when utilizing the initialization
block, which uses values of TLEN and RLEN to specify
the transmit and receive descriptor ring lengths. However, the ring lengths can be manually defined (up to
65535) by writing the transmit and receive ring length
registers (CSR76,78) directly.
Each ring entry contains the following information:
■ The address of the actual message data buffer in
user or host memory
■ The length of the message buffer
■ Status information indicating the condition of the
buffer
Receive descriptor entries are similar (but not identical)
to transmit descriptor entries. Both are composed of
four registers, each 16 bits wide for a total of 8 bytes.
To permit the queuing and de-queuing of message
buffers, ownership of each buffer is allocated to either
the PCnet-ISA II controller or the host. The OWN bit
66
within the descriptor status information, either TMD or
RMD (see section on TMD or RMD), is used for this
purpose. “Deadly Embrace” conditions are avoided by
the ownership mechanism. Only the owner is permitted
to relinquish ownership or to write to any field in the
descriptor entry. A device that is not the current owner
of a descriptor entry cannot assume ownership or
change any field in the entry.
Descriptor Ring Access Mechanism
At initialization, the PCnet-ISA II controller reads the
base address of both the transmit and receive descriptor rings into CSRs for use by the PCnet-ISA II controller during subsequent operation.
When transmit and receive functions begin, the base
address of each ring is loaded into the current descriptor address registers and the address of the next
descriptor entry in the transmit and receive rings is
computed and loaded into the next descriptor address
registers.
Am79C961A
N
N
24-Bit Base Address
Pointer to
Initialization Block
CSR2
RES
N
•
•
•
RCV Descriptor
Ring
RX DESCRIPTOR
RINGS
1st desc.
start
CSR1
IADR[23:16]
N
2nd desc.
start
IADR[15:0]
RMD0
RMD0
RMD1 RMD2
RMD3
Initialization
Block
PADR[31:16]
PADRF[47:32]
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
M
M
M
RX DESCRIPTOR RINGS
RDRA[15:0]
TLEN
Data
Buffer 2
M
LADRF[63:48]
RLEN
Data
Buffer 1
RCV
Buffers
•
•
•
MODE
PADR[15:0]
Data
Buffer
N
•
•
•
XMT Descriptor
Ring
RX DESCRIPTOR
RINGS
RES
RDRA[23:16]
TDRA[15:0]
TDRA[23:16]
RES
2nd desc.
start
1st desc.
start
TMD0
TMD0
TMD1
Data
Buffer 2
Initialization Block and Descriptor Rings
Polling
When there is no channel activity and there is no preor post-receive or transmit activity being performed by
the PCnet-ISA II controller then the PCnet-ISA II controller will periodically poll the current receive and
transmit descriptor entries in order to ascertain their
ownership. If the DPOLL bit in CSR4 is set, then the
transmit polling function is disabled.
TMD3
•
•
•
Data
Buffer 1
XMT
Buffers
TMD2
Data
Buffer
M
19364B-15
A typical polling operation consists of the following: The
PCnet-ISA II controller will use the current receive
descriptor address stored internally to vector to the
appropriate Receive Descriptor Table Entry (RDTE). It
will then use the current transmit descriptor address
(stored internally) to vector to the appropriate Transmit
Descriptor Table Entry (TDTE). These accesses will be
made to RMD1 and RMD0 of the current RDTE and
TMD1 and TMD0 of the current TDTE at periodic poll-
Am79C961A
67
ing intervals. All information collected during polling
activity will be stored internally in the appropriate
CSRs. (i.e. CSR18–19, CSR40, CSR20–21, CSR42,
CSR50, CSR52). Unowned descriptor status will be
internally ignored.
A typical receive poll occurs under the following
conditions:
1. PCnet-ISA II controller does not possess ownership
of the current RDTE and
the poll time has elapsed and
RXON = 1,
or
2. PCnet-ISA II controller does not possess ownership
of the next RDTE and
the poll time has elapsed and
RXON = 1,
If RXON = 0, the PCnet-ISA II controller will never poll
RDTE locations.
If RXON = 1, the system should always have at least
one RDTE available for the possibility of a receive
event. When there is only one RDTE, there is no polling
for next RDTE.
A typical transmit poll occurs under the following
conditions:
1. PCnet-ISA II controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
the poll time has elapsed,
or
2. PCnet-ISA II controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
a packet has just been received,
or
3. PCnet-ISA II controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
a packet has just been transmitted.
The poll time interval is nominally defined as 32,768
crystal clock periods, or 1.6 ms. However, the poll time
register is controlled internally by microcode, so any
other microcode controlled operation will interrupt the
incrementing of the poll count register. For example,
when a receive packet is accepted by the PCnet-ISA II
controller, the device suspends execution of the
poll-time-incrementing microcode so that a receive
m ic r o c o de r o u ti n e may i ns t e ad b e exec u te d .
Poll-time-incrementing code is resumed when the
receive operation has completely finished. Note, how68
ever, that following the completion of any receive or
transmit operation, a poll operation will always be performed. The poll time count register is never reset.
Note that if a non-default is desired, then a strict sequence of setting the INIT bit in CSR0, waiting for the
IDON bit in CSR0, then writing to CSR47, and then setting STRT in CSR0 must be observed, otherwise the
default value will not be overwritten. See the CSR47
section for details.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately perform a polling operation. If RDTE ownership
has not been previously established, then an RDTE
poll will be performed ahead of the TDTE poll.
Transmit Descriptor Table Entry (TDTE)
If, after a TDTE access, the PCnet-ISA II controller
finds that the OWN bit of that TDTE is not set, then the
PCnet-ISA II controller resumes the poll time count and
re-examines the same TDTE at the next expiration of
the poll time count.
If the OWN bit of the TDTE is set, but STP = 0, the PCnet-ISA II controller will immediately request the bus in
order to reset the OWN bit of this descriptor; this condition would normally be found following a LCOL or
RETRY error that occurred in the middle of a transmit
packet chain of buffers. After resetting the OWN bit of
this descriptor, the PCnet-ISA II controller will again
immediately request the bus in order to access the next
TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be reset. In the LANCE the buffer length of 0 is
interpreted as a 4096-byte buffer. It is acceptable to
have a 0 length buffer on transmit with STP=1 or
STP=1 and ENP = 1. It is not acceptable to have 0
length buffer with STP = 0 and ENP = 1.
If the OWN bit is set and the start of packet (STP) bit is
set, then microcode control proceeds to a routine that
will enable transmit data transfers to the FIFO.
If the transmit buffers are data chained (ENP = 0 in the
first buffer), then the PCnet-ISA II controller will look
ahead to the next transmit descriptor after it has performed at least one transmit data transfer from the first
buffer. More than one transmit data transfer may possibly take place, depending upon the state of the transmitter. The transmit descriptor look ahead reads TMD0
first and TMD1 second. The contents of TMD0 and
TMD1 will be stored in Next TX Descriptor Address
(CSR32), Next TX Byte Count (CSR66) and Next TX
Status (CSR67) regardless of the state of the OWN bit.
This transmit descriptor lookahead operation is
performed only once.
If the PCnet-ISA II controller does not own the next
TDTE (i.e. the second TDTE for this packet), then it will
complete transmission of the current buffer and then
Am79C961A
update the status of the current (first) TDTE with the
BUFF and UFLO bits being set. If DXSUFLO is 0 (bit 6
CSR3), then this will cause the transmitter to be disabled (CSR0, TXON = 0). The PCnet-ISA II controller
will have to be restarted to restore the transmit function.
The situation that matches this description implies that
the system has not been able to stay ahead of the PCnet-ISA II controller in the transmit descriptor ring and
therefore, the condition is treated as a fatal error. To
avoid this situation, the system should always set the
transmit chain descriptor own bits in reverse order.
If the PCnet-ISA II controller does own the second
TDTE in a chain, it will gradually empty the contents of
the first buffer (as the bytes are needed by the transmit
operation), perform a single-cycle DMA transfer to
update the status (reset the OWN bit in TMD1) of the
first descriptor, and then it may perform one data DMA
access on the second buffer in the chain before executing another lookahead operation. (i.e. a lookahead to
the third descriptor).
The PCnet-ISA II controller can queue up to two packets in the transmit FIFO. Call them packet “X” and
packet “Y”, where “Y” is after “X”. Assume that packet
“X” is currently being transmitted. Because the PCnet-ISA II controller can perform lookahead data transfer over an ENP, it is possible for the PCnet-ISA II
controller to update a TDTE in a buffer belonging to
packet “Y” while packet “X” is being transmitted if
packet “Y” uses data chaining. This operation will result
in non-sequential TDTE accesses as packet “X” completes transmission and the PCnet-ISA II controller
writes out its status, since packet “X”’s TDTE is before
the TDTE accessed as part of the lookahead data
transfer from packet “Y”.
This should not cause any problem for properly written
software which processes buffers in sequence, waiting
for ownership before proceeding.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, then
TMD2 and TMD1 of the current buffer will be written; in
that case, data transfers from the next buffer will not
commence. Instead, following the TMD2/TMD1 update, the PCnet-ISA II controller will go to the next
transmit packet, if any, skipping over the rest of the
packet which experienced an error, including chained
buffers.
This is done by returning to the polling microcode
where it will immediately access the next descriptor
and find the condition OWN = 1 and STP = 0 as
described earlier. In that case, the PCnet-ISA II controller will reset the own bit for this descriptor and continue
in like manner until a descriptor with OWN = 0 (no more
transmit packets in the ring) or OWN = 1 and STP = 1
(the first buffer of a new packet) is reached.
At the end of any transmit operation, whether successful or with errors, and the completion of the descriptor
updates, the PCnet-ISA II controller will always perform
another poll operation. As described earlier, this poll
operation will begin with a check of the current RDTE,
unless the PCnet-ISA II controller already owns that
descriptor. Then the PCnet-ISA II controller will
proceed to polling the next TDTE. If the transmit
descriptor OWN bit has a zero value, then the PCnet-ISA II controller will resume poll time count
incrementation. If the transmit descriptor OWN bit has
a value of ONE, then the PCnet-ISA II controller will
begin filling the FIFO with transmit data and initiate a
transmission. This end-of-operation poll avoids inserting poll time counts between successive transmit
packets.
Whenever the PCnet-ISA II controller completes a
transmit packet (either with or without error) and writes
the status information to the current descriptor, then the
TINT bit of CSR0 is set to indicate the completion of a
transmission. This causes an interrupt signal if the
IENA bit of CSR0 has been set and the TINTM bit of
CSR3 is reset.
Receive Descriptor Table Entry (RDTE)
If the PCnet-ISA II controller does not own both the current and the next Receive Descriptor Table Entry, then
the PCnet-ISA II controller will continue to poll according to the polling sequence described above. If the
receive descriptor ring length is 1, there is no next
descriptor, and no look ahead poll will take place.
If a poll operation has revealed that the current and the
next RDTE belongs to the PCnet-ISA II controller, then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the PCnet-ISA II controller retains ownership to the current and the next RDTE.
When receive activity is present on the channel, the
PCnet-ISA II controller waits for the complete address
of the message to arrive. It then decides whether to
accept or reject the packet based on all active addressing schemes. If the packet is accepted the PCnet-ISA II
controller checks the current receive buffer status register CRST (CSR40) to determine the ownership of the
current buffer.
If ownership is lacking, then the PCnet-ISA II controller
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the PCnet-ISA
II controller has no buffer in which to store the incoming
message. The MISS bit will be set in CSR0 and an
interrupt will be generated if IENA = 1 (CSR0) and
MISSM = 0 (CSR3). Another poll of the current RDTE
will not occur until the packet has finished.
If the PCnet-ISA II controller sees that the last poll
(either a normal poll or the last-ditch effort described in
Am79C961A
69
the above paragraph) of the current RDTE shows valid
ownership, then it proceeds to a poll of the next RDTE.
Following this poll, and regardless of the outcome of
this poll, transfers of receive data from the FIFO may
begin.
or post-message processing. These features include
the ability to disable retries after a collision, dynamic
FCS generation on a packet-by-packet basis, and automatic pad field insertion and deletion to enforce
minimum frame size attributes.
Regardless of ownership of the second receive
descriptor, the PCnet-ISA II controller will continue to
perform receive data DMA transfers to the first buffer,
using burst-cycle DMA transfers. If the packet length
exceeds the length of the first buffer, and the PCnet-ISA II controller does not own the second buffer,
ownership of the current descriptor will be passed back
to the system by writing a zero to the OWN bit of RMD1
and status will be written indicating buffer (BUFF = 1)
and possibly overflow (OFLO = 1) errors.
The two primary attributes of the MAC engine are:
If the packet length exceeds the length of the first (current) buffer, and the PCnet-ISA II controller does own
the second (next) buffer, ownership will be passed
back to the system by writing a zero to the OWN bit of
RMD1 when the first buffer is full. Receive data transfers to the second buffer may occur before the PCnet-ISA II controller proceeds to look ahead to the
ownership of the third buffer. Such action will depend
upon the state of the FIFO when the status has been
updated on the first descriptor. In any case, lookahead
will be performed to the third buffer and the information
gathered will be stored in the chip, regardless of the
state of the ownership bit. As in the transmit flow, lookahead operations are performed only once.
This activity continues until the PCnet-ISA II controller
recognizes the completion of the packet (the last byte of
this receive message has been removed from the
FIFO). The PCnet-ISA II controller will subsequently update the current RDTE status with the end of packet
(ENP) indication set, write the message byte count
(MCNT) of the complete packet into RMD2 and overwrite the “current” entries in the CSRs with the “next” entries.
■ Transmit and receive message data encapsulation
— Framing (frame boundary delimitation, frame
synchronization)
— Addressing (source and destination address
handling)
— Error detection (physical medium transmission
errors)
■ Media access management
— Medium allocation (collision avoidance)
— Contention resolution (collision handling)
Transmit and Receive Message Data
Encapsulation
The MAC engine provides minimum frame size
enforcement for transmit and receive packets. When
APAD_XMT = 1 (bit 11 in CSR4), transmit messages
will be padded with sufficient bytes (containing 00h) to
ensure that the receiving station will observe an information field (destination address, source address,
length/type, data and FCS) of 64-bytes. When
ASTRP_RCV = 1 (bit 10 in CSR4), the receiver will
automatically strip pad bytes from the received message by observing the value in the length field, and
stripping excess bytes if this value is below the minimum data size (46 bytes). Both features can be independently over-ridden to allow illegally short (less than
64 bytes of packet data) messages to be transmitted
and/or received. The use of these features reduce bus
bandwidth usage because the pad bytes are not transferred to or from host memory.
Framing (frame boundary delimitation, frame
synchronization)
Media Access Control
The Media Access Control engine incorporates the
essential protocol requirements for operation of a compliant Ethernet/802.3 node, and provides the interface
between the FIFO sub-system and the Manchester
Encoder/Decoder (MENDEC).
This section describes operation of the MAC engine
when operating in Half Duplex mode. When in Half
Duplex mode, the MAC engine is fully compliant to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard 1990
Second Edition) and ANSI/IEEE 802.3 (1985). When
operating in Full Duplex mode, the MAC engine behavior
changes as described in the Full Duplex Operation section.
The MAC engine will autonomously handle the construction of the transmit frame. Once the Transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80), and providing access to the channel is currently permitted, the MAC engine will commence the 7-byte preamble sequence (10101010b,
where first bit transmitted is a 1). The MAC engine will
subsequently append the Start Frame Delimiter (SFD)
byte (10101011b) followed by the serialized data from
the Transmit FIFO. Once the data has been completed,
the MAC engine will append the FCS (most significant
bit first) which was computed on the entire data portion
of the message.
The MAC engine provides programmable enhanced
features designed to minimize host supervision and pre
Note that the user is responsible for the correct ordering and content in each of the fields in the frame,
70
Am79C961A
including the destination address, source address,
length/type and packet data.
The receive section of the MAC engine will detect an
incoming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8 bits of information before searching for the SFD sequence. Once the SFD is detected,
all subsequent bits are treated as part of the frame. The
MAC engine will inspect the length field to ensure minimum frame size, strip unnecessary pad characters (if
enabled), and pass the remaining bytes through the
Receive FIFO to the host. If pad stripping is performed,
the MAC engine will also strip the received FCS bytes,
although the normal FCS computation and checking
will occur. Note that apart from pad stripping, the frame
will be passed unmodified to the host. If the length field
has a value of 46 or greater, the MAC engine will not
attempt to validate the length against the number of
bytes contained in the message.
If the frame terminates or suffers a collision before
64 bytes of infor mation (after SFD) have been
received, the MAC engine will automatically delete the
f r a m e f r o m t h e R e c e i v e F I F O, w i t h o u t h o s t
intervention.
Addressing (source and destination address
handling)
The first 6 bytes of information after SFD will be interpreted as the destination address field. The MAC
engine provides facilities for physical, logical, and
broadcast address reception. In addition, multiple
physical addresses can be constructed (perfect
address filtering) using external logic in conjunction
with the EADI interface.
Error detection (physical medium transmission
errors)
The MAC engine provides several facilities which
report and recover from errors on the medium. In addition, the network is protected from gross errors due to
inability of the host to keep pace with the MAC engine
activity.
On completion of transmission, the following transmit
status is available in the appropriate TMD and CSR
areas:
■ The exact number of transmission retry attempts
(ONE, MORE, or RTRY).
■ Whether the MAC engine had to Defer (DEF) due to
channel activity.
■ Loss of Carrier, indicating that there was an interruption in the ability of the MAC engine to monitor its
own transmission. Repeated LCAR errors indicate
a p o ten ti a ll y fau l ty tra n sc e ive r or ne two r k
connection.
■ Late Collision (LCOL) indicates that the transmission suffered a collision after the slot time. This is
indicative of a badly configured network. Late collisions should not occur in a normal operating network.
■ Collision Error (CERR) indicates that the transceiver did not respond with an SQE Test message
within the predetermined time after a transmission
completed. This may be due to a failed transceiver,
disconnected or faulty transceiver drop cable, or the
fact the transceiver does not support this feature (or
the feature is disabled).
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails
to keep the Transmit FIFO filled sufficiently, causing an
underflow, the MAC engine will guarantee the message
is either sent as a runt packet (which will be deleted by
the receiving station) or has an invalid FCS (which will
also cause the receiver to reject the message).
The status of each receive message is available in the
appropriate RMD and CSR areas. FCS and Framing
errors (FRAM) are reported, although the received
frame is still passed to the host. The FRAM error will
only be reported if an FCS error is detected and there
are a non-integral number of bits in the message. The
MAC engine will ignore up to seven additional bits at
the end of a message (dribbling bits), which can occur
under normal network operating conditions. The reception of eight additional bits will cause the MAC engine
to de-serialize the entire byte, and will result in the
received message and FCS being modified.
The PCnet-ISA II controller can handle up to 7 dribbling
bits when a received packet terminates. During the
reception, the CRC is generated on every serial bit
(including the dribbling bits) coming from the cable,
although the internally saved CRC value is only
updated on the eighth bit (on each byte boundary). The
framing error is reported to the user as follows:
1. If the number of the dribbling bits are 1 to 7 and
there is no CRC error, then there is no Framing error
(FRAM = 0).
2. If the number of the dribbling bits are less than 8
and there is a CRC error, then there is also a
Framing error (FRAM = 1).
3. If the number of dribbling bits = 0, then there is no
Framing error. There may or may not be a CRC
(FCS) error.
Counters are provided to report the Receive Collision
Count and Runt Packet Count used for network statistics and utilization calculations.
Note that if the MAC engine detects a received packet
which has a 00b pattern in the preamble (after the first
Am79C961A
71
8 bits, which are ignored), the entire packet will be
ignored. The MAC engine will wait for the network to go
inactive before attempting to receive the next packet.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The 802.3/
Ethernet protocol defines a media access mechanism
which permits all stations to access the channel with
equality. Any node can attempt to contend for the channel by waiting for a predetermined time (Inter Packet
Gap interval) after the last activity, before transmitting
on the medium. The channel is a multidrop
communications medium (with various topological configurations permitted) which allows a single station to
transmit and all other stations to receive. If two nodes
simultaneously contend for the channel, their signals
will interact, causing loss of data (defined as a collision).
It is the responsibility of the MAC to attempt to avoid
and recover from a collision, to guarantee data integrity
for the end-to-end transmission to the receiving station.
Medium Allocation (collision avoidance)
The IEEE 802.3 Standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
traffic by looking for carrier activity. When carrier is
detected the medium is considered busy, and the MAC
should defer to the existing message.
The IEEE 802.3 Standard also allows optional two part
deferral after a receive message.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
“Note: It is possible for the PLS carrier sense
indication to fail to be asserted during a collision on the media. If the deference process
simply times the interpacket gap based on this
indication it is possible for a short interFrame
gap to be generated, leading to a potential reception failure of a subsequent frame. To enhance system robustness the following optional measures, as specified in 4.2.8, are recommended when InterFrameSpacingPart1 is
other than zero:
(1) Upon completing a transmission, start timing
the interpacket gap, as soon as transmitting
and carrier Sense are both false.
(2) When timing an interpacket gap following reception, reset the interpacket gap timing if carrier Sense becomes true during the first 2/3 of
the interpacket gap timing interval. During the
final 1/3 of the interval the timer shall not be reset to ensure fair access to the medium. An initial period shorter than 2/3 of the interval is
permissible including zero.”
The MAC engine implements the optional receive two
p a r t d e fe r r a l a l g o r i t h m , w i t h a f i r s t p a r t i n ter-frame-spacing time of 6.0 µs. The second part of
the inter-frame-spacing interval is therefore 3.6 µs.
72
The PCnet-ISA II controller will perform the two-part
deferral algorithm as specified in Section 4.2.8 (Process Deference). The Inter Packet Gap (IPG) timer will
start timing the 9.6 µs InterFrameSpacing after the
receive carrier is de-asserted. During the first part
deferral (InterFrameSpacingPart1 – IFS1) the PCnet-ISA II controller will defer any pending transmit
frame and respond to the receive message. The IPG
counter will be reset to zero continuously until the carrier de-asserts, at which point the IPG counter will
resume the 9.6 µs count once again. Once the IFS1
period of 6.0 µs has elapsed, the PCnet-ISA II controller will begi n timin g the s econ d p ar t defer ral
(InterFrameSpacingPart2 – IFS2) of 3.6 µs. Once IFS1
has completed, and IFS2 has commenced, the PCnet-ISA II controller will not defer to a receive packet if
a transmit packet is pending. This means that the PCnet-ISA II controller will not attempt to receive the receive packet, since it will start to transmit, and generate
a collision at 9.6 µs. The PCnet-ISA II controller will
guarantee to complete the preamble (64-bit) and jam
(32-bit) sequence before ceasing transmission and
invoking the random backoff algorithm.
In addition, transmit two part deferral is implemented
as an option which can be disabled using the
DXMT2PD bit (CSR3). Two-part deferral after transmission is useful for ensuring that severe IPG shrinkage cannot occur in specific circumstances, causing a
transmit message to follow a receive message so
closely as to make them indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should generate the SQE Test message (a nominal 10 MHz burst
of 5-15 bit times duration) on the CI± pair (within 0.6 µs
– 1.6 µs after the transmission ceases). During the time
period in which the SQE Test message is expected the
PCnet-ISA II controller will not respond to receive carrier sense.
See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1):
“At the conclusion of the output function, the
DTE opens a time window during which it expects to see the signal_quality_error signal asserted on the Control In circuit. The time window begins when the CARRIER_STATUS becomes CARRIER_OFF. If execution of the output function does not cause CARRIER_ON to
occur, no SQE test occurs in the DTE. The duration of the window shall be at least 4.0 µs but
no more than 8.0 µs. During the time window
the Carrier Sense Function is inhibited.”
The PCnet-ISA II controller implements a carrier sense
“blinding” period within 0 – 4.0 µs from de-assertion of
carrier sense after transmission. This effectively means
that when transmit two par t deferral is enabled
(DXMT2PD is cleared) the IFS1 time is from 4 µs to 6
Am79C961A
µs after a transmission. However, since IPG shrinkage
below 4 µs will rarely be encountered on a correctly
configured network, and since the fragment size will be
larger than the 4 µs blinding window, then the IPG
counter will be reset by a worst case IPG shrinkage/
fragment scenario and the PCnet-ISA II controller will
defer its transmission. In addition, the PCnet-ISA II
controller will not restart the “blinding” period if carrier
is detected within the 4.0 µs – 6.0 µs IFS1 period, but
will commence timing of the entire IFS1 period.
Contention resolution (collision handling)
Collision detection is performed and reported to the
MAC engine by the integrated Manchester Encoder/
Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the preamble/SFD has been completed, but prior to 512 bits
being transmitted, the MAC Engine will abort the transmission, and append the jam sequence immediately.
The jam sequence is a 32-bit all zeroes pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of collision will cause the transmission to be re-scheduled,
dependent on the backoff time that the MAC Engine
computes. If a single retry was required, the ONE bit
will be set in the Transmit Frame Status (TMD1 in the
Transmit Descriptor Ring). If more than one retry was
required, the MORE bit will be set. If all 16 attempts experienced collisions, the RTRY bit (in TMD3) will be set
(ONE and MORE will be clear), and the transmit message will be flushed from the FIFO. If retries have been
disabled by setting the DRTY bit in the MODE register
(CSR15), the MAC Engine will abandon transmission
of the frame on detection of the first collision. In this
case, only the RTRY bit will be set and the transmit
message will be flushed from the FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the
jam sequence, and set the LCOL bit. No retry attempt
will be scheduled on detection of a late collision, and
the FIFO will be flushed.
The IEEE 802.3 Standard requires use of a “truncated
binary exponential backoff” algorithm which provides a
controlled pseudo-random mechanism to enforce the
collision backoff interval, before re-transmission is
attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming),
the CSMA/CD sublayer delays before attempting to re-transmit the frame. The delay is an integer multiple of slot Time. The number of slot
times to delay before the nth re-transmission
attempt is chosen as a uniformly distributed
random integer r in the range:
0 ≤ r < 2k, where k = min (n,10).”
The PCnet-ISA II controller provides an alternative
algorithm, which suspends the counting of the slot
time/IPG during the time that receive carrier sense is
detected. This algorithm aids in networks where large
numbers of nodes are present, and numerous nodes
can be in collision. The algorithm effectively accelerates the increase in the backoff time in busy networks,
and allows nodes not involved in the collision to access
the channel while the colliding nodes await a reduction
in channel activity. Once channel activity is reduced,
the nodes resolving the collision time out their slot time
counters as normal.
Manchester Encoder/Decoder (MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Layer Signaling) functions required
for a fully compliant IEEE 802.3 station. The MENDEC
provides the encoding function for data to be transmitted on the network using the high accuracy on-board
oscillator, driven by either the crystal oscillator or an external CMOS-level compatible clock. The MENDEC
also provides the decoding function from data received
from the network. The MENDEC contains a Power On
Reset (POR) circuit, which ensures that all analog portions of the PCnet-ISA II controller are forced into their
correct state during power-up, and prevents erroneous
data transmission and/or reception during this time.
External Crystal Characteristics
When using a crystal to drive the oscillator, the crystal
specification shown in the specification table may be
used to ensure less than ±0.5 ns jitter at DO±.
Am79C961A
73
External Crystal Characteristics
Parameter
Min
1. Parallel Resonant Frequency
Nom Max Unit
20
MHz
2. Resonant Frequency Error
(CL = 20 pF)
–50
+50
PPM
3.Change in Resonant
Frequency With Respect
To Temperature
(0° – 70° C; CL = 20 pF)*
–40
+40
PPM
20
pF
4. Crystal Capacitance
5. Motional Crystal Capacitance
(C1)
0.022
pF
6. Series Resistance
25
Ω
7. Shunt Capacitance
7
pF
8. Drive Level
TBD mW
Requires trimming crystal spec; no trim is 50 ppm total
74
Am79C961A
External Clock Drive Characteristics
Receive Path
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than ±0.5 ns jitter at DO±.
The principal functions of the receiver are to signal the
PCnet-ISA II controller that there is information on the
receive pair, and to separate the incoming Manchester
encoded data stream into clock and NRZ data.
Clock Frequency:
20 MHz ±0.01%
Rise/Fall Time (tR/tF):
< 6 ns from 0.5 V to VDD–0.5
XTAL1 HIGH/LOW Time
(tHIGH/tLOW):
40 – 60% duty cycle
XTAL1 Falling Edge to
Falling Edge Jitter:
< ±0.2 ns at 2.5 V input (VDD/2)
The receiver section (see Receiver Block Diagram)
consists of two parallel paths. The receive data path is
a zero threshold, wide bandwidth line receiver. The
carrier path is an offset threshold bandpass detecting
line receiver. Both receivers share common bias
networks to allow operation over a wide input common
mode range.
Input Signal Conditioning
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO ± ) are
designed to operate into terminated transmission lines.
When operating into a 78 Ω terminated transmission
line, the transmit signaling meets the required output
levels and skew for Cheaper net, Ethernet, and
IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental-mode crystal oscillator provides the basic timing reference for the MENDEC portion of the PCnet-ISA II controller. The crystal input is
divided by two to create the internal transmit clock reference. Both clocks are fed into the Manchester
Encoder to generate the transitions in the encoded
data stream. The internal transmit clock is used by the
MENDEC to internally synchronize the Internal Transmit Data (ITXDAT) from the controller and Internal
Transmit Enable (ITXEN). The internal transmit clock is
also used as a stable bit-rate clock by the receive section of the MENDEC and controller.
The oscillator requires an external 0.005% crystal, or
an external 0.01% CMOS-level input as a reference.
The accuracy requirements, if an external crystal is
used, are tighter because allowance for the on-chip
oscillator must be made to deliver a final accuracy of
0.01%.
Transmission is enabled by the controller. As long as
the ITXEN request remains active, the serial output of
the controller will be Manchester encoded and appear
at DO±. When the internal request is dropped by the
controller, the differential transmit outputs go to one of
two idle states, dependent on TSEL in the Mode
Register (CSR15, bit 9):
TSEL LOW:
The idle state of DO± yields “zero”
differential to operate transformer-coupled
loads
TSEL HIGH:
In this idle state, DO+ is positive with respect
to DO– (logical HIGH).
Transient noise pulses at the input data stream are
rejected by the Noise Rejection Filter. Pulse width
rejection is proportional to transmit data rate which is
fixed at 10 MHz for Ethernet systems but which could
be different for proprietary networks. DC inputs more
negative than minus 100 mV are also suppressed.
The Carrier Detection circuitry detects the presence of
an incoming data packet by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock
acquisition. Clock acquisition requires a valid
Manchester bit pattern of 1010b to lock onto the incoming message.
When input amplitude and pulse width conditions are
met at DI±, a clock acquisition cycle is initiated.
Clock Acquisition
When there is no activity at DI± (receiver is idle), the
receive oscillator is phase-locked to STDCLK. The first
negative clock transition (bit cell center of first valid
Manchester “0") after clock acquisition begins interrupts the receive oscillator. The oscillator is then
restarted at the second Manchester “0" (bit time 4) and
is phase-locked to it. As a result, the MENDEC
acquires the clock from the incoming Manchester bit
pattern in 4 bit times with a “1010" Manchester bit pattern.
The internal receiver clock, IRXCLK, and the internal
received data, IRXDAT, are enabled 1/4 bit time after
clock acquisition in bit cell 5. IRXDAT is at a HIGH state
when the receiver is idle (no IRXCLK). IRXDAT however, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever IRXCLK is enabled. At 1/4 bit time through bit cell 5, the
controller portion of the PCnet-ISA II controller sees the
first IRXCLK transition. This also strobes in the
incoming fifth bit to the MENDEC as Manchester “1".
IRXDAT may make a transition after the IRXCLK rising
edge in bit cell 5, but its state is still undefined. The
Manchester “1" at bit 5 is clocked to IRXDAT output at
1/4 bit time in bit cell 6.
Am79C961A
75
PLL Tracking
After clock acquisition, the phase-locked clock is compared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a correction circuit. This circuit ensures that the
DI ±
phase-locked clock remains locked on the received
signal. Individual bit cell phase corrections of the
Voltage Controlled Oscillator (VCO) are limited to 10%
of the phase difference between BCC and phaselocked clock.
Data
Receiver
Manchester
Decoder
Noise
Reject
Filter
Carrier
Detect
Circuit
IRXDAT*
IRXCLK*
IRXCRS*
*Internal signal
19364B-16
Receiver Block Diagram
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI± inputs
after IRXCRS is asserted for an end of message.
IRXCRS de-asserts 1 to 2 bit times after the last positive transition on the incoming message. This initiates
the end of reception cycle. The time delay from the last
rising edge of the message to IRXCRS deassert allows
the last bit to be strobed by IRXCLK and transferred to
the controller section, but prevents any extra bit(s) at
the end of message. When IRXCRS de-asserts an
IRXCRS hold off timer inhibits IRXCRS assertion for at
least 2 bit times.
are specified so that the Ethernet specification for cable
termination impedance is met using standard 1%
resistor terminators. If SIP devices are used, 39 Ω is
the nearest usable equivalent value. The CI± differential inputs are terminated in exactly the same way as
the DI± pair.
AUI Isolation
Transformer
DI+
PCnet-ISA II
DI
Data Decoding
40.2 Ω
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the DI± inputs. Input
error is less than ±35 mV to minimize sensitivity to input
rise and fall time. IRXCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following IRXCLK. The data receiver also
generates the signal used for phase detector comparison to the internal MENDEC voltage controlled
oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI ±)
should be externally terminated by two 40.2 Ω ±1%
resistors and one optional common-mode bypass
capacitor, as shown in the Differential Input Termination diagram below. The differential input impedance,
ZIDF, and the common-mode input impedance, ZICM,
76
40.2 Ω
0.01 µF
to 0.1 µF
19364A-17
Differential Input Termination
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI± inputs.
This collision signal passes through an input stage
which detects signal levels and pulse duration. When
the signal is detected by the MENDEC it sets the internal collision signal, ICLSN, HIGH. The condition contin-
Am79C961A
ues for approximately 1.5 bit times after the last
LOW-to-HIGH transition on CI±.
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with
the values 1010b. Clock is phase-locked to the negative transition at the bit cell center of the second “0" in
the pattern.
Since data is strobed at 1/4 bit time, Manchester transitions which shift from their nominal placement
through 1/4 bit time will result in improperly decoded
data. With this as the criteria for an error, a definition of
“Jitter Handling” is:
The peak deviation approaching or crossing
1/4 bit cell position from nominal input transition, for which the MENDEC section will
properly decode data.
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which connects the DTE to a MAU. The differential interface provided by the PCnet-ISA II controller is fully compliant
with Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).
After the PCnet-ISA II controller initiates a transmission, it will expect to see data “looped-back” on the DI±
pair (when the AUI port is selected). This will internally
generate a “carrier sense”, indicating that the integrity
of the data path to and from the MAU is intact, and that
the MAU is operating correctly. This “carrier sense” signal must be asserted within sometime before end of
transmission. If “carrier sense” does not become active
in response to the data transmission, or becomes inactive before the end of transmission, the loss of carrier
(LCAR) error bit will be set in the Transmit Descriptor
Ring (TMD3, bit 11) after the packet has been
transmitted.
Twisted Pair Transceiver (T-MAU)
This section describes operation of the T-MAU when
operating in the Half Duplex mode. When in Half
Duplex mode, the T-MAU implements the Medium
Attachment Unit (MAU) functions for the Twisted Pair
Medium as specified by the supplement to IEEE 802.3
standard (Type 10BASE-T). When operating in Full
Duplex mode, the MAC engine behavior changes as
described in the Full Duplex Operation section. The
T-MAU provides twisted pair driver and receiver circuits, including on-board transmit digital predistortion
and receiver squelch, and a number of additional features including Link Status indication, Automatic
Twisted Pair Receive Polarity Detection/Correction and
Indication, Receive Carrier Sense, Transmit Active and
Collision Present indication.
Twisted Pair Transmit Function
The differential driver circuitry in the TXD± and TXP±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted Pair cable, as specified
by the 10BASE-T supplement to the IEEE 802.3 Standard. The transmit function for data output meets the
propagation delays and jitter specified by the standard.
Twisted Pair Receive Function
The receiver complies with the receiver specifications
of the IEEE 802.3 10BASE-T Standard, including noise
immunity and received signal rejection criteria (‘Smart
Squelch’). Signals meeting these criteria appearing at
the RXD ± differential input pair are routed to the
MENDEC. The receiver function meets the propagation
delays and jitter requirements specified by the standard. The receiver squelch level drops to half its threshold value after unsquelch to allow reception of
minimum amplitude signals and to offset carrier fade in
the event of worst case signal attenuation conditions.
Note that the 10BASE-T Standard defines the receive
input amplitude at the external Media Dependent Interface (MDI). Filter and transformer loss are not specified. The T-MAU receiver squelch levels are designed
to account for a 1 dB insertion loss at 10 MHz for the
type of receive filters and transformers usually used.
Normal 10BASE-T compatible receive thresholds are
invoked when the LRT bit (CSR15, bit 9) is LOW. When
the LRT bit is set, the Low Receive Threshold option is
invoked, and the sensitivity of the T-MAU receiver is
increased. Increasing T-MAU sensitivity allows the use
of lines longer than the 100 m target distance of standard 10BASE-T (assuming typical 24 AWG cable).
Increased receiver sensitivity compensates for the
increased signal attenuation caused by the additional
cable distance.
However, making the receiver more sensitive means
that it is also more susceptible to extraneous noise, primarily caused by coupling from co-resident services
(crosstalk). For this reason, end users may wish to
invoke the Low Receive Threshold option on 4-pair
cable only. Multi-pair cables within the same outer
sheath have lower crosstalk attenuation, and may allow
noise emitted from adjacent pairs to couple into the
receive pair, and be of sufficient amplitude to falsely
unsquelch the T-MAU.
Link Test Function
The link test function is implemented as specified by
10BASE-T standard. During periods of transmit pair
inactivity,’Link beat pulses’ will be periodically sent over
the twisted pair medium to constantly monitor medium
integrity.
Am79C961A
77
When the link test function is enabled (DLNKTST bit in
CSR15 is cleared), the absence of link beat pulses and
receive data on the RXD± pair will cause the TMAU to
go into the Link Fail state. In the Link Fail state, data
transmission, data reception, data loopback and the
collision detection functions are disabled and remain
disabled until valid data or greater than 5 consecutive
link pulses appear on the RXD± pair. During Link Fail,
the Link Status (LNKST indicated by LED0) signal is
inactive. When the link is identified as functional, the
LNKST signal is asserted, and LED0 output will be
activated. Upon power up or assertion of the RESET
pin, the T-MAU will be forced into the Link Fail state.
Reading the RESET register of the PCnet-ISA+ (software RESET) has no effect on the T-MAU
In order to inter-operate with systems which do not
implement Link Test, this function can be disabled by
setting the DLNKTST bit. With Link Test disabled, the
Data Driver, Receiver and Loopback functions as well
as Collision Detection remain enabled irrespective of
the presence or absence of data or link pulses on the
RXD± pair. Link Test pulses continue to be sent regardless of the state of the DLNKTST bit.
Polarity Detection and Reversal
The T-MAU receive function includes the ability to
invert the polarity of the signals appearing at the RXD±
pair if the polarity of the received signal is reversed
(such as in the case of a wiring error). This feature
allows data packets received from a reverse wired
RXD± input pair to be corrected in the T-MAU prior to
transfer to the MENDEC. The polarity detection function is activated following reset or Link Fail, and will
reverse the receive polarity based on both the polarity
of any previous link beat pulses and the polarity of subsequent packets with a valid End Transmit Delimiter
(ETD).
When in the Link Fail state, the T-MAU will recognize
link beat pulses of either positive or negative polarity.
Exit from the Link Fail state occurs at the reception of
5 – 6 consecutive link beat pulses of identical polarity.
On entry to the Link Pass state, the polarity of the last
5 link beat pulses is used to determine the initial
receive polarity configuration and the receiver is
reconfigured to subsequently recognize only link beat
pulses of the previously recognized polarity.
Positive link beat pulses are defined as transmitted signal with a positive amplitude greater than 585 mV with
a pulse width of 60 ns – 200 ns. This positive excursion
may be followed by a negative excursion. This definition is consistent with the expected received signal at a
correctly wired receiver, when a link beat pulse, which
fits the template of Figure 14-12 of the 10BASE-T Standard, is generated at a transmitter and passed through
100 m of twisted pair cable.
78
Negative link beat pulses are defined as transmitted
signals with a negative amplitude greater than 585 mV
with a pulse width of 60 ns – 200 ns. This negative
excursion may be followed by a positive excursion. This
definition is consistent with the expected received signal at a reverse wired receiver, when a link beat pulse
which fits the template of Figure 14-12 in the
10BASE-T Standard is generated at a transmitter and
passed through 100 m of twisted pair cable.
The polarity detection/correction algorithm will remain
“armed” until two consecutive packets with valid ETD of
identical polarity are detected. When “armed,” the
receiver is capable of changing the initial or previous
polarity configuration according to the detected ETD
polarity.
On receipt of the first packet with valid ETD following
reset or link fail, the T-MAU will use the inferred polarity
information to configure its RXD± input, regardless of
its previous state. On receipt of a second packet with a
valid ETD with correct polarity, the detection/correction
algorithm will “lock-in” the received polarity. If the second (or subsequent) packet is not detected as confirming the previous polarity decision, the most recently
detected ETD polarity will be used as the default. Note
that packets with invalid ETD have no effect on updating the previous polarity decision. Once two consecutive packets with valid ETD have been received, the
T-MAU will lock the correction algorithm until either a
Link Fail condition occurs or RESET is asserted.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when
enabled by the LED control bits in the ISA Bus Configuration Registers (ISACSR5, 6, 7).
Twisted Pair Interface Status
Three internal signals (XMT, RCV and COL) indicate
whether the T-MAU is transmitting, receiving, or in a
collision state. These signals are internal signals and
the behavior of the LED outputs depends on how the
LED output circuitry is programmed.
The T-MAU will power up in the Link Fail state and the
normal algorithm will apply to allow it to enter the Link
Pass state. In the Link Pass state, transmit or receive
activity will be indicated by assertion of RCV signal
going active. If T-MAU is selected using the PORTSEL
bits in CSR15, when moving from AUI to T-MAU selection, the T-MAU will be forced into the Link Fail state.
In the Link Fail state, XMT, RCV and COL are inactive.
Collision Detect Function
Activity on both twisted pair signals RXD± and TXD±
constitutes a collision, thereby causing the COL signal
to be asserted. (COL is used by the LED control circuits) COL will remain asserted until one of the two col-
Am79C961A
liding signals changes from active to idle. COL stays
active for 2 bit times at the end of a collision.
erating in the Full Duplex mode, the following changes
to device operation are made:
Signal Quality Error (SQE) Test
(Heartbeat) Function
Bus Interface/Buffer Management Unit changes:
The SQE function is disabled when the 10BASE-T port
is selected and in Link Fail state.
Jabber Function
The Jabber function inhibits the twisted pair transmit
function of the T-MAU if the TXD± circuit is active for an
excessive period (20 ms–150 ms). This prevents any
one node from disrupting the network due to a
‘stuck-on’ or faulty transmitter. If this maximum transmit
time is exceeded, the T-MAU transmitter circuitry is disabled, the JAB bit is set (CSR4, bit 1), and the COL signal asserted. Once the transmit data stream to the
T-MAU is removed, an “unjab” time of 250 ms – 750 ms
will elapse before the T-MAU deasserts COL and
re-enables the transmit circuitry.
Power Down
The T-MAU circuitry can be made to go into low power
mode. This feature is useful in battery powered or low
duty cycle systems. The T-MAU will go into power
down mode when RESET is active, coma mode is active, or the T-MAU is not selected. Refer to the Power
Down Mode section for a description of the various
power down modes.
Any of the three conditions listed above resets the
internal logic of the T-MAU and places the device into
power down mode. In this mode, the Twisted Pair
driver pins (TXD±,TXP±) are asserted LOW, and the internal T-MAU status signals (LNKST, RCVPOL, XMT,
RCV and COLLISION) are inactive.
Once the SLEEP pin is deasserted, the T-MAU will be
forced into the Link Fail state. The T-MAU will move to
the Link Pass state only after 5–6 link beat pulses and/
or a single received message is detected on the RXD±
pair.
In Snooze mode, the T-MAU receive circuitry will
remain enabled even while the SLEEP pin is driven
LOW.
The T-MAU circuitry will always go into power down
mode if RESET is asserted, coma is enabled, or the
T-MAU is not selected.
Full Duplex Operation
1. The first 64 bytes of every transmit frame are not
preserved in the transmit FIFO during transmission
of the first 512 bits transmitted on the network, as
described in the Transmit Exception Conditions
section. Instead, when Full Duplex mode is active
and a frame is being transmitted, the XMTFW bits
(CSR80, bits 9, 8) always govern when transmit
DMA is requested.
2. Successful reception of the first 64 bytes of every
receive frame is not a requirement for Receive DMA
to begin as described in the Receive Exception
Conditions section. Instead, receive DMA will be
requested as soon as either the RCVFW threshold
(CSR80 bits 12, 13) is reached or a complete valid
receive frame is in the Receive FIFO, regardless of
length. This receive FIFO operation is identical to
when the RPA bit (CSR124, bit 3) is set during Half
Duplex mode operation.
MAC Engine changes:
1. Changes to the Transmit Deferral mechanism:
A. Transmission is not deferred while receive is
active.
B. The Inter Packet Gap (IPG) counter which governs transmit deferral during the IPG between
back-to-back transmits is started when transmit
activity for the first packet ends instead of when
transmit and carrier activity ends.
2. When the AUI or GPSI port is active, Loss of Carrier
(LCAR) reporting is disabled (LCAR is still reported
when the 10BASE-T port is active if a packet is
transmitted while in the Link Fail state).
3. The 4.0 µs carrier sense blinding period after a
transmission during which the SQE test normally
occurs is disabled.
4. When the AUI or GPSI port is active, the SQE Test
error (Collision Error, CERR) reporting is disabled
(CERR is still reported when the 10BASE-T port is
active if a packet is transmitted while in the Link Fail
state).
5. The collision indication input to the MAC Engine is
ignored.
T-MAU changes:
The PCnet-ISA II supports Full Duplex operation on the
10BASE-T, AUI, and GPSI ports. Full Duplex operation
allows simultaneous transmit and receive activity on
the TXD± and RXD± pairs of the 10BASE-T port, the
DO± and DI± pairs of the AUI port, and the TXDAT and
RXDAT pins of the GPSI port. It is enabled by the
FDEN and AUIFD bits located in ISACSR9. When op-
1. The transmit to receive loopback path in the
T-MAU is disabled.
2. The collision detect circuit is disabled.
3. The “heartbeat” generation (SQE Test function)
is disabled.
Am79C961A
79
EADI (External Address Detection
Interface)
This interface is provided to allow external address filtering. It is selected by setting the EADISEL bit in
ISACSR2. This feature is typically utilized for terminal
servers, bridges and/or router type products. The use
of external logic is required to capture the serial bit
stream from the PCnet-ISA II controller, compare it with
a table of stored addresses or identifiers, and perform
the desired function.
The EADI interface operates directly from the NRZ
decoded data and clock recovered by the Manchester
decoder or input to the GPSI, allowing the external
address detection to be performed in parallel with
frame reception and address comparison in the MAC
Station Address Detection (SAD) block.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic.
SRDCLK runs only during frame reception activity.
Once a received frame commences and data and clock
are available, the EADI logic will monitor the alternating
(“1,0") preamble pattern until the two ones of the Start
Frame Delimiter (“1,0,1,0,1,0,1,1") are detected, at
which point the SF/BD output will be driven HIGH.
After SF/BD is asserted the serial data from SRD
should be de-serialized and sent to a content addressable memory (CAM) or other address detection device.
To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the
delineation of bytes, subsequent to the SFD. This provides a mechanism to allow not only capture and/or decoding of the physical or logical (group) address, it also
facilitates the capture of header information to
determine protocol and or inter-networking information.
The EAR pin is driven LOW by the external address
comparison logic to reject the frame.
If an internal address match is detected by comparison
with either the Physical or Logical Address field, the
frame will be accepted regardless of the condition of
EAR. Incoming frames which do not pass the internal
address comparison will continue to be received. This
allows approximately 58 byte times after the last destination address bit is available to generate the EAR
signal, assuming the device is not configured to accept
runt packets. EAR will be ignored after 64 byte times
after the SFD, and the frame will be accepted if EAR
has not been asserted before this time. If Runt Packet
Accept is configured, the EAR signal must be
generated prior to the receive message completion,
which could be as short as 12 byte times (assuming 6
bytes for source address, 2 bytes for length, no data, 4
bytes for FCS) after the last bit of the destination
address is available. EAR must have a pulse width of at
least 200 ns.
Note that setting the PROM bit (CSR15, bit 15) will
cause all receive frames to be received, regardless of
the state of the EAR input.
If the DRCUPA bit (CSR15.B) is set and the logical
address (LADRF) is set to zero, only frames which are
not rejected by EAR will be received.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
set). This situation is useful as a power down mode in
that the PCnet-ISA II controller will not perform any
DMA operations; this saves power by not utilizing the
ISA bus driver circuits. However, external circuitry
could still respond to specific frames on the network to
facilitate remote node control.
The table below summarizes the operation of the EADI
features.
Internal/External Address Recognition Capabilities
PROM
EAR
Required Timing
1
X
No timing requirements
All Received Frames
0
1
No timing requirements
All Received Frames
0
0
Low for 200 ns within 512 bits after SFD
Physical/Logical Matches
General Purpose Serial Interface (GPSI)
The PCnet-ISA II controller contains a General
Purpose Serial Interface (GPSI) designed for testing
the digital portions of the chip. The MENDEC, AUI, and
twisted pair interface are by-passed once the device is
set up in the special “test mode” for accessing the GPSI
functions. Although this access is intended only for
testing the device, some users may find the non-enc od e d d at a fu n c ti o n s u s ef u l i n s o me s p e c i al
80
Received Messages
applications. Note, however, that the GPSI functions
can be accessed only when the PCnet-ISA II devices
operate as a bus master.
The PCnet-ISA II GPSI signals are consistent with the
LANCE digital serial interface. Since the GPSI functions can be accessed only through a special test
mode, expect some loss of functionality to the device
when the GPSI is invoked. The AUI and 10BASE-T
analog interfaces are disabled along with the internal
Am79C961A
MENDEC logic. The LA (unlatched address) pins are
removed and become the GPSI signals, therefore, only
20 bits of address space is available. The table below
shows the GPSI pin configuration:
To invoke the GPSI signals, follow the procedure below:
1. After reset or I/O read of Reset Address, write 10b
to PORTSEL bits in CSR15.
2. Set the ENTST bit in CSR4
3. Set the GPSIEN bit in CSR124 (see note below)
(The pins LA17–LA23 will change function after the
completion of the above three steps.)
4. Clear the ENTST bit in CSR4
5. Clear Media Select bits in ISACSR2
6. Define the PORTSEL bits in the MODE register
(CSR15) to be 10b to define GPSI port. The MODE
register image is in the initialization block.
Note: LA pins will be tristated before writing to GPSIEN bit.
After writing to GPSIEN, LA[17–21] will be inputs, LA[22–23]
will be outputs.
GPSI Pin Configurations
GPSI Function
Receive Data
GPSI
I/O Type
LANCE
GPSI Pin
PCnet-ISA II
GPSI Pin
PCnet-ISA II
Pin Number
PCnet-ISA II Normal
Pin Function
I
RX
RXDAT
5
LA17
Receive Clock
I
RCLK
SRDCLK
6
LA18
Receive Carrier Sense
I
RENA
RXCRS
7
LA19
Collision
I
CLSN
CLSN
9
LA20
Transmit Clock
I
TCLK
STDCLK
10
LA21
Transmit Enable
O
TENA
TXEN
11
LA22
Transmit Data
O
TX
TXDAT
12
LA23
Note:
The GPSI Function is available only in the Bus Master Mode of operation.
Am79C961A
81
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board-level continuity test and diagnostics. All digital input, output, and input/output pins are
tested. Analog pins, including the AUI differential driver
(DO±) and receivers (DI±, CI±), and the crystal input
(XTAL1/XTAL2) pins, are tested. The T-MAU drivers
TXD±, TXP±, and receiver RXD± are also tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the PCnet-ISA II controller.
Boundary Scan Circuit
The boundary scan test circuit requires four extra pins
(TCK, TMS, TDI and TDO), defined as the Test Access
Port (TAP). It includes a finite state machine (FSM), an
instruction register, a data register array, and a
power-on reset circuit. Internal pull-up resistors are
provided for the TDI, TCK, and TMS pins. The TCK pin
must not be left unconnected. The boundary scan circuit remains active during sleep.
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power-up or RESET. An
independent power-on reset circuit is provided to
ensure the FSM is in the TEST_LOGIC_RESET state
at power-up.
additional instructions (IDCODE, TRIBYP
and SETBYP) are provided to further ease board-level
testing. All unused instruction codes are reserved. See
the table below for a summary of supported instructions.
Instruction Register and Decoding Logic
After hardware or software RESET, the IDCODE
instruction is always invoked. The decoding logic gives
signals to control the data flow in the DATA registers
according to the current instruction.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch are
used in the SERIAL SHIFT STAGE and the PARALLEL
OUTPUT STAGE, respectively.
There are four possible operational modes in the BSR cell:
1
2
3
4
Other Data Registers
(1) BYPASS REG (1 BIT)
(2) DEV ID REG (32 bits)
Bits 31–28:
Version
Bits 27–12:
Part number (2261h)
Bits 11–1:
Manufacturer ID. The 11 bit
manufacturer ID code for AMD is
00000000001 according to JEDEC
Publication 106-A.
Bit 0:
Always a logic 1
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST and SAMPLE instructions), three
Capture
Shift
Update
System Function
IEEE 1149.1 Supported Instruction Summary
Instruction
Name
Description
Mode
Instruction
Code
BSR
Test
0000
EXTEST
External Test
IDCODE
ID Code Inspection
ID REG
Normal
0001
SAMPLE
Sample Boundary
BSR
Normal
0010
TRIBYP
Force Tristate
Bypass
Normal
0011
SETBYP
Control Boundary to 1/0
Bypass
Test
0100
BYPASS
Bypass Scan
Bypass
Normal
1111
Power Saving Modes
The PCnet-ISA II controller supports two hardware
power-savings modes. Both are entered by asserting
the SLEEP pin LOW.
In coma mode, the PCnet-ISA II controller will go into
deep sleep with no support to automatically wake itself
up. Sleep mode is enabled when the AWAKE bit in
82
Selected
Data Reg
ISACSR2 is reset. This mode is the default powerdown
mode.
In Snooze mode, enabled by setting the AWAKE bit in
ISACSR2 and driving the SLEEP pin LOW, the T-MAU
receive circuitry will remain enabled even while the
SLEEP pin is driven LOW. The LED0 output will also
continue to function, indicating a good 10BASE-T link if
Am79C961A
there are link beat pulses or valid frames present. This
LED0 pin can be used to drive a LED and/or external
hardware that directly controls the SLEEP pin of the
PCnet-ISA II controller. This configuration effectively
wakes the system when there is any activity on the
10BASE-T link.
IEEE Address Access
Access Operations (Software)
Boot PROM Access
We begin by describing how byte and word data are
addressed on the ISA bus, including conversion cycles
where 16-bit accesses are turned into 8-bit accesses
because the resource accessed did not support 16-bit
operations. Then we describe how registers and other
resources are accessed. This section is for the device
programmer, while the next section (bus cycles) is for
the hardware designer.
The boot PROM is an external memory resource
located by the address selected by the EEPROM or the
BPAM input in slave mode. It may be software
accessed as an 8-bit or 16-bit resource but the latter is
recommended for best performance.
I/O Resources
The PCnet-ISA II controller has both I/O and memory
resources. In the I/O space the resources are organized as indicated in the following table:
Offset
#Bytes
Register
0h
16
IEEE Address
10h
2
RDP
12h
2
RAP(shared by RDP and IDP)
14h
2
Reset
16h
2
IDP
Static RAM Access
The static RAM is only present in the Bus Slave mode.
In the Bus Slave mode, two SRAM access schemes
are available. When the Shared Memory architecture
mode is selected, the SRAM is accessed using ISA
memory cycles to the address range selected by the
SMAM input. It may be accessed as an 8 or 16-bit
resource but the latter is recommended for best performance. When the Programmed I/O architecture mode
is selected, the SRAM is accessed through ISACSR0
and ISACSR1 using the RAP and IDP.
Bus Cycles (Hardware)
The PCnet-ISA II controller does not respond to any
addresses outside of the offset range 0-17h. I/O offsets
18h and up are not used by the PCnet-ISA II controller.
I/O Register Access
The register address port (RAP) is shared by the register data port (RDP) and the ISACSR data port (IDP) to
save registers. To access the Ethernet controller’s RDP
or IDP, the RAP should be written first, followed by the
read or write access to the RDP or IDP. I/O register
accesses should be coded as 16-bit accesses, even if
the PCnet-ISA II controller is hardware configured for
8-bit I/O bus cycles. It is acceptable (and transparent)
for the motherboard to turn a 16-bit software access
into two separate 8-bit hardware bus cycles. The motherboard accesses the low byte before the high byte and
the PCnet-ISA II controller has circuitry to specifically
support this type of access.
The reset register causes a reset when read. Any value
will be accepted and the cycle may be 8 or 16 bits wide.
Writes are ignored.
All PCnet-ISA II controller register accesses should be
coded as 16-bit operations.
“Note that the RAP is cleared on Reset.”
The address PROM may be an external memory
device that contains the node’s unique physical Ethernet address and any other data stored by the board
manufacturer. The software accesses must be 16-bit.
This information may be stored in the EEPROM.
The PCnet-ISA II controller supports both 8-bit and
16-bit hardware bus cycles. The following sections outline where any limitations apply based upon the architecture mode and/or the resource that is being
accessed (PCnet-ISA II controller registers, address
PROM, boot PROM, or shared memory SRAM). For
completeness, the following sections are arranged by
architecture (Bus Master Mode or Bus Slave Mode).
SRAM resources apply only to Bus Slave Mode.
All resources (registers, PROMs, SRAM) are presented to the ISA bus by the PCnet-ISA II controller.
With few exceptions, these resources can be configured for either 8-bit or 16-bit bus cycles. The I/O
resources (registers, address PROM) are width configured using the EEPROM. The memory resources
(boot PROM, SRAM) are width configured by external
hardware.
For 16-bit memory accesses, hardware external to the
PCnet-ISA II controller asserts MEMCS16 when either
of the two memory resources is selected. The ISA bus
requires that all memory resources within a block of
128 Kbytes be the same width, either 8- or 16-bits. The
reason for this is that the MEMCS16 signal is generally
a decode of the LA17-23 address lines. 16-bit memory
capability is desirable since two 8-bit accesses take the
same amount of time as four 16-bit accesses.
All accesses to 8-bit resources (which do not return
MEMCS16 or IOCS16) use SD0-7. If an odd byte is
accessed, the Current Master swap buffer turns on.
Am79C961A
83
During an odd byte read the swap buffer copies the
data from SD0-7 to the high byte. During an odd byte
write the Current Master swap buffer copies the data
from the high byte to SD0-7. The PCnet-ISA II controller can be configured to be an 8-bit I/O resource even
in a 16-bit system; this is set by the EEPROM. It is recommended that the PCnet-ISA II controller be configured for 8-bit only I/O bus cycles for maximum
compatibility with PC/AT clone motherboards.
When the PCnet-ISA II controller is in an 8-bit system
such as a PC/XT, SBHE and IOCS16 must be left
unconnected (these signals do not exist in the PC/XT).
This will force ALL resources (I/O and memory) to support only 8-bit bus cycles. The PCnet-ISA II controller
will function in an 8-bit system only if configured for Bus
Slave Mode.
Accesses to 16-bit resources (which do retur n
MEMCS16 or IOCS16) use either or both SD0–7 and
SD8–15. A word access is indicated by A0=0 and
SBHE=0 and data is transferred on all 16 data lines. An
even byte access is indicated by A0=0 and SBHE=1
and data is transferred on SD0–7. An odd-byte access
is indicated by A0=1 and SBHE=0 and data is transferred on SD8-15. It is illegal to have A0=1 and
SBHE=1 in any bus cycle. The PCnet-ISA II controller
returns only IOCS16; MEMCS16 must be generated by
external hardware if desired. The use of MEMCS16
applies only to Shared Memory Mode.
The following table describes all possible types of ISA
bus accesses, including Permanent Master as Current
Master and PCnet-ISA II controller as Current Master.
The PCnet-ISA II controller will not work with 8-bit
memory while it is Current Master. Any descriptions of
8-bit memory accesses are for when the Permanent
Master is Current Master.
The two byte columns (D0–7 and D8–15) indicate
whether the bus master or slave is driving the byte.
CS16 is a shorthand for MEMCS16 and IOCS16.
Bus Master Mode
The PCnet-ISA II controller can be configured as a Bus
Master only in systems that support bus mastering. In
addition, the system is assumed to support 16-bit
memory (DMA) cycles (the PCnet-ISA II controller
does not use the MEMCS16 signal on the ISA bus).
This does not preclude the PCnet-ISA II controller from
doing 8-bit I/O transfers. The PCnet-ISA II controller
will not function as a bus master in 8-bit platforms such
as the PC/XT.
Refresh Cycles
Although the PCnet-ISA II controller is neither an originator or a receiver of refresh cycles, it does need to
avoid unintentional activity during a refresh cycle in bus
master mode. A refresh cycle is performed as follows:
First, the REF signal goes active. Then a valid refresh
address is placed on the address bus. MEMR goes active, the refresh is performed, and MEMR goes inactive. The refresh address is held for a short time and
them goes invalid. Finally, REF goes inactive. During
a refresh cycle, as indicated by REF being active, the
PCnet-ISA II controller ignores DACK if it goes active
until it goes inactive. It is necessary to ignore DACK
during a refresh because some motherboards generate a false DACK at that time.
ISA Bus Accesses
R/W
A0
SBHE
CS16
D0–7
D8–15
Comments
RD
0
1
x
Slave
Float
Low byte RD
RD
1
0
1
Slave
Float
High byte RD with swap
RD
0
0
1
Slave
Float
16-Bit RD converted to low byte RD
RD
1
0
0
Float
Slave
High byte RD
RD
0
0
0
Slave
Slave
16-Bit RD
WR
0
1
x
Master
Float
Low byte WR
WR
1
0
1
Master
Float
High byte WR with swap
WR
0
0
1
Master
Master
16-Bit WR converted to
low byte WR
WR
1
0
0
Float
Master
High byte WR
WR
0
0
0
Master
Master
16-Bit WR
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA II controller Private Data
84
Bus. The PCnet-ISA II controller will support only 8-bit
ISA I/O bus cycles for the address PROM; this limitation is transparent to software and does not preclude
16-bit software I/O accesses. An access cycle begins
Am79C961A
with the Permanent Master driving AEN LOW, driving
the addressess valid, and driving IOR active. The
PCnet-ISA II controller detects this combination of signals and arbitrates for the Private Data Bus (PRDB) if
necessary. IOCHRDY is driven LOW during accesses
to the address PROM.
When the Private Data Bus becomes available, the
PCnet-ISA II controller drives APCS active, releases
IOCHRDY, turns on the data path from PRD0-7, and
enables the SD0-7 drivers (but not SD8-15). During
this bus cycle, IOCS16 is not driven active. This condition is maintained until IOR goes inactive, at which time
the bus cycle ends. Data is removed from SD0-7 within
30 ns.
Address PROM Cycles Using EEPROM Data
Default mode. In this mode, the IEEE address information is stored not in an external parallel PROM but in the
EEPROM along with other configuration information.
PCnet-ISA II will respond to I/O reads from the IEEE
address (the first 16 bytes of the I/O map) by supplying
data from an internal RAM inside PCnet-ISA II. This internal RAM is loaded with the IEEE address at RESET
and is write protected.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, IDP) are naturally 16-bit resources but can be configured to operate
with 8-bit bus cycles provided the proper protocol is followed. This means on a read, the PCnet-ISA II controller will only drive the low byte of the system data bus; if
an odd byte is accessed, it will be swapped down. The
high byte of the system data bus is never driven by the
PCnet-ISA II controller under these conditions. On a
write cycle, the even byte is placed in a holding register.
An odd byte write is internally swapped up and augmented with the even byte in the holding register to provide an internal 16-bit write. This allows the use of 8-bit
I/O bus cycles which are more likely to be compatible
with all ISA-compatible clones, but requires that both
bytes be written in immediate succession. This is
accomplished simply by treating the PCnet-ISA II controller registers as 16-bit software resources. The
motherboard will convert the 16-bit accesses done by
software into two sequential 8-bit accesses, an even
byte access followed immediately by an odd byte
access.
An access cycle begins with the Permanent Master
driving AEN LOW, driving the address valid, and driving
IOR or IOW active. The PCnet-ISA II controller detects
this combination of signals and drives IOCHRDY LOW.
IOCS16 will also be driven LOW if 16-bit I/O bus cycles
are enabled. When the register data is ready,
IOCHRDY will be released HIGH. This condition is
maintained until IOR or IOW goes inactive, at which
time the bus cycle ends.
RESET Cycles
A read to the reset address causes an PCnet-ISA II
controller reset. This has the same effect as asserting
the RESET pin on the PCnet-ISA+ controller (which
happens on system power up or on a hard boot) except
that the T-MAU is NOT reset. The T-MAU will retain its
link pass/fail state, disregarding the software RESET
command. The subsequent write cycle needed in the
NE2100 LANCE based family of Ethernet cards is not
required but does not have any harmful effects.
IOCS16 is not asserted in this cycle.
ISA Configuration Register Cycles
The ISA configuration registers are accessed by placing the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA II controller register bus cycles.
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA II controller Private Data Bus (PRDB) and
can occupy up to 64K of address space. Since the PCnet-ISA II controller does not generate MEMCS16, only
8-bit ISA memory bus cycles to the boot PROM are
supported in Bus Master Mode; this limitation is transparent to software and does not preclude 16-bit software memory accesses. A boot PROM access cycle
begins with the Per manent Master driving the
addresses valid, REF inactive, and MEMR active. (AEN
is not involved in memory cycles). The PCnet-ISA II
controller detects this combination of signals, drives
IOCHRDY LOW, and reads a byte out of the Boot
PROM. The data byte read is driven onto the lower system data bus lines and IOCHRDY is released. This
condition is maintained until MEMR goes inactive, at
which time the access cycle ends.
The BPCS signal generated by the PCnet-ISA II controller is three 20 MHz clock cycles wide (300 ns).
Including delays, the Boot PROM has 275 ns to
respond to the BPCS signal from the PCnet-ISA II controller. This signal is intended to be connected to the
CS pin on the boot PROM, with the PROM OE pin tied
to ground.
Current Master Operation
Current Master operation only occurs in the Bus Master
mode. It does not occur in the Bus Slave mode.
There are three phases to the use of the bus by the PCnet-ISA II controller as Current Master, the Obtain
Phase, the Access Phase, and the Release Phase.
Obtain Phase
A Master Mode Transfer Cycle begins by asserting
DRQ. When the Permanent Master asserts DACK, the
PCnet-ISA II controller asserts MASTER, signifying it
has taken control of the ISA bus. The Permanent Master tristates the address, command, and data lines
Am79C961A
85
within 60 ns of DACK going active. The Permanent
Master drives AEN inactive within 71 ns of MASTER
going active.
Access Phase
The ISA bus requires a wait of at least 125 ns after
MASTER is asserted before the new master is allowed
to drive the address, command, and data lines. The
PCnet-ISA II controller will actually wait 3 clock cycles
or 150 ns.
The following signals are not driven by the Permanent
Master and are simply pulled HIGH: BALE, IOCHRDY,
IOCS16, MEMCS16, SRDY. Therefore, the PCnet-ISA
II controller assumes the memory which it is accessing
is 16 bits wide and can complete an access in the time
programmed for the PCnet-ISA II controller MEMR and
MEMW signals. Refer to the ISA Bus Configuration
Register description section.
Release Phase
When the PCnet-ISA II controller is finished with the
bus, it drives the command lines inactive. 50 ns later,
the controller tri-states the command, address, and
data lines and drives DRQ inactive. 50 ns later, the controller drives MASTER inactive.
The Permanent Master drives AEN active within 71 ns
of MASTER going inactive. The Permanent Master is
allowed to drive the command lines no sooner than 60
ns after DACK goes inactive.
Master Mode Memory Read Cycle
After the PCnet-ISA II controller has acquired the ISA
bus, it can perform a memory read cycle. All timing is
generated relative to the 20 MHz clock (network clock).
Since there is no way to tell if memory is 8-bit or 16-bit
or when it is ready, the PCnet-ISA II controller by
default assumes 16-bit, 1 wait state memory. The wait
state assumption is based on the default value in the
MSRDA register in ISACSR0.
The cycle begins with SA0-19, SBHE, and LA17-23
being presented. The ISA bus requires them to be valid
for at least 28 ns before a read command and the PCnet-ISA II controller provides one clock or 50 ns of
setup time before asserting MEMR.
The ISA bus requires MEMR to be active for at least
219 ns, and the PCnet-ISA II controller provides a
default of 5 clocks, or 250 ns, but this can be tuned for
faster systems with the Master Mode Read Active
(MSRDA) register (see section 2.5.2). Also, if
IOCHRDY is driven LOW, the PCnet-ISA II controller
will wait. The wait state counter must expire and
IOCHRDY must be HIGH for the PCnet-ISA II controller
to continue.
The PCnet-ISA II controller then accepts the memory
read data. The ISA bus requires all command lines to
remain inactive for at least 97 ns before starting
86
another bus cycle and the PCnet-ISA II controller provides at least two clocks or 100 ns of inactive time.
The ISA bus requires read data to be valid no more
than 173 ns after receiving MEMR active and the PCnet-ISA II controller requires 10 ns of data setup time.
The ISA bus requires read data to provide at least 0 ns
of hold time and to be removed from the bus within 30
ns after MEMR goes inactive. The PCnet-ISA II controller requires 0 ns of data hold time.
Master Mode Memory Write Cycle
After the PCnet-ISA II controller has acquired the ISA
bus, it can perform a memory write cycle. All timing is
generated relative to a 20 MHz clock which happens to
be the same as the network clock. Since there is no
way to tell if memory is 8- or 16-bit or when it is ready,
the PCnet-ISA II controller by default assumes 16-bit, 1
wait state memory. The wait state assumption is based
on the default value in the MSWRA register in
ISACSR1.
The cycle begins with SA0-19, SBHE, and LA17-23
being presented. The ISA bus requires them to be valid
at least 28 ns before MEMW goes active and data to be
valid at least 22 ns before MEMW goes active. The PCnet-ISA II controller provides one clock or 50 ns of
setup time for all these signals.
The ISA bus requires MEMW to be active for at least
219 ns, and the PCnet-ISA II controller provides a
default of 5 clocks, or 250 ns, but this can be tuned for
faster systems with the Master Mode Write Active
(MSWRA) register (ISACSR1). Also, if IOCHRDY is
driven LOW, the PCnet-ISA II controller will wait.
IOCHRDY must be HIGH for the PCnet-ISA II controller
to continue.
The ISA bus requires data to be valid for at least 25 ns
after MEMW goes inactive, and the PCnet-ISA II controller provides one clock or 50 ns.
The ISA bus requires all command lines to remain
inactive for at least 97 ns before starting another bus
cycle. The PCnet-ISA II controller provides at least two
clocks or 100 ns of inactive time when bit 4 in ISACSR2
is set. The EISA bus requires all command lines to
remain inactive for at least 170 ns before starting
another bus cycle. When bit 4 in ISACSR4 is cleared,
the PCnet-ISA II controller provides 200 ns of inactive
time.
Back-to-Back DMA Requests
The PCnet-ISA II provides for fair bus bandwidth sharing between two bus mastering devices on the ISA bus
through an adaptive delay which is inserted between
back-to-back DMA requests.
When the PCnet-ISA II requires bus access immediately following a bus ownership period, it first checks
the status of the three currently unused DRQ pins. If a
Am79C961A
lower priority DRQ pin than the one currently being
used by the PCnet-ISA II is asserted, the PCnet-ISA II
will wait 2.6 µs after the deassertion of DACK before
re-asserting its DRQ pin. If no lower priority DRQ pin is
asserted, the PCnet-ISA II may re-assert its DRQ pin
after as short as 1.1 µs following DACK deassertion.
The priorities assumed by the PCnet-ISA II are ordered
DRQ3, DRQ5, DRQ6, DRQ7, with DRQ3 having highest priority and DRQ7 having the lowest priority. This
priority ordering matches that used by typical ISA bus
DMA controllers.
This adaptive delay scheme allows for fair bus bandwidth sharing when two bus mastering devices, e.g.
two PCnet-ISA II devices, are on an ISA bus. The controller using the higher priority DMA channel cannot
lock out the controller using the lower priority DMA
channel because of the 2.6 µs delay that is inserted
before DRQ reassertion when a lower priority DRQ pin
is asserted. When there is no lower priority DMA
request asserted, the PCnet-ISA II re-requests the bus
immediately, providing optimal performance when
there is no competition for bus access.
Bus Slave Mode
The PCnet-ISA II can be configured to be a bus slave
for systems that do not support bus mastering or
require a local memory to tolerate high bus latencies.
In the Bus Slave mode, the I/O map of the PCnet-ISA
II is identical to the I/O map when in the Bus Master
mode (see I/O Resources section). Hence, the address
PROM, controller registers, and Reset por t are
accessed through I/O cycles on the ISA bus. However,
the initialization block, descriptor rings, and buffers,
which are located in system memory when in the Bus
Master mode, are located in a local SRAM when in the
Bus Slave mode. The local SRAM can be accessed by
memory cycles on the ISA bus (Shared Memory architecture) or by I/O cycles on the ISA bus (Programmed
I/O mode).
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA II controller Private Data
Bus (PRDB). The PCnet-ISA II controller will support
only 8-bit ISA I/O bus cycles for the address PROM;
this limitation is transparent to software and does not
preclude 16-bit software I/O accesses. An access cycle
begins with the Permanent Master driving AEN LOW,
driving the addresses valid, and driving IOR active. The
PCnet-ISA II controller detects this combination of signals and arbitrates for the Private Data Bus if necessary. IOCHRDY is always driven LOW during address
PROM accesses.
When the Private Data Bus becomes available, the
PCnet-ISA II controller drives APCS active, releases
IOCHRDY, turns on the data path from PRD0-7, and
enables the SD0-7 drivers (but not SD8-15). During
this bus cycle, IOCS16 is not driven active. This condition is maintained until IOR goes inactive, at which time
the access cycle ends. Data is removed from SD0-7
within 30 ns.
The PCnet-ISA II controller will perform 8-bit ISA bus
cycle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, ISACSR) are
naturally 16-bit resources but can be configured to
operate with 8-bit bus cycles provided the proper protocol is followed. This is programmable by the
EEPROM. This means on a read, the PCnet-ISA II controller will only drive the low byte of the system data
bus; if an odd byte is accessed, it will be swapped
down. The high byte of the system data bus is never
driven by the PCnet-ISA II controller under these conditions. On a write, the even byte is placed in a holding
register. An odd-byte write is internally swapped up and
augmented with the even byte in the holding register to
provide an internal 16-bit write. This allows the use of
8-bit I/O bus cycles which are more likely to be compatible with all clones, but requires that both bytes be written in immediate succession. This is accomplished
simply by treating the PCnet-ISA II controller controller
registers as 16-bit software resources. The motherboard will convert the 16-bit accesses done by software into two sequential 8-bit accesses, an even-byte
access followed immediately by an odd-byte access.
An access cycle begins with the Permanent Master
driving AEN LOW, driving the address valid, and driving IOR or IOW active. The PCnet-ISA II controller detects this combination of signals and drives IOCHRDY
LOW. IOCS16 will also be driven LOW if 16-bit I/O bus
cycles are enabled. When the register data is ready,
IOCHRDY will be released HIGH. This condition is
maintained until IOR or IOW goes inactive, at which
time the bus cycle ends.
The PCnet-ISA II controller will perform 8-bit ISA bus
cycle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
RESET Cycles
A read to the reset address causes an PCnet-ISA II
controller reset. This has the same effect as asserting
the RESET pin on the PCnet-ISA+ controller (which
happens on system power up or on a hard boot) except
that the T-MAU is NOT reset. The T-MAU will retain its
link pass/fail state, disregarding the software RESET
command. The subsequent write cycle needed in the
NE2100 LANCE- based family of Ethernet cards is not
required but does not have any harmful effects.
IOCS16 is not asserted in this cycle.
Am79C961A
87
ISA Configuration Register Cycles
The ISA configuration register is accessed by placing
the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA II controller register bus cycles.
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA II controller Private Data Bus (PRDB), and
can occupy up to 64 Kbytes of address space. In
Shared Memory Mode, an external address comparator is responsible for asserting BPAM to the PCnet-ISA
II controller. BPAM is intended to be a perfect decode
of the boot PROM address space, i.e. LA17-23, SA16.
The LA bus must be latched with BALE in order to provide stable signal for BPAM. REF inactive must be
used by the external logic to gate boot PROM address
decoding. This same logic must assert MEMCS16 to
the ISA bus if 16-bit Boot PROM bus cycles are
desired.
In the Bus Slave mode, boot PROM cycles can be programmed to be 8 or 16-bit ISA memory cycles with the
BP_16B bit (PnP 0x42). If the BP_16B bit is set, the
PCnet-ISA II assumes 16-bit ISA memory cycles for
the boot PROM. In this case, the external hardware
responsible for generating BPAM must also generate
MEMCS16. A 16-bit boot PROM bus cycle begins with
the Permanent Master driving the addresses valid and
MEMR active. (AEN is not involved in memory cycles).
External hardware would assert BPAM and MEMCS16.
The PCnet-ISA II controller detects this combination of
signals, drives IOCHRDY LOW, and reads two bytes
out of the boot PROM. The data bytes read from the
PROM are driven by the PCnet-ISA II controller onto
SD0-15 and IOCHRDY is released. This condition is
maintained until MEMR goes inactive, at which time the
access cycle ends.
The PCnet-ISA II controller will perform 8-bit ISA bus
cycle operation for all resource (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
The BPCS signal generated by the PCnet-ISA II controller is three 20 MHz clock cycles wide (350 ns).
Including delays, the Boot PROM has 275 ns to
respond to the BPCS signal from the PCnet-ISA II controller. This signal is intended to be connected to the
CS pin on the boot PROM, with the PROM OE pin tied
to ground.
Static RAM Cycles – Shared Memory Architecture
In the Shared Memory Architecture mode, the SRAM is
an 8-bit device connected to the PCnet-ISA II controller
Private Bus, and can occupy up to 64 Kbytes of
address space. The SRAM is memory mapped into the
ISA memory space at an address range determined by
external decode logic. The external address compara-
88
tor is responsible for asserting SMAM to the PCnet-ISA
II controller. SMAM is intended to be a perfect decode
of the SRAM address space, i.e. LA17-23, SA16 for 64
Kbytes of SRAM. The LA signals must be latched by
BALE in order to provide a stable decode for SMAM.
The PCnet-ISA II controller assumes 16-bit ISA memory bus cycles for the SRAM, so this same logic must
assert MEMCS16 to the ISA bus if 16-bit bus cycles are
to be supported.
A 16-bit SRAM bus cycle begins with the Permanent
Master driving the addresses valid, REF inactive, and
either MEMR or MEMW active. (AEN is not involved in
memory cycles). External hardware would assert
SMAM and MEMCS16. The PCnet-ISA II controller
detects this combination of signals and initiates the
SRAM access.
In a write cycle, the PCnet-ISA II controller stores the
data into an internal holding register, allowing the ISA
bus cycle to finish normally. The data in the holding register will then be written to the SRAM without the need
for ISA bus control. In the event the holding register is
already filled with unwritten SRAM data, the PCnet-ISA
II controller will extend the ISA write cycle by driving
IOCHRDY LOW until the unwritten data is stored in the
SRAM. The current ISA bus cycle will then complete
normally.
In a read cycle, the PCnet-ISA II controller arbitrates for
the Private Bus. If it is unavailable, the PCnet-ISA II
controller drives IOCHRDY LOW. The PCnet-ISA II
controller compares the 16 bits of address on the System Address Bus with that of a data word held in an
internal pre-fetch register.
If the address does not match that of the prefetched
SRAM data, then the PCnet-ISA II controller drives
IOCHRDY LOW and reads two bytes from the SRAM.
The PCnet-ISA II controller then proceeds as though
the addressed data location had been prefetched.
If the internal prefetch buffer contains the correct data,
then the pre-fetch buffer data is driven on the System
Data bus. If IOCHRDY was previously driven LOW due
to either Private Data Bus arbitration or SRAM access,
then it is released HIGH. The PCnet-ISA II controller
remains in this state until MEMR is de-asserted, at
which time the PCnet-ISA II controller performs a new
prefetch of the SRAM. In this way memory read wait
states can be minimized.
The PCnet-ISA II controller performs prefetches of the
SRAM between ISA bus cycles. The SRAM is
prefetched in an incrementing word address fashion.
Prefetched data are invalidated by any other activity on
the Private Bus, including Shared Memory Writes by
either the ISA bus or the network interface, and also
address and boot PROM reads.
Am79C961A
The only way to configure the PCnet-ISA II controller
for 8-bit ISA bus cycles for SRAM accesses is to configure the entire PCnet-ISA II controller to support only
8-bit ISA bus cycles. This is accomplished by leaving
the SBHE pin disconnected. The PCnet-ISA II controller will perform 8-bit ISA bus cycle operation for all
resources (registers, PROMs, SRAM) if SBHE has
never been driven active since the last RESET, such as
in the case of an 8-bit system like the PC/XT. In this
case, the external address decode logic must not
assert MEMCS16 to the ISA bus, which will be the case
if MEMCS16 is left unconnected. It is possible to manufacture a dual 8/16 bit PCnet-ISA II controller adapter
card, as the MEMCS16 and SBHE signals do not exist
in the PC/XT environment.
At the memory device level, each SRAM Private Bus
read cycle takes two 50 ns clock periods for a maximum read access time of 75 ns. The timing looks like
this:
XTAL1
(20 MHz)
Address
SROE
19364B-18
Static RAM Read Cycle
The address and SROE go active within 20 ns of the
clock going HIGH. Data is required to be valid 5 ns
before the end of the second clock cycle. Address and
SROE have a 0 ns hold time after the end of the second
clock cycle. Note that the PCnet-ISA II controller does
not normally provide a separate SRAM CS signal;
SRAM CS must always be asserted.
SRAM Private Bus write cycles require three 50 ns
clock periods to guarantee non-negative address setup
and hold times with regard to SRWE. The timing is
illustrated as follows:
XTAL1
(20 MHz)
Address/
Data
SRWE
Static
19364B-19
Address and data are valid 20 ns after the rising edge
of the first clock period. SRWE goes active 20 ns after
the falling edge of the first clock period. SRWE goes
inactive 20 ns after the falling edge of the third clock
period. Address and data remain valid until the end of
the third clock period. Rise and fall times are nominally
5 ns. Non-negative setup and hold times for address
and data with respect to SRWE are guaranteed. SRWE
has a pulse width of typically 100 ns, minimum 75 ns.
Static RAM Cycles – Programmed I/O Architecture
In the Programmed I/O Architecture mode, the SRAM
is an 8-bit device connected to the PCnet-ISA II controller Private Bus, and can occupy up to 64 Kbytes of
address space. The SRAM is accessed through the
ISACSR0 and ISACSR1 registers which serve as the
SRAM Data port and SRAM Address pointer, respectively. Since the ISACSRs are used to access the
SRAM, simple I/O accesses (to RAP and IDP) which
are decoded by the PCnet-ISA II are used to access
the SRAM without any external decoding logic.
The RAP and IDP ports are naturally 16-bit resources
and can be accessed with 16-bit ISA I/O cycles if the
IO_MODE bit (PnP 0xF0) is set. As discussed in the
Ethernet Controller Register Cycles section, 8-bit I/O
cycles are also allowed, provided the proper protocol is
followed. This protocol requires that byte accesses
must be performed in pairs, with the even byte access
always being followed by associated odd byte access.
In the Programmed I/O architecture mode, when
a c c e s s i n g t h e S R A M D a t a Po r t i n p a r t i c u l a r
(ISACSR0), the restrictions on byte accesses are
slightly different. Even byte accesses (accesses where
A0 = 0, SBHE = 1) may be performed to ISACSR0 without any restriction. A corresponding odd byte access
need not be performed following the even byte access
as is required when accessing all other controller registers. In fact, odd byte accesses (accesses where A0
= 1, SBHE = 1) may not be performed to ISACSR0, except when they are the result of a software 16-bit
access that are automatically converted to two byte accesses by motherboard logic.
Since the internal PCnet-ISA II registers are used to
access the SRAM in the Programmed I/O architecture
mode, the access cycle on the ISA bus is identical to
that described in the Ethernet Controller Register
Cycles section.
To minimize the number of I/O cycles required to
access the SRAM, the PCnet-ISA II auto-increments
the SRAM Address Pointer (ISACSR1) by one or two
following every read or write to the SRAM Data Port
(ISACSR0). If a single byte read or write to the SRAM
Data Port occurs, the SRAM Address Pointer is automatically incremented by 1. If a word read or write to
the SRAM Data Port occurs, the SRAM Address
Pointer is automatically incremented by 2. This allows
Am79C961A
89
reads and writes to adjacent ascending addresses in
the SRAM to be performed without intervening writes to
the SRAM Address Pointer. Since buffer accesses
comprise a high percentage of all accesses to the
SRAM, and buffer accesses are typically performed in
adjacent ascending order, the auto-increment of the
SRAM Address Pointer reduces the required ISA bus
cycles significantly.
In addition to the auto-incrementing of the SRAM
Address pointer, the PCnet-ISA II performs write posting on writes to the SRAM and read prefetching on
reads from the SRAM to maximize performance in the
Programmed I/O architecture mode.
Write Posting: When a write cycle to the SRAM Data
Port occurs, the PCnet-ISA II controller stores the data
into an internal holding register, allowing the ISA bus
cycle to finish normally. The data in the holding register
will then be written to the SRAM without the need for
ISA bus control. In the event that the holding register is
already filled with unwritten SRAM data, the PCnet-ISA
II controller will extend the ISA write cycle by driving
OCHRDY LOW until the unwritten data is stored in the
SRAM. Once the data is written into the SRAM, the
new write data is stored into the internal holding register and IOCHRDY is released allowing the ISA bus
cycle to complete.
Read Prefetching: To gain performance on read
accesses to the SRAM, the PCnet-ISA II performs
prefetches of the SRAM after every read from the
SRAM Data Port. The prefetch is performed using the
speculated address that results from the auto-increment that occurs on the SRAM Address Pointer following every access to the SRAM Data Port. Following
every read access, the 16-bit word following the
just-read SRAM byte or word is prefetched and placed
in a holding register. If a word read from the SRAM
Data Port occurs before a “prefetch invalidation event”
occurs, the prefetched word is driven onto the SD[15:0]
pins without a wait state (no IOCHRDY LOW assertion). A “prefetch invalidation event” is defined as any
activity on the Private Bus other than SRAM reads.
This includes SRAM writes by either the ISA bus or the
network interface, address or boot PROM reads, or any
write to the SRAM Address Pointer.
The PCnet-ISA II interface to the SRAM in the Programmed I/O architecture mode is identical to that in
the Shared Memory Architecture mode. Hence, the
SRAM Read and Write cycle descriptions and diagrams shown in the “Static RAM Cycles – Shared
Memory Architecture” section apply.
Transmit Operation
The transmit operation and features of the PCnet-ISA
II controller are controlled by programmable options.
90
Transmit Function Programming
Automatic transmit features, such as retry on collision,
FCS generation/transmission, and pad field insertion,
can all be programmed to provide flexibility in the
(re-)transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initialization block.
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4. If APAD_XMT is set, automatic pad field insertion is enabled, the DXMTFCS feature is over-ridden, and the 4-byte FCS will be added to
the transmitted frame unconditionally. If APAD_XMT is
cleared, no pad field insertion will take place and runt
packet transmission is possible.
The disable FCS generation/transmission feature can
be programmed dynamically on a frame by frame
basis. See the ADD_FCS description of TMD1.
Transmit FIFO Watermark (XMTFW in CSR80) sets
the point at which the BMU (Buffer Management Unit)
requests more data from the transmit buffers for the
FIFO. This point is based upon how many 16-bit bus
transfers (2 bytes) could be performed to the existing
empty space in the transmit FIFO.
Transmit Start Point (XMTSP in CSR80) sets the point
when the transmitter actually tries to go out on the
media. This point is based upon the number of bytes
written to the transmit FIFO for the current frame.
When the entire frame is in the FIFO, attempts at transmission of preamble will commence regardless of the
value in XMTSP. The default value of XMTSP is 10b,
meaning 64 bytes full.
Automatic Pad Generation
Transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). This
allows the minimum frame size of 64 bytes (512 bits)
for 802.3/Ethernet to be guaranteed with no software
intervention from the host/controlling process. Setting
the APAD_XMT bit in CSR4 enables the automatic
padding feature. The pad is placed between the LLC
data field and FCS field in the 802.3 frame. FCS is always added if the frame is padded, regardless of the
state of DXMTFCS. The transmit frame will be padded
by bytes with the value of 00h. The default value of
APAD_XMT is 0, and this will disable auto pad generation after RESET.
It is the responsibility of upper layer software to correctly define the actual length field contained in the
message to correspond to the total number of LLC
Data bytes encapsulated in the packet (length field as
defined in the IEEE 802.3 standard). The length value
contained in the message is not used by the PCnet-ISA
II controller to compute the actual number of pad bytes
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to be inserted. The PCnet-ISA II controller will append
pad bytes dependent on the actual number of bits
transmitted onto the network. Once the last data byte of
the frame has completed prior to appending the FCS,
the PCnet-ISA II controller will check to ensure that 544
bits have been transmitted. If not, pad bytes are added
to extend the frame size to this value, and the FCS is
then added.
generate and append the FCS to the transmitted frame.
I f t h e a u t o m a t i c p a d d i n g fe a t u r e i s i n vo k e d
(APAD_XMT is SET in CSR4), the FCS will be
appended by the PCnet-ISA II controller regardless of
the state of DXMTFCS. Note that the calculated FCS is
transmitted most-significant bit first. The default value
of DXMTFCS is 0 after RESET.
The 544 bit count is derived from the following:
Exception conditions for frame transmission fall into
two distinct categories; those which are the result of
normal network operation, and those which occur due
to abnormal network and/or host related events.
Minimum frame size (excluding preamble,
including FCS)
64 bytes
512 bits
Preamble/SFD size 8 bytes
64 bits
FCS size
4 bytes
32 bits
To be classed as a minimum-size frame at the receiver,
the transmitted frame must contain:
Preamble
+
(Min Frame Size + FCS) bits
At the point that FCS is to be appended, the transmitted
frame should contain:
Preamble
64+
+
(Min Frame Size - FCS) bits
(512- 32) bits
A minimum-length transmit frame from the PCnet-ISA
II controller will, therefore, be 576 bits after the FCS is
appended.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS bit
in CSR15. When DXMTFCS = 0 the transmitter will
Transmit Exception Conditions
Normal events which may occur and which are handled
autonomously by the PCnet-ISA II controller are basically collisions within the slot time with automatic retry.
The PCnet-ISA II controller will ensure that collisions
which occur within 512 bit times from the start of transmission (including preamble) will be automatically
retried with no host intervention. The transmit FIFO ensures this by guaranteeing that data contained within
the FIFO will not be overwritten until at least 64 bytes
(512 bits) of data have been successfully transmitted
onto the network.
If 16 total attempts (initial attempt plus 15 retries) fail,
the PCnet-ISA II controller sets the RTRY bit in the current transmit TDTE in host memory (TMD2), gives up
ownership (sets the OWN bit to zero) for this packet,
and processes the next packet in the transmit ring for
transmission.
Preamble
1010....1010
SYNC
10101011
Dest.
ADDR
SRCE.
ADDR.
Length
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
LLC
Data
Pad
FCS
4
Bytes
46-1500
Bytes
19364B-20
ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
Am79C961A
91
Abnormal network conditions include:
Host related transmit exception conditions include
BUFF and UFLO as described in the Transmit Descriptor section.
■ Loss of carrier
■ Late collision
■ SQE Test Error (Does not apply to 10BASE-T port.)
These should not occur on a correctly configured 802.3
network, and will be reported if they do.
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in
the current descriptor. The OWN bit(s) in the subsequent descriptor(s) will be reset until the STP (the next
frame) is found.
Loss of Carrier
A loss of carrier condition will be reported if the PCnet-ISA II controller cannot observe receive activity
while it is transmitting on the AUI port. After the PCnet-ISA II controller initiates a transmission, it will expect to see data “looped back” on the DI± pair. This will
internally generate a “carrier sense,” indicating that the
integrity of the data path to and from the MAU is intact,
and that the MAU is operating correctly. This “carrier
sense” signal must be asserted before the end of the
transmission. If “carrier sense” does not become active
in response to the data transmission, or becomes inactive before the end of transmission, the loss of carrier
(LCAR) error bit will be set in TMD2 after the frame has
been transmitted. The frame will not be re-tried on the
basis of an LCAR error. In 10BASE-T mode LCAR will
indicate that Jabber or Link Fail state has occurred.
Late Collision
A late collision will be reported if a collision condition
occurs after one slot time (512 bit times) after the transmit process was initiated (first bit of preamble commenced). The PCnet-ISA II controller will abandon the
transmit process for the particular frame, set Late Collision (LCOL) in the associated TMD3, and process the
next transmit frame in the ring. Frames experiencing a
late collision will not be re-tried. Recovery from this
condition must be performed by upper-layer software.
SQE Test Error
During the inter packet gap time following the completion of a transmitted message, the AUI CI ± pair is
asserted by some transceivers as a self-test. The integral Manchester Encoder/Decoder will expect the SQE
Test Message (nominal 10 MHz sequence) to be
returned via the CI± pair within a 40 network bit time
period after DI± pair goes inactive. If the CI± inputs are
not asserted within the 40 network bit time period following the completion of transmission, then the PCnet-ISA II controller will set the CERR bit in CSR0.
CERR will be asserted in 10BASE-T mode after transmit if T-MAU is in Link Fail state. CERR will never cause
INTR to be activated. It will, however, set the ERR bit in
CSR0.
92
Receive Operation
The receive operation and features of the PCnet-ISA II
controller are controlled by programmable options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4; this can provide flexibility in
the reception of messages using the 802.3 frame format.
All receive frames can be accepted by setting the
PROM bit in CSR15. When PROM is set, the PCnet-ISA II controller will attempt to receive all messages, subject to minimum frame enforcement.
Promiscuous mode overrides the effect of the Disable
Receive Broadcast bit on receiving broadcast frames.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established
during reset is 10b, which sets the threshold flag at 64
bytes empty.
Automatic Pad Stripping
During reception of an 802.3 frame the pad field can be
stripped automatically. ASTRP_RCV (bit 10 in CSR4) =
1 enables the automatic pad stripping feature. The pad
field will be stripped before the frame is passed to the
FIFO, thus preserving FIFO space for additional
frames. The FCS field will also be stripped, since it is
computed at the transmitting station based on the data
and pad field characters, and will be invalid for a
receive frame that has had the pad characters stripped.
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the IEEE
802.3 definition) contained in the frame. The length
indicates the actual number of LLC data bytes contained in the message. Any received frame which contains a length field less than 46 bytes will have the pad
field stripped (if ASTRP_RCV is set). Receive frames
which have a length field of 46 bytes or greater will be
passed to the host unmodified.
Since any valid Ethernet Type field value will always be
greater than a normal 802.3 Length field (≥46), the PCnet-ISA II controller will not attempt to strip valid Ethernet frames.
Note that for some network protocols the value passed
in the Ethernet Type and/or 802.3 Length field is not
compliant with either standard and may cause problems.
The diagram below shows the byte/bit ordering of the
received length field for an 802.3 compatible frame
format.
Am79C961A
56
Bits
Preamble
1010....1010
8
Bits
6
Bytes
6
Bytes
2
Bytes
SYNCH
10101011
Dest.
ADDR.
Srce.
ADDR.
Length
Bytes
4
Bytes
LLC
DATA
Pad
1–1500
Bytes
45–0
Bytes
FCS
Start of Packet
at Time= 0
Bit Bit
7 0
Bit
0
Increasing Time
Most
Significant
Byte
Bit
7
Least
Significant
Byte
19364B-21
IEEE/ANSI 802.3 Frame and Length Field Transmission Order
Receive FCS Checking
■ FCS errors
Reception and checking of the received FCS is performed automatically by the PCnet-ISA II controller.
Note that if the Automatic Pad Stripping feature is
enabled, the received FCS will be verified against the
value computed for the incoming bit stream including
pad characters, but it will not be passed to the host. If
a FCS error is detected, this will be reported by the
CRC bit in RMD1.
■ Late collision
Receive Exception Conditions
Loopback is a mode of operation intended for system
diagnostics. In this mode, the transmitter and receiver
are both operating at the same time so that the
controller receives its own transmissions. The controller provides two types of internal loopback and three
types of external loopback. In internal loopback mode,
the transmitted data can be looped back to the receiver
at one of two places inside the controller without actually transmitting any data to the external network. The
receiver will move the received data to the next receive
buffer, where it can be examined by software. Alternatively, external loopback causes transmissions to go
off-chip. For the AUI port, frame transmission occurs
normally and assumes that an external MAU will loop
the frame back to the chip. For the 10BASE-T port, two
external loopback options are available, both of which
require a valid link pass state and both of which transmit data frames at the RJ45 interface. Selection of
these modes is defined by the TMAU_LOOPE bit in
ISACSR2. One option loops the data frame back inside
the chip, and is compatible with a ‘live’ network. The
Exception conditions for frame reception fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to
abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA II controller are basically collisions within the slot time and automatic runt
packet rejection. The PCnet-ISA II controller will ensure
that collisions which occur within 512 bit times from the
start of reception (excluding preamble) will be automatically deleted from the receive FIFO with no host intervention. The receive FIFO will delete any frame which
is composed of fewer than 64 bytes provided that the
Runt Packet Accept (RPA bit in CSR124) feature has
not been enabled. This criteria will be met regardless of
whether the receive frame was the first (or only) frame
in the FIFO or if the receive frame was queued behind
a previously received message.
Abnormal network conditions include:
These should not occur on a correctly configured 802.3
network and will be reported if they do.
Host related receive exception conditions include
MISS, BUFF, and OFLO. These are described in the
Receive Descriptor section.
Loopback Operation
Am79C961A
93
other option requires an external device (such as a
‘loopback plug’) to loop the data back to the chip, a
function normally not available on a 10BASE-T
network.
The PCnet-ISA II chip has two dedicated FCS generators, eliminating the traditional LANCE limitations on
loopback FCS operation. The receive FCS generation
logic is always enabled. The transmit FCS generation
logic can be disabled (to emulate LANCE type loopback operation) by setting the DXMTFCS bit in the
Mode register (CSR15). In this configuration, software
must generate the FCS and append the four FCS bytes
to the transmit frame data.
The loopback facilities of the MAC Engine allow full
operation to be verified without disturbance to the network. Loopback operation is also affected by the state
of the Loopback Control bits (LOOP, MENDECL, and
INTL) in CSR15. This affects whether the internal
MENDEC is considered part of the internal or external
loop- backpath.
The receive FCS generation logic in the PCnet-ISA II
chip is used for multicast address detection. Since this
FCS logic is always enabled, there are no restrictions
to the use of multicast addressing while in loopback
mode.
When performing an internal loopback, no frame will be
transmitted to the network. However, when the PCnet-ISA II controller is configured for internal loopback
the receiver will not be able to detect network traffic.
External loopback tests will transmit frames onto the
network if the AUI port is selected, and the PCnet-ISA
II controller will receive network traffic while configured
for external loopback when the AUI port is selected.
Runt Packet Accept is automatically enabled when any
loopback mode is invoked.
Loopback mode can be performed with any frame size.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is
invoked. This is to be backwards compatible to the
LANCE (Am7990) software.
LEDs
The PCnet-ISA II controller’s LED control logic allows
programming of the status signals, which are displayed
on 3 LED outputs. One LED (LED0) is dedicated to displaying 10BASE-T Link Status. The status signals
available are Collision, Jabber, Receive, Receive Polarity, Transmit, Receive Address Match, and Full Duplex
Link Status. If more than one status signal is enabled,
they are ORed together. An optional pulse stretcher is
available for each programmable output. This allows
emulation of the TPEX (Am79C98) and TPEX +
(Am79C100) LED outputs.
94
Signal
Behavior
COL
Active during collision activity on the network
FDLS
Active when Full Duplex operation is enabled
and functioning on the selected network port
JAB
Active when the PCnet-ISA II is jabbering on
the network
LNKST
Active during Link OK Not active during Link
Down
RCV
Active while receiving data
RVPOL
Active during receive polarity is OK Not active
during reverse receive polarity
RCVADDM Active during Receive with Address Match
XMT
Active while transmitting data
Each status signal is ANDed with its corresponding
enable signal. The enabled status signals run to a common OR gate:
FDLS
FDLSE
AND
RCVM
RCVM E
AND
XMT
XMT E
AND
RVPOL
RVPOL E
AND
RCV
RCV E
AND
JAB
JAB E
AND
COL
COL E
AND
RCVADDM
RCVADDE
AND
OR
To
Pulse
Stretcher
19364B-22
LED Control Logic
The output from the OR gate is run through a pulse
stretcher, which consists of a 3-bit shift register clocked
at 38 Hz. The data input of the shift register is at logic
0. The OR gate output asynchronously sets all three
bits of the shift register when its output goes active. The
output of the shift register controls the associated LEDx
pin. Thus, the pulse stretcher provides an LED output
of 52 ms to 78 ms.
Am79C961A
Refer to the section “ISA Bus Configuration Registers”
for information on LED control via the ISACSRs.
deactivated by setting the STOP bit or resetting the
MP_ENBL bit (CSR5, bit 2).
MAGIC PACKET OPERATION
Interrupt Indication. Interrupt pin could be activated
by the receive of the Magic Packet. The MP_I_ENBL bit
(CSR5, bit 3) and IENA bit (CSR0, bit 6) should be set
to enable this feature.
In the Magic Packet mode, PCnet-ISA II completes any
transmit and receive operations in progress, suspends
normal activity, and enters into a state where only a
Magic Packet could be detected. A Magic Packet frame
is a frame that contains a data sequence which repeats
the Physical Address (PADR[47:00]) at least sixteen
times frame sequentially, with bit[00] received first. In
Magic Packet suspend mode, the PCnet-ISA II remains
powered up. Slave accesses to the PCnet-ISA II are
still possible, the same as any other mode. All of the
received packets are flushed from the receive FIFO. An
LED and/or interrupt pin could be activated, indicating
the receive of a Magic Packet frame. This indication
could be used for a variety of management tasks.
Magic Packet Mode Activation
Bit
Name
Description
1
MP_MODE
2
MP_ENBL
3
MP_I_ENBL
4
MP_INT
9
MP
Magic Packet Mode.
Setting this bit is a prerequisite
for entering the Magic Packet
mode. It also redefines the
SLEEP pin to be a Magic Packet
enable pin. Read/Write accessible always. It is cleared by asserting the RESET pin, or reading the RESET register.
Magic Packet Enable.
This bit when set, will force the
PCnet-ISA II into the Magic
Packet mode. Read/Write accessible always. It is cleared by
asserting the RESET pin or
reading the RESET register.
Magic Packet Interrupt Enable.
Acts as an unmask bit for the
MP_INT (CSR5, bit 4). Read/
Write accessible always. It is
cleared by asserting the RESET
pin or reading the RESET register, or setting the STOP bit.
Magic Packet Receive Interrupt.
Will be set when a Magic Packet
has been received. Writing a
“one” will clear this bit. It is
cleared by asserting the RESET
pin, or reading the RESET register.
Magic Packet LED Enable.
When set, the LED output will be
asserted to indicate that a Magic
Packet has been received.
This mode can be enabled by either software or external hardware means, but in either case, the MP_MODE
bit (CSR5, bit 1) must be set first.
Hardware Activation. This is done by driving the
SLEEP pin low. Deasserting the SLEEP pin will return
the PCnet-ISA II to normal operation.
Software Activation. This is done by setting the
MP_ENBL bit (CSR5, bit 2). Resetting this bit will return
the PCnet-ISA II to normal operation.
Magic Packet Receive Indicators
The reception of a Magic Packet can be indicated either
through one of the LEDs 1, 2 or 3, and/or the activation
of the interrupt pin. MP_INT bit (CSR5, bit 4) will also
be set upon the receive of the Magic Packet.
LED Indication. Either one of the LEDs 1, 2, or 3 could
be activated by the receive of the Magic Packet. The
“Magic Packet enable” bit (bit 9) in the ISACSR 5, 6 or
7 should be set to enable this feature. Note that the
polarity of the LED2 could be controlled by the
LEDXOR bit (ISACSR6, bit 14). The LED could be
Am79C961A
95
PCNET-ISA II CONTROLLER REGISTERS
The PCnet-ISA II controller implements all LANCE
(Am7990) registers, plus a number of additional registers. The PCnet-ISA II controller registers are compatible with the original LANCE, but there are some places
where previously reserved LANCE bits are now used
by the PCnet-ISA II controller. If the reserved LANCE
bits were used as recommended, there should be no
compatibility problems.
13
CERR
12
MISS
11
MERR
Register Access
Internal registers are accessed in a two-step operation.
First, the address of the register to be accessed is written into the register address port (RAP). Subsequent
read or write operations will access the register pointed
to by the contents of the RAP. The data will be read
from (or written to) the selected register through the
data port, either the register data port (RDP) for control
and status registers (CSR) or the ISACSR register data
por t (IDP) for ISA control and status registers
(ISACSR).
RAP: Register Address Port
Bit
Name
Description
15-7
RES
6-0
RAP
Reserved locations. Read and
written as zeroes.
Register Address Port select.
Selects the CSR or ISACSR
location to be accessed. RAP is
cleared by RESET.
Control and Status Registers
CSR0: PCnet-ISA II Controller Status Register
Bit
Name
Description
15
ERR
14
BABL
Error is set by the ORing of
BABL, CERR, MISS, and
MERR. ERR remains set as long
as any of the error flags are true.
ERR is read only; write operations are ignored.
Babble is a transmitter time-out
error. It indicates that the transmitter has been on the channel
longer than the time required to
send the maximum length
frame. BABL will be set if 1519
bytes or greater are transmitted.
When BABL is set, IRQ is asserted if IENA = 1 and the mask
bit BABLM (CSR3.14) is clear.
BABL assertion will set the ERR
bit.
BABL is set by the MAC layer
and cleared by writing a “1".
Writing a “0" has no effect. BABL
96
Am79C961A
is cleared by RESET or by setting the STOP bit.
Collision Error indicates that the
collision inputs to the AUI port
failed to activate within 20 network bit times after the chip terminated transmission (SQE
Test). This feature is a transceiver test feature. CERR will be set
in 10BASE-T mode during
transmit if in Link Fail state.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
CERR is set by the MAC layer
and cleared by writing a “1".
Writing a “0" has no effect.
CERR is cleared by RESET or
by setting the STOP bit.
Missed Frame is set when PCnet-ISA II controller has lost an
incoming receive frame because
a Receive Descriptor was not
available. This bit is the only indication that receive data has
been lost since there is no receive descriptor available for
status information.
When MISS is set, IRQ is
asserted if IENA = 1 and the
mask bit MISSM (CSR3.12) is
clear. MISS assertion will set the
ERR bit.
MISS is set by the Buffer Management Unit and cleared by writing a “1". Writing a “0" has no
effect. MISS is cleared by RESET
or by setting the STOP bit.
Memory Error is set when PCnet-ISA II controller is a bus
master and has not received
DACK assertion after 50 µs after
DRQ assertion. Memory Error
indicates that PCnet-ISA II controller is not receiving bus mastership in time to prevent overflow/underflow conditions in the
receive and transmit FIFOs.
(MERR indicates a slightly different condition for the LANCE; for
the LANCE MERR occurs when
READY has not been asserted
25.6 µs after the address has
been asserted.)
When MERR is set, IRQ is asserted if IENA = 1 and the mask
bit MERRM (CSR3.11) is clear.
MERR assertion will set the
ERR bit.
10
9
8
7
RINT
TINT
IDON
INTR
MERR is set by the Bus Interface Unit and cleared by writing
a “1". Writing a “0" has no effect.
MERR is cleared by RESET or
by setting the STOP bit.
Receive Interrupt is set after reception of a receive frame and
toggling of the OWN bit in the
last buffer in the Receive
Descriptor Ring.
When RINT is set, IRQ is asserted if IENA = 1 and the mask bit
RINTM (CSR3.10) is clear.
RINT is set by the Buffer Management Unit after the last
receive buffer has been updated
and cleared by writing a “1".
Writing a “0" has no effect. RINT
is cleared by RESET or by
setting the STOP bit.
Transmit Interrupt is set after
transmission of a transmit frame
and toggling of the OWN bit in
the last buffer in the Transmit
Descriptor Ring.
When TINT is set, IRQ is
asserted if IENA = 1 and the
mask bit TINTM (CSR3.9) is
clear.
TINT is set by the Buffer Management Unit after the last transmit buffer has been updated and
cleared by writing a “1". Writing a
“0" has no effect. TINT is cleared
by RESET or by setting the
STOP bit.
Initialization Done indicates that
the initialization sequence has
completed. When IDON is set,
PCnet-ISA II controller has read
the Initialization block from
memory.
When IDON is set, IRQ is asserted if IENA = 1 and the mask bit
IDONM (CSR3.8) is clear.
IDON is set by the Buffer Management Unit after the initialization block has been read from
memory and cleared by writing a
“1". Writing a “0" has no effect.
IDON is cleared by RESET or by
setting the STOP bit.
Interrupt Flag indicates that one
or more of the following interrupt
causing
conditions
has
occurred: BABL, MISS, MERR,
MPCO, RCVCCO, RINT, TINT,
IDON, JAB or TXSTRT; and its
associated mask bit is clear. If
6
IENA
5
RXON
4
TXON
3
TDMD
Am79C961A
IENA = 1 and INTR is set, IRQ
will be active.
INTR is cleared automatically
when the condition that caused
interrupt is cleared.
INTR is read only. INTR is
cleared by RESET or by setting
the STOP bit.
Interrupt Enable allows IRQ to
be active if the Interrupt Flag is
set. If IENA = “0" then IRQ will be
disabled regardless of the state
of INTR.
IENA is set by writing a “1" and
cleared by writing a “0". IENA is
cleared by RESET or by setting
the STOP bit.
Receive On indicates that the
Receive function is enabled.
RXON is set if DRX (CSR15.0) =
“0" after the START bit is set. If
INIT and START are set together, RXON will not be set until
after the initialization block has
been read in.
RXON is read only. RXON is
cleared by RESET or by setting
the STOP bit.
Transmit On indicates that the
Transmit function is enabled.
TXON is set if DTX (CSR15.1) =
“0" after the START bit is set. If
INIT and START are set together, TXON will not be set until
after the initialization block has
been read in.
TXON is read only. TXON is
cleared by RESET or by setting
the STOP bit.
Transmit Demand, when set,
causes the Buffer Management
Unit to access the Transmit
Descriptor Ring without waiting
for the poll-time counter to
elapse. If TXON is not enabled,
TDMD bit will be reset and no
Transmit Descriptor Ring access
will occur. TDMD is required to
be set if the DPOLL bit in CSR4
is set; setting TDMD while
DPOLL = 0 merely hastens the
PCnet-ISA II controller’s response to a Transmit Descriptor
Ring Entry.
TDMD is set by writing a “1".
Writing a “0" has no effect.
TDMD will be cleared by the
Buffer Management Unit when it
fetches a Transmit Descriptor.
97
2
1
0
STOP
STRT
INIT
TDMD is cleared by RESET or
by setting the STOP bit.
STOP assertion disables the
chip from all external activity.
The chip remains inactive until
either STRT or INIT are set. If
STOP, STRT and INIT are all set
together, STOP will override
STRT and INIT.
STOP is set by writing a “1" or by
RESET. Writing a “0" has no effect. STOP is cleared by setting
either STRT or INIT.
STRT assertion enables PCnetISA II controller to send and
receive frames, and perform
buffer management operations.
Setting STRT clears the STOP
bit. If STRT and INIT are set together, PCnet-ISA II controller
initialization will be performed
first.
STRT is set by writing a “1". Writing a “0" has no effect. STRT is
cleared by RESET or by setting
the STOP bit.
INIT assertion enables PCnet-ISA II controller to begin the
initialization procedure which
reads in the initialization block
from memory. Setting INIT
clears the STOP bit. If STRT and
INIT are set together, PCnet-ISA
II controller initialization will be
performed first. INIT is not
cleared when the initialization
sequence has completed.
INIT is set by writing a “1". Writing a “0" has no effect. INIT is
cleared by RESET or by setting
the STOP bit.
7-0 IADR [23:16]
Upper 8 bits of the address of
the Initialization Block. Bit locations 15-8 must be written with
zeros. Whenever this register is
written, CSR17 is updated with
CSR2’s contents.
Read/Write accessible only
when the STOP or SPND bits
are set. Unaffected by RESET.
CSR3: Interrupt Masks and Deferral Control
Bit
Name
Description
15
RES
14
BABLM
13
RES
12
MISSM
11
MERRM
10
RINTM
9
TINTM
8
IDONM
7
RES
6
DXSUFLO
Reserved location. Written as
zero and read as undefined.
Babble Mask. If BABLM is set,
the BABL bit in CSR0 will be
masked and will not set INTR
flag in CSR0.
BABLM is cleared by RESET
and is not affected by STOP.
Reserved location. Written as
zero and read as undefined.
Missed Frame Mask. If MISSM
is set, the MISS bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
MISSM is cleared by RESET
and is not affected by STOP.
Memory Error Mask. If MERRM
is set, the MERR bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
MERRM is cleared by RESET
and is not affected by STOP.
Receive Interrupt Mask. If
RINTM is set, the RINT bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
RINTM is cleared by RESET
and is not affected by STOP.
Transmit Interrupt Mask. If
TINTM is set, the TINT bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
TINTM is cleared by RESET and
is not affected by STOP.
Initialization Done Mask. If
IDONM is set, the IDON bit in
CSR0 will be masked and will
not set INTR flag in CSR0.
IDONM is cleared by RESET
and is not affected by STOP.
Reserved locations. Written as
zero and read as undefined.
Disable Transmit Stop on
Underflow error.
CSR1: IADR[15:0]
Bit
Name
15-0 IADR [15:0]
Description
Lower address of the Initialization address register. Bit location
0 must be zero. Whenever this
register is written, CSR16 is
updated with CSR1’s contents.
Read/Write accessible only
when the STOP or SPND bits
are set. Unaffected by RESET.
CSR2: IADR[23:16]
Bit
Name
Description
15-8
RES
Reserved locations. Read and
written as zero.
98
Am79C961A
5
LAPPEN
When DXSUFLO is set to ZERO,
the transmitter is turned off when
an UFLO error occurs (CSR0,
TXON = 0).
When DXSUFLO is set to ONE,
the PCnet-ISA II controller
gracefully recovers from an
UFLO error. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
Read/Write accessible always.
DXSUFLO is cleared by asserting
the RESET pin or reading the
Reset register and is not affected
by STOP.
Look Ahead Packet Processing
(LAPPEN). When set to a one,
the LAPPEN bit will cause the
PCnet-ISA II controller to generate an interrupt following the
descriptor write operation to the
first buffer of a receive packet.
This interrupt will be generated
in addition to the interrupt that is
generated following the descriptor write operation to the last
buffer of a receive packet. The
interrupt will be signaled through
the RINT bit of CSR0.
Setting LAPPEN to a one also
enables the PCnet-ISA II controller to read the STP bit of the
receive descriptors. PCnet-ISA
II controller will use STP information to determine where it
should begin writing a receive
packet’s data. Note that while in
this mode, the PCnet-ISA II controller can write intermediate
packet data to buffers whose
descriptors do not contain STP
bits set to one. Following the
write to the last descriptor used
by a packet, the PCnet-ISA II
controller will scan through the
next descriptor entries to locate
the next STP bit that is set to a
one. The PCnet-ISA II controller
will begin writing the next packet’s data to the buffer pointed to
by that descriptor.
Note that because several
descriptors may be allocated by
the host for each packet, and not
all messages may need all of the
descriptors that are allocated
between descriptors that contain
STP = one, then some descriptors/buffers may be skipped in
the ring. While performing the
4
DXMT2PD
3
EMBA
Am79C961A
search for the next STP bit that
is set to one, the PCnet-ISA II
controller will advance through
the receive descriptor ring
regardless of the state of ownership bits. If any of the entries that
are examined during this search
indicate OWN = one, PCnet-ISA
II will RESET the OWN bit to
zero in these entries. If a
scanned entry indicates host
ownership with STP=“0", then
the PCnet-ISA II controller will
not alter the entry, but will
advance to the next entry.
When the STP bit is found to be
true, but the descriptor that contains this setting is not owned by
the PCnet-ISA II controller, then
the PCnet-ISA II controller will
stop advancing through the ring
entries and begin periodic polling of this entry. When the STP
bit is found to be true, and the
descriptor that contains this setting is owned by the PCnet-ISA II
controller, then the PCnet-ISA II
controller will stop advancing
through the ring entries, store
the descriptor information that is
has just read, and wait for the
next receive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
“header” portion of a receive
packet will always be written to a
particular memory area, and the
“data” portion of a receive packet will always be written to a separate memory area. The interrupt is generated when the
“header” bytes have been written to the “header” memory
area.
Read/Write accessible always.
The LAPPEN bit will be reset
zero by RESET and will
unaffected by the STOP. See
Appendix E for more information
on LAPP.
Disable Transmit Two Part
Deferral. (Described in the
Media Access Management
section). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
DXMT2PD is cleared by RESET
and is not affected by STOP.
Enable Modified Back-off Algorithm. If EMBA is set, a modified
99
back-off
algorithm
is
implemented as described in the
Media Access Management
section.
Read/Write accessible. EMBA is
cleared by RESET and is not
affected by STOP.
2-0
RES
Reserved locations. Written as
zero and read as undefined.
CSR4: Test and Features Control
Bit
Name
Description
15
ENTST
14
DMAPLUS
13
TIMER
Enable Test Mode operation.
When ENTST is set, writing to
test mode registers CSR124 and
CSR126 is allowed, and other
register test functions are
enabled. In order to set ENTST, it
must be written with a “1" during
the first write access to CSR4
after RESET. Once a “0" is written to this bit location, ENTST
cannot be set until after the PCnet-ISA II controller is reset.
ENTST is cleared by RESET.
When DMAPLUS = “1", the burst
transaction counter in CSR80 is
disabled. If DMAPLUS = “0", the
burst transaction counter is
enabled.
Caution: When using DMAPLUS
AND/OR TIMER bits in a PC
environment, care must be taken
not to hold the bus for more than
the required refresh time.
DMAPLUS is cleared by RESET.
Timer Enable Register. If TIMER
is set, the Bus Activity Timer register (CSR82) is enabled and the
PCnet-ISA II may perform any
combination of accesses (buffer
reads, buffer writes, descriptor
reads, and descriptor writes)
during a single bus mastership
period. The bus is held until
either the Bus Activity Timer
expires or there are no further
pending operations to be performed. The PCnet-ISA II determines whether there are further
pending bus operations by waiting approximately 1 µs after the
completion of every bus operation (e.g. a descriptor or FIFO
access). If, during the 1 µs
period, no further bus operations
are requested by the internal
Buffer Management Unit, the
PCnet-ISA II determines that
100
12
DPOLL
11
APAD_XMT
10 ASTRP_RCV
9
MFCO
8
MFCOM
Am79C961A
there are no further pending
operations and gives up bus
ownership.
If TIMER is cleared, the Bus
Activity Timer register is disabled and the PCnet-ISA II performs only one type of access
(descriptor read, descriptor
write, buffer read, or buffer
write) and buffer accesses are
performed
to
adjacent
ascending addresses during
each bus mastership period.
TIMER is cleared by RESET.
Disable Transmit Polling. If
DPOLL is set, the Buffer Management Unit will disable transmit polling. Likewise, if DPOLL is
cleared, automatic transmit polling is enabled. If DPOLL is set,
TDMD bit in CSR0 must be periodically set in order to initiate a
manual poll of a transmit
descriptor. Transmit descriptor
polling will not take place if
TXON is reset.
DPOLL is cleared by RESET.
Auto Pad Transmit. When set,
APAD_XMT enables the automatic padding feature. Transmit
frames will be padded to extend
them to 64 bytes, including FCS.
The FCS is calculated for the entire frame (including pad) and
appended after the pad field.
APAD_XMT will override the
programming of the DXMTFCS
bit (CSR15.3).
APAD_ XMT is reset by activation of the RESET pin.
ASTRP_RCV enables the automatic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames
and not placed in the FIFO.
ASTRP_ RCV is reset by activation of the RESET pin.
Missed Frame Counter Overflow
Interrupt.
This bit indicates the MFC
(CSR112) has overflowed. Can
be cleared by writing a “1" to this
bit. Also cleared by RESET or
setting the STOP bit. Writing a
“0" has no effect.
Missed Frame Counter Overflow
Mask.
If MFCOM is set, MFCO will not
set INTR in CSR0.
7-6
5
RES
RCVCCO
4
RCVCCOM
3
TXSTRT
2
TXSTRTM
1
JAB
0
JABM
MFCOM is set by Reset and is
not affected by STOP.
Reserved locations. Read and
written as zero.
Receive Collision Counter Overflow.
This bit indicates the Receive
Collision Counter (CSR114) has
overflowed. It can be cleared by
writing a 1 to this bit. Also
cleared by RESET or setting the
STOP bit. Writing a 0 has no
effect.
Receive Collision Counter Overflow Mask.
If RCVCCOM is set, RCVCCO
will not set INTR in CSR0.
RCVCCOM is set by RESET
and is not affected by STOP.
Transmit Start status is set whenever PCnet-ISA II controller
begins transmission of a frame.
When TXSTRT is set, IRQ is
asserted if IENA = 1 and the
mask bit TXSTRTM (CSR4.2) is
clear.
TXSTRT is set by the MAC Unit
and cleared by writing a “1", setting RESET or setting the STOP
bit. Writing a “0" has no effect.
Transmit
Start
Mask.
If
TXSTRTM is set, the TXSTRT bit
in CSR4 will be masked and will
not set INTR flag in CSR0.
TXSTRTM is set by RESET and
is not affected by STOP.
Jabber Error is set when the
PCnet-ISA II controller Twisted-pair MAU function exceeds
an allowed transmission limit.
Jabber is set by the TMAU circuit and can only be asserted in
10BASE-T mode.
When JAB is set, IRQ is asserted if IENA = 1 and the mask bit
JABM (CSR4.4) is clear.
The JAB bit can be reset even if
the jabber condition is still
present.
JAB is set by the TMAU circuit
and cleared by writing a “1".
Writing a “0" has no effect. JAB
is also cleared by RESET or setting the STOP bit.
Jabber Error Mask. If JABM is
set, the JAB bit in CSR4 will be
masked and will not set INTR
flag in CSR0.
JABM is set by RESET and is
not affected by STOP.
CSR5: Control 1
Bit
Name
Description
0
SPND
Suspend. Setting SPND to ONE
will cause the PCnet-ISA II controller to start entering the suspend mode. The host must poll
SPND until it reads a ONE back,
to determine that the PCnet-ISA
II controller has entered the suspend mode. Setting SPND to
ZERO will get the PCnet-ISA II
controller out of suspend mode
and back into its active state.
SPND can only be set to ONE if
STOP (CSR0, bit 2) is set to
ZERO. Asserting the RESET
pin, reading the RESET register,
or setting the STOP bit forces
the PCnet-ISA II controller out of
suspend mode.
When the host requests the PCnet-ISA II controller to enter the
suspend mode, the device first
finishes all on-going transmit
activity and updates the
corresponding transmit descriptor entries. It then completes
any frame reception occurring
at the time the SPND bit was
set, and updates the corresponding receive descriptor entries. Any subsequent frames
incident upon the PCnet-ISA II
during suspend mode will not
be received, nor will any notification be given as to the missed
frames (the MISS bit in CSR0
will not be updated while in suspend mode). It then sets the
read-version of SPND to ONE
and enters the suspend mode.
In suspend mode, all of the
CSR registers are accessible.
As long as the PCnet-ISA II
controller is not reset while in
suspend mode (by asserting the
RESET pin, reading the RESET
register, or setting the STOP
bit), no reinitialization of the
device is required after the
device comes out of suspend
mode. The PCnet-ISA II controller will continue at the transmit
and receive descriptor ring
locations, where it had left,
when it entered the suspend
mode.
Am79C961A
101
Read/Write accessible always.
SPND is cleared by asserting
the RESET pin, reading the
RESET register, or setting the
STOP bit
1
MP_MODE
Magic Packet Mode.
Setting this bit is a prerequisite
for entering the Magic Packet
mode. It also redefines the
SLEEP pin to be a Magic Packet
enable pin. Read/Write accessible always. It is cleared by asserting the RESET pin, or reading the RESET register.
2
MP_ENBL
Magic Packet Enable.
This bit when set, will force the
PCnet-ISA II into the Magic
Packet mode. Read/Write accessible always. It is cleared by
asserting the RESET pin or
reading the RESET register.
3
MP_I_ENBL
Magic Packet Interrupt Enable.
Acts as an unmask bit for the
MP_INT (CSR5, bit 4). Read/
Write accessible always. It is
cleared by asserting the RESET
pin or reading the RESET register, or setting the STOP bit.
4
MP_INT
Magic Packet Receive Interrupt.
Will be set when a Magic Packet
has been received. Writing a
“one” will clear this bit. It is
cleared by asserting the RESET
pin, or reading the RESET register.
CSR6: RCV/XMT Descriptor Table Length
Bit
15-12
11-8
102
Name
TLEN
RLEN
Read accessible only when
STOP or SPND bits are set. Write
operations have no effect and
should not be performed. RLEN is
only defined after initialization.
7-0
RES
Reserved locations. Read as
zero. Write operations should
not be performed.
CSR8: Logical Address Filter, LADRF[15:0]
Bit
Name
Description
15-0 LADRF[15:0]
Logical Address Filter, LADRF
[15:0]. Undefined until initialized
either automatically by loading
the initialization block or directly
by an I/O write to this register.
Read/write accessible only
when STOP or SPND bits are
set.
CSR9: Logical Address Filter, LADRF[31:16]
Bit
Name
Description
15-0 LADRF[31:16] Logical
Address
Filter,
LADRF[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only
when STOP or SPND bits are
set.
CSR10: Logical Address Filter, LADRF[47:32]
Bit
Name
Description
Description
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during PCnet-ISA II controller initialization. This field is written
during the PCnet-ISA II controller
initialization routine.
Read accessible only when STOP
or SPND bits are set. Write operations have no effect and should
not be performed. TLEN is only
defined after initialization.
Contains a copy of the receive
encoded ring length (RLEN)
read from the initialization
block during PCnet-ISA II controller initialization. This field is
written during the PCnet-ISA II
controller initialization routine.
15-0 LADRF[47:32] Logical
Address
Filter,
LADRF[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only
when STOP or SPND bits are
set.
CSR11: Logical Address Filter, LADRF[63:48]
Bit
Name
Description
15-0 LADRF[63:48] Logical
Address
Filter,
LADRF[63:48]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Am79C961A
Read/write accessible only
when STOP or SPND bits are
set.
CSR12: Physical Address Register, PADR[15:0]
Bit
Name
15
PROM
14
DRCVBC
13
DRCVPA
12
DLNKTST
11
DAPC
Description
15-0 PADR[15:0]
Physical Address Register,
PADR[15:0]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only
when STOP or SPND bits are
set.
CSR13: Physical Address Register, PADR[31:16]
Bit
Name
Description
15-0PADR[31:16]
Physical Address Register,
PADR[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only
when STOP or SPND bits are
set.
CSR14: Physical Address Register, PADR[47:32]
Bit
Name
Description
15-0 PADR[47:32]
Physical Address Register,
PADR[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only
when STOP or SPND bits are
set.
CSR15: Mode Register
Bit
Name
Description
This register’s fields are loaded
during the PCnet-ISA II controller
initialization routine with the corresponding Initialization Block
values. The register can also be
loaded directly by an I/O write.
Am79C961A
Activating the RESET pin clears
all bits of CSR15 to zero.
Promiscuous Mode.
When PROM = “1", all incoming
receive frames are accepted.
Read/write accessible only
when STOP or SPND bits are
set.
DisableReceiveBroadcast .
When set, disables the PCnet-ISA
II controller from receiving broadcast messages. Used for protocols that do not support broadcast
addressing, except as a function
of multicast. DRCVBC is cleared
by activation of the RESET pin
(broadcast messages will be
received).
Read/write accessible only
when STOP or SPND bits are
set.
Disable Receive Physical Address. When set, the physical
address detection (Station or
node ID) of the PCnet-ISA II controller will be disabled. Frames
addressed
to
the
nodes
individual physical address will
not be recognized (although the
frame may be accepted by the
EADI mechanism).
Read/write accessible only
when STOP or SPND bits are
set.
Disable Link Status. When
DLNKTST = “1", monitoring of
Link Pulses is disabled. When
DLNKTST = “0", monitoring of
Link Pulses is enabled. This bit
only has meaning when the
10BASE-T network interface is
selected.
Read/write accessible only
when STOP or SPND bits are
set.
Disable
Automatic
Polarity
Correction. When DAPC = “1",
the 10BASE-T receive polarity
reversal algorithm is disabled.
Likewise, when DAPC = “0", the
polarity reversal algorithm is
enabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write accessible only
when STOP or SPND bits are
set.
103
10
9
MENDECL
LRT/TSEL
LRT
TSEL
8-7
104
PORTSEL
[1:0]
MENDEC Loopback Mode. See
the description of the LOOP bit
in CSR15.
Read/write accessible only
when STOP or SPND bits are
set.
Low Receive Threshold (T-MAU
Mode only)
Transmit Mode Select (AUI
Mode only)
Low Receive Threshold. When
LRT = “1", the internal twisted
pair receive thresholds are
reduced by 4.5 dB below the
standard
10BASE-T
value
(approximately 3/5) and the
unsquelch threshold for the RXD
circuit will be 180-312 mV peak.
When LRT = “0", the unsquelch
threshold for the RXD circuit will
be the standard 10BASE-T
value, 300-520 mV peak.
In either case, the RXD circuit
post squelch threshold will be
one half of the unsquelch threshold.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write accessible only
when STOP or SPND bits are
set. Cleared by RESET.
Transmit Mode Select. TSEL
controls the levels at which the
AUI drivers rest when the AUI
transmit port is idle. When TSEL
= 0, DO+ and DO- yield “zero” differential to operate transformer
coupled loads (Ethernet 2 and
802.3). When TSEL = 1, the DO+
idles at a higher value with
respect to DO-, yielding a logical
HIGH state (Ethernet 1).
This bit only has meaning when
the AUI network interface is
selected. Not available under
Auto-Select Mode.
Read/write accessible only
when STOP or SPND bits are
set. Cleared by RESET.
Port Select bits allow for software
controlled selection of the network medium. PORTSEL active
only when Media-Select Bit set
to 0 in ISACSR2.
Read/write accessible only
when STOP or SPND bits are
set. Cleared by RESET.
The network port configuration
are as follows:
PORTSEL[1:0]
Network Port
00
AUI
01
10BASE-T
10
GPSI*
11
Reserved
*Refer to the section on General Purpose Serial Interface for
detailed information on accessing GPSI.
6
INTL
5
DRTY
4
FCOLL
3
DXMTFCS
Am79C961A
Internal Loopback. See the
description of LOOP, CSR15.2.
Read/write accessible only
when STOP bit is set.
Disable Retry. When DRTY =
“1", PCnet-ISA II controller will
attempt only one transmission. If
DRTY = “0", PCnet-ISA II controller will attempt to transmit 16
times before signaling a retry
error.
Read/write accessible only
when STOP or SPND bits are
set.
Force Collision. This bit allows
the collision logic to be tested.
PCnet-ISA II controller must be
in internal loopback for FCOLL
to be valid. If FCOLL = “1", a collision will be forced during loopback transmission attempts; a
Retry Error will ultimately result.
If FCOLL = “0", the Force Collision logic will be disabled.
Read/write accessible only
when STOP or SPND bits are
set.
Disable Transmit CRC (FCS).
When DXMTFCS = “0", the
transmitter will generate and
append a FCS to the transmitted
frame. When DXMTFCS = “1",
the FCS logic is allocated to the
receiver and no FCS is generated or sent with the transmitted
frame.
See also the ADD_FCS bit in
TMD1. If DXMTFCS is set, no
FCS will be generated. If both
DXMTFCS is set and ADD_FCS
is clear for a particular frame, no
FCS will be generated. If
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be appended on that frame by the
transmit circuitry.
2
1
0
In loopback mode, this bit determines if the transmitter appends
FCS or if the receiver checks the
FCS.
This bit was called DTCR in the
LANCE (Am7990).
Read/write accessible only
when STOP or SPND bits are
set.
Loopback Enable allows PCnet-ISA II controller to operate in
full duplex mode for test purposes. When LOOP = “1", loopback
is enabled. In combination with
INTL and MENDECL, various
loopback modes are defined as
follows.
LOOP
LOOP
INTL
MENDECL
0
X
X
Non-loopback
1
0
X
External Loopback
1
1
0
Internal Loopback
Include MENDEC
1
1
1
Internal Loopback
Exclude MENDEC
DTX
DRX
Loopback Mode
Read/write accessible only
when STOP or SPND bits are
set. LOOP is cleared by RESET.
Disable Transmit. If this bit is set,
the PCnet-ISA II controller will
not
access the
Transmit
Descriptor Ring and, therefore,
no transmissions will occur. DTX
= “0" will set TXON bit (CSR0.4)
after STRT (CSR0.1) is asserted. DTX is defined after the initialization block is read.
Read/write accessible only
when STOP or SPND bits are
set.
Disable Receiver. If this bit is
set, the PCnet-ISA II controller
will not access the Receive
Descriptor Ring and, therefore,
all receive frame data are
ignored. DRX = “0" will set
RXON bit (CSR0.5) after STRT
(CSR0.1) is asserted. DRX is
defined after the initialization
block is read.
Read/write accessible only
when STOP or SPND bits are
set.
CSR16: Initialization Block Address Lower
Bit
Name
Description
15-0
IADR
Bit
Name
15-8
RES
Bit
Name
31-24
RES
Bit
Name
Description
31-24
RES
23-0
CXBA
Reserved locations. Written as
zero and read as undefined.
Contains the current transmit
buffer address from which the
PCnet-ISA II controller is transmitting.
Read/write accessible only when
STOP or SPND bits are set.
Lower 16 bits of the address of
the Initialization Block. Bit location 0 must be zero. This register
is an alias of CSR1. Whenever
this register is written, CSR1 is
updated with CSR16’s contents.
Read/Write accessible only
when the STOP or SPND bits
are set. Unaffected by RESET.
CSR17: Initialization Block Address Upper
Description
Reserved locations. Written as
zero and read as undefined.
7-0
IADR
Upper 8 bits of the address of
the Initialization Block. Bit locations 15-8 must be written with
zeros. This register is an alias of
CSR2. Whenever this register is
written, CSR2 is updated with
CSR17’s contents.
Read/Write accessible only
when the STOP or SPND bits
are set. Unaffected by RESET.
CSR18-19: Current Receive Buffer Address
Description
Reserved locations. Written as
zero and read as undefined.
23-0 CRBA
Contains the current receive
buffer address to which the PCnet-ISA II controller will store incoming frame data.
Read/write accessible only when
STOP or SPND bits are set.
CSR20-21: Current Transmit Buffer Address
Am79C961A
105
CSR22-23: Next Receive Buffer Address
Bit
Name
31-24
RES
Read/write accessible only
when STOP or SPND bits are
set.
CSR32-33: Next Transmit Descriptor Address
Description
Reserved locations. Written as
zero and read as undefined.
23-0 NRBA
Contains the next receive buffer
address to which the PCnet-ISA
II controller will store incoming
frame data.
Read/write accessible only
when STOP or SPND bits are
set.
CSR24-25: Base Address of Receive Ring
Bit
31-24
Name
Description
Reserved locations. Written as
zero and read as undefined.
23-0 BADR
Contains the base address of
the Receive Ring.
Read/write accessible only
when STOP or SPND bits are
set.
CSR26-27: Next Receive Descriptor Address
Bit
31-24
Bit
Name
31-24
RES
Bit
Name
31-24
RES
Bit
Name
Reserved locations. Written as
zero and read as undefined.
23-0 NXDA
Contains the next TDRE address
pointer.
Read/write accessible only
when STOP or SPND bits are
set.
CSR34-35: Current Transmit Descriptor Address
Description
RES
Name
Description
Reserved locations. Written as
zero and read as undefined.
23-0 NRDA
Contains the next RDRE
address pointer.
Read/write accessible only
when STOP or SPND bits are
set.
CSR28-29: Current Receive Descriptor Address
Reserved locations. Written as
zero and read as undefined.
23-0 CXDA
Contains the current TDRE
address pointer.
Read/write accessible only
when STOP or SPND bits are
set.
CSR36-37: Next Next Receive Descriptor Address
Description
RES
Bit
Name
31-24
RES
31-0
Contains the next next RDRE
address pointer.
Read/write accessible only
when STOP or SPND bits are
set.
CSR38-39: Next Next Transmit Descriptor Address
Bit
NNRDA
Name
Description
Description
31-0
Reserved locations. Written as
zero and read as undefined.
23-0 CRDA
Contains the current RDRE
address pointer.
Read/write accessible only
when STOP or SPND bits are
set.
CSR30-31: Base Address of Transmit Ring
Contains the next next TDRE
address pointer.
Read/write accessible only
when STOP or SPND bits are
set.
CSR40-41: Current Receive Status and Byte Count
Bit
NNXDA
Name
31-24 CRST
Bit
Name
Description
31-24
RES
23-0
BADX
Reserved locations. Written as
zero and read as undefined.
Contains the base address of
the Transmit Ring.
23-12
106
Description
Am79C961A
RES
Description
Current Receive Status. This
field is a copy of bits 15:8 of
RMD1 of the current receive
descriptor.
Read/write accessible only
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
11-0
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD2 of the current
receive descriptor.
Read/write accessible only
when STOP or SPND bits are
set.
CSR42-43: Current Transmit Status and Byte
Count
Bit
CRBC
Name
Description
31-24 CXST
Current Transmit Status. This
field is a copy of bits 15:8 of
TMD1 of the current transmit
descriptor.
Read/write accessible only when
STOP or SPND bits are set.
23-12 RES
Reserved locations. Written as
zero and read as undefined.
11-0 CXBC
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD2 of the current
transmit descriptor.
Read/write accessible only when
STOP or SPND bits are set.
CSR44-45: Next Receive Status and Byte Count
Bit
Name
Description
31-24 NRST
Next Receive Status. This field
is a copy of bits 15:8 of RMD1 of
the next receive descriptor.
Read/write accessible only when
STOP or SPND bits are set.
23-12 RES
Reserved locations. Written as
zero and read as undefined.
11-0 NRBC
Next Receive Byte Count. This
field is a copy of the BCNT field
of RMD2 of the next receive
descriptor.
Read/write accessible only when
STOP or SPND bits are set.
CSR46: Poll Time Counter
Bit
Name
Description
15-0
POLL
Poll Time Counter. This counter
is incriminated by the PCnet-ISA
II controller microcode and is
used to trigger the descriptor
ring polling operation of the PCnet-ISA II controller.
Read/write accessible only when
STOP or SPND bits are set.
CSR47: Polling Interval
Bit
Name
31-16
RES
Bit
Name
31-0
TMP0
Bit
Name
31-0
TMP1
Description
Reserved locations. Written as
zero and read as undefined.
15-0 POLLINT
Polling Interval. This register
contains the time that the PCnet-ISA II controller will wait between
successive
polling
operations. The POLLINT value
is expressed as the two’s complement of the desired interval,
where each bit of POLLINT represents one-half of an XTAL1
period of time. POLLINT[3:0] are
ignored. (POLINT[16] is implied
to be a one, so POLLINT[15] is
significant, and does not represent the sign of the two’s
complement POLLINT value.)
The default value of this register
is 0000. This corresponds to a
polling interval of 32,768 XTAL1
periods. The POLINT value of
0000 is created during the microcode initialization routine, and
therefore might not be seen when
reading CSR47 after RESET.
If the user desires to program a
value for POLLINT other than
the default, then the correct
procedure is to first set INIT only
in CSR0. Then, when the initialization sequence is complete,
the user must set STOP in
CSR0. Then the user may write
to CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000 in CSR47 will be
overwritten with the desired user
value.
Read/write accessible only
when STOP or SPND bits are
set.
CSR48-49: Temporary Storage
Description
Temporary Storage location.
Read/write accessible only
when STOP or SPND bits are
set.
CSR50-51: Temporary Storage
Am79C961A
Description
Temporary Storage location.
107
Read/write accessible only when
STOP or SPND bits are set.
CSR52-53: Temporary Storage
Bit
Name
31-0
TMP2
Bit
Name
31-0
TMP3
Description
Temporary Storage location.
Read/write accessible only
when STOP or SPND bits are
set.
CSR54-55: Temporary Storage
Description
Temporary Storage location.
Read/write accessible only
when STOP or SPND bits are
set.
CSR56-57: Temporary Storage
Read/write accessible only
when STOP or SPND bits are
set.
23-12 RES
Reserved locations. Written as
zero and read as undefined.
Accessible only when STOP bit
is set.
11-0 PXBC
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD2 of the previous
transmit descriptor.
Read/write accessible only
when STOP or SPND bits are
set.
CSR64-65: Next Transmit Buffer Address
Bit
Name
31-24
RES
Name
Description
Bit
Name
31-0
TMP4
Temporary Storage location.
Read/write accessible only
when STOP or SPND bits are
set.
CSR58-59: Temporary Storage
Reserved locations. Written as
zero and read as undefined.
23-0 NXBA
Contains the next transmit buffer
address from which the PCnet-ISA II controller will transmit
an outgoing frame.
Read/write accessible only
when STOP or SPND bits are
set.
CSR66-67: Next Transmit Status and Byte Count
Bit
Name
Bit
31-0
TMP5
Bit
Name
31-24
RES
Description
Description
Temporary Storage location.
Read/write accessible only
when STOP or SPND bits are
set.
CSR60-61: Previous Transmit Descriptor Address
Description
Reserved locations. Written as
zero and read as undefined.
23-0 PXDA
Contains the previous TDRE
address pointer. The PCnet-ISA
II controller has the capability to
stack multiple transmit frames.
Read/write accessible only
when STOP or SPND bits are
set.
CSR62-63: Previous Transmit Status and Byte
Count
Bit
Name
31-24 NXST
108
Next Transmit Status. This field
is a copy of bits 15:8 of TMD1 of
the next transmit descriptor.
Read/write accessible only
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Accessible only when STOP bit
is set.
Next Transmit Byte Count. This
field is a copy of the BCNT field
of TMD2 of the next transmit
descriptor.
Read/write accessible only
when STOP or SPND bits are
set.CSR68-69: Transmit Status
Temporary Storage
23-12
RES
11-0
NXBC
Bit
Name
Description
XSTMP
Transmit Status Temporary
Storage location.
Read/write accessible only
when STOP or SPND bits are
set.
Description
31-0
31-24 PXST
Description
Previous Transmit Status. This
field is a copy of bits 15:8 of
TMD1 of the previous transmit
descriptor.
Am79C961A
CSR70-71: Temporary Storage
Bit
Name
31-0
TMP8
Read/write accessible only
when STOP or SPND bits are
set.
CSR78: Transmit Ring Length
Description
Temporary Storage location.
Read/write accessible only
when STOP or SPND bits are
set.
CSR72: Receive Ring Counter
Bit
15-0
Name
Description
Receive Ring Counter location.
Contains a Two’s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only
when STOP or SPND bits are
set.
CSR74: Transmit Ring Counter
Bit
RCVRC
Name
Description
Bit
15-0
Name
XMTRL
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the PCnet-ISA II controller initialization routine based on the
value in the TLEN field of the initialization block. This register
can be manually altered; the
actual transmit ring length is
defined by the current value in
this register.
Read/write accessible only
when STOP or SPND bits are
set.
CSR80: Burst and FIFO Threshold Control
Bit
Name
Description
15-14
RES
Reserved locations. Read as
ones. Written as zero.
Receive
FIFO
Watermark.
RCVFW controls the point at
which ISA bus receive DMA is
requested in relation to the number of received bytes in the
receive FIFO. RCVFW specifies
the number of bytes which must
be present (once the frame has
been verified as a non-runt)
before receive DMA is requested. Note however that, if the network interface is operating in
half-duplex mode, in order for
receive DMA to be performed for
a new frame, at least 64 bytes
must have been received. This
effectively avoids having to react
to receive frames which are
runts or suffer a collision during
the slot time (512 bit times). If
the Runt Packet Accept feature
is enabled, receive DMA will be
requested as soon as either the
RCVFW threshold is reached, or
a complete valid receive frame is
detected (regardless of length).
RCVFW is set to a value of 10b
(64 bytes) after RESET.
Read/write accessible only
when STOP or SPND bits are
set.
13-12RCVFW[1:0]
15-0
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only
when STOP or SPND bits are
set.
CSR76: Receive Ring Length
Bit
15-0
XMTRC
Name
Description
RCVRL
Receive Ring Length. Contains
the Two’s complement of the
receive descriptor ring length.
This register is initialized during
the PCnet-ISA II controller initialization routine based on the
value in the RLEN field of the initialization block. This register
can be manually altered; the
actual receive ring length is
defined by the current value in
this register.
Description
Am79C961A
109
.
RCVFW[1:0]
00
01
10
11
Bytes Received
16
32
64
Reserved
11-10XMTSP[1:0]Transmit Start
Point. XMTSP controls the point
at which preamble transmission
attempts commence in relation
to the number of bytes written to
the transmit FIFO for the current
transmit frame. When the entire
frame is in the FIFO, transmission will start regardless of the
value in XMTSP. XMTSP is
given a value of 10b (64 bytes)
after RESET. Regardless of
XMTSP, the FIFO will not internally over-write its data until at
least 64 bytes (or the entire
frame if <64 bytes) have been
transmitted onto the network.
This ensures that for collisions
within the slot time window,
transmit data need not be
re-written to the transmit FIFO,
and retries will be handled
autonomously by the MAC. This
bit is read/write accessible only
when the STOP or SPND bits
are set.
XMTSP[1:0]
Bytes Written
00
4
01
16
10
64
11
112
9-8 XMTFW[1:0]
110
Write Cycles
00
8
01
16
Write Cycles
10
32
11
Reserved
7-0
DMABR
DMA Burst Register. This register contains the maximum
allowable number of transfers
to system memory that the Bus
Interface will perform during a
single DMA cycle. The Burst
Register is not used to limit the
number of transfers during
Descriptor transfers. A value of
zero will be interpreted as one
transfer. During RESET a
value of 16 is loaded in the
BURST register. If DMAPLUS
(CSR4.14) is set, the DMA
Burst Register is disabled.
When the Bus Activity Timer
register (CSR82: DMABAT) is
enabled, the PCnet-ISA II controller will relinquish the bus
when either the time specified
in DMABAT has elapsed or the
number of transfers specified
in DMABR have occurred or no
more pending operation left to
be performed.
Read/write accessible only
when STOP or SPND bits are
set.
CSR82: Bus Activity Timer
Bit
Name
15-0 DMABAT
Transmit FIFO Watermark.
XMTFW specifies the point at
which transmit DMA stops,
based upon the number of write
cycles that could be performed
to the transmit FIFO without
FIFO overflow. Transmit DMA is
allowed at any time when the
number of write cycles specified
by XMTFW could be executed
without causing transmit FIFO
overflow. XMTFW is set to a
value of 00b (8 cycles) after
hardware RESET. Read/write
accessible only when STOP or
SPND bits are set.
XMTFW[1:0]
XMTFW[1:0]
Am79C961A
Description
Bus Activity Timer. If the TIMER
bit in CSR4 is set, this register
contains the maximum allowable
time that the PCnet-ISA II controller will take up on the system
bus during FIFO data transfers
in each bus mastership period.
The DMABAT starts counting
upon receipt of DACK from the
host system. The DMABAT Register does not limit the number of
transfers
during
Descriptor
transfers.
A value of zero will limit the PCnet-ISA II controller to one bus
cycle per mastership period. A
non-zero value is interpreted as
an unsigned number with a resolution of 100 ns. For instance, a
value of 51 µs would be programmed with a value of 510.
When the TIMER bit in CSR4 is
set, DMABAT is enabled and
must be initialized by the user.
The DMABAT register is undefined until written.
When the Bus Activity Timer
register (CSR82: DMABAT) is
enabled, the PCnet-ISA II controller will relinquish the bus
when either the time specified in
DMABAT has elapsed or the
number of transfers specified in
DMABR have occurred or no
more pending operation left to
be performed. When ENTST
(CSR4.15) is asserted, all writes
to this register will automatically
perform a decrement cycle.
Read/write accessible only
when STOP or SPND bits are
set.
CSR84-85: DMA Address
Bit
31-0
Name
Description
DMABA
DMA Address Register.
This register contains the address
of system memory for the current
DMA cycle. The Bus Interface
Unit controls the Address Register
by issuing increment commands
to increment the memory address
for sequential operations. The
DMABA register is undefined until
the first PCnet-ISA II controller
DMA operation.
This register has meaning only if
the PCnet-ISA II controller is in
Bus Master Mode.
Read/write accessible only
when STOP or SPND bits are
set.
CSR86: Buffer Byte Counter
Bit
Name
Description
15-12
RES
Reserved, Read and written with
ones.
DMA Byte Count Register.
Contains the Two’s complement of the current size of the
remaining transmit or receive
buffer in bytes. This register is
incriminated by the Bus Interface Unit. The DMABC register
is undefined until written.
Read/write accessible only
when STOP or SPND bits are
set.
11-0 DMABC
CSR88-89: Chip ID
Bit
Name
Description
31-28
Version. This 4-bit pattern is
silicon revision dependent.
27-12
Part Number. The 16-bit code
for the PCnet-ISA II controller is
0010001001100001b (2261h).
11-1
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
0
Always a logic 1.
This register is exactly the same
as the Chip ID register in the
JTAG description.
This register is readable only
when STOP or SPND bits are
set.
CSR92: Ring Length Conversion
Bit
Name
Description
15-0
RCON
Bit
Name
Description
15-10
RES
Reserved locations. Read and
written as zero.
Time Domain Reflectometry
reflects the state of an internal
counter that counts from the
start of transmission to the
occurrence of loss of carrier.
TDR is incriminated at a rate of
10 MHz.
Read accessible only when
STOP or SPND bits are set.
Write operations are ignored.
XMTTDR is cleared by RESET.
Ring Length Conversion Register. This register performs a
ring length conversion from an
encoded value as found in the
initialization block to a Two’s
complement value used for
internal counting. By writing
bits 15–12 with an encoded
ring length, a Two’s complemented value is read. The
RCON register is undefined
until written.
Read/write accessible only
when STOP or SPND bits are
set.
CSR94: Transmit Time Domain Reflectometry
Count
9-0
Am79C961A
XMTTDR
111
CSR96-97: Bus Interface Scratch Register 0
CSR108-109: Buffer Management Scratch
Bit
Name
Bit
31-0
SCR0
Bit
Name
Description
31-0
SCR1
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All
Descriptor Data communications between the BIU and BMU
are written and read through
SCR0 and SCR1 registers.
Read/write accessible only
when STOP or SPND bits are
set.
Description
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All
Descriptor Data communications between the BIU and BMU
are written and read through
SCR0 and SCR1 registers. The
SCR0 register is undefined until
written.
Read/write accessible only when
STOP or SPND bits are set.
CSR98-99: Bus Interface Scratch Register 1
CSR104-105: SWAP
Bit
Name
Description
31-0
SWAP
This register performs word and
byte swapping depending upon
if 32-bit or 16-bit internal write
operations are performed. This
register is used internally by the
BIU/BMU as a word or byte
swapper. The swap register can
perform 32-bit operations that
the PC can not; the register is
externally accessible for test
reasons only. CSR104 holds the
lower 16 bits and CSR105 holds
the upper 16 bits.
The swap function is defined as
follows:
Internal Write Operation
32-Bit word
Lower 16-Bit
(CSR104)
31-0
Description
BMSCR
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status.
This register is also used as the
primary scan register for Buffer
Management
Test
Modes.
BMSCR register is undefined
until written.
Read/write accessible only
when STOP bit is set.
CSR112: Missed Frame Count
Bit
Name
15-0
MFC
Bit
Name
Description
Counts the number of missed
frames.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When MFC is all 1’s (65535) and
a missed frame occurs, MFC
increments to 0 and sets MFC0
bit (CSR4.9).
CSR114: Receive Collision Count
15-0
Description
Counts the number of Receive
collisions seen, regular and late.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When RCVCC is all 1’s (65535)
and a receive collision occurs,
RCVCC increments to 0 and
sets RCVCC0 bit (CSR4.5)
CSR124: Buffer Management Unit Test
Bit
RCVCC
Name
SWAP Register Result
SRC[31:16]→SWAP[15:0]
SRC[15:0]→SWAP[31:16]
SRC[15:8]→SWAP[7: 0]
SRC[7:0]→SWAP[15:8]
Read/write accessible only
when STOP or SPND bits are
set.
15-5
4
112
Name
Am79C961A
RES
GPSIEN
Description
This register is used to place the
BMU/BIU into various test
modes to support Test/Debug.
This register is writeable when
the ENTST bit in CSR4 is set.
Reserved locations. Written as
zero and read as undefined.
This mode places the PCnet-ISA
II controller in the GPSI Mode.
This mode will reconfigure the
External Address Pins so that
the GPSI port is exposed. This
allows bypassing the MENDECTMAU logic. This bit should only
be set if the external logic supports GPSI operation. Damage
to the device may occur in a
3
RPA
2-0
RES
Am79C961A
non-GPSI configuration. Refer
to the GPSI section.
Runt Packet Accept. This bit
forces the CORE receive logic to
accept Runt Packets. This bit
allows for faster testing.
For test purposes only. Reserved
locations. Written as zero and
read as undefined.
113
ISA Bus Configuration Registers
The ISA Bus Data Port (IDP) allows access to registers
which are associated with the ISA bus. These registers
are called ISA Bus Configuration Registers (ISACSRs),
and are indexed by the value in the Register Address
Port (RAP). The table below defines the ISACSRs
which can be accessed. All registers are 16 bits. The
“Default” value is the value in the register after reset
and is hexadecimal.Refer to the section “LEDs” for information on LED control logic.
ISACSR
MNEMONIC
Default
0
MSRDA
0005H
Master Mode
Read Active
1
MSWRA
0005H
Master Mode
Write Active
2
MC
0002H
Miscellaneous
Configuration
3
EC
8000H*
EEPROM
Configuration
4
LED0
0000H
Link Integrity
5
LED1
0084H
Default: RCV
6
LED2
0008H
Default:
RCVPOL
7
LED3
0090H
Default: XMT
0000H
Software
Configuration
(Read-Only
register)
8
SC
9
DUP
0000H
Name
Default: Half
Duplex
This value can be 0000H for systems that do not support
EEPROM option.
ISACSR0: Master Mode Read Active/SRAM Data
Port
When in the Bus Master mode:
Bit
Name
Description
15-4
RES
3-0
MSRDA
Reserved locations. Written as
zero and read as undefined.
Master Mode Read Active time.
This register is used to tune the
MEMR command signal active
time when the PCnet-ISA II is in
the Bus Master mode. The value
stored in MSRDA defines the
number of 50 ns periods that the
command signal is active. The
default value of 5h indicates
250ns pulse widths. A value of 0
should not be used and may
result in no command assertion.
114
When in the Bus Slave, Programmed I/O architecture
mode:
15-0 SRAMDP
SRAM Data Port. This register
serves as a data port for accessing the SRAM when the PCnet-ISA II is in the Bus Slave,
Programmed I/O architecture
mode. Accesses to this port are
directed to the SRAM location
that is addressed by the
SRAMAP register (ISACSR1).
Word accesses and byte
accesses to the even byte (least
significant bits) are allowed. Byte
accesses to the odd byte are not
allowed except when they are
performed
automatically
by
motherboard logic as discussed
in the Bus Cycles (Hardware)
section.
Read
and
write
accesses to this register will have
the side effect that the SRAMAP
register (ISACSR1) will increment by 1 or 2 depending on
whether a byte or word access,
respectively, is performed.
ISACSR1: Master Mode Write Active/SRAM
Address Pointer
When in the Bus Master mode:
Bit
Name
15-4
RES
Description
Reserved locations. Written as
zero and read as undefined.
3-0 MSWRA
Master Mode Write Active time.
This register is used to tune the
MEMW command signal active
time when the PCnet-ISA II is in
the Bus Master mode. The value
stored in MSWRA defines the
number of 50 ns periods that the
command signal is active. The
default value of 5h indicates
250ns pulse widths. A value of 0
should not be used and may
result in no command assertion.
When in the Bus Slave, Programmed I/O architecture
mode:
15-0 SRAMAP
Am79C961A
SRAM Address Pointer. This
register functions as an address
pointer for accessing the SRAM
when the PCnet-ISA II is in the
Bus Slave, Programmed I/O
architecture mode. Accesses to
the SRAMDP (ISACSR0) register are directed to the SRAM
location that is addressed by this
register. This register is auto-
matically incriminated by 1 or 2
when byte or word accesses,
respectively, are performed to
the
SRAMDP
register
(ISACSR0).
ISACSR2: Miscellaneous Configuration 1
Bit
Name
11 ISA_PROTECT
Description
15 MODE_STATUS Mode Status. This is a read-only
register which indicates whether
the PCnet-ISA II is configured in
slave mode. A set condition indicates slave mode while a clear
condition indicates bus-master
condition.
14 TMAU_LOOPE 10BASE-T External Loop back
Enable. This bit is usable only
when 10BASE-T is selected
AND PCnet-ISA II is in external
loop back. External loop back is
set during initialization via the
MODE
register.
When
TMAU_LOOPE is set, a board
level test is enabled via a loop
back clip which ties the
10BASE-T RJ45 transmit pair to
the receiver pair. This will test all
external components (i.e. transformers, resistors, etc.) of the
10BASE-T
path.
TMAU_
LOOPE assertion is not suitable
for live network tests. When
TMAU_LOOPE is deasserted,
default condition, external loop
back in 10BASE-T is allowed.
13
PIOSEL
Programmed I/O Select. When
operating in the Bus Slave mode
with this bit reset to ZERO, a
shared memory implementation
is selected and the local SRAM
is accessible through memory
cycles on the ISA bus interface.
When operating in the Bus Slave
mode with this bit set to ONE, a
Programmed I/O implementation is selected and the local
SRAM is accessible through I/O
cycles on the ISA bus interface.
Refer to the Shared Memory and
Programmed I/O sections for
details on these two architecture
schemes.
When operating in the Bus Master
mode, this bit has no effect.
PIOSEL is reset to ZERO.
12
SLOT_ID
Slot Identification. This is a
read-only register bit which indicates if PCnet-ISA II is either in
an 16 or 8 bit slot. Reading a one
indicates an 8 bit slot. Zero indi-
10 EISA_DECODE
9
P&P_ACT
8
APWEN
7
EISA_LVL
6
DSDBUS
5 10BASE5_SEL
Am79C961A
cates a 16-bit slot. (SLOT_ID bit
is not valid after the INIT bit is set
in CSR0.)
ISA Protect. When set, the
ISACSR’s 0–2 and 4–9 are
protected from being written
over by software drivers. When
ISA_ PROTECT is cleared,
ISACSR’s 0–2 and 4–9 are
allowed to be written over by
software and reset by reading
the Software reset I/O location.
(Default is zero)
EISA Decode. This control bit
allows EISA product identifier registers 12-bit decode xC80 - xC83
(4 Bytes). Default is zero.
Plug and Play Active. When
this bit is set, PCnet-ISA II will
become active after serially
reading the EEPROM. If check
sum failure exist, PCnet-ISA II
will not become active and
alternate access method to
Plug and Play registers will
occur. Default is zero.
Address PROM Write Enable. It
is reset to zero by RESET. When
asserted, this pin allows write
access to the internal Address
PROM RAM. APWEN is used
also to protect the Flash device
from write cycles. When programming of the Flash device is
required, the APWEN bit needs
to be set. When reset, this pin
protects the internal Address
PROM RAM, and external Flash
device from being overwritten.
EISA Level. This bit is a
read-only register. It indicates if
the level or edge sensitive interrupts have been selected. A set
condition indicates level sensitive interrupts. A clear condition
indicates ISA edge.
Disable Staggered Data Bus.
When this bit is a zero, the data
bus driver timing is staggered
from the address bus driver
timing in Bus Master mode.
When this bit is a one, the data
bus is not staggered. It is similar
to the PCnet-ISA (Am79C960)
timing. This bit is reset to zero.
For most applications, this bit
should not have to be set.
10BASE5 Select. When set, this
bit inverts the polarity of the DXCVR pin only when the AUI port
115
4
3
2
1,0
116
ISAINACT
EADISEL
is
active.
When
the
10BASE5_SEL bit is set and the
AUI port is active, the DXCVR is
driven such that an external
DC-DC converter will be
disabled. The actual polarity of
the DXCVR pin is determined by
the DXCVRP bit in PnP Register
0xF0.
When the 10BASE-T port is
active, this bit has no effect.
10BASE5_SEL is reset to ZERO.
ISAINACT allows for reduced
inactive timing appropriate for
modern ISA machines. ISAINACT
is cleared when RESET is asserted. When ISAINACT is a zero,
tMMR3 and tMMW3 parameters
are nominally 200 ns, which is
compatible with EISA system.
When ISAINACT is set by writing
a one, tMMR3 and tMMW3 are
nominally set to 100 ns.
EADI Select. Enables EADI
match mode.
When EADI mode is selected,
the pins named LED1, LED2,
and LED3 change in function
while LED0 continues to indicate
10BASE-T Link Status.
LED
EADI Function
1
SF/BD
2
SRD
3
SRDCLK
AWAKE
MEDSEL
Auto-Wake. If AWAKE = “1", the
10BASE-T receive circuitry is
active during sleep and listens
for Link Pulses. LED0 indicates
Link Status and goes active if the
10BASE-T port comes out of
“link fail” state. This LED0 pin
can be used by external circuitry
to re-enable the PCnet-ISA II
controller and/or other devices.
When AWAKE = “0", the Auto-Wake circuity is disabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Media Select. It was previously
defined as ASEL (Auto Select)
and XMAUSEL (External MAU
Select) in the PCnet-ISA. They
are now combined together and
defined to be software compatible
with ASEL and XMAUSEL in the
PCnet-ISA (Am79C960).
MEDSEL
(1:0)
Function
0
0
Software Select (Mode Reg, CSR15)
0
1
10BASE-T Port
1
0
Auto Selection (Default)
1
1
AUI Port
ISACSR3: EEPROM Configuration
Bit
Name
Description
15
EE_VALID
14
EE_LOAD
EEPROM Valid. This bit is a
read-only register. When a one
is read, EE_PROM has a valid
checksum. The sum of the total
bytes reads should equals FF
hex. When a zero is read, checksum failed, or SHFTBUSY pin
was sampled with a zero which
indicates no EEPROM present.
EEPROM Load. When written
with a one, the device will load
the EEPROM into the PCnet-ISA II, performing self configuration. This command must
be last write to ISACSR3 Register. PCnet-ISA II will not respond
to any slave commands while
loading the EEPROM register.
EE_LOAD will be reset with a
zero after EEPROM is read. It
takes approximately, 1.4 ms for
serial EEPROM load process to
complete.
Reserved. Read and written as
zeros.
EEPROM Enable. When EE_EN
is written with a one, the lower
three bits of PRDB becomes SK,
DI and DO, respectively. EECS
and SHFBUSY are controlled by
the software select bits. This bit
must be written with a one to
write to or read from the EEPROM. PCnet-ISA II should be
in the STOP state when EE_EN
is written. When EE_EN is
cleared, DI/DO, SK, EECS and
SHFBUSY have no control.
Shift Busy. SHFBUSY allows for
the control of the SHFBUSY pin.
When a one is written, SHFBUSY
goes high provided EE_EN is a 1.
When a zero is written, SHFBUSY is held to a zero. When
EE_EN is cleared, SHFBUSY will
maintain the last value programmed. (Refer to Bit 4 above,
13–5
N/A
4
EE_EN
3
SHFBUSY
Am79C961A
EE_EN, for detailed use of this
bit).
2
EECS
EEPROM Chip Select. EECS
asserts the chip select to the
Serial EEPROM. (Refer to Bit 4
above, EE_EN, for detailed use
of this bit).
1
SK
Serial Shift Clock. SK controls
the SK input to the Serial EEPROM and the optional External
Shift Logic. (Refer to Bit 4 above,
EE_EN, for detailed use of this
bit).
0
DI/DO
Serial Shift Data In and Serial
Shift Data Out. When written,
this bit controls the DI input of
the serial EEPROM. When read,
this bit represents the DO value
of the serial EEPROM. (Refer to
Bit 4 above, EE_EN, for detailed
use of this bit).
ISACSR4: LED0 Status (Link Integrity)
Bit
15
Name
LNKST
14-0
RES
Reserved locations. Written as
zero, read as undefined.
ISACSR5: LED1 Status
Bit
Name
15
LEDOUT
14-10
RES
9
MP
8
FDLSE
7
PSE
Description
ISACSR4 is a non-programmable register that uses one bit to
reflect the status of the LED0
pin. This pin defaults to twisted
pair MAU Link Status (LNKST)
and is not programmable.
10BASE-T Link Status. LNKST
is a read-only bit that indicates
whether the Link Status LED is
asserted. When LNKST is read
as zero, the Link Status LED is
not asserted. When LNKST is
read as one, the Link Status LED
is asserted, indicating good
10BASE-T link integrity.
Note that the LNKST LED is
masked if the 10BASE-T port is
operating in Full Duplex mode,
AUIFD (ISACSR9, bit 1) is
cleared, and any one of the
FDLSE bits is set in ISACSR5,
6, or 7. Hence, an adapter card
with a 10BASE2 port (through
the AUI port) and a 10BASE-T
port that can be software
enabled for Half or Full Duplex
operation can have a Half
Duplex Link Status LED and a
Full Duplex Link Status LED in
which only one will be allowed
ON, depending on if FDEN
(ISACSR9, bit 0) is set. 14-0
RESReserved locations. Written
as zero, read as undefined.
Am79C961A
Description
ISACSR5 controls the function(s)
that the LED1 pin displays. Multiple functions can be simultaneously enabled on this LED pin.
The LED display will indicate the
logical OR of the enabled functions. ISACSR5 defaults to
Receive Status (RCV) with pulse
stretcher enabled (PSE = 1) and
is fully programmable.
Indicates the current (nonstretched) state of the function(s)
generated. Read only.
Reserved locations. Read and
written as zero.
Magic Packet LED Enable.
When set, the LED output will be
asserted to indicate that a Magic
Packet has been received.
Full Duplex Link Status Enable.
Indicates the Full Duplex Link
Test Status. When this bit is set,
a value of ONE is passed to the
LEDOUT signal when the PCnet-ISA II is functioning in a link
pass state with Full Duplex capability. When the PCnet-ISA II
is not functioning in a link pass
state with Full Duplex capability,
a value of ZERO is passed to the
LEDOUT signal.
When the 10BASE-T port is
active, a value of ONE is passed
to the LEDOUT signal whenever
the Link Test Function (described
in the T-MAU section) detects a
Link Pass state and the FDEN
(ISACSR9, bit 0) bit is set. When
the AUI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex operation on the AUI port is enabled
(both FDEN and AUIFD bits in
ISACSR9 are set to ONE). When
the GPSI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex operation on the GPSI port is enabled
(FDEN bit in ISACSR9 is set to
ONE).
Pulse Stretcher Enable. Extends
the LED illumination for each
enabled function occurrence.
117
0 is disabled, 1 is enabled.
6
RES
Reserved locations. Read and
written as zero.
5
RCVADDM
Receive Address Match. This bit
when set allows for LED control
of only receive packets which
match internal address match.
4
XMT E
Enable Transmit Status Signal.
Indicates PCnet-ISA II controller
transmit activity.
0 disables the signal, 1 enables
the signal.
3
RVPOL E
Enable Receive Polarity Signal.
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to be
ignored.
2
RCV E
Enable Receive Status Signal.
Indicates receive activity on the
network.
0 disables the signal, 1 enables
the signal.
1
JAB E
Enable Jabber Signal. Indicates
the PCnet-ISA II controller is jabbering on the network.
0 disables the signal, 1 enables
the signal.
0
COL E
Enable Collision Signal. Indicates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
ISACSR6: LED2 Status
Bit
Name
15
LEDOUT
14
LEDXOR
118
Note: This bit when used in conjunction with the
RVPOLE bit (Bit 3) of ISACSR6 can be used to create
a “Polarity Bad” LED.)
RVPOLE
LEDXOR
0
X
10BASE-T polarity function
ignored
1
0
LED2 pin low with “Good”
10BASE-T polarity (LED on)
1
1
LED2 pin high with “Good”
10BASE-T polarity (LED off)
13-10
RES
9
MP
8
FDLSE
7
PSE
6
RES
5
RCVADDM
Description
ISACSR6 controls the function(s) that the LED2 pin displays. Multiple functions can be
simultaneously enabled on this
LED pin. The LED display will
indicate the logical OR of the
enabled functions. ISACSR6
defaults to twisted pair MAU
Receive Polarity (RCVPOL)
with pulse stretcher enabled
(PSE = 1) and is fully programmable.
Indicates the current (nonstretched) state of the function(s) generated. Read only.
This bit when set causes LED2
to be an active high signal when
asserted. When this bit is
cleared, LED2 will be active low
when asserted.
Am79C961A
Result
Reserved locations. Read and
written as zero.
Magic Packet LED Enable.
When set, the LED output will be
asserted to indicate that a Magic
Packet has been received.
Full Duplex Link Status Enable.
Indicates the Full Duplex Link
Test Status. When this bit is set,
a value of ONE is passed to the
LEDOUT signal when the PCnet-ISA II is functioning in a link
pass state with Full Duplex capability. When the PCnet-ISA II
is not functioning in a link pass
state with Full Duplex capability,
a value of ZERO is passed to the
LEDOUT signal.
When the 10BASE-T port is
active, a value of ONE is passed
to the LEDOUT signal whenever
the Link Test Function (described
in the T-MAU section) detects a
Link Pass state and the FDEN
(ISACSR9, bit 0) bit is set. When
the AUI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex operation on the AUI port is enabled
(both FDEN and AUIFD bits in
ISACSR9 are set to ONE). When
the GPSI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex operation on the GPSI port is enabled
(FDEN bit in ISACSR9 is set to
ONE).
Pulse Stretcher Enable. Extends
the LED illumination for each
enabled function occurrence.
0 is disabled, 1 is enabled.
Reserved locations. Read and
written as zero.
Receive Address Match. This bit
when set allows for LED control
of only receive packets that
match internal address match.
4
XMT E
Enable Transmit Status Signal.
Indicates PCnet-ISA II controller
transmit activity.
0 disables the signal, 1 enables
the signal.
3
RVPOL E
Enable Receive Polarity Signal.
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to be
ignored.
2
RCV E
Enable Receive Status Signal.
Indicates receive activity on the
network.
0 disables the signal, 1 enables
the signal.
1
JAB E
Enable Jabber Signal. Indicates
the PCnet-ISA II controller is jabbering on the network.
0 disables the signal, 1 enables
the signal.
0
COL E
Enable Collision Signal. Indicates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
ISACSR7: LED3 Status
Bit
15
Name
LEDOUT
14-10
RES
9
MP
8
FDLSE
Description
ISACSR7 controls the function(s)
that the LED3 pin displays. Multiple functions can be simultaneously enabled on this LED pin.
The LED display will indicate the
logical OR of the enabled functions. ISACSR7 defaults to
Transmit Status (XMT) with pulse
stretcher enabled (PSE = 1) and
is fully programmable.
Indicates the current (nonstretched) state of the function(s) generated. Read only.
Reserved locations. Read and
written as zero.
Magic Packet LED Enable.
When set, the LED output will be
asserted to indicate that a Magic
Packet has been received.
Full Duplex Link Status Enable.
Indicates the Full Duplex Link
Test Status. When this bit is set,
a value of ONE is passed to the
LEDOUT signal when the PC-
7
PSE
6
RES
5
RCVADDM
4
XMT E
3
RVPOL E
2
RCV E
1
JAB E
Am79C961A
net-ISA II is functioning in a link
pass state with Full Duplex capability. When the PCnet-ISA II is
not functioning in a link pass state
with Full Duplex capability, a value of ZERO is passed to the
LEDOUT signal.
When the 10BASE-T port is
active, a value of ONE is passed
to the LEDOUT signal whenever
the Link Test Function (described
in the T-MAU section) detects a
Link Pass state and the FDEN
(ISACSR9, bit 0) bit is set. When
the AUI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex operation on the AUI port is enabled
(both FDEN and AUIFD bits in
ISACSR9 are set to ONE). When
the GPSI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex operation on the GPSI port is enabled
(FDEN bit in ISACSR9 is set to
ONE).
Pulse Stretcher Enable. Extends
the LED illumination for each
enabled function occurrence.
0 is disabled, 1 is enabled.
Reserved locations. Read and
written as zero.
Receive Address Match. This bit
when set allows for LED control
of only receive packets that
match internal address match.
Enable Transmit Status Signal.
Indicates PCnet-ISA II controller
transmit activity.
0 disables the signal, 1 enables
the signal.
Enable Receive Polarity Signal.
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to be
ignored.
Enable Receive Status Signal.
Indicates receive activity on the
network.
0 disables the signal, 1 enables
the signal.
Enable Jabber Signal. Indicates
the PCnet-ISA II controller is jabbering on the network.
0 disables the signal, 1 enables
the signal.
119
0
that Full Duplex operation will
not be enabled on the
10BASE-T port if DLNKST
(CSR15, bit 12) is set.
FDEN is read/write accessible
always. It is reset to ZERO by
the RESET pin, and is unaffected by reading the Reset register
or setting the STOP bit.
COL E
Enable Collision Signal. Indicates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
ISACSR8: Software Configuration Register
(Read-Only Register)
Bit
Description
15-12
Read-only image of SRAM(3:0) of PnP register
0x48-0x49.
11-8
Read-only image of BPAM(3:0) of PnP register
0x40-0x41.
7-4
Read-only image of IRQSEL(3:0) of PnP
register 0x70.
3
2-0
Read only bit indicating whether the SRAM is
activated as a memory resource. Set when the
Shared Memory is not activated as an ISA
memory resource.
Read-only image of DMASEL(2:0) of PnP
register 0x74.
Bit
Name
Description
1
AUIFD
AUI Full Duplex. AUIFD controls
whether Full Duplex operation
on the AUI port is enabled.
AUIFD is only meaningful if
FDEN (ISACSR9, bit 0) is set to
ONE. If the FDEN bit is ZERO,
the AUI port will always operate
in Half Duplex mode. In addition,
if FDEN is set to ONE but the
AUIFD bit is reset to ZERO, the
AUI port will always operate in
Half Duplex mode. If FDEN is set
to ONE and AUIFD is set to
ONE, Full Duplex operation on
the AUI port is enabled.
AUIFD is read/write accessible
always. It is reset to ZERO by
the RESET pin, and is unaffected by reading the Reset register
or setting the STOP bit.
Full Duplex Enable. FDEN controls whether Full Duplex operation is enabled. When FDEN is
cleared, Full Duplex operation
is not enabled and the PCnet-ISA II will always operate in
the Half Duplex mode. When
FDEN is set, the PCnet-ISA II
will operate in Full Duplex mode
when the 10BASE-T or GPSI
port is enabled or when the AUI
port is enabled and the AUIFD
(ISACSR9, bit 1) bit is set. Note
120
FDEN
The figure below shows the Initialization Block memory
configuration. Note that the Initialization Block must be
based on a word (16-bit) boundary.
Address
ISACSR9: Miscellaneous Configuration 2
0
Initialization Block
Bits
15–12
Bits
11–8
Bits
7–4
IADR+00
MODE 15–00
IADR+02
PADR 15–00
IADR+04
PADR 31–16
IADR+06
PADR 47–32
IADR+08
LADRF 15–00
IADR+10
LADRF 31–16
IADR+12
LADRF 47–32
IADR+14
LADRF 63–48
IADR+16
RDRA 15–00
IADR+18
RLEN
IADR+20
IADR+22
RES
Bits
3–0
RDRA 23–16
TDRA 15–00
TLEN
RES
TDRA 23–16
RLEN and TLEN
The TLEN and RLEN fields in the initialization block are
3 bits wide, occupying bits 15,14, and 13, and the value
in these fields determines the number of Transmit and
Receive Descriptor Ring Entries (DRE) which are used
in the descriptor rings. Their meaning is as follows:
R/TLEN
# of DREs
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
If a value other than those listed in the above table is
desired, CSR76 and CSR78 can be written after initialization is complete. See the description of the appropriate
CSRs.
Am79C961A
RDRA and TDRA
TDRA and RDRA indicate where the transmit and
receive descriptor rings, respectively, begin. Each DRE
must be located on an 8-byte boundary.
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask
that is used to accept incoming Logical Addresses. If
the first bit in the incoming address (as transmitted on
the wire) is a “1", the address is deemed logical. If the
first bit is a “0", it is a physical address and is compared
against the physical address that was loaded through
the initialization block.
A logical address is passed through the CRC generator, producing a 32-bit result. The high order 6 bits of
the CRC are used to select one of the 64 bit positions
in the Logical Address Filter. If the selected filter bit is
set, the address is accepted and the frame is placed
into memory.
The Logical Address Filter is used in multicast addressing
schemes. The acceptance of the incoming frame based
on the filter value indicates that the message may be
intended for the node. It is the node’s responsibility to
determine if the message is actually intended for the node
by comparing the destination address of the stored message with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all zeroes
and promiscuous mode is disabled, all incoming logical
addresses except broadcast will be rejected.
7. If the Disable Broadcast Bit is cleared, the
broadcast address is accepted.
8. If the Disable Broadcast Bit is set and promiscuous
mode is enabled, the broadcast address is
accepted.
9. If the Disable Broadcast Bit is set and promiscous
mode is disabled, the broadcast address is
rejected.
If external loopback is used, the FCS logic must be
allocated to the receiver (by setting the DXMTFCS bit
in CSR15, and clearing the ADD_FCS bit in TMD1)
when using multicast addressing.
PADR
This 48-bit value represents the unique node address
assigned by the IEEE and used for internal address
comparison. PADR[0] is the first address bit transmitted on the wire, and must be zero. The six-hex-byte nomenclature used by the IEEE maps to the PCnet-ISA II
controller PADR register as follows: the first byte comprises PADR[7:0], with PADR[0] being the least significant bit of the byte. The second IEEE byte maps to
PADR[15:8], again from LSbit to MSbit, and so on. The
sixth byte maps to PADR[47:40], the LSbit being
PADR[40].
MODE
The mode register in the initialization block is copied
into CSR15 and interpreted according to the description of CSR15.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is handled as
follows:
.
32-Bit Resultant CRC
Received Message
Destination Address
47
31
26
0
1 0
1
CRC
GEN
63
SEL
Logical
Address
Filter
(LADRF)
0
64
MATCH = 1:
Packet Accepted
MATCH = 0:
Packet Rejected
MUX
MATCH
6
Address Match Logic
Am79C961A
19364B-23
121
Receive Descriptors
The Receive Descriptor Ring Entries (RDREs) are
composed of four receive message fields (RMD0-3).
Together they contain the following information:
11
CRC
10
BUFF
9
STP
8
ENP
■ The address of the actual message data buffer in
user (host) memory
■ The length of that message buffer
■ Status information indicating the condition of the
buffer. The eight most significant bits of RMD1
(RMD1[15:0]) are collectively termed the STATUS
of the receive descriptor.
RMD0
Holds LADRF [15:0]. This is combined with HADR [7:0]
in RMD1 to form the 24-bit address of the buffer
pointed to by this descriptor table entry. There are no
restrictions on buffer byte alignment or length.
RMD1
Bit
Name
Description
15
OWN
This bit indicates that the descriptor entry is owned by the host
(OWN=0) or by the PCnet-ISA II
controller (OWN=1). The PCnetISA II controller clears the OWN
bit after filling the buffer pointed
to by the descriptor entry. The
host sets the OWN bit after emptying the buffer. Once the PCnet-ISA II controller or host has
relinquished ownership of a buffer, it must not change any field in
the descriptor entry.
ERR is the OR of FRAM, OFLO,
CRC, or BUFF. ERR is written
by the PCnet-ISA II controller.
FRAMING ERROR indicates
that the incoming frame contained a non-integer multiple of
eight bits and there was an FCS
error. If there was no FCS error
on the incoming frame, then
FRAM will not be set even if
there was a non integer multiple
of eight bits in the frame. FRAM
is not valid in internal loopback
mode. FRAM is valid only when
ENP is set and OFLO is not.
FRAM is written by the PCnet-ISA II controller.
OVERFLOW error indicates that
the receiver has lost all or part of
the incoming frame, due to an
inability to store the frame in a
memory buffer before the internal FIFO overflowed. OFLO is
valid only when ENP is not set.
14
13
12
122
ERR
FRAM
OFLO
7-0
HADR
OFLO is written by the PCnet-ISA II controller.
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is written by
the PCnet-ISA II controller.
BUFFER ERROR is set any time
the PCnet-ISA II controller does
not own the next buffer while
data chaining a received frame.
This can occur in either of two
ways:
1) The OWN bit of the next
buffer is zero
2) FIFO overflow occurred
before the PCnet-ISA II
controller polled the next
descriptor
If a Buffer Error occurs, an Overflow Error may also occur internally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and
OFLO errors occur at the same
time. BUFF is written by the PCnet-ISA II controller.
START OF PACKET indicates
that this is the first buffer used by
the PCnet-ISA II controller for
this frame. It is used for data
chaining buffers. STP is written
by the PCnet-ISA II controller in
normal operation. In SRPINT
Mode (CSR3.5 set to 1) this bit is
written by the driver.
END OF PACKET indicates that
this is the last buffer used by the
PCnet-ISA II controller for this
frame. It is used for data chaining buffers. If both STP and ENP
are set, the frame fits into one
buffer and there is no data chaining. ENP is written by the PCnet-ISA II controller.
The HIGH ORDER 8 address
bits of the buffer pointed to by
this descriptor. This field is written by the host and is not
changed by the PCnet-ISA II
controller.
RMD2
Bit
Name
15-12 ONES
Am79C961A
Description
MUST BE ONES. This field is
written by the host and
11-0
BCNT
unchanged by the PCnet-ISA II
controller.
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length
of the buffer. This field is written
by the host and is not changed
by the PCnet-ISA II controller.
RMD3
Bit
Name
15-12 RES
11-0 MCNT
14
ERR
13
ADD_FCS
12
MORE
11
ONE
10
DEF
Description
RESERVED and read as zeros.
MESSAGE BYTE COUNT is the
length in bytes of the received
message, expressed as an unsigned binary integer. MCNT is
valid only when ERR is clear and
ENP is set. MCNT is written by
the PCnet-ISA II controller and
cleared by the host.
MCNT Includes: DEST + SRC +
Length + Data + CRC unless the
auto strip on receive bit is set. In
this case, the Pad and CRC are
thrown away by the controller.
Transmit Descriptors
The Transmit Descriptor Ring Entries (TDREs) are
composed of four transmit message fields (TMD0-3).
Together they contain the following information:
■ The address of the actual message data buffer in
user or host memory
■ The length of the message buffer
■ Status information indicating the condition of the
buffer. The eight most significant bits of TMD1
(TMD1[15:8]) are collectively termed the STATUS
of the transmit descriptor.
Note that bit 13 of TMD1, which was formerly a
reserved bit in the LANCE (Am7990), is assigned a
new meaning, ADD_FCS.
TMD0
Holds LADR [15:0]. This is combined with HADR [7:0]
in TMD1 to form a 24-bit address of the buffer pointed
to by this descriptor table entry. There are no restrictions on buffer byte alignment or length.
TMD1
Bit
Name
Description
15
OWN
This bit indicates that the
descriptor entry is owned by the
host (OWN=0) or by the PCnet-ISA II controller (OWN=1).
Am79C961A
The host sets the OWN bit after
filling the buffer pointed to by the
descriptor entry. The PCnet-ISA
II controller clears the OWN bit
after transmitting the contents of
the buffer. Both the PCnet-ISA II
controller and the host must not
alter a descriptor entry after it
has relinquished ownership.
ERR is the OR of UFLO, LCOL,
LCAR, or RTRY. ERR is written
by the PCnet-ISA II controller.
This bit is set in the current descriptor when the error occurs,
and therefore may be set in any
descriptor of a chained buffer
transmission.
ADD_FCS dynamically controls
the generation of FCS on a
frame by frame basis. It is valid
only if the STP bit is set. When
ADD_FCS is set, the state of
DXMTFCS is ignored and transmitter FCS generation is activated. When ADD_FCS = 0, FCS
generation is controlled by
DXMTFCS. ADD_FCS is written
by the host, and unchanged by
the PCnet-ISA II controller. This
was a reserved bit in the LANCE
(Am7990).
MORE indicates that more than
one re-try was needed to transmit a frame. MORE is written by
the PCnet-ISA II controller. This
bit has meaning only if the ENP
or the ERR bit is set.
ONE indicates that exactly one
re-try was needed to transmit a
frame. ONE flag is not valid
when LCOL is set. ONE is written by the PCnet-ISA II controller. This bit has meaning only if
the ENP or the ERR bit is set.
DEFERRED indicates that the
PCnet-ISA II controller had to
defer while trying to transmit a
frame. This condition occurs if
the channel is busy when the
PCnet-ISA II controller is ready
to transmit. DEF is written by the
PCnet-ISA II controller. This bit
has meaning only if the ENP or
ERR bits are set.
123
9
STP
8
ENP
7-0
HADR
START OF PACKET indicates
that this is the first buffer to be
used by the PCnet-ISA II controller for this frame. It is used for
data chaining buffers. The STP
bit must be set in the first buffer
of the frame, or the PCnet-ISA II
controller will skip over the
descriptor and poll the next
descriptor(s) until the OWN and
STP bits are set.
STP is written by the host and is
not changed by the PCnet-ISA II
controller.
END OF PACKET indicates that
this is the last buffer to be used
by the PCnet-ISA II controller for
this frame. It is used for data
chaining buffers. If both STP and
ENP are set, the frame fits into
one buffer and there is no data
chaining. ENP is written by the
host and is not changed by the
PCnet-ISA II controller.
The HIGH ORDER 8 address
bits of the buffer pointed to by
this descriptor. This field is written by the host and is not
changed by the PCnet-ISA II
controller.
14
UFLO
13
RES
12
LCOL
11
LCAR
10
RTRY
TMD2
Bit
Name
15-12 ONES
11-0
BCNT
Description
MUST BE ONES. This field is
written by the host and
unchanged by the PCnet-ISA II
controller.
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length
of the buffer. This is the number
of bytes from this buffer that will
be transmitted by the PCnet-ISA
II controller. This field is written
by the host and is not changed
by the PCnet-ISA II controller.
There are no minimum buffer
size restrictions. Zero length
buffers are allowed for protocols
which require it.
TMD3
Bit
Name
Description
15
BUFF
BUFFER ERROR is set by the
PCnet-ISA II controller during
transmission when the PCnet-ISA II controller does not find
124
Am79C961A
the ENP flag in the current buffer
and does not own the next buffer. This can occur in either of two
ways:
1) The OWN bit of the next
buffer is zero.
2) FIFO underflow occurred
before the PCnet-ISA II
controller obtained the
next STATUS byte
(TMD1[15:8]).
BUFF error will turn off the
transmitter (CSR0, TXON = 0),
if DXSUFLO = 0 (bit 6 CSR3). If
a Buffer Error occurs, an
Underflow Error will also occur.
BUFF is not valid when LCOL
or RTRY error is set during
transmit data chaining. BUFF
is written by the PCnet-ISA II
controller.
UNDERFLOW ERROR indicates that the transmitter has
truncated a message due to
data late from memory. UFLO
indicates that the FIFO has emptied before the end of the frame
was reached. Upon UFLO error,
the transmitter is turned off
(CSR0, TXON = 0), if DXSUFLO
= 0 (bit 6 CSR3). UFLO is written
by the PCnet-ISA II controller.
RESERVED bit. The PCnet-ISA
II controller will write this bit with
a “0".
LATE COLLISION indicates that
a collision has occurred after the
slot time of the channel has
elapsed. The PCnet-ISA II controller does not re-try on late collisions. LCOL is written by the
PCnet-ISA II controller.
LOSS OF CARRIER is set in
AUI mode when the carrier is
lost during an PCnet-ISA II controller- initiated transmission.
The PCnet-ISA II controller does
not stop transmission upon loss
of carrier. It will continue to
transmit the whole frame until
done. LCAR is written by the
PCnet-ISA II controller.
In 10BASE-T mode, LCAR will
be set when the T-MAU is in link
fail state.
RETRY ERROR indicates that
the transmitter has failed after
16 attempts to successfully
transmit a message, due to
repeated collisions on the
09-00
TDR
medium. If DRTY = 1 in the
MODE register, RTRY will set
after one failed transmission attempt. RTRY is written by the
PCnet-ISA II controller.
TIME DOMAIN REFLECTOMETRY reflects the state of an internal PCnet-ISA II controller
counter that counts at a 10 MHz
rate from the start of a transmission to the occurrence of a collision or loss of carrier. This value
Am79C961A
is useful in determining the
approximate distance to a cable
fault. The TDR value is written
by the PCnet-ISA II controller
and is valid only if RTRY is set.
Note that 10 MHz gives very low
resolution and in general has not
been found to be particularly
useful. This feature is here
primarily to maintain full compatibility with the LANCE.
125
Register Summary
Ethernet Controller Registers (Accessed via RDP Port)
RAP Addr
Symbol
Width
User Register
00
CSR0
16-bit
Y
PCnet-ISA II controller status
01
CSR1
16-bit
Y
Lower IADR: maps to location 16
02
CSR2
16-bit
Y
Upper IADR: maps to location 17
03
CSR3
16-bit
Y
Mask Register
04
CSR4
16-bit
Y
Miscellaneous Register
05
CSR5
16-bit
Reserved
06
CSR6
16-bit
RXTX: RX/TX Encoded Ring Lengths
07
CSR7
16-bit
08
CSR8
16-bit
Y
LADR0: LADRF[15:0]
09
CSR9
16-bit
Y
LADR1: LADRF[31:16]
10
CSR10
16-bit
Y
LADR2: LADRF[47:32]
11
CSR11
16-bit
Y
LADR3: LADRF[63:48]
12
CSR12
16-bit
Y
PADR0: PADR[15:0]
13
CSR13
16-bit
Y
PADR1: PADR[31:16]
14
CSR14
16-bit
Y
PADR2: PADR[47:32]
Y
126
Comments
Reserved
15
CSR15
16-bit
16-17
CSR16
32-bit
IADR: Base Address of INIT Block
MODE: Mode Register
18-19
CSR18
32-bit
CRBA: Current RCV Buffer Address
20-21
CSR20
32-bit
CXBA: Current XMT Buffer Address
22-23
CSR22
32-bit
24-25
CSR24
32-bit
NRBA: Next RCV Buffer Address
26-27
CSR26
32-bit
NRDA: Next RCV Descriptor Address
28-29
CSR28
32-bit
CRDA: Current RCV Descriptor Address
30-31
CSR30
32-bit
32-33
CSR32
32-bit
NXDA: Next XMT Descriptor Address
34-35
CSR34
32-bit
CXDA: Current XMT Descriptor Address
36-37
CSR36
32-bit
Next Next Receive Descriptor Address
Y
Y
BADR: Base Address of RCV Ring
BADX: Base Address of XMT Ring
38-39
CSR38
32-bit
Next Next Transmit Descriptor Address
40-41
CSR40
32-bit
CRBC: Current RCV Stat and Byte Count
42-43
CSR42
32-bit
CXBC: Current XMT Status and Byte Count
44-45
CSR44
32-bit
NRBC: Next RCV Stat and Byte Count
46
CSR46
16-bit
47
CSR47
32-bit
48-49
CSR48
32-bit
TMP0: Temporary Storage
50-51
CSR50
32-bit
TMP1: Temporary Storage
52-53
CSR52
32-bit
TMP2: Temporary Storage
54-55
CSR54
32-bit
TMP3: Temporary Storage
56-57
CSR56
32-bit
TMP4: Temporary Storage
58-59
CSR58
32-bit
TMP5: Temporary Storage
60-61
CSR60
32-bit
PXDA: Previous XMT Descriptor Address
62-63
CSR62
32-bit
PXBC: Previous XMT Status and Byte Count
POLL: Poll Time Counter
Y
Am79C961A
Polling Interval
Register Summary
Ethernet Controller Registers (Accessed via RDP Port)
RAP Addr
Symbol
Width
User Register
64-65
CSR64
32-bit
NXBA: Next XMT Buffer Address
66-67
CSR66
32-bit
NXBC: Next XMT Status and Byte Count
68-69
CSR68
32-bit
XSTMP: XMT Status Temporary
70-71
CSR70
32-bit
RSTMP: RCV Status Temporary
72
CSR72
16-bit
RCVRC: RCV Ring Counter
74
CSR74
16-bit
XMTRC: XMT Ring Counter
76
CSR76
16-bit
Y
RCVRL: RCV Ring Length
78
CSR78
16-bit
Y
XMTRL: XMT Ring Length
80
CSR80
16-bit
Y
DMABR: Burst Register
82
CSR82
16-bit
Y
DMABAT: Bus Activity Timer
84-85
CSR84
32-bit
DMABA: Address Register
86
CSR86
16-bit
DMABC: Byte Counter/Register
88-89
CSR88
32-bit
92
CSR92
16-bit
RCON: Ring Length Conversion Register
94
CSR94
16-bit
XMTTDR: Transmit Time Domain Reflectometry
96-97
CSR96
32-bit
SCR0: BIU Scratch Register 0
98-99
CSR98
32-bit
SCR1: BIU Scratch Register 1
104-105
CSR104
32-bit
SWAP:16-bit Word/Byte Swap Register
108-109
CSR108
32-bit
BMSCR: BMU Scratch Register
112
CSR112
16-bit
Y
Missed Frame Count
114
CSR114
16-bit
Y
Receive Collision Count
124
CSR124
16-bit
Y
BMU Test Register
126
CSR126
16-bit
Y
Comments
Chip ID Register
Reserved
Note:
Although the PCnet-ISA II controller has many registers that can be accessed by software, most of these registers are intended
for debugging and production testing purposes only. The registers with a "Y" are the only registers that should be accessed by
network software.
Am79C961A
127
Register Summary
ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port)
RAP Addr
Mnemonic
Default
0
MSRDA
0005H
Master Mode Read Active
1
MSWRA
0005H
Master Mode Write Active
2
MC
0002H
Miscellaneous Configuration
3
EC
8000*H
EEPROM Configuration
4
LED0
0000H
LED0 Status (Link Integrity)
5
LED1
0084H
LED1Status (Default: RCV)
6
LED2
0008H
LED2 Status (Default: RCVPOL)
7
LED3
0090H
LED3 Status (Default: XMT)
8
SC
0000H
Software Configuration (Read-Only Register)
9
DUP
0000H
Full/Half Duplex Conditions (Default: Half
Duplex)
* This value can be 0000H for systems that do not support EEPROM option
I/O Address Offset
Offset
#Bytes
0h
16
Address PROM
10h
2
RDP
12h
2
RAP(shared by RDP and IDP)
14h
2
Reset
16h
2
IDP
128
Register
Am79C961A
Name
SYSTEM APPLICATION
ISA Bus Interface
Compatibility Considerations
Although 8 MHz is now widely accepted as the standard
speed at which to run the ISA bus, many machines have
been built which operate at higher speeds with non-standard timing. Some machines do not correctly support
16-bit I/O operations with wait states. Although the PCnet-ISA II controller is quite fast, some operations still require an occasional wait state. The PCnet-ISA II
controller moves data through memory accesses, therefore, I/O operations do not affect performance. By configuring the PCnet-ISA II controller as an 8-bit I/O device,
compatibility with PC/AT-class machines is obtained at
virtually no cost in performance. To treat the PCnet-ISA
II controller as an 8-bit software resource (for non-ISA
applications), the even-byte must be accessed first,
followed by an odd-byte access.
Memory cycle timing is an area where some tradeoffs
may be necessary. Any slow down in a memory cycle
translates directly into lower bandwidth. The PCnet-ISA II controller starts out with much higher bandwidth than most slave type controllers and should
continue to be superior even if an extra 50 or 100 ns
are added to memory cycles.
The memory cycle active time is tunable in 50 ns increments with a default of 250 ns. The memory cycle idle
time defaults to 200 ns and can be reprogrammed to
100 ns. See register description for ISACS42. Most
machines should not need tuning.
The PCnet-ISA II controller is compatible with NE2100
and NE1500T software drivers. All the resources such
as address PROM, boot PROM, RAP, and RDP are in
the same location with the same semantics. An additional set of registers (ISA CSR) is available to configure on board resources such as ISA bus timing and
LED operation. However, loopback frames for the PCnet-ISA II controller must contain more than 64 bytes of
data if the Runt Packet Accept feature is not enabled;
this size limitation does not apply to LANCE (Am7990)
based boards such as the NE2100 and NE1500T.
Bus Master
Bus Master mode is the preferred mode for client applications on PC/AT or similar machines supporting 16-bit
DMA with its unsurpassed combination of high performance and low cost.
Shared Memory
The shared memory mode is recommended for file
servers or other applications where there is very high,
average or peak latency.
The address compare circuit has the following functions. It receives the 7 LA signals, generates
MEMCS16, and compares them to the desired shared
memory and boot PROM addresses. The logic latches
the address compare result when BALE goes inactive
and uses the appropriate SA signals to generate
SMAM and BPAM.
All these functions can be performed in one PAL
device. To operate in an 8-bit PC/XT environment, the
LA signals should have weak pull-down resistors connected to them to present a logic 0 level when not
driven.
Am79C961A
129
BPCS
OE
CE
PRDB[0-7]
16-Bit System Data
D[0–7]
Boot
PROM
SD[0–15]
PCnet-ISA II
Controller
ISA
Bus
24-Bit System
Address
PRDB[2]/EEDO
A[0–15]
PRDB[1]/EEDI
PRDB[0]/EESK
DO
DI
SK
CS
SA[0–19]
LA[17–23]
SHFBUSY
EECS
EEPROM
VCC
ORG
VCC
19364B-24
Bus Master Block Diagram Plug and Play Compatible
BPCS
ISA
Bus
24-Bit
System
Address
IEEE
Address
PROM
PRDB[0]
SD[0–15]
16-Bit
System
Data
A[0–4]
D[0–7]
G
PRDB[0]/EESK
PCnet-ISA II
Controller
PRDB[1]/EEDI
PRDB[2]/EEDO
SA[0]
LA[17–23]
EECS
IRQ15/
IRQ12/FlashWE SHFBUSY
VCC
WE
A[0–15]
D[0–7]
Flash
CS
OE
SK
DI
EEPROM
VCC
DO
CS
Bus Master Block Diagram Plug and Play Compatible with Flash Support
130
Am79C961A
ORG
19364B-25
A[0–15]
PRAB(0:15)
16-Bit
System Data
24-Bit System
Address
SD[0–15]
CE
OE
D[0-7]
BPCS
PRDB[0–7]
PCnet-ISA II
Controller
PRDB[2]/EEDO
2
DO
PRDB[1]/EEDI
1
DI
PRDB[0]/EESK
0
SK
SA[0–15]
SMAM
Boot
PROM
EECS
EEPROM
CS
VCC
ORG
SHFBUSY
BPAM
SRWE
SROE
ISA
Bus
A[0-15]
D[0-7]
WE
SRAM
CS
VCC
OE
BPAM
SHFBUSY
CLK
SMAM
SA[16]
LA[17-23]
External
Glue
Logic
SIN
MEMCS16
Shared Memory Block Diagram Plug and Play Compatible
Am79C961A
19364B-26
131
A[0-15]
PRAB[0-15]
PRDB[0–7]
WE
BPCS
CS
SD[0–15]
16-Bit
System Data
PCnet-ISA II
Controller
24-Bit System
Address
SA[0–19]
D[0-7]
FLASH
OE
SROE
PRDB[2]/EEDO
DO
PRDB[1]/EEDI
DI
PRDB[0]/EESK
EECS
SK
CS
EEPROM
VCC
ORG
SRWE
SHFBUSY SRAM BPAM IRQ12/SRCS
ISA
Bus
OE
A[0-15]
WE
SRAM
CS
D[0-7]
SIN
MEMCS16
CLK
VCC
External
BPAM
Glue
SRAM Logic
SHFBUSY
SA[16] LA[17-23]
19364B-27
Shared Memory Block Diagram Plug and Play Compatible with Flash Memory Support
Optional Address PROM Interface
Boot PROM Interface
The suggested address PROM is the Am27LS19, a
32x8 device. APCS should be connected directly to the
device’s G input.
The boot PROM is a 8K – 64K EPROM. Its OE pin
should be tied to ground, and chip enable CE to BPCS
to minimize power consumption at the expense of
speed. Shown below is a 27C128.
A4–A0
G
Higher density EPROMs place an address line on the
pin that is defined for lower density EPROMs as the
VPP (programming voltage) pin. For READ only operation on an EPROM, the VPP pin can assume any logic
level, as long as the voltage on the VPP pin does not
exceed the programming voltage threshold (typically
7 V to 12 V). Therefore, a socket with a 27512 pinout
will also support 2764 and 27128 EPROM devices.
27LS19
32 x 8 PROM
Q7–Q0
Address PROM Example
19364B-28
132
Am79C961A
EEPROM Interface
A13–A0
The suggested EEPROM is the industry standard
93C56 2 Kbit serial EEPROM. This is used in the 16-bit
mode to provide 128 x 16-bit EEPROM locations to
store configuration information as well as the Plug and
Play information.
DQ7–DQ0
27C128
16K x 8 EPROM
CE
OE
19364B-29
93C56
Static RAM Interface (for Shared Memory
Only)
The SRAM is an 8Kx8 or 32Kx8 device. The PCnet-ISA
II controller can support 64 Kbytes of SRAM address
space. The PCnet-ISA II controller provides SROE and
SRWE outputs which can go directly to the OE and
pins of the SRAM, respectively. The address lines are
connected as described in the shared memory section
and the data lines go to the Private Data Bus.
EECS
CS
PRDB2/EEDO
DO
PRDB1/EEDI
DI
PRDB0/EESK
CLK
VCC
ORG
19364B-30
Boot PROM Example
AUI
10BASE-T Interface
The PCnet-ISA II controller drives the AUI through a set
of transformers. The DI and CI inputs should each be
terminated with a pair of matched 39 Ω or 40.2 Ω resistors connected in series with the middle node bypassed
to ground with a.01 µF to 0.1 µF capacitor. Refer to the
PCnet-ISA Technical Manual (PID #16850B) for network
interface design and refer to Appendix A for a list of
compatible AUI isolation transformers.
The diagram below shows the proper 10BASE-T network
interface design. Refer to the PCnet Family Technical
Manual (PID #18216A) for more design details, and refer
to Appendix A for a list of compatible 10BASE-T filter/
transformer modules.
Filter &
Transformer
Module
61.9
TXD+
422.0
1:1
TXP+
PCnet-ISA II
Controller TXD-
61.9
1.21 K
XMT
Filter
RJ45
Connector
TD+ 1
TD- 2
422.0
TXP1:1
RXD+
RXD-
100
RCV
Filter
RD+ 3
RD- 6
19364B-31
10BASE-T External Components and Hookup
Am79C961A
133
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .
Under Bias . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Ambient Temperature (TA) . . . . . . . . . . . 0°C to+70°C
Supply Voltage to AVss
or DVSS (AVDD, DVDD). . . . . . . . . . . –0.3 V to +6.0 V
Ambient Temperature (TA) . . . . . . . . . –40°C to+85°C
Industrial (I) Devices
VCC Supply Voltages. . . . . . (AVDD, DVDD) 5 V ±5%
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
All inputs within the range: . . AVSS – 0.5 V ≤ VIN ≤
AVDD + 0.5 V, or
DVSS – 0.5 V ≤ VIN ≤
DVDD + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS (Unless otherwise noted, parametric values are the same
between Commercial devices and Industrial devices)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
0.8
V
DVDD + 0.5
V
0.5
V
Digital Input Voltage
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
2.0
Digital Output Voltage
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
(Note 1)
2.4
VDD = 5 V, VIN = 0 V
(Note 2)
–10
–10
V
Digital Input Leakage Current
IIX
Input Leakage Current
10
µA
Digital Output Leakage Current
IOZL
Output Low Leakage Current
(Note 3)
VOUT = 0 V
IOZH
Output High Leakage Current
(Note 3)
VOUT = VDD
µA
10
µA
Crystal Input Current
VILX
XTAL1 Input LOW Threshold
Voltage
VIN = External Clock
–0.5
0.8
V
VILHX
XTAL1 Input HIGH Threshold
Voltage
VIN = External Clock
3.5
VDD + 0.5
V
IILX
XTAL1 Input LOW Current
VIN = DVSS
Active
–120
0
µA
Sleep
–10
+10
µA
IIHX
XTAL1 Input HIGH Current
VIN = VDD
Active
0
120
µA
400
µA
Sleep
Attachment Unit Interface
134
IIAXD
Input Current at DI+ and DI–
AVSS < VIN < AVDD
–500
+500
µA
IIAXC
Input current at CI+ and CI–
AVSS < VIN < AVDD
–500
+500
µA
VAOD
Differential Output Voltage |(DO+)–
RL = 78 Ω
(DO–)|
630
1200
mV
Am79C961A
DC CHARACTERISTICS (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Attachment Unit Interface (continued)
VAODOFF
Transmit Differential Output Idle
Voltage
RL = 78 Ω
–40
+40
mV
IAODOFF
Transmit Differential Output Idle
Current
RL = 78 Ω (Note 4)
–1
+1
mA
VCMT
Transmit Output Common Mode
Voltage
RL = 78 Ω
2.5
AVDD
V
VODI
DO± Transmit Differential Output
Voltage Imbalance
RL = 78 Ω (Note 5)
25
mV
VATH
Receive Data Differential Input
Threshold
(Note 5)
–35
35
mV
VASQ
DI± and CI± Differential Input
Threshold (Squelch)
–275
–160
mV
DI± and CI± Differential Mode Input
Voltage Range
–1.5
+1.5
V
AVDD–3.0
AVDD–1.0
V
–100
mV
500
µA
VIRDVD
VICM
DI± and CI± Input Bias Voltage
IIN = 0 mA
VOPD
DO± Undershoot Voltage at Zero
Differential on Transmit Return to
Zero (ETD)
(Note 5)
Twisted Pair Interface
IIRXD
Input Current at RXD±
RRXD
RXD± Differential Input Resistance (Note 5)
VTIVB
RXD+, RXD– Open Circuit Input
Voltage (Bias)
IIN = 0 mA
VTIDV
Differential Mode Input Voltage
Range (RXD±)
VTSQ+
AVSS < VIN < AVDD
–500
10
KΩ
AVDD – 3.0
AVDD – 1.5
V
AVDD = +5 V
–3.1
+3.1
V
RXD Positive Squelch Threshold
(Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
300
520
mV
VTSQ–
RXD Negative Squelch Threshold
(Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
–520
–300
mV
VTHS+
RXD Post-Squelch
Positive Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
150
293
mV
VTHS–
RXD Post-Squelch
Negative Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
–293
–150
mV
VLTSQ+
RXD Positive Squelch Threshold
(Peak)
LRT = 1 (Note 6)
180
312
mV
VLTSQ–
RXD Negative Squelch Threshold
(Peak)
LRT = 1 (Note 6)
–312
–180
mV
VLTHS+
RXD Post-Squelch Positive
Threshold (Peak)
LRT = 1 (Note 6)
90
156
mV
VLTHS–
RXD Post-Squelch Negative
Threshold (Peak)
LRT = 1 (Note 6)
–156
–90
mV
Am79C961A
135
DC CHARACTERISTICS (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
–35
35
mV
DVDD
V
Twisted Pair Interface (continued)
RXD Switching Threshold
(Note 5)
VTXH
TXD± and TXP± Output HIGH
Voltage
DVSS = 0 V
DVDD – 0.6
VTXL
TXD± and TXP± Output LOW
Voltage
DVDD = +5 V
DVSS
VTXI
TXD± and TXP± Differential Output
Voltage Imbalance
VRXDTH
VTXOFF
RTX
DVSS
+
0.6
V
–40
+40
mV
–40
+40
mV
TXD± and TXP± Idle Output
Voltage
DVDD = +5 V
TXD± Differential Driver Output
Impedance
(Note 5)
40
Ω
TXP± Differential Driver Output
Impedance
(Note 5)
80
Ω
0.8
V
IEEE 1149.1 (JTAG) Test Port
VIL
TCK, TMS, TDI
VIH
TCK, TMS, TDI
VOL
TDO
IOL = 2.0 mA
VOH
TDO
IOH = –0.4 mA
IIL
TCK, TMS, TDI
VDD = 5.5 V, VI = 0.5 V
–200
µA
IIH
TCK, TMS, TDI
VDD =5.5 V, VI = 2.7 V
–100
µA
IOZ
TDO
0.4 V < VOUT < VDD
+10
µA
2.0
V
0.4
V
2.4
–10
V
Power Supply Current
IDD
IDDCOMA
IDDSNOOZE
Active Power Supply Current
XTAL1 = 20 MHz
75
mA
Coma Mode Power
Supply Current
SLEEP active
200
µA
Snooze Mode Mall Power
Supply Current
Awake bit set active
10
mA
1. VOH does not apply to open-drain output pins.
2. IIX applies to all input only pins except DI+, CI+, XTAL1 and PRDB[7:0].
3. OZL applies to all three-state output pins and bi-directional pins, except PRDB[7:0]. IOZH applies to pins PRDB[7:0].
4. Correlated to other tested parameters—not tested directly.
5. Parameter not tested.
6. LRT is bit 9 of Mode register (CSR15)
136
Am79C961A
SWITCHING CHARACTERISTICS: BUS MASTER MODE (Unless otherwise noted,
parametric values are the same between Commercial devices and Industrial devices)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Input/Output Write Timing
tIOW1
AEN, SBHE, SA0–9 Setup to
↓ IOW
10
ns
tIOW2
AEN, SBHE,SA0–9 Hold After
↑ IOW
5
ns
tIOW3
IOW Assertion
100
ns
tIOW4
IOW Inactive
55
ns
tIOW5
SD Setup to ↑ IOW
10
ns
tIOW6
SD Hold After ↑ IOW
10
ns
tIOW7
↓ IOCHRDY Delay from ↓ IOW
0
tIOW8
IOCHRDY Inactive
tIOW9
↑IOCHRDY to ↑ IOW
35
ns
125
ns
0
ns
Input/Output Read Timing
tIOR1
AEN, SBHE, SA0–9 Setup to
↓ IOR
15
ns
tIOR2
AEN, SBHE, SA0–9 Hold After
↑ IOR
5
ns
tIOR3
IOR Inactive
55
ns
tIOR4
SD Hold After ↑ IOR
0
20
ns
tIOR5
SD Valid from ↓ IOR
0
110
ns
tIOR6
↓ IOCHRDY Delay from ↓ IOR
0
35
ns
tIOR7
IOCHRDY Inactive
125
tIOR8
SD Valid from ↑ IOCHRDY
–130
ns
10
ns
I/O to Memory Command Inactive
tIOM1
↑ IOW/MEMW to ↓ (S)MEMR/IOR
55
ns
tIOM2
↑ (S)MEMR/IOR to ↓ IOW/MEMW
55
ns
tIOCS1
AEN, SBHE, SA0–9 to ↓ IOCS16
0
35
ns
tIOCS2
AEN, SBHE, SA0–9 to IOCS16
Tristated
0
25
ns
IOCS16 Timing
Master Mode Bus Acquisition
tMMA1
REF Inactive to ↓ DACK
5
ns
tMMA2
↑ DRQ to ↓ DACK
0
ns
tMMA3
DACK Inactive
55
ns
tMMA4
↓ DACK to ↓ MASTER
tMMA5
↓ MASTER to Active Command,
SBHE, SA0–19, LA17–23
125
Am79C961A
35
ns
185
ns
137
SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
65
ns
Master Mode Bus Release
tMMBR1
Command Deassert to ↓ DRQ
45
tMMBR2
↓ DRQ to ↑ DACK
0
tMMBR3
↓ DRQ to ↑ MASTER
40
60
ns
tMMBR4
↓ DRQ to Command, SBHE,
SA0–19, LA17–23 Tristated
–15
0
ns
ns
Master Write Cycles
tMMW1
SBHE, SA0–19, LA17–23, Active
to ↓ MEMW
(Note 1)
EXTIME + 45
EXTIME + 65
ns
tMMW2
MEMW Active
(Note 2)
MSWRA – 10
MSWRA + 5
ns
tMMW3
MEMW Inactive
(Note 1)
EXTIME + 97
EXTIME + 105
ns
tMMW4
↑ MEMW to SBHE, SA0–19,
LA17–23,SD Inactive
45
55
ns
tMMW5
SBHE, SA0–19, LA17–23, SD
Hold After ↑ MEMW
45
60
ns
tMMW6
SBHE, SA0–19, LA17–23, SD
Setup to ↓ MEMW
EXTIME + 45
EXTIME + 55
ns
tMMW7
↓ IOCHRDY Delay from
↓ MEMW
tMMW8
(Note 1)
tMMW2 – 175
ns
IOCHRDY Inactive
55
ns
tMMW9
↑ IOCHRDY to ↑ MEMW
130
ns
tMMW10
SD Active to ↓ MEMW
(Note 1)
EXTIME + 20
EXTIME + 60
ns
tMMW11
SD Setup to ↓ MEMW
(Note 1)
EXTIME + 20
EXTIME + 60
ns
Master Read Cycles
tMMR1
SBHE, SA0–19, LA17–23, Active
to ↓ MEMR
(Note 1)
EXTIME + 45
EXTIME + 60
ns
tMMR2
MEMR Active
(Note 2)
MSRDA – 10
MSRDA + 5
ns
tMMR3
MEMR Inactive
(Note 1)
EXTIME + 97
EXTIME + 105
ns
tMMR4
↑ MEMR to SBHE, SA0–19,
LA17–23 Inactive
45
55
ns
tMMR5
SBHE, SA0–19, LA17–23 Hold
After ↑ MEMW
45
55
ns
tMMR6
SBHE, SA0–19, LA17–23 Setup to
↓ MEMR
EXTIME + 45
EXTIME + 55
ns
tMMR7
↓ IOCHRDY Delay from ↓ MEMR
tMMR8
(Note 1)
tMMR2 – 175
ns
IOCHRDY Inactive
55
ns
tMMR9
↑ IOCHRDY to ↑ MEMR
130
ns
tMMR10
SD Setup to ↑ MEMR
30
ns
tMMR11
SD Hold After ↑ MEMR
0
ns
138
Am79C961A
SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Master Mode Address PROM Read
tMA1
↓ IOR to ↓ APCS
125
260
ns
tMA2
APCS Active
140
155
ns
tMA3
PRDB Setup to ↑ APCS
20
ns
tMA4
PRDB Hold After ↑ APCS
0
ns
tMA5
↑ APCS to ↑ IOCHRDY
45
65
ns
tMA6
SD Valid from ↑ IOCHRDY
0
10
ns
Master Mode Boot PROM Read
tMB1
REF, SBHE,SA0–19 Setup to ↓
SMEMR
10
ns
tMB2
REF, SBHE,SA0–19 Hold ↑
SMEMR
5
ns
tMB3
↓ IOCHRDY Delay from ↓ SMEMR
0
tMB4
SMEMR Inactive
55
tMB5
↓ SMEMR to ↓ BPCS
125
260
ns
tMB6
BPCS Active
290
305
ns
tMB7
↑ BPCS to ↑ IOCHRDY
45
65
ns
tMB8
PRDB Setup to ↑ BPCS
20
ns
tMB9
PRDB Hold After ↑ BPCS
0
ns
tMB10
SD Valid from ↑ IOCHRDY
0
10
ns
tMB11
SD Hold After ↑ SMEMR
0
20
ns
tMB12
LA20–23 Hold from ↓ BALE
10
ns
tMB13
LA20–23 Setup to ↓ MEMR
10
ns
tMB14
↑ BALE Setup to ↓ MEMR
10
ns
35
ns
ns
Notes:
1. EXTIME is 100 ns when ISACSR2, bit 4, is cleared (default). EXTIME is 0 ns when ISACSR2, bit 4, is set.
2. MSRDA and MSWDA are parameters which are defined in registers ISACSR0 and ISACSR1, respectively.
Am79C961A
139
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tMFR1
REF, SBHE,SA0–19 Setup to
↓ MEMR
10
ns
tMFR2
REF, SBHE,SA0–19 Hold from
↑ MEMR
5
ns
tMFR3
↓ IOCHRDY to MEMR
0
tMFR4
↓ MEMR Inactive
55
tMFR5
↓ MEMR to ↓ BPCS
125
260
ns
tMFR6
BPCS Active
190
205
ns
tMFR7
↑ BPCS to ↑ IOCHRDY
45
65
ns
tMFR8
PRDB Setup to ↑ of BPCS
20
ns
tMFR9
PRDB Hold to ↑ of BPCS
0
ns
tMFR10
SD Valid from ↑ IOCHRDY
0
10
ns
tMFR11
SD Tristate to ↑ MEMR
0
20
ns
tMFR12
LA20–23 Hold from ↓ BALE
10
ns
tMFR13
LA20–23 Setup to ↓ MEMR
10
ns
tMFR14
↑ BALE Setup to ↓ MEMR
15
ns
35
ns
ns
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH WRITE CYCLE
Parameter
Symbol
Parameter Description
tMFW1
SBHE, SA0–19 Setup to ↓ MEMW
10
ns
tMFW2
SBHE, SA0–19 Hold from ↑
MEMW
5
ns
tMFW3
↓ IOCHRDY to ↓ MEMW
0
tMFW4
MEMW Inactive
50
tMFW5
↑ FL_WE to ↑ IOCHRDY
20
tMFW6
↑ MEMW Hold from
↑ IOCHRDY
0
tMFW7
SD Valid from ↓ MEMW
tMFW8
SD Hold from ↑ MEMW
tMFW9
PRDB Valid from ↓ MEMW
tMFW10
PRDB Setup to ↓ FL_WE
15
tMFW11
FL_WE Active
140
tMFW12
PRDB Hold from ↑ FL_WE
15
tMFW13
LA20–23 Hold from ↓ BALE
10
ns
tMFW14
LA20–23 Setup to ↓ MEMW
10
ns
tMFW15
↑ BALE Setup to ↓ MEMW
15
ns
140
Test Conditions
Min
Max
35
ns
ns
90
ns
ns
175
0
ns
ns
175
Am79C961A
Unit
ns
ns
155
ns
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (Unless otherwise noted,
parametric values are the same between Commercial devices and Industrial devices)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Input/Output Write Timing
tIOW1
AEN, SBHE, SA0–9 Setup to
↓ IOW
10
ns
tIOW2
AEN, SBHE,SA0–9 Hold from
↑ IOW
5
ns
tIOW3
IOW Assertion
150
ns
tIOW4
IOW Inactive
55
ns
tIOW5
SD Setup to ↑ IOW
10
ns
tIOW6
SD Hold After ↑ IOW
10
ns
tIOW7
↓ IOCHRDY Delay from
↓ IOW
0
tIOW8
IOCHRDY Inactive
tIOW9
↑IOCHRDY to ↑ IOW
35
ns
125
ns
0
ns
Input/Output Read Timing
tIOR1
AEN, SBHE, SA0–9 Setup to
↓ IOR
15
ns
tIOR2
AEN, SBHE,SA0–9 Hold After
↑ IOR
5
ns
tIOR3
IOR Inactive
55
ns
tIOR4
SD Hold from ↑ IOR
0
20
ns
tIOR5
SD Valid from ↓ IOR
0
110
ns
tIOR6
↓ IOCHRDY Delay from ↓ IOR
0
35
ns
tIOR7
IOCHRDY Inactive
125
tIOR8
SD Valid from ↑ IOCHRDY
–130
ns
10
ns
Memory Write Timing
tMW1
SA0–15, SBHE, ↓ SMAM Setup to
↓ MEMW
10
ns
tMW2
SA0–15, SBHE, ↑ SMAM Hold
from ↑ MEMW
5
ns
tMW3
MEMW Assertion
150
ns
tMW4
MEMW Inactive
55
ns
tMW5
SD Setup to ↑ MEMW
10
ns
tMW6
SD Hold from ↑ MEMW
10
ns
tMW7
↓ IOCHRDY Delay from ↓ MEMW
0
tMW8
IOCHRDY Inactive
tMW9
↑ MEMW to ↑ IOCHRDY
Am79C961A
35
ns
125
ns
0
ns
141
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Memory Read Timing
tMR1
SA0–15, SBHE, ↓ SMAM/BPAM
Setup to ↓ MEMR
10
ns
tMR2
SA0–15, SBHE, ↑ SMAM/BPAM
Hold from ↑ MEMR
5
ns
tMR3
MEMR Inactive
55
ns
tMR4
SD Hold from ↑ MEMR
0
20
ns
tMR5
SD Valid from ↓ MEMR
0
110
ns
tMR6
↓ IOCHRDY Delay from ↓ MEMR
0
35
ns
tMR7
IOCHRDY Inactive
125
tMR8
SD Valid from ↑ IOCHRDY
–130
ns
10
ns
I/O to Memory Command Inactive
tIOM1
↓ IOW/MEMW to ↓ (S)MEMR/IOR
55
ns
tIOM2
↓ (S)MEMR/IOR to ↓ IOW/MEMW
55
ns
tIOCS1
AEN, SBHE, SA0–9 to ↓ IOCS16
0
35
ns
tIOCS2
AEN, SBHE, SA0–9 to IOCS16
Tristated
0
25
ns
105
ns
IOCS16 Timing
SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus
142
tPR4
PRAB Change to PRAB Change,
SRAM Access
95
tPR5
PRDB Setup to PRAB Change,
SRAM Access
20
ns
tPR6
PRDB Hold from PRAB Change,
SRAM Access
0
ns
tPR7
PRAB Change to PRAB Change,
APROM Access
145
Am79C961A
155
ns
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus (continued)
tPR8
PRDB Setup to PRAB Change,
APROM Access
20
ns
tPR9
PRDB Hold After PRAB Change,
APROM Access
0
ns
tPR10
PRAB Change to PRAB Change,
BPROM Access
290
tPR11
PRDB Setup to PRAB Change,
BPROM Access
20
ns
tPR12
PRDB Hold After PRAB Change,
BPROM Access
0
ns
tPR13
PRAB Change to PRAB Change,
SRAM Write
145
155
ns
tPR14
PRAB Change to ↓ SRWE
20
30
ns
tPR15
PRAB Change to ↑ SRWE
120
130
ns
tPR16
PRAB Change to PRAB Change,
Flash Access
190
205
ns
tPR17
PRAB Change to PRAB Change,
Flash Write
190
205
ns
tPR18
PRAB Change to ↑ SRWE
170
180
ns
Am79C961A
305
ns
143
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tMFR1
BPAM, REF, SBHE, SA0–19 Setup
to ↓ MEMR
10
ns
tMFR2
BPAM, REF, SBHE, SA0–19 Hold
from ↑ MEMR
5
ns
tMFR3
↓ IOCHRDY to ↓ MEMR
0
tMFR4
MEMR Inactive
55
tMFR5
↓ MEMR to ↓ BPCS/SROE
125
260
ns
tMFR6
BPCS/SROE Active
190
205
ns
tMFR7
↑ BPCS/SROE to ↑ IOCHRDY
45
65
ns
tMFR8
PRDB Setup to ↑ of BPCS/SROE
20
ns
tMFR9
PRDB Hold to ↑ of BPCS/SROE
0
ns
tMFR10
SD Valid from ↑ IOCHRDY
0
10
ns
tMFR11
SD Tristate to ↑ MEMR
0
20
ns
35
ns
ns
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH WRITE CYCLE
Parameter
Symbol
144
Parameter Description
Test Conditions
Min
Max
Unit
tMFW1
BPAM, SBHE, SA0–19 Setup to
↓ MEMW
10
ns
tMFW2
BPAM, SBHE, SA0–19 Hold After
↑ MEMW
5
ns
tMFW3
↓ IOCHRDY to ↓ MEMW
0
tMFW4
MEMW Inactive
50
tMFW5
↑ SRWE to ↑ IOCHRDY
20
tMFW6
↑ MEMW Hold from
↑ IOCHRDY
0
tMFW7
SD Valid from ↓ MEMW
tMFW8
SD Hold from ↑ MEMW
tMFW9
BPCS/PRDB Valid from
↓ MEMW
tMFW10
BPCS/PRDB Setup to
↓ SRWE
15
tMFW11
SRWE Active
140
tMFW12
BPCS/PRDB Hold from
↑ SRWE
15
35
ns
90
ns
ns
175
0
ns
ns
175
Am79C961A
ns
ns
ns
155
ns
ns
SWITCHING CHARACTERISTICS: EADI (Unless otherwise noted, parametric values are
the same between Commercial devices and Industrial devices)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tEAD1
SRD Setup to ↑ SRDCLK
40
ns
tEAD2
SRD Hold to ↑ SRDCLK
40
ns
tEAD3
SF/BD Change to ↓ SRDCLK
–15
tEAD4
EAR Deassertion to ↑ SRDCLK
(First Rising Edge)
50
tEAD5
EAR Assertion from SFD Event
(Packet Rejection)
0
tEAD6
EAR Assertion
+15
ns
ns
51,090
110
ns
ns
Note:
External Address Detection interface is invoked by setting bit 3 in ISACSR2 and resetting bit 0 in ISACSR2. External MAU select
is not available when EADISEL bit is set.
SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE (Unless otherwise
noted, parametric values are the same between Commercial devices and Industrial
devices)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tJTG1
TCK HIGH Assertion
20
ns
tJTG2
TCK Period
100
ns
tJTG3
TDI Setup to ↑ TCK
5
ns
tJTG4
TDI, TMS Hold from ↑ TCK
5
ns
tJTG5
TMS Setup to ↑ TCK
8
ns
tJTG6
TDO Active from ↓ TCK
0
30
ns
tJTG7
TDO Change from ↓ TCK
0
30
ns
tJTG8
TDO Tristate from ↓ TCK
0
25
ns
Note:
JTAG logic is reset with an internal Power-On Reset circuit independent of Sleep Modes.
Am79C961A
145
SWITCHING CHARACTERISTICS: GPSI (Unless otherwise noted, parametric values are
the same between Commercial devices and Industrial devices)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
99.99
100.01
ns
Transmit Timing
tGPT1
STDCLK Period (802.3 Compliant)
tGPT2
STDCLK HIGH Time
40
60
ns
tGPT3
TXDAT and TXEN Delay from ↑ TCLK
0
70
ns
tGPT4
RXCRS Setup to ↑ STDCLK (Last Bit)
210
ns
tGPT5
RXCRS Hold from ↓ TENA
0
ns
tGPT6
CLSN Active Time to Trigger Collision
110
ns
tGPT7
CLSN Active to ↓ RXCRS to Prevent
LCAR Assertion
0
ns
tGPT8
CLSN Active to ↓ RXCRS for SQE
Hearbeat Window
0
4.0
µs
tGPT9
CLSN Active to ↑ RXCRS for Normal Collision
0
51.2
µs
(Note 1)
Receive Timing
tGPR1
SRDCLK Period
(Note 2)
80
120
ns
tGPR2
SRDCLK High Time
(Note 2)
30
80
ns
tGPR3
SRDCLK Low Time
(Note 2)
30
80
ns
tGPR4
RXDAT and RXCRS Setup to
↑ SRDCLK
15
ns
tGPR5
RXDAT Hold from ↑ RCLK
15
ns
tGPR6
RXCRS Hold from ↓ SRDCLK
0
ns
tGPR7
CLSN Active to First ↑ SRDCLK
(Collision Recognition)
0
ns
tGPR8
CLSN Active to ↑ SRDCLK for Address Type
Designation Bit
51.2
µs
tGPR9
CLSN Setup to last ↑ SRDCLK for
Collision Recognition
210
ns
tGPR10
CLSN Active
110
ns
tGPR11
CLSN Inactive Setup to First ↑ RCLK
300
ns
tGPR12
CLSN Inactive Hold to Last ↑ RCLK
300
ns
(Note 3)
Notes:
1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may
not result in CLSN recognition.
2. RCLK should meet jitter requirements of IEEE 802.3 specification.
3. CLSN assertion before 51.2 µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be
considered as a Late Receive Collision.
146
Am79C961A
SWITCHING CHARACTERISTICS: AUI (Unless otherwise noted, parametric values are the
same between Commercial devices and Industrial devices)
Parameter
Symbol
Test Conditions
Parameter Description
Min
Max
Unit
AUI Port
tDOTR
DO+,DO- Rise Time (10% to 90%)
2.5
5.0
ns
tDOTF
DO+,DO- Fall Time (90% to 10%)
2.5
5.0
ns
tDORM
DO+,DO- Rise and fall Time Mismatch
1.0
ns
tDOETD
DO+/- End of Transmission
200
375
ns
tPWODI
DI Pulse Width Accept/Reject Threshold
|VIN| > |VASQ| (Note 1)
15
45
ns
tPWKDI
DI Pulse Width Maintain/Turn-Off
Threshold
|VIN| > |VASQ| (Note 2)
136
200
ns
tPWOCI
CI Pulse Width Accept/Reject Threshold
|VIN| > |VASQ| (Note 3)
10
26
ns
tPWKCI
CI Pulse Width Maintain/Turn-Off
Threshold
|VIN| > |VASQ| (Note 4)
90
160
ns
50.005
ns
Internal MENDEC Clock Timing
tX1
XTAL1 Period
VIN = External Clock
49.995
tX1H
XTAL1 HIGH Pulse Width
VIN = External Clock
20
ns
tX1L
XTAL1 LOW Pulse width
VIN = External Clock
20
ns
tX1R
XTAL1 Rise Time
VIN = External Clock
5
ns
tX1F
XTAL1 Fall Time
VIN = External Clock
5
ns
Notes:
1. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.
2. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn
internal DI carrier sense off.
3. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.
4. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn
internal CI carrier sense off.
Am79C961A
147
SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE (Unless otherwise noted,
parametric values are the same between Commercial devices and Industrial devices)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
250
350
ns
Transmit Timing
tTETD
Transmit Start of Idle
tTR
Transmitter Rise Time
(10% to 90%)
5.5
ns
tTF
Transmitter Fall Time
(90% to 10%)
5.5
ns
tTM
Transmitter Rise and Fall Time
Mismatch
2
ns
8
24
ms
tPERLP
Idle Signal Period
tPWLP
Idle Link Pulse Width
(Note 1)
75
120
ns
tPWPLP
Predistortion Idle Link Pulse
Width
(Note 1)
45
55
ns
tJA
Transmit Jabber Activation
Time
20
150
ms
tJR
Transmit Jabber Reset Time
250
750
ms
Receive Timing
tPWNRD
RXD Pulse Width Not to Turn
Off Internal Carrier Sense
VIN > VTHS (min)
tPWROFF
RXD Pulse Width to Turn Off
VIN > VTHS (min)
136
ns
200
ns
Note:
1. Not tested; parameter guaranteed by characterization.
SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERFACE (Unless otherwise noted,
parametric values are the same between Commercial devices and Industrial devices)
Parameter
Symbol
148
Parameter Description
Test Conditions
Min
Max
Unit
tSR1
EESK High Time
790
ns
tSR2
EESK Low Time
790
ns
tSR3
↑ EECS EEDI from ↓ EESK
– 15
15
ns
tSR4
↓ EECS, EEDI and SHFBUSY
from ↓ EESK
– 15
15
ns
tSR5
EECS Low Time
1590
ns
tSR6
EEDO Setup to ↑ EESK
35
ns
tSR7
EEDO Hold from ↑ EESK
0
ns
tSL1
EEDO Setup to ↓ IOR
95
ns
tSL2
EEDO Setup to ↑ IOCHRDY
140
ns
tSL3
EESK, EEDI, EECS and
SHFBUSY Delay from↑ IOW
160
Am79C961A
235
ns
SWITCHING TEST CIRCUITS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010
Am79C961A
149
SWITCHING TEST CIRCUITS
IOL
Sense Point
VTHRESHOLD
CL
IOH
19364B-32
Normal and Three-State Outputs
AVDD
52.3 Ω
DO+
DO–
Test Point
100 pF
154 Ω
AVSS
AUI DO Switching Test Circuit
150
Am79C961A
19364B-33
SWITCHING TEST CIRCUITS
DVDD
294 Ω
TXD+
TXD–
Test Point
294 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
19364B-34
TXD Switching Test Circuit
DVDD
715 Ω
TXP+
TXP–
Test Point
715 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
19364B-35
TXD Outputs Test Circuit
Am79C961A
151
SWITCHING WAVEFORMS: BUS MASTER MODE
AEN, SBHE,
SA0–9
Stable
tIOW1
tIOW2
tIOW3
IOW
tIOW4
tIOW5
tIOW6
SD
19364B-36
I/O Write without Wait States
AEN, SBHE,
SA0–9
Stable
tIOW2
tIOW1
IOW
tIOW7
tIOW8
tIOW9
tIOW4
IOCHRDY
tIOW5
tIOW6
SD
19364B-37
I/O Write with Wait States
152
Am79C961A
SWITCHING WAVEFORMS: BUS MASTER MODE
EESK
(PRDB0)
EECS
EEDI
(PRDB1)
0
1
1
0
A7
A6
A5
A4
A3
A2
A1
A0
EEDO
(PRDB2)
D0
D1
D2
D14 D15
Falling transition at 26th Word, if checksum is 0xFF.
SHFBUSY
19364B-38
Serial Shift EEPROM Interface Read Timing
tSR1
EESK
(PRDB0)
tSR2
tSR3
tSR4
tSR5
EECS
EEDI
(PRDB1)
SHFBSY
EED0
(PRDB2)
Stable
tSR6
tSR7
19364B-39
Serial EEPROM Control Timing
Am79C961A
153
SWITCHING WAVEFORMS: BUS MASTER MODE
EED0
(PRDB2)
tSL1
IOR
tSL2
IOCHRDY
IOW
tSL3
EESK, EEDI,
EECS,
SHFBUSY
19364B-40
Slave Serial EEPROM Latency Timing
AEN, SBHE,
SA0–9
Stable
tIOR1
tIOR2
IOR
tIOR3
tIOR4
tIOR5
Stable
SD
19364B-41
I/O Read without Wait States
154
Am79C961A
SWITCHING WAVEFORMS: BUS MASTER MODE
AEN, SBHE,
SA0–9
Stable
tIOR1
tIOR2
IOR
tIOR6
tIOR3
tIOR7
IOCHRDY
tIOR8
tIOR4
Stable
SD
19364B-42
I/O Read with Wait States
IOW, MEMW
tIOM1
tIOM2
MEMR, IOR
I/O to Memory Command Inactive Time
Am79C961A
19364B-43
155
SWITCHING WAVEFORMS: BUS MASTER MODE
AEN, SBHE,
SA0–9
tIOCS
tIOCS2
IOCS16
19364B-44
IOCS16 Timings
REF
tMMA1
DRQ
tMMA2
DACK
tMMA3
MASTER
tMMA4
MEMR/MEMW
tMMA5
SBHE,
SA0–19,
LA17–23
Bus Acquisition
156
Am79C961A
19364B-45
SWITCHING WAVEFORMS: BUS MASTER MODE
DRQ
tMMBR1
tMMBR2
DACK
tMMBR3
MASTER
MEMR/MEMW
tMMBR4
SBHE, SA0–19,
LA17–23
19364B-46
Bus Release
(Non Wait)
(Wait States Added)
tMMW5
tMMW6
SBHE, SA0–19,
LA17–23
tMMW1
tMMW2
tMMW4
tMMW3
MEMW
tMMW7
IOCHRDY
tMMW8
tMMW9
tMMW11
tMMW10
SD0–15
Write Cycles
Am79C961A
19364B-47
157
SWITCHING WAVEFORMS: BUS MASTER MODE
(Non Wait)
SBHE, SA0–19,
LA17–23
tMMR6
tMMR5
(Wait States Added)
Stable
Stable
tMMR1
tMMR4
tMMR3
tMMR2
MEMR
tMMR7
tMMR8
tMMR9
IOCHRDY
tMMR11
tMMR10
tMMR10
Stable
SD0–15
tMMR11
Stable
19364B-48
Read Cycles
AEN, SBHE,
SA0–9
Stable
tIOR2
tIOR1
IOR
tIOR3
tIOR6
tMA5
IOCHRDY
APCS
(IRQ15)
tMA1
tMA2
tMA3
tMA4
PRDB0–7
tMA6
SD0–7
Stable
External Address PROM Read Cycle
158
tIOR4
Am79C961A
19364B-49
SWITCHING WAVEFORMS: BUS MASTER MODE
BALE
tMB12
Stable
LA20–23
tMB13
REF, SBHE,
SA0–19
Stable
tMB1
tMB2
MEMR
tMB14
tMB3
tMB4
tMB7
IOCHRDY
tMB5
BPCS
tMB6
tMB8
tMB9
PRDB0–7
tMB11
tMB10
SD0–7
Stable
Boot PROM Read Cycle
Am79C961A
19634B-50
159
SWITCHING WAVEFORMS: BUS MASTER MODE
BALE
tMFR12
Stable
LA20–23
tMFR13
REF, SBHE,
SA0–19
Stable
tMFR2
tMFR1
MEMR
tMFR14
tMFR3
tMFR7
tMFR4
IOCHRDY
tMFR5
BPCS
tMFR6
tMFR8
tMFR9
PRDB0–7
tMFR11
tMFR10
SD0–7
Stable
Flash Read Cycle
160
Am79C961A
19364B-51
SWITCHING WAVEFORMS: BUS MASTER MODE
BALE
tMFW13
Stable
LA20–23
tMFW14
SBHE,
SA0–19
Stable
tMFW1
tMFW2
MEMW
tMFW15
tMFW6
tMFW3
tMFR4
tMFW5
IOCHRDY
tMFW7
tMFW8
SD0-7
Stable
tMFW10
tMFW11
FL_WE (IRQ12)
tMFW9
tMFW12
Stable
PRDB0-7
Flash Write Cycle
Am79C961A
19364B-52
161
SWITCHING WAVEFORMS: SHARED MEMORY MODE
AEN, SBHE,
SA0–9
Stable
tIOW
tIOW1
tIOW
IOW
tIOW5
tIOW6
tIOW4
SD
19364B-53
I/O Write without Wait States
AEN, SBHE,
SA0–9
Stable
tIOW2
tIOW1
IOW
tIOW
tIOW8
tIOW4
tIOW9
IOCHRDY
tIOW5
tIOW
SD
19664B-54
I/O Write with Wait States
162
Am79C961A
SWITCHING WAVEFORMS: SHARED MEMORY MODE
AEN, SBHE,
SA0–9
Stable
tIOR1
tIOR2
IOR
tIOR4
tIOR5
SD
tIOR3
Stable
19364B-55
I/O Write without Wait States
AEN, SBHE,
SA0–9
Stable
tIOR2
tIOR1
IOR
tIOR6
tIOR3
tIOR7
IOCHRDY
tIOR8
SD
tIOR4
Stabl
I/O Read with Wait States
Am79C961A
19364B-56
163
SWITCHING WAVEFORMS: SHARED MEMORY MODE
SA0–15,
SBHE
Stable
SMAM
tMW1
tMW2
tMW3
MEMW
tMW4
tMW5
tMW6
SD
19364B-57
Memory Write without Wait States
SA0–15,
SBHE
Stable
SMAM
tMW2
tMW1
MEMW
tMW4
tMW7
IOCHRDY
tMW8
tMW9
tMW5
tMW6
SD
Memory Write with Wait States
164
Am79C961A
19364B-58
SWITCHING WAVEFORMS: SHARED MEMORY MODE
SA0–15,
SBHE
Stable
SMAM
tMR1
tMR2
MEMR
tMR4
tMR5
SD
tMR3
Stable
19364B-59
Memory Read without Wait States
SA0–15,
SBHE
Stable
SMAM/BPAM
tMR1
tMR2
MEMR
tMR6
tMR3
tMR7
IOCHRDY
tMR4
tMR8
SD
Stable
Memory Write with Wait States
Am79C961A
19364B-60
165
SWITCHING WAVEFORMS: SHARED MEMORY MODE
IOW, MEMW
tIOM1
tIOM2
MEMR, IOR
19364B-61
I/O to Memory Command Inactive Time
AEN, SBHE,
SA0–9
tIOCS2
tIOCS1
IOCS16
IOCS16 Timings
166
Am79C961A
19364B-62
SWITCHING WAVEFORMS: SHARED MEMORY MODE
SBHE,
SA0–15,
BPAM
Stable
tSFW1
tSFW2
MEMW
tSFW6
tSFW3
tSFR4
tSFW5
IOCHRDY
tSFW7
tSFW8
SD0-7
Stable
tSFW10
tSFW11
SRWE
BPCS
tSFW12
tSFW9
Stable
PRDB0-7
Flash Write Cycle
Am79C961A
19364B-63
167
SWITCHING WAVEFORMS: SHARED MEMORY MODE
REF,
SBHE
SA0-15
Stable
tSFR1
tSFR2
MEMR
tSFR3
tSFR4
IOCHRDY
SROE
tSFR7
tSFR5
tSFR6
BPCS
tSFR8
tSFR9
PRDB0–7
tSFR11
tSFR10
SD0–7
Stable
Flash Read Cycle
168
Am79C961A
19364B-64
SWITCHING WAVEFORMS: SHARED MEMORY MODE
tPR13
tPR13
PRAB
tPR14
tPR14
tPR15
tPR15
SRWE
PRDB
SRCS
(IRQ12)
SRAM Write on Private Bus (When FL_Sel is Enabled)
tPR4
19364B-65
tPR4
PRAB
SROE
tPR5
tPR6
tPR5
tPR6
PRDB
SRCS
(IRQ12)
SRAM Read on Private Bus (When FL_Sel is Enabled)
Am79C961A
19364B-66
169
SWITCHING WAVEFORMS: SHARED MEMORY MODE
tPR10
tPR10
PRAB
BPCS
tPR11
tPR11
tPR12
tPR12
PRDB
19364B-67
Boot PROM Read on Private Bus
tPR7
PRAB0–9
APCS
(IRQ15)
tPR8
tPR9
PRDB
Address PROM Read on Private Bus
170
Am79C961A
19364B-68
SWITCHING WAVEFORMS: SHARED MEMORY MODE
tPR17
tPR17
PRAB0
tPR14
tPR14
tPR18
tPR18
SRWE
PRDB
FLCS
19364B-69
Flash Write on Private Bus
tPR16
tPR16
PRAB0
FLOE
FLCS
tPR11
tPR12
tPR11
tPR12
PRDB
Flash Read on Private Bus
Am79C961A
19364B-70
171
SWITCHING WAVEFORMS: GPSI
(Last Bit)
(First Bit Preamble)
tGPT1
tGPT2
Transmit
Clock
(STDCLK)
tGPT3
Transmit
Data
(TXDAT)
tGPT3
tGPT3
Transmit
Enable
(TXEN)
tGPT4
Carrier
Present
(RXCRS)
(Note 1)
tGPT5
tGPT9
tGPT6
Collision
(CLSN)
(Note 2)
tGPT7
tGPT8
Transmit Timing
19364B-71
Notes:
1. RXCRS is not present during transmission, LCAR bit in TMD3 will be set.
2. CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.
(First Bit Preamble)
(Address Type Designation Bit) (Last Bit)
tGPR1
Receive
Clock
(SRDCLK)
Receive
Data
(RXDAT)
tGPR4
tGPR2
tGPR3
tGPR5
tGPR5
tGPR4
tGPR6
Carrier
Present
(RXCRS)
tGPR8
tGPR10
tGPR7
Collision
(CLSN),
Active
Collision
(CLSN),
Inactive
tGPR12
tGPR11
(No Collision)
Receive Timing
172
tGPR9
Am79C961A
19364B-72
SWITCHING WAVEFORMS: EADI
Preamble
Data Field
SRDCLK (LED3)
One Zero One
SRD (LED2)
tEAD1
SF/BD (LED1)
SFD Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
Bit 8 Bit 0
Bit 7 Bit 8
tEAD2
tEAD4
tEAD3
tEAD3
Accept
EAR (MAUSEL)
tEAD5
Reject
tEAD6
EADI Reject Timing
19364B-73
SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE
tJTG1
TCK
tJTG3
tJTG4
tJTG2
TDI
tJTG5
TMS
tJTG6
tJTG7
tJTG8
TDO
Test Access Port Timing
Am79C961A
19364B-74
173
SWITCHING WAVEFORMS: AUI
tX1H
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
tX1L
tX1F
tX1R
tXI
1
1
ITXDAT+
(Note 1)
1
1
0
0
tDOTR
tDOTF
DO+
DO–
DO±
1
19364B-75
Transmit Timing—Start of Packet
Note:
1. Internal signal and is shown for clarification only.
174
Am79C961A
SWITCHING WAVEFORMS: AUI
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
ITXDAT+
(Note 1)
0
0
DO+
DO–
DO±
1
0
tDOETD
0
Typical > 200 ns
Bit (n–2)
Bit (n–1)
Bit (n)
19364B-76
Transmit Timing—End of Packet (Last Bit = 0)
Note:
1. Internal signal and is shown for clarification only.
Am79C961A
175
SWITCHING WAVEFORMS: AUI
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
1
ITXDAT+
(Note 1)
0
DO+
DO–
DO±
tDOETD
1
Bit (n–2)
0
Typical > 250 ns
Bit (n–1) Bit (n)
Transmit Timing—End of Packet (Last Bit = 1)
Note:
1. Internal signal and is shown for clarification only.
176
Am79C961A
19364B-77
SWITCHING WAVEFORMS: AUI
tPWKDI
DI+/–
VASQ
tPWKDI
tPWODI
Receive Timing Diagram
19364B-78
tPWKCI
CI+/–
VASQ
tPWOCI
tPWKCI
Collision Timing Diagram
19364B-79
tDOETD
DO+/–
40 mV
0V
100 mV max.
80 Bit Times
Port DO ETD Waveform
Am79C961A
19364B-80
177
SWITCHING WAVEFORMS: 10BASE-T INTERFACE
tTR
tTF
tTETD
TXD+
TXP+
TXD–
TXP–
XMT
(Note 1)
Transmit Timing
19364B-81
Note:
1. Internal signal and is shown for clarification only.
tPWPLP
TXD+
TXP+
TXD–
TXP–
tPWLP
tPERLP
Idle Link Test Pulse
178
Am79C961A
19364B-82
SWITCHING WAVEFORMS: 10BASE-T INTERFACE
VTSQ+
VTHS+
RXD±
VTHS–
VTSQ–
Receive Thresholds (LRT = 0 in CSR15 bit 9)
19364B-83
VLTSQ+
VLTHS+
RXD±
VLTHS–
VLTSQ–
Receive Thresholds (LRT = 1 in CSR15 bit 9)
Am79C961A
19364B-84
179
PHYSICAL DIMENSIONS*
PQB132
Plastic Quad Flat Pack Trimmed and Formed (measured in inches)
1.075
1.085
Pin 132
1.097
1.103
0.947
0.953
Pin 99
Pin 1 I.D.
0.947
0.953
1.075
1.085
1.097
1.103
Pin 33
Pin 66
0.008
0.012
TOP VIEW
0.025 BASIC
0.130
0.150
0.160
0.180
SEATING
PLANE
0.80 REF
BOTTOM VIEW
180
Am79C961A
0.020
0.040
16-038-PQB
PQB132
DB87
7-26-94 ae
PHYSICAL DIMENSIONS*
PQB132
Molded Carrier Ring Plastic Quad Flat Pack
(measured in inches, Ring measured in millimeters)
45.87
45.50 46.13
41.37 45.90
37.87 41.63
35.15 38.13
35.25
32.15
1.097 32.25
1.103
.944
.952
Pin 66
Z1
1.50 DIA.
Z2
1.50 DIA.
Pin 33
45.87
46.13
45.50
45.90
32.15
32.25
41.37
41.63
37.87
38.13
1.097
1.103
.944
.952
Pin 99
35.15
35.25
Pin 1
1.50 DIA.
.750
NOM.
256 NOM.
Pin 132
2.00
1.80
4.80
SIDE VIEW
Am79C961A
181
182
Am79C961A
APPENDIX A
PCnet-ISA II Compatible Media
Interface Modules
PCnet-ISA II COMPATIBLE 10BASE-T
FILTERS AND TRANSFORMERS
The table below provides a sample list of PCnet-ISA II
compatible 10BASE-T filter and transformer modules
Manufacturer
Part No.
available from various vendors. Contact the respective
manufacturer for a complete and updated listing of
components.
Filters
Filters
Filters
Filters and
Transformers Transformers Transformers
Transformers
and Choke
Dual Choke
Dual Chokes
Package
Bel Fuse
A556-2006-DE 16-pin 0.3" DIL
√
Bel Fuse
0556-2006-00
14-pin SIP
√
Bel Fuse
0556-2006-01
14-pin SIP
√
Bel Fuse
0556-6392-00
16-pin 0.5" DIL
√
Halo Electronics
FD02-101G
16-pin 0.3" DIL
Halo Electronics
FD12-101G
16-pin 0.3" DIL
Halo Electronics
FD22-101G
16-pin 0.3" DIL
PCA Electronics
EPA1990A
16-pin 0.3" DIL
PCA Electronics
EPA2013D
16-pin 0.3" DIL
PCA Electronics
EPA2162
16-pin 0.3" SIP
√
√
√
√
√
√
√
Pulse Engineering
PE-65421
16-pin 0.3" DIL
Pulse Engineering
PE-65434
16-pin 0.3" SIL
√
Pulse Engineering
PE-65445
16-pin 0.3" DIL
√
Pulse Engineering
PE-65467
12-pin 0.5" SMT
Valor Electronics
PT3877
16-pin 0.3" DIL
Valor Electronics
FL1043
16-pin 0.3" DIL
PCnet-ISA II Compatible AUI Isolation
Transformers
√
√
√
various vendors. Contact the respective manufacturer
for a complete and updated listing of components.
The table below provides a sample list of PCnet-ISA II
compatible AUI isolation transformers available from
Manufacturer
Part No.
Package
Bel Fuse
A553-0506-AB
16-pin 0.3" DIL
50 µH
Bel Fuse
S553-0756-AE
16-pin 0.3" SMD
75 µH
Halo Electronics
TD01-0756K
16-pin 0.3" DIL
75 µH
Halo Electronics
TG01-0756W
16-pin 0.3" SMD
75 µH
PCA Electronics
EP9531-4
16-pin 0.3" DIL
50 µH
Pulse Engineering
PE64106
16-pin 0.3" DIL
50 µH
Pulse Engineering
PE65723
16-pin 0.3" SMT
75 µH
Valor Electronics
LT6032
16-pin 0.3" DIL
75 µH
Valor Electronics
ST7032
16-pin 0.3" SMD
75 µH
Am79C961A
Description
183
PCnet-ISA II Compatible DC/DC
Converters
vendors. Contact the respective manufacturer for a
complete and updated listing of components.
The table below provides a sample list of PCnet-ISA II
compatible DC/DC converters available from various
Manufacturer
Part No.
Package
Voltage
Remote On/Off
Halo Electronics
DCU0-0509D
24-pin DIP
5/-9
No
Halo Electronics
DCU0-0509E
24-pin DIP
5/-9
Yes
PCA Electronics
EPC1007P
24-pin DIP
5/-9
No
PCA Electronics
EPC1054P
24-pin DIP
5/-9
Yes
PCA Electronics
EPC1078
24-pin DIP
5/-9
Yes
Valor Electronics
PM7202
24-pin DIP
5/-9
No
Valor Electronics
PM7222
24-pin DIP
5/-9
Yes
MANUFACTURER CONTACT
INFORMATION
Contact the following companies for further information
on their products:
Company
U.S. and Domestic
Asia
Europe
33-1-69410402
33-1-69413320
Bel Fuse
Phone:
FAX:
(201) 432-0463
(201) 432-9542
852-328-5515
852-352-3706
Halo Electronics
Phone:
FAX:
(415) 969-7313
(415) 367-7158
65-285-1566
65-284-9466
PCA Electronics
(HPC in Hong Kong)
Phone:
FAX:
818-892-0761
818-894-5791
852-553-0165
852-873-1550
33-1-44894800
33-1-42051579
Pulse Engineering
Phone:
FAX:
(619) 674-8100
(619) 675-8262
852-425-1651
852-480-5974
353-093-24107
353-093-24459
Valor Electronics
Phone:
FAX:
(619) 537-2500
(619) 537-2525
852-513-8210
852-513-8214
49-89-6923122
49-89-6926542
184
Am79C961A
APPENDIX B
Layout Recommendations
for Reducing Noise
DECOUPLING LOW-PASS R/C
FILTER DESIGN
via to VDD
The PCnet-ISA II controller is an integrated, single-chip
Ethernet controller, which contains both digital and
analog circuitry. The analog circuitry contains a high
speed Phase-Locked Loop (PLL) and Voltage Controlled Oscillator (VCO). Because of the mixed signal
characteristics of this chip, some extra precautions must
be taken into account when designing with this device.
Described in this section is a simple decoupling
low-pass R/C filter that can significantly increase noise
immunity of the PLL circuit, thus, prevent noise from
disrupting the VCO. Bit error rate, a common measurement of network performance, as a result can be drastically reduced. In certain cases the bit error rate can be
reduced by orders of magnitude.
Implementation of this filter is not necessary to achieve
a functional product that meets the IEEE 802.3 specification and provides adequate performance. However,
this filter will help designers meet those specifications
with more margin.
Digital Decoupling
The DVSS pins that are sinking the most current are
those that provide the ground for the ISA bus output
signals since these outputs require 24 mA drivers.
The DVSS10 and DVSS12 pins provide the ground
for the internal digital logic. In addition, DVSS11
provides ground for the internal digital and for the
Input and I/O pins.
The CMOS technology used in fabricating the PCnet-ISA II controller employs an n-type substrate. In this
technology, all VDD pins are electrically connected to
each other internally. Hence, in a four-layer board, when
decoupling between VDD and critical VSS pins, the specific VDD pin that you connect to is not critical. In fact, the
VDD connection of the decoupling capacitor can be
made directly to the power plane, near the closest VDD
pin to the VSS pin of interest. However, we recommend
that the VSS connection of the decoupling capacitor be
made directly to the VSS pin of interest as shown.
VDD Pin
VSS Pin
via to VSS plane
PCnet-ISA II
19364B-85
AMD recommends that at least one low-frequency
bulk decoupling capacitor be used in the area of the
PCnet-ISA II controller. 22 µF capacitors have worked
well for this. In addition, a total of four or five 0.1 µF
capacitors have proven sufficient around the DVSS
and DVDD pins that supply the drivers of the ISA bus
output pins.
Analog Decoupling
The most critical pins are the analog supply and ground
pins. All of the analog supply and ground pins are located
in one corner of the device. Specific requirements of the
analog supply pins are listed below.
AVSS1 and AVDD3
These pins provide the power and ground for the
Twisted Pair and AUI drivers. Hence, they are very
noisy. A dedicated 0.1 µF capacitor between these pins
is recommended.
AVSS2 and AVDD2
These pins are the most critical pins on the PCnet-ISA
II controller because they provide the power and
ground for the PLL portion of the chip. The VCO portion
of the PLL is sensitive to noise in the 60 kHz-200 kHz
range. To prevent noise in this frequency range from
disrupting the VCO, AMD strongly recommends that
the low-pass filter shown below be implemented on
these pins. Tests using this filter have shown significantly increased noise immunity and reduced Bit Error
Rate (BER) statistics in designs using the PCnet-ISA II
controller.
Am79C961A
185
VDD Plane
AVDD2
Pin 108
AVSS2
Pin 98
voltage drop across the resistor, the R value should not
be more than 20 Ω.
33 µF to 6.8 µF
R1
1 Ω to 20 Ω
PCnet-ISA II
19364B-86
To determine the value for the resistor and capacitor,
the formula is:
R * C ≥ 88
C
2.7 Ω
33 µF
4.3 Ω
22 µF
6.8 Ω
15 µF
10 Ω
10 µF
20 Ω
6.8 µF
AVSS2 and AVDD2/AVDD4
These pins provide power and ground for the AUI and
twisted pair receive circuitry. No specific decoupling
has been necessary on these pins.
Where R is in ohms and C is in microfarads. Some possible combinations are given below. To minimize the
186
R
Am79C961A
APPENDIX C
Sample Plug and Play Configuration Record
SAMPLE CONFIGURATION FILE
The following is a sample configuration record for the
PCnet-ISA II device used in an AMD Ethernet card.
This card requires one DMA channel, one interrupt,
one I/O port in the 0x200-0x3FF range (0x20 bytes
aligned). The vendor ID of AMD is ADV. The vendor
assigned part number for this card is 2100 and the serial number is 0x12345678. The card has only one log-
ical device, that is an ethernet controller. There are no
compatible devices with this logical device. The following record should be returned by the card during the
identification process.
Note:
All data stored in the EEPROM is stored in bit-reversal format. Each word (16 bits) must be written into the EEPROM
with bit 15 swapped with bit 0, bit 14 swapped with bit 1, etc.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Plug and Play Header
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x04
; Vendor EISA ID Byte 0
DB 0x96
; Vendor EISA ID Byte 1
DB 0x00
; Vendor Assigned ID Byte 0
DB 0x21
; Vendor Assigned ID Byte 1
DB 0x78
; Serial Number byte 0
DB 0x56
; Serial Number byte 1
DB 0x34
; Serial Number byte 2
DB 0x12
; Serial Number byte 3
DB Checksum
; Checksum calculated on above bits
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Plug and Play Version
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x0A
; Small Item, Plug and Play version
DB 0x10
; BCD major version [7:4] = 1
; BCD minor version [3:0] = 0
DB 0x00
; Vendor specific version number
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Identifier String
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x82
; Large Item, Type Identifier string (ANSI)
DB 0x1C
; Length Byte 0 (28 bytes)
DB 0x00
; Length Byte 1
DB “AMD PCnet-ISA II Ethernet
Network Adapter“
; Identifier String
187
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Logical Device ID
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x15
DB 0x04
DB 0x96
DB 0x55
DB 0xAA
DB 0x02
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Compatible Device ID
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x1C
DB 0x41
DB 0xD0
DB 0x82
DB 0x8C
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; I/O Port Descriptor
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x47
DB 0x00
DB 0x00
DB 0x02
DB 0xE0
DB 0x03
DB 0x20
DB 0x18
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; DMA Descriptor
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x2A
DB 0xE8
DB 0x05
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;IRQ Format
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x23
DB 0x38
DB 0x9E
DB 0x09
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; End Tag
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x79
DB Checksum
188
; Small Item, Type Logical Device ID
; Logical Device ID byte 0
; Logical Device ID byte 1
; Logical Device ID byte 2
; Logical Device ID byte 3
; Logical Device Flags [0] – required for boot
; Small Item, Type Compatible Device ID
; Compatible Device ID byte 0
; Compatible Device ID byte 1
; Compatible Device ID byte 2
; Compatible Device ID byte 3
; Small Item, type I/O Port
; Information, [0] = 0, 10 bit Decode
; Minimum Base Address [07:00]
; Minimum Base Address [15:08]
; Maximum Base Address [07:00]
; Maximum Base Address [15:08]
; Base Address Increment (32 ports)
; Number of ports required
; Small Item, type DMA Format
; DMA channel mask ch 3, 5, 6, 7
; 16-Bit only, Bus Master
; Small Item, type IRQ Format
; IRQs supported [7:0]
3, 4, 5
; IRQs supported [15:8]
9, 10, 11, 12, 15
; Information: High true, edge
Low true, level
; Small item, type END TAG
; Checksum
APPENDIX D
Alternative Method
for Initialization
The PCnet-ISA II controller may be initialized by
performing I/O writes only. That is, data can be written
directly to the appropriate control and status registers
(CSR) instead of reading from the Initialization Block in
memory. The registers that must be written are shown
in the table below. These are followed by writing the
START bit in CSR0.
Control and Status
Register
Comment
CSR8
LADRF[15:0]
CSR9
LADRF[31:16]
CSR10
LADRF[47:32]
CSR11
LADRF[63:48]
CSR12
PADR[15:0]
CSR13
PADR[31:16]
CSR14
PADR[47:32]
CSR15
Mode
CSR24–25
BADR
CSR30–31
BADX
CSR47
POLLINT
CSR76
RCVRL
CSR78
XMTRL
Note:
The INIT bit must not be set or the initialization block will be
accessed instead.
Am79C961A
189
190
Am79C961A
APPENDIX E
Introduction of the LookAhead Packet Processing (LAPP) Concept
A driver for the PCnet-ISA II controller would normally
require that the CPU copy receive frame data from the
controller’s buffer space to the application’s buffer
space after the entire frame has been received by the
controller. For applications that use a ping-pong
windowing style, the traffic on the network will be
halted until the current frame has been completely
processed by the entire application stack. This means
that the time between last byte of a receive frame
arriving at the client’s Ethernet controller and the
client’s transmission of the first byte of the next
outgoing frame will be separated by:
1. the time that it takes the client’s CPU’s interrupt
procedure to pass software control from the current
task to the driver
2. plus the time that it takes the client driver to pass the
header data to the application and request an
application buffer
3. plus the time that it takes the application to generate
the buffer pointer and then return the buffer pointer
to the driver
4. plus the time that it takes the client driver to transfer
all of the frame data from the controller’s buffer
space into the application’s buffer space and then
call the application again to process the complete
frame
5. plus the time that it takes the application to process
the frame and generate the next outgoing frame
6. plus the time that it takes the client driver to set up
the descriptor for the controller and then write a
TDMD bit to CSR0
The sum of these times can often be about the same
as the time taken to actually transmit the frames on the
wire, thereby yielding a network utilization rate of less
than 50%.
An important thing to note is that the PCnet-ISA II controller’s data transfers to its buffer space are such that
the system bus is needed by the PCnet-ISA II controller
for approximately 4% of the time. This leaves 96% of the
system bus bandwidth for the CPU to perform some of
the inter-frame operations in advance of the completion
of network receive activity, if possible. The question then
becomes: how much of the tasks that need to be performed between reception of a frame and transmission
of the next frame can be performed before the reception
of the frame actually ends at the network, and how can
the CPU be instructed to perform these tasks during the
network reception time?
The answer depends upon exactly what is happening
in the driver and application code, but the steps that
can be performed at the same time as the receive data
are arriving include as much as the first three steps and
part of the fourth step shown in the sequence above.
By performing these steps before the entire frame has
arrived, the frame throughput can be substantially
increased.
A good increase in performance can be expected
when the first three steps are performed before the
end of the network receive operation. A much more
significant performance increase could be realized if
the PCnet-ISA II controller could place the frame
data directly into the application’s buffer space; (i.e.
eliminate the need for step four). In order to make
this work, it is necessary that the application buffer
pointer be determined before the frame has completely arrived, then the buffer pointer in the next
desriptor for the receive frame would need to be
modified in order to direct the PCnet-ISA II controller
to write directly to the application buffer. More details
on this operation will be given later.
An alternative modification to the existing system can
gain a smaller, but still significant improvement in performance. This alternative leaves step four unchanged
in that the CPU is still required to perform the copy
operation, but it allows a large portion of the copy operation to be done before the frame has been completely
received by the controller, (i.e. the CPU can perform
the copy operation of the receive data from the PCnet-ISA II controller’s buffer space into the application
buffer space before the frame data has completely arrived from the network). This allows the copy operation
of step four to be performed concurrently with the arrival of network data, rather than sequentially, following
the end of network receive activity.
Outline of the LAPP Flow:
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the PCnet-ISA II controller.
Am79C961A
191
Note:
The labels in the following text are used as references in the
timeline diagram that follows.
SETUP:
The driver should set up descriptors in groups of 3, with
the OWN and STP bits of each set of three descriptors
to read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5.
The software should set this bit. When set, the LAPPEN
bit directs the PCnet-ISA II to generate an INTERRUPT
when STP has been written to a receive descriptor by
the PCnet-ISA II controller.
does not know if buffer space in buffer number 2
will be sufficient or not, for this frame, but it has no
way to tell except by trying to move the entire message into that space. Only when the message
does not fit will it signal a buffer error condition—
there is no need to panic at the point that it discovers that it does not yet own descriptor number 3.]
S2: The first task of the driver’s interrupt service
routine is to collect the header information from
the PCnet-ISA II controller’s first buffer and pass it
to the application.
N0: Frame preamble appears on the wire, followed by
SFD and destination address.
S3: The application will return an application buffer
pointer to the driver. The driver will add an offset
to the application data buffer pointer, since the
PCnet-ISA II controller will be placing the first
portion of the message into the first and second
buffers. (The modified application data buffer
pointer will only be directly used by the PCnet-ISA
II controller when it reaches the third buffer.) The
driver will place the modified data buffer pointer
into the final descriptor of the group (#3) and will
grant ownership of this descriptor to the PCnet-ISA II controller.
N1: The 64th byte of frame data arrives from the wire.
This causes the PCnet-ISA II controller to begin
frame data DMA operations to the first buffer.
C5: Interleaved with S2, S3 and S4 driver activity, the
PCnet-ISA II controller will write frame data to
buffer number 2.
C0: When the 64th byte of the message arrives, the
PCnet-ISA II controller performs a lookahead operation to the next receive descriptor. This descriptor
should be owned by the PCnet-ISA II controller.
S4: The driver will next proceed to copy the contents
of the PCnet-ISA II controller’s first buffer to the
beginning of the application space. This copy will
be to the exact (unmodified) buffer pointer that
was passed by the application.
FLOW:
The PCnet-ISA II controller polls the current receive
descriptor at some point in time before a message
arrives. The PCnet-ISA II controller determines that
this receive buffer is OWNed by the PCnet-ISA II
controller and it stores the descriptor information to
be used when a message does arrive.
C1: The PCnet-ISA II controller intermittently requests
the bus to transfer frame data to the first buffer as
it arrives on the wire.
S0: The driver remains idle.
C2: When the PCnet-ISA II controller has completely
filled the first buffer, it writes status to the first
descriptor.
C3: When the first descriptor for the frame has been
written, changing ownership from the PCnet-ISA II
controller to the CPU, the PCnet-ISA II controller
will generate an SRP INTERRUPT. (This interrupt appears as a RINT interrupt in CSR0.)
S1: The SRP INTERRUPT causes the CPU to switch
tasks to allow the PCnet-ISA II controller’s driver
to run.
C4: During the CPU interrupt-generated task switching, the PCnet-ISA II controller is performing a
lookahead operation to the third descriptor. At this
point in time, the third descriptor is owned by the
CPU. [Note: Even though the third buffer is not
owned by the PCnet-ISA II controller, existing
AMD Ethernet controllers will continue to perform
data DMA into the buffer space that the controller
already owns (i.e. buffer number 2). The controller
192
S5: After copying all of the data from the first buffer
into the beginning of the application data buffer,
the driver will begin to poll the ownership bit of the
second descriptor. The driver is waiting for the
PCnet-ISA II controller to finish filling the second
buffer.
C6: At this point, knowing that it had not previously
owned the third descriptor, and knowing that the
current message has not ended (there is more
data in the fifo), the PCnet-ISA II controller will
make a “last ditch lookahead” to the final (third)
descriptor; This time, the ownership will be TRUE
(i.e. the descriptor belongs to the controller),
because the driver wrote the application pointer
into this descriptor and then changed the ownership to give the descriptor to the PCnet-ISA II controller back at S3. Note that if steps S1, S2 and S3
have not completed at this time, a BUFF error will
result.
C7: After filling the second buffer and performing the
last chance lookahead to the next descriptor, the
PCnet-ISA II controller will write the status and
change the ownership bit of descriptor number 2.
Am79C961A
S6: After the ownership of descriptor number 2 has
been changed by the PCnet-ISA II controller, the
next driver poll of the 2nd descriptor will show
ownership granted to the CPU. The driver now
copies the data from buffer number 2 into the
“middle section” of the application buffer space.
This operation is interleaved with the C7 and C8
operations.
C8: The PCnet-ISA II controller will perform data DMA
to the last buffer, whose pointer is pointing to
application space. Data entering the last buffer
will not need the infamous “double copy” that is
required by existing drivers, since it is being
placed directly into the application buffer space.
N2: The message on the wire ends.
Ethernet
Wire
activity:
S7: When the driver completes the copy of buffer
number 2 data to the application buffer space, it
begins polling descriptor number 3.
C9: When the PCnet-ISA II controller has finished all
data DMA operations, it writes status and changes
ownership of descriptor number 3.
S8: The driver sees that the ownership of descriptor
number 3 has changed, and it calls the application
to tell the application that a frame has arrived.
S9: The application processes the received frame and
generates the next TX frame, placing it into a TX
buffer.
S10: The driver sets up the TX descriptor for the PCnet-ISA II controller.
Ethernet
Controller
activity:
Software
activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.
S8: Driver calls application
to tell application that
packethas arrived.
}
C9: Controller writes descriptor #3.
S7: Driver polls descriptor of buffer #3.
N2:EOM C8: Controller is performing intermittent
bursts of DMA to fill data buffer #3.
Buffer
#3
C6: "Last chance" lookahead to
descriptor #3 (OWN).
S4: Driver copies data from buffer #1 to the application
buffer.
S3: Driver writes modified application
pointer to descriptor #3.
Packet data arriving
C5: Controller is performing intermittent
bursts of DMA to fill data buffer #2
C4: Lookahead to descriptor #3 (OWN).
C3: SRP interrupt is
generated.
S5: Driver polls descriptor #2.
}
Buffer
#2
}
C7: Controller writes descriptor #2.
S6: Driver copies data from buffer #2 to the application
buffer.
S2: Driver call to application to
get application buffer pointer.
S1: Interrupt latency.
}
C2: Controller writes descriptor #1.
C1: Controller is performing intermittent
bursts of DMA to fill data buffer #1.
Buffer
#1
S0: Driver is idle.
C0: Lookahead to descriptor #2.
{
N1: 64th byte of packet
data arrives.
N0: Packet preamble, SFD
and destination address
are arriving.
19364B-87
Figure 1.
Look Ahead Packet Processing (LAPP) Timeline
Am79C961A
193
LAPP Enable Software Requirements
Software needs to set up a receive ring with descriptors
formed into groups of 3. The first descriptor of each
group should have OWN = 1 and STP = 1, the second
descriptor of each group should have OWN = 1 and
STP = 0. The third descriptor of each group should
have OWN = 0 and STP = 0. The size of the first buffer
(as indicated in the first descriptor), should be at least
equal to the largest expected header size; However,
for maximum efficiency of CPU utilization, the first
buffer size should be larger than the header size. It
should be equal to the expected number of message
bytes, minus the time needed for Interrupt latency and
minus the application call latency, minus the time
needed for the driver to write to the third descriptor,
minus the time needed for the driver to copy data from
buffer #1 to the application buffer space, and minus the
time needed for the driver to copy data from buffer #2
to the application buffer space. Note that the time
needed for the copies performed by the driver depends
upon the sizes of the 2nd and 3rd buffers, and that the
sizes of the second and third buffers need to be set according to the time needed for the data copy operations! This means that an iterative self-adjusting
mechanism needs to be placed into the software to determine the correct buffer sizing for optimal operation.
Fixed values for buffer sizes may be used; In such a
case, the LAPP method will still provide a significant
performance increase, but the performance increase
will not be maximized.
The following diagram illustrates this setup for a receive ring size of 9:
Descriptor
#1
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
Descriptor
#2
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
Descriptor
#3
OWN = 0 STP = 0
SIZE = S6
Descriptor
#4
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
Descriptor
#5
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
Descriptor
#6
OWN = 0 STP = 0
SIZE = S6
Descriptor
#7
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
Descriptor
#8
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
Descriptor
#9
OWN = 0 STP = 0
SIZE = S6
LAPP Enable Rules for Parsing of
Descriptors
When using the LAPP method, software must use a
modified form of descriptor parsing as follows:
Software will examine OWN and STP to determine
where a RCV frame begins. RCV frames will only
begin in buffers that have OWN = 0 and STP = 1.
Software shall assume that a frame continues until it
finds either ENP = 1 or ERR= 1.
Software must discard all descriptors with OWN = 0
and STP = 0 and move to the next descriptor when
searching for the beginning of a new frame; ENP and
ERR should be ignored by software during this search.
Software cannot change an STP value in the receive
descriptor ring after the initial setup of the ring is
complete, even if software has ownership of the STP
descriptor unless the previous STP descriptor in the
ring is also OWNED by the software.
When LAPPEN = 1, then hardware will use a modified
form of descriptor parsing as follows:
The controller will examine OWN and STP to determine where to begin placing a RCV frame. A new RCV
frame will only begin in a buffer that has OWN = 1 and
STP = 1.
The controller will always obey the OWN bit for determining whether or not it may use the next buffer for a
chain.
The controller will always mark the end of a frame with
either ENP = 1 or ERR= 1.
A = Expected message size in bytes
S1 = Interrupt latency
S2 = Application call latency
S3 = Time needed for driver to write
to third descriptor
S4 = Time needed for driver to copy
data from buffer #1 to
application buffer space
S6 = Time needed for driver to copy
data from buffer #2 to
application buffer space
Note that the times needed for tasks S1,
S2, S3, S4, and S6 should be divided by
0.8 microseconds to yield an equivalent
number of network byte times before
subtracting these quantities from the
expected message size A.
19364B-88
Figure 2. LAPP 3 Buffer Grouping
194
Am79C961A
Some Examples of LAPP Descriptor
Interaction
The controller will discard all descriptors with OWN = 1
and STP = 0 and move to the next descriptor when
searching for a place to begin a new frame. It discards these desciptors by simply changing the ownership bit from OWN=1 to OWN = 0. Such a descriptor is
unused for receive purposes by the controller, and the
driver must recognize this. (The driver will recognize
this if it follows the software rules.)
Choose an expected frame size of 1060 bytes.
Choose buffer sizes of 800, 200 and 200 bytes.
1. Assume that a 1060 byte frame arrives correctly,
and that the timing of the early interrupt and the software is smooth. The descriptors will have changed
from:
The controller will ignore all descriptors with OWN = 0
and STP = 0 and move to the next descriptor when
searching for a place to begin a new frame. In other
words, the controller is allowed to skip entries in the
ring that it does not own, but only when it is looking for
a place to begin a new frame.
Before the Frame Arrived
After the Frame Has Arrived
Descriptor
Number
OWN
STP
ENP*
OWN
STP
ENP*
1
1
1
X
0
1
0
Bytes 1–800
2
1
0
X
0
0
0
Bytes 801–1000
3
0
0
X
0
0
1
Bytes 1001–1060
4
1
1
X
1
1
X
Controller’s current location
5
1
0
X
1
0
X
Not yet used
6
0
0
X
0
0
X
Not yet used
etc.
1
1
X
1
1
X
Not yet used
Comments
(After Frame Arrival)
*ENP or ERR
2. Assume that instead of the expected 1060 byte
frame, a 900 byte frame arrives, either because
there was an error in the network, or because this is
the last frame in a file transmission sequence.
Before the Frame Arrived
After the Frame Has Arrived
Descriptor
Number
OWN
STP
ENP*
OWN
STP
ENP*
Comments
(After Frame Arrival)
1
1
1
X
0
1
0
Bytes 1–800
2
1
0
X
0
0
1
Bytes 801–900
3
0
0
X
0
0
?**
4
1
1
X
1
1
X
Controller’s current location
5
1
0
X
1
0
X
Not yet used
6
0
0
X
0
0
X
Not yet used
etc.
1
1
X
1
1
X
Not yet used
Discarded buffer
*ENP or ERR
** Note that the PCnet-ISA II controller might write a ZERO to ENP location in the 3rd descriptor. Here are the two possibilities:
1. If the controller finishes the data transfers into buffer number 2 after the driver writes the application’s modified buffer pointer
into the third descriptor, then the controller will write a ZERO to ENP for this buffer and will write a ZERO to OWN and STP.
2. If the controller finishes the data transfers into buffer number 2 before the driver writes the application’s modified buffer pointer
into the third descriptor, then the controller will complete the frame in buffer number two and then skip the then unowned third
buffer. In this case, the PCnet-ISA II controller will not have had the opportunity to RESET the ENP bit in this descriptor, and
it is possible that the software left this bit as ENP=1 from the last time through the ring. Therefore, the software must treat
the location as a don’t care; The rule is, after finding ENP=1 (or ERR=1) in descriptor number 2, the software must ignore
ENP bits until it finds the next STP=1.
Am79C961A
195
3. Assume that instead of the expected 1060 byte
frame, a 100 byte frame arrives, because there was
an error in the network, or because this is the last
frame in a file transmission sequence, or perhaps
because it is an acknowledge frame.
*
Before the Frame Arrived
After the Frame Has Arrived
Descriptor
Number
OWN
STP
ENP*
OWN
STP
ENP*
1
1
1
X
0
1
1
2
1
0
X
0
0
0***
Discarded buffer
3
0
0
X
0
0
?**
Discarded buffer
4
1
1
X
1
1
X
Controller’s current location
5
1
0
X
1
0
X
Not yet used
6
0
0
X
0
0
X
Not yet used
etc.
1
1
X
1
1
X
Not yet used
Comments
(After Frame Arrival)
Bytes 1–100
ENP or ERR
** Same as note in case 2 above, except that in this case, it is very unlikely that the driver can respond to the interrupt and get the
pointer from the application before the PCnet-ISA II controller has completed its poll of the next descriptors. This means that for
almost all occurrences of this case, the PCnet-ISA II controller will not find the OWN bit set for this descriptor and therefore, the
ENP bit will almost always contain the old value, since the PCnet-ISA II controller will not have had an opportunity to modify it.
*** Note that even though the PCnet-ISA II controller will write a ZERO to this ENP location, the software should treat the location
as a don’t care, since after finding the ENP=1 in descriptor number 2, the software should ignore ENP bits until it finds the
next STP=1.
Buffer Size Tuning
For maximum performance, buffer sizes should be
adjusted depending upon the expected frame size and
the values of the interrupt latency and application call
latency. The best driver code will minimize the CPU
utilization while also minimizing the latency from frame
end on the network to frame sent to application from
driver (frame latency). These objectives are aimed at
increasing throughput on the network while decreasing
CPU utilization.
Note that the buffer sizes in the ring may be altered at
any time that the CPU has ownership of the corresponding descriptor. The best choice for buffer sizes
will maximize the time that the driver is swapped out,
while minimizing the time from the last byte written by
the PCnet-ISA II controller to the time that the data is
passed from the driver to the application. In the
diagram, this corresponds to maximizing S0, while minimizing the time between C9 and S8. (The timeline
happens to show a minimal time from C9 to S8.)
Note that by increasing the size of buffer number 1, we
increase the value of S0. However, when we increase
the size of buffer number 1, we also increase the value
of S4. If the size of buffer number 1 is too large, then
the driver will not have enough time to perform tasks
S2, S3, S4, S5 and S6. The result is that there will be
196
delay from the execution of task C9 until the execution
of task S8. A perfectly timed system will have the
values for S5 and S7 at a minimum.
An average increase in performance can be achieved if
the general guidelines of buffer sizes in Figure 2 is followed. However, as was noted earlier, the correct sizing
for buffers will depend upon the expected message size.
There are two problems with relating expected message
size with the correct buffer sizing:
1. Message sizes cannot always be accurately
predicted, since a single application may expect
different message sizes at different times, therefore,
the buffer sizes chosen will not always maximize
throughput.
2. Within a single application, message sizes might be
somewhat predictable, but when the same driver is
to be shared with multiple applications, there may
not be a common predictable message size.
Additional problems occur when trying to define the
correct sizing because the correct size also depends
upon the interrupt latency, which may vary from system
to system, depending upon both the hardware and the
software installed in each system.
In order to deal with the unpredictable nature of the
message size, the driver can implement a self tuning
Am79C961A
mechanism that examines the amount of time spent in
tasks S5 and S7 as such: While the driver is polling for
each descriptor, it could count the number of poll operations performed and then adjust the number 1 buffer
size to a larger value, by adding “t” bytes to the buffer
count, if the number of poll operations was greater than
“x”. If fewer than “x” poll operations were needed for
each of S5 and S7, then the software should adjust the
buffer size to a smaller value by, subtracting “y” bytes
from the buffer count. Experiments with such a tuning
mechanism must be performed to determine the best
values for “X” and “y.”
Note whenever the size of buffer number 1 is adjusted,
buffer sizes for buffer number 2 and buffer 3 should
also be adjusted.
In some systems the typical mix of receive frames on a
network for a client application consists mostly of large
data frames, with very few small frames. In this case,
for maximum efficiency of buffer sizing, when a frame
arrives under a certain size limit, the driver should not
adjust the buffer sizes in response to the short frame.
An Alternative LAPP Flow - the TWO Interrupt
Method
An alternative to the above suggested flow is to use
two interrupts, one at the start of the Receive frame
and the other at the end of the receive frame, instead
of just looking for the SRP interrupt as was described
above. This alternative attempts to reduce the
amount of time that the software “wastes” while polling for descriptor own bits. This time would then be
available for other CPU tasks. It also minimizes the
amount of time the CPU needs for data copying. This
savings can be applied to other CPU tasks.
The time from the end of frame arrival on the wire to
delivery of the frame to the application is labeled as
frame latency. For the one-interrupt method, frame
latency is minimized, while CPU utilization increases.
For the two-interrupt method, frame latency becomes
greater, while CPU utilization decreases.
Note that some of the CPU time that can be applied to
non-Ethernet tasks is used for task switching in the
CPU. One task switch is required to swap a non-Ethernet task into the CPU (after S7A) and a second task
switch is needed to swap the Ethernet driver back in
again (at S8A). If the time needed to perform these
task switches exceeds the time saved by not polling
descriptors, then there is a net loss in performance with
this method. Therefore, the NEW WORD method implemented should be carefully chosen.
Figure 3 shows the event flow for the two-interrupt
method.
Figure 4 shows the buffer sizing for the two-interrupt
method. Note that the second buffer size will be about
the same for each method.
There is another alternative which is a marriage of the
two previous methods. This third possibility would use
the buffer sizes set by the two-interrupt method, but
would use the polling method of determining frame
end. This will give good frame latency but at the price
of very high CPU utilization.
And still, there are even more compromise positions
that use various fixed buffer sizes and effectively, the
flow of the one-interrupt method. All of these compromises will reduce the complexity of the one-interrupt
method by removing the heuristic buffer sizing code,
but they all become less efficient than heuristic code
would allow.
Am79C961A
197
Ethernet
Wire
activity:
Ethernet
Controller
activity:
Software
activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.
S8: Driver calls application
to tell application that
packethas arrived.
S8A: Interrupt latency.
}
C10: ERP interrupt
is generated.
}
C9: Controller writes descriptor #3.
}
C8: Controller is performing intermittent
bursts of DMA to fill data buffer #3.
N2:EOM
C7: Controller writes descriptor #2.
S7: Driver is swapped out, allowing a non-Ethernet
application to run.
S7A: Driver Interrupt Service
Routine executes
RETURN.
S6: Driver copies data from buffer #2 to the application
buffer.
Buffer
#3
S5: Driver polls descriptor #2.
C6: "Last chance" lookahead to
descriptor #3 (OWN).
S4: Driver copies data from buffer #1 to the application
buffer.
S3: Driver writes modified application
pointer to descriptor #3.
Packet data arriving
C4: Lookahead to descriptor #3 (OWN).
C3: SRP interrupt is
generated.
}
Buffer
#2
}
C5: Controller is performing intermittent
bursts of DMA to fill data buffer #2
S2: Driver call to application to
get application buffer pointer.
S1: Interrupt latency.
}
C2: Controller writes descriptor #1.
C1: Controller is performing intermittent
bursts of DMA to fill data buffer #1.
Buffer
#1
S0: Driver is idle.
C0: Lookahead to descriptor #2.
{
N1: 64th byte of packet
data arrives.
N0: Packet preamble, SFD
and destination address
are arriving.
19364B-89
Figure 3. LAPP TImeline for TWO-INTERRUPT Method
198
Am79C961A
Descriptor
#1
Descriptor
#2
OWN = 1
STP = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
OWN = 1
SIZE = S1+S2+S3+S4
STP = 0
Descriptor
#3
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
Descriptor
#4
OWN = 1
STP = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
Descriptor
#5
OWN = 1
SIZE = S1+S2+S3+S4
Descriptor
#6
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
Descriptor
#7
OWN = 1
STP = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
Descriptor
#8
OWN = 1
SIZE = S1+S2+S3+S4
Descriptor
#9
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
STP = 0
STP = 0
A = Expected message size in bytes
S1 = Interrupt latency
S2 = Application call latency
S3 = Time needed for driver to write
to third descriptor
S4 = Time needed for driver to copy
data from buffer #1 to
application buffer space
S6 = Time needed for driver to copy
data from buffer #2 to
application buffer space
Note that the times needed for tasks S1,
S2, S3, S4, and S6 should be divided by
0.8 microseconds to yield an equivalent
number of network byte times before
subtracting these quantities from the
expected message size A.
19364B-90
Figure 4.
LAPP 3 Buffer Grouping for TWO-INTERRUPT Method
Am79C961A
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Am79C961A
APPENDIX F
Some Characteristics of the
XXC56 Serial EEPROMs
SWITCHING CHARACTERISTICS of a TYPICAL XXC56 SERIAL EEPROM INTERFACE
Applicable over recommended operating range from TA = –40×C to +85×C, VCC = +1.8 V
to +5.5 V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
0
0.5
MHz
fSK
SK Clock Frequency
tSKH
SK High Time
(Note 1)
500
ns
tSKL
SK Low Time
(Note 1)
500
ns
tCS
Minimum CS Low Time
(Note 2)
500
ns
tCSS
CS Setup Time
Relative to SK
100
ns
tDIS
DI Setup Time
Relative to SK
200
ns
tCSH
CS Hold Time
Relative to SK
0
ns
tDIH
DI Hold Time
Relative to SK
200
ns
tPD1
Output Delay to ‘1’
AC Test
1000
ns
tPD0
Output Delay to ‘0’
AC Test
1000
ns
tSV
CS to Status Valid
AC Test
1000
ns
tDF
CS to DO in High Impedance
AC Test; CS = VIL
200
ns
tWP
Write Cycle Time
10
ms
Endurance
Number of Data
Changes per Bit
Typical 100,000
Cycles
Notes:
1. The SK frequency specifies a minimum SK clock period of 2 µs, therefore in an SK clock cycle tSKH + tSKL must be greater
than or equal to 2 µs. For example, if the tSKL = 500 ns then the minimum tSKH = 1.5 µs in order to meet the SK frequency
specification.
2. CS must be brought low for a minimum of 500 ns (tCS) between consecutive instruction cycles.
Am79C961A
201
INSTRUCTION SET FOR THE XXC56 SERIES OF EEPROMS
Address
Data
Instruction
SB
Op
Code
READ
1
10
A8–A0
A7–A0
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
1
11
A8–A0
A7–A0
WRITE
1
01
A0–A0
A7–A0
ERAL
1
00
10XXXXXXX
10XXXXXX
WRAL
1
00
01XXXXXXX
01XXXXXX
EWDS
1
00
00XXXXXXX
00XXXXXX
CS
SK
DI
DO (READ)
x8
x16
x8
x16
Comments
Reads data stored in memory, at
specified address
Write enable must precede all
programming modes
Erases memory location An–A0
D7–D0
D15–D0
Writes memory location An–A0
Erases all memory locations.
Valid only at VCC = 4.5 V to 5.5 V
D7–D0
D15–D0
Writes all memory locations. Valid
when VCC = 5.0 V ± 10% and
Disable Register cleared
Disables all programming
instructions
VIH
VIL
1 µs (1)
tCSS
tSKH
tCSH
tSKL
VIH
VIL
tDIS
tDIH
VIH
VIL
tPDO
VOH
tPDI
tDF
VOL
tDF
tSV
DO (PROGRAM)
VOH
Status Valid
VOL
19364B-91
Typical XXC56 Series
Serial EEPROM Control Timing
Note:
1. This is the minimum SK period.
202
Am79C961A
APPENDIX G
Am79C961A PCnet-ISA II
Silicon Errata Report
AM79C961A REV FD SILICON STATUS
The items below are the known errata for Rev FD silicon. Rev FD silicon is the production silicon.
Note: A signal followed by "*" indicates active low; i.e., MASTER*.
The Description section of this document gives an external description of the problem. The Implication section
gives an explanation of how the PCnet-ISA II controller behaves and its impact on the system. The Work-around
section describes a work around for the problem.
The Status section indicates when and how the problem will be fixed.
Current package marking for this revision: Line 1: <Logo>
Line 2: PCnet(tm)-ISA II
Line 3: Am79C961AKC (Assuming package is PQFP)
Line 4: <Date Code> FD
Line 5: (c) 1993 AMD
Value of chip identification registers, CSR89+CSR88 [31:0] for this revision = 32261003h.
1) False BABL errors generated
Description: The PCnet-ISA II FD device will intermittenly give BABL error indications when the network traffic has
frames equal to or greater than 1518 bytes.
Implication: False BABL errors on the receiving station can be passed up to the upper layer software if PCnet-ISA
II FD device is just coming out of deferral and the multi-purpose counter used to count the number of bytes re-cevied
reaches 1518 at the same time. If the network is heavily loaded with full-size frames, then the probability of a false
BABL error is high.
Work-around: There are two possible work-arounds.
1. If the user has no intention to transmit frames larger than 1518 bytes, then the BABL bit may be masked to ignore
babble errors. In this case the false babble error will not cause an interrupt, nor will it be passed to the higher level
software.
2. Check to see if the device is transmitting in ISR (Interrupt Service Routine), which is induced by the BABL error.
The BCRs which control the LED settings can be programmed to indicate a transmit activity, assuming the interrupt
latency is not longer than one mininum IFG (inter-frame gap) time.
If (ISR_LATENCY < 9.6 us)
True_bable_err = BABL * ( TINT + XMT_LED)
{ i.e. False_bable_err = ~ (BABL * ( TINT + XMT_LED))}
else
Cannot tell if the BABL error is true or false just by reading BABL, TINT, XMT_LED
bits in ISR.
Status: No current plan to fix this item.
Am79C961A
203
2) DRQ inactive to MASTER* inactive time
Description: The data sheet lists a minimum limit of 40ns for the time that DRQ goes inactive until MASTER* goes
inactive. During the course of device characterization a minimum value of less than 40ns has been observed.
The lower limit for this parameter therefore has been changed to 30ns. (DRQ inactive to MASTER* inactive time).
Implication: There is no jeopardy because of this change. The device tristates its active command, SBHE, SA, and
LA lines before MASTER* goes inactive.
Work-around: None required.
Status: Data sheet limit will be changed. There will be no change to the silicon.
3) DRQ inactive to Command, SBHE*, SA0-9 and LA17-23 tristated.
Description: The data sheet lists a maximum limit of 0ns for the time that DRQ goes inactive until Command,
SBHE*, SA0-9 and LA17-23 signals tristate. During the course of device characterization a maximum value of more
than 0ns has been observed. The upper limit for this parameter therefore has been changed to 10ns. (DRQ inactive
to Command, SBHE*, SA0-9 and LA17-23 tristated)
Implication: There is no jeopardy because of this change. The MASTER* which controls the IO on the bus goes
inactive after this time.
Work-around: None required.
Status: Data sheet limit will be changed. There will be no change to the silicon.
204
Am79C961A
The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci-fications and product descriptions at any
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Trademarks
Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
PCnet, PCnet-ISA and Magic Packet are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am79C961A
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Am79C961A