IDT GRM155R71C103KA01D 6-bit 0.5 db digital step attenuator Datasheet

IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
This document describes the specification for the
IDTF1951 Digital Step Attenuator. The F1951 is part of a
family of Glitch-FreeTM DSAs optimized for the demanding
requirements of communications Infrastructure. These
devices are offered in a compact 4x4 QFN package with
50 Ω impedances for ease of integration into the radio
system.
COMPETITIVE ADVANTAGE
Digital step attenuators are used in Receivers and
Transmitters to provide gain control. The IDTF1951 is a
6-bit step attenuator optimized for these demanding
applications. The silicon design has very low insertion
loss and low distortion (+65 dBm IP3I.) The device has
pinpoint accuracy and settles to final attenuation value
within 400 nsec. Most importantly, the F1951 includes
IDT’s Glitch-FreeTM technology which results in less
than 0.6 dB of overshoot ringing during MSB transitions.
This is in stark contrast to competing DSAs that glitch as
much as 10 dB during MSB transitions (see p.10)
Glitch-FreeTM, < 0.6 dB transient overshoot
Spurious Free Design
3V to 5V supply
Attenuation Error < 0.2 dB @ 2 GHz
Low Insertion Loss < 1.2 dB @ 2 GHz
Excellent Linearity +65 dBm IP3I
Fast settling time, < 450 nsec
Class 2 JEDEC ESD (> 2kV HBM)
Serial Interface 31.5 dB Range
Stable Integral Non-Linearity over temperature
4x4 mm Thin QFN 24 pin package
DEVICE BLOCK DIAGRAM
Lowest insertion loss for best SNR
RF1
Glitch-FreeTM when transitioning –
won’t damage PA or ADC
Extremely accurate with low distortion
RF2
TM
Glitch-FreeTM
APPLICATIONS
•
Bias
Base Station 2G, 3G, 4G, TDD radiocards
•
Repeaters and E911 systems
•
Digital Pre-Distortion
•
Point to Point Infrastructure
•
Public Safety Infrastructure
•
WIMAX Receivers and Transmitters
•
Military Systems, JTRS radios
VDD
•
RFID handheld and portable readers
•
Cable Infrastructure
DEC
SPI
RST
CLK SDI CS SDO
ORDERING INFORMATION
Omit IDT
prefix
PART# MATRIX
Part#
Freq range
Resolution
/ Range
Control
IL
Pinout
F 1951
100 - 4000
0.50 / 31.5
Serial Only
- 1 .2
HITT
F1950
150 - 4000
0.25 / 31.5
Serial Only
-1.3
PE
F1952
100 – 4000
0.50 / 15.5
Serial Only
-0.9
HITT
Glitch-FreeTM Digital Step Attenuator
Tape &
Reel
0.8 mm height
package
IDTF1951NBGI8
RF product Line
1
Green
Industrial
Temp range
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
ABSOLUTE MAXIMUM RATINGS
VDD to GND
D[5:0], DATA, CLK,CSb,SDO, RSTb
RF Input Power (RF1, RF2) calibration and testing
RF Input Power (RF1, RF2) continuous RF operation
θJA (Junction – Ambient)
θJC (Junction – Case) The Case is defined as the exposed paddle
Operating Temperature Range (Case Temperature)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s) .
Glitch-FreeTM Digital Step Attenuator
-0.3V to +5.25V
-0.3V to 3.6V
+29 dBm
+23 dBm
+50°C/W
+3°C/W
TC = -40°C to +100°C
140°C
-65°C to +150°C
+260°C
2
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
IDTF1951 SPECIFICATION (31.5 dB Range)
Specifications apply at VDD = +3.3V, fRF = 2000MHz, TC= +25°C unless otherwise noted, EVkit losses are de-embedded (see p. 17)
Parameter
Comment
Sym.
min
Logic Input High
CLK, CSb, DATA, D[5:0], RSTb
VIH
2.3
Logic Input Low
CLK, CSb, DATA, D[5:0], RSTb
VIL
Logic Current
VMODE
IIH, IIL
Supply Voltage(s)
Main Supply
VDD
typical
-5
max
units
3.6
V
0.7
V
+5
µA
3.0 to 5.25
V
1
Supply Current
Total
IDD
1.1
Temperature Range
Operating Range (Case)
TC
-40 to +100
degC
Frequency Range
Operating Range
fRF
100 to 4000
MHz
RF1, RF2 Return Loss
dB(s11), dB(s22)
S11, S22
-22
dB
Minimum Attenuation
D[5:0] = [111111]
AMIN or IL
1.2
Maximum Attenuation
Minimum Gain Step
• D[5:0] = [000000]
• VDD = 3.3V
AMAX
Least Significant Bit
LSB
32.2
2
mA
1.9
dB
32.5
dB
0.50
dB
Phase Delta
Phase change AMIN vs. AMAX
Φ∆
33
deg
Differential Non-Linearity
Error: adjacent steps
DNL
0.08
dB
Integral Non-Linearity
Error: absolute to 14 dB
ATTN
INL1
0.03
0.34
dB
Integral Non-Linearity
Max Error vs. line (AMIN ref) to
31.5 dB ATTN [VDD = 3.3V]
INL2
0.21
0.38
dB
D[5:0] = [111111] = AMIN
IP3I1
+61
2
+64
D[5:0] = [100000] = A15.5
IP3I2
+59
+61
D[5:0] = [000000] = AMAX
IP3I3
+57
+61
dBm
Input IP3
PIN = +10 dBm per tone
50 MHz Tone Separation
VDD = 3.3V
D[5:0] = [111010] = A2.5
Baseline PIN = 20 dBm
P0.1
29
dBm
Settling Time
Start LE rising edge > VIH
End +/-0.10 dB Pout settling
15.5 – 16.0 transition
TLSB
400
nsec
Serial Clock Speed
SPI 4 wire bus
FCLK
20
Reset to Serial Setup
SPI 4 wire bus
A
20
nsec
Serial Data Hold Time
SPI 4 wire bus
B
5
nsec
CSb setup delay
SPI 4 wire bus
C
40
Serial Data Out Delay
SPI 4 wire bus
D
8
0.1 dB Compression
Please note ABS MAX
8
50
MHz
100
nsec
8
Cycles
SPECIFICATION NOTES:
1 – Items in min/max columns in bold italics are Guaranteed by Test
2 – All other Items in min/max columns are Guaranteed by Design Characterization
Glitch-FreeTM Digital Step Attenuator
3
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
SERIAL CONTROL MODE
Data is clocked in LSB first via serial mode. Note the timing diagram below.
An RSTb pulse resets the shift register to [00000000]. If the RSTb pulse is followed immediately by a CSb pulse the
device will be set to Maximum Attenuation.
Note – The IDTF1951 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device
is not being programmed. When CSb is high (> VIH), the CLK input is disabled and serial data (SDI) will not be clocked
into the shift register. It is recommended that CSb be pulled high (>VIH) when the device is not being programmed
SERIAL REGISTER TIMING DIAGRAM [SINGLE DEVICE]: (Note the Timing Spec Intervals in Blue)
SERIAL REGISTER TIMING DIAGRAM [TWO OR MORE DEVICES]:
The contents of the shift register is delayed by 8 clock cycles while CSb is low. This feature allows one to program
nd
multiple DSAs (in a MIMO transceiver for instance) with a single common CSb line by daisy-chaining the SDO of the 2
st
DSA to the SDI of the 1 DSA and so forth:
Glitch-FreeTM Digital Step Attenuator
4
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
SERIAL REGISTER DEFAULT CONDITION [F1951]:
When the device is first powered up, it will default to the Maximum Attenuation setting as described below:
Note that for the F1951 (High or 1) = Attenuation Stepped OUT. (0 or Low) = Attenuation Stepped IN.
Default Register Settings
0
0
0
0
0
0
0
D1
D2
D3
D4
R0
R1
D0
RSV
RSV
LSB
0
D5
MSB
SERIAL REGISTER TIMING TABLE [F1951]:
Interval
Symbol
Description
Min
Spec
A
B
C
D
Reset to Serial Setup Time
Serial Data Hold Time
CSb setup delay
Serial Data Out Delay
20
5
40
8
Glitch-FreeTM Digital Step Attenuator
5
Max
Spec
100
8
Units
nsec
nsec
nsec
Cycles
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
TYPICAL OPERATING PARAMETRIC CURVES
(EVKit loss de-embedded, 3.3V unless otherwise noted)
Attenuation vs. Freq [TCASE = +25C, 0.5 dB steps]
Insertion Loss vs. Frequency [AMIN]
0
-0.5
-5
-1.0
-10
DSA Loss (dB)
Insertion Loss (dB)
0.0
-1.5
-2.0
-40 degC - 3.3 V
-2.5
25 degC - 3.3 V
-15
-20
-25
-3.0
100 degC - 3.3 V
-30
-3.5
-4.0
200
600
1000
1400
1800
2200
2600
3000
3400
-35
200
3800
600
1000
0
0
-5
-5
-10
-10
RF2 Return Loss (dB)
RF1 Return Loss (dB)
2200
2600
3000
3400
3800
S22 vs. Frequency [TCASE = +25C, 0.5 dB steps]
S11 vs. Frequency [TCASE = +25C, 0.5 dB steps]
-15
-20
-25
-30
-15
-20
-25
-30
-35
-35
600
1000
1400
1800
2200
2600
3000
3400
-40
200
3800
600
1000
1400
1800
2200
2600
3000
3400
3800
RF Frequency (MHz)
RF Frequency (MHz)
S22 vs. Attenuation State
S11 vs. Attenuation State
0
0
-10
-40 degC - 900 MHz
-40 degC - 2000 MHz
25 degC - 900 MHz
25 degC - 2000 MHz
100 degC - 900 MHz
100 degC - 2000 MHz
-40 degC - 900 MHz
-40 degC - 2000 MHz
25 degC - 900 MHz
25 degC - 2000 MHz
100 degC - 900 MHz
100 degC - 2000 MHz
-5
RF2 Return Loss (dB)
RF1
-5
RF1 Return Loss (dB)
1800
RF Frequency (MHz)
RF Frequency (MHz)
-40
200
1400
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
-35
-40
0
4
8
12
16
20
24
-40
28
0
Attenuation Setting (dB)
Glitch-FreeTM Digital Step Attenuator
4
8
12
16
20
24
28
Attenuation Setting (dB)
6
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
TOCS CONTINUED (-2-)
Phase vs. Frequency
Phase vs. Attenuation Setting
10
0
0
-10
S21 Phase (degrees)
-10
-20
S21 Phase (degrees)
-20
-30
-40
-50
-60
-70
-80
-90
-100
-40 degC - 31.5 dB
-40 degC - 0.0 dB
25 degC - 31.5 dB
25 degC - 0.0 dB
100 degC - 31.5 dB
100 degC - 0.0 dB
-30
-40
-50
100 MHz
400 MHz
-60
900 MHz
1400 MHz
-70
1900 MHz
2400 MHz
-80
2900 MHz
3400 MHz
-90
3900 MHz
-110
200
-100
600
1000
1400
1800
2200
2600
3000
3400
3800
0
4
8
RF Frequency (MHz)
12
16
20
24
28
Attenuation Setting (dB)
Supply Current IDD
Input IP3 [fRF = 900 MHz]
1.50
90
-40 degC - 3.3 V
80
25 degC - 3.3 V
1.25
70
Input IP3 (dBm)
Total IDD (mA)
100 degC - 3.3 V
1.00
0.75
0.50
60
50
40
30
0.25
20
0.00
0
4
8
12
16
20
24
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 5.0 V
100 degC - 3.3 V
10
28
0
Attenuation Setting (dB)
4
8
12
16
20
24
28
Attenuation Setting (dB)
Input IP3 [fRF = 1900 MHz]
Compression [fRF = 2000 MHz, ATTN = 2.5 dB]
90
0.7
Loss Compression (dB)
80
70
Input IP3 (dBm)
-40 degC - 5.0 V
60
50
40
30
-40 degC - 5.0 V
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 5.0 V
100 degC - 3.3 V
0.6
0.5
-40 degC - 5.0 V
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 5.0 V
100 degC - 3.3 V
0.4
0.3
0.2
0.1
20
0.0
10
0
4
8
12
16
20
24
28
20
Attenuation Setting (dB)
Glitch-FreeTM Digital Step Attenuator
21
22
23
24
25
26
27
28
Attenuation Setting (dB)
7
Rev2 April 2013
29
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
TOCS CONTINUED (-3-)
DNL [400 MHz]
DNL [150 MHz]
0.75
0.75
-40 degC
-40 degC
0.50
0.50
25 degC
25 degC
100 degC
Step Error (dB)
Step Error (dB)
100 degC
0.25
0.00
-0.25
0.25
0.00
-0.25
-0.50
-0.50
-0.75
-0.75
0
4
8
12
16
20
24
0
28
4
8
12
16
20
24
28
Attenuation Setting (dB)
Attenuation Setting (dB)
DNL [1900 MHz]
DNL [900 MHz]
0.75
0.75
-40 degC
-40 degC
0.50
0.50
25 degC
25 degC
100 degC
Step Error (dB)
Step Error (dB)
100 degC
0.25
0.00
-0.25
0.25
0.00
-0.25
-0.50
-0.50
-0.75
-0.75
0
4
8
12
16
20
24
0
28
4
8
16
20
24
28
Worst Setting DNL
DNL [2800 MHz]
1.00
0.75
-40 degC
0.75
0.50
0.25
0.00
-0.25
-0.50
Worst Setting Step Error (dB)
25 degC
100 degC
Step Error (dB)
12
Attenuation Setting (dB)
Attenuation Setting (dB)
4
8
12
16
20
24
28
25 degC - Max of DNL (dB)
100 degC - Min of DNL (dB)
100 degC - Max of DNL (dB)
0.00
-0.25
-0.50
-0.75
500
900
1300
1700
2100
2500
2900
3300
3700
RF Frequency (MHz)
Attenuation Setting (dB)
Glitch-FreeTM Digital Step Attenuator
-40 degC - Max of DNL (dB)
25 degC - Min of DNL (dB)
0.25
-1.00
100
-0.75
0
0.50
-40 degC - Min of DNL (dB)
8
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
TOCS CONTINUED (-4-)
INL [150 MHz]
INL [400 MHz]
0.25
0.25
-40 degC
0.00
25 degC
100 degC
-0.25
-0.50
-0.75
Absolute Error (dB)
Absolute Error (dB)
0.00
-0.25
-0.50
-40 degC
-0.75
25 degC
-1.00
-1.00
-1.25
-1.25
100 degC
-1.50
-1.50
0
4
8
12
16
20
24
0
28
4
8
0.25
0.00
0.00
Absolute Error (dB)
Absolute Error (dB)
0.25
-0.25
-0.50
-40 degC
25 degC
20
24
28
24
28
-0.25
-0.50
-40 degC
-0.75
25 degC
-1.00
-1.00
100 degC
100 degC
-1.25
-1.25
-1.50
-1.50
0
4
8
12
16
20
24
0
28
4
8
12
16
20
Attenuation Setting (dB)
Attenuation Setting (dB)
Worst Setting INL
INL [2900 MHz]
1.0
Worst Setting Absolute Error (dB)
0.25
0.00
Absolute Error (dB)
16
INL [1900 MHz]
INL [900 MHz]
-0.75
12
Attenuation Setting (dB)
Attenuation Setting (dB)
-0.25
-0.50
-40 degC
-0.75
25 degC
-1.00
100 degC
-1.25
4
8
12
16
20
24
28
-1.0
-1.5
-2.0
-40 degC
-2.5
25 degC
-3.0
100 degC
-3.5
500
900
1300
1700
2100
2500
2900
3300
3700
RF Frequency (MHz)
Attenuation Setting (dB)
Glitch-FreeTM Digital Step Attenuator
0.0
-0.5
-4.0
100
-1.50
0
0.5
9
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
TOCS CONTINUED (-5-) [fRF = 900 MHz]
Transient [ 16.0 to 15.5 (MSB-) 5.0V F1951 ]
-10.0
4.0
Pwr (dBm)
Trigger
-11.0
-12.0
3.0
-12.0
3.0
-13.0
2.5
-13.0
2.5
-14.0
2.0
-15.0
Glitch ~ 0.5 dB
1.5
-16.0
Settling Time = 400 nsec (+/- 0.1 dB)
1.0
200
300
400
500
600
-15.0
1.5
-16.0
Settling Time = 390 nsec (+/- 0.1 dB)
1.0
0.0
-0.5
-19.0
-0.5
-1.0
-20.0
-100
0.0
100
2.0
Glitch ~ 0.5 dB
-18.0
-18.0
0
-14.0
0.5
0.5
-20.0
-100
3.5
-17.0
-17.0
-19.0
LE Trigger (volts)
Trigger
Envelope Power (dBm)
3.5
Pwr (dBm)
-11.0
Envelope Power (dBm)
-10.0
4.0
700
LE Trigger (volts)
Transient [ 15.5 to 16.0 (MSB+) 3.3V F1951 ]
-1.0
0
100
200
300
400
500
600
700
Time (nsec)
Time (nsec)
The graphs ABOVE show the transient overshoot and
settling time performance for both the MSB+ and
MSB- cases for the F1951. The device settles very
quickly (~400) nsec with benign (~0.5) dB overshoot.
The graphs BELOW show the transient overshoot and
settling time performance for a popular competing
DSA. Note the overshoot/undershoot excursion of
almost 10 dB and the very long settling time. For the
MSB- case, the settling time is off the scale, ~ 3 usec.
Transient [ 15.75 to 16.00 (MSB+) Standard DSA ]
Transient [ 16.00 to 15.75 (MSB-) Standard DSA ]
4.0
-3.57
3.5
-4.57
-7.20
3.0
-5.57
3.0
-8.20
2.5
-6.57
2.5
-7.57
2.0
Envelope Power (dBm)
-9.20
2.0
-10.20
Settling Time = 600nsec (+/- 0.1 dB)
-11.20
1.5
300
400
500
600
-11.57
0.0
-0.5
-0.5
-1.0
-13.57
-100
700
-1.0
0
100
200
300
400
500
600
700
Time (nsec)
Time (nsec)
Glitch-FreeTM Digital Step Attenuator
1.5
Settling Time >> 1 usec
-12.57
0.0
200
-8.57
0.5
-13.20
100
3.5
1.0
0.5
0
Trigger
-10.57
-12.20
-15.20
-100
4.0
Pwr (dBm)
-9.57
1.0
-14.20
Envelope Power (dBm)
Trigger
LE Trigger (volts)
Pwr (dBm)
-6.20
10
Rev2 April 2013
LE Trigger (volts)
-5.20
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
PIN DIAGRAM (F1951)
TOP View
(looking through the top of the package)
2
20
19
Exposed Pad
35
*RF1
21
0.
1
22
18
NC
17
*RF2
16
GND [internal NC]
15
NC
14
VDD
13
NC
C
O
NC
23
m
m
24
Package Drawing
4 mm x 4 mm package dimension
GND [internal NC]
2.80 mm x 2.80 mm exposed pad
3
0.5 mm pitch
NC
4
SDO
5
NC
6
24 pins
0.75 mm height
0.25 mm pad width
0.40 mm pad length
7
8
9
10
11
12
* Device is RF Bi-Directional
Glitch-FreeTM Digital Step Attenuator
11
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
PACKAGE DRAWING (4X4 24 PIN)
Glitch-FreeTM Digital Step Attenuator
12
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
PIN DESCRIPTIONS
Pin
#
Pin
Name
1
NC
2
RF1
Device RF input or output (bi-directional). Must AC couple to this pin.
3
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
4
NC
Internally unconnected. Recommended connection is GND.
5
SDO
Serial Data OutKDelayed 8 clock cycles from Serial Data In.
6
NC
Internally unconnected. Recommended connection is GND.
7
RSTb
8
CLK
Serial Clock.
9
CSb
Chip Select Bar. Serial Data latched into active register on Rising Edge.
10
NC
Internally unconnected. Recommended connection is GND.
11
SDI
Serial Data Input.
12
NC
Internally unconnected. Recommended connection is GND.
13
NC
Internally unconnected.
14
VDD
15
NC
16
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
17
RF2
Device RF output or input (bi-directional). Must AC couple to this pin.
18
NC
19
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
20
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
21
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
22
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
23
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
24
GND
Exposed
Paddle
Connect directly to paddle ground or as close as possible to pin with thru via.
EP
Glitch-FreeTM Digital Step Attenuator
Pin Function
Internally unconnected. Recommended connection is GND.
Reset BAR. Falling Edge resets the device to Max Attenuation [D5:D0] =
[000000].
Main Supply. Use 3.3V or 5V. Current is < 1 mA.
Internally unconnected. Recommended connection is GND.
Internally unconnected. Recommended connection is GND.
Connect to Ground with multiple vias for good thermal relief.
13
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
EVKIT SCHEMATIC
The diagram below describes the recommended applications / EVkit circuit:
+
VLH
-
Parallel Control Switch (not placed)
16
TP1
9
J2
R12
C1
C2
-
+ o
+ o
-
+ o
-
+ o
-
-
+ o
+ o
-
+ o
-
-
+ o
U1
J7
1
2
3
4
5
6
7
8
R6
R7
8 pin Header
J6
R5
R4
R3
R2
R8
VDD
C7
R1
C4
J5
C5
C10 4 pin Header
C9
C8
C6
J1
C3
C11
C12
12
R1
NC
11
10
9
8
7
C15
13
6
14
5
R9
NC
C16
VDD
VDD
R10
J2
NC
GND
RF1
J3
SDO
C13
RF2
15
4
IDTF1951
R11
16
3
17
2
18
GND
RF1
C17
RF2
C14
J4
1
NC
NC
19
Glitch-FreeTM Digital Step Attenuator
NC
20
21
14
22
23
24
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
EVKIT OPERATION (Email:
100 MHz to 4000 MHz
[email protected] to request an EVkit, Serial Control HW/SW, or TRL cal board)
The picture and graphic below describe how to operate the EVkit
SDI
CSb
CLK
RSTb
Unused
SDO
DC Power
RF1
RF2
Glitch-FreeTM Digital Step Attenuator
15
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
EVKIT BOM
F1951 BOM Rev 02 PCB Rev 01 10/26/2012
Item # Value
Size
Description
Mfr. Part #
Mfr.
Ref Des
Qty
1
1000pF
0402
CAP CER 1000PF 50V C0G 0402
GRM1555C1H102JA01D
MURATA
C13,14
2
2
10nF
0402
CAP CER 10000PF 16V 10% X7R 0402
GRM155R71C103KA01D
MURATA
C12
1
3
0.1uF
0402
CAP CER 0.1UF 16V 10% X7R 0402
GRM155R71C104KA88D
MURATA
C11
1
4
Header 2 Pin
TH 2
CONN HEADER VERT SGL 2POS GOLD
961102-6404-AR
3M
J5
1
5
Header 4 Pin
TH 4
CONN HEADER VERT SGL 4POS GOLD
961104-6404-AR
3M
J8
1
6
Header 8 Pin
TH 8
CONN HEADER VERT SGL 8POS GOLD
961108-6404-AR
3M
J6
1
7
SMA_END_LAUNCH
.062
SMA_END_LAUNCH (Small)
142-0711-821
Emerson Johnson
J2,3,4
3
8
0
0402
RES 0.0 OHM 1/10W 0402 SMD
ERJ-2GE0R00X
Panasonic
R7,8,10
3
9
3K
0402
RES 3.00K OHM 1/10W 1% 0402 SMD
ERJ-2RKF3001X
Panasonic
R3,5,6
3
10
Digital Step Attenuator
F1951
F1951
IDT
U2
1
PCB
PCB Rev 01
F195XS Evkit Rev 01
11
1
Total
18
TOPMARKINGS
Part Number
IDTF19
51NBGI
Z207AGA
●
Glitch-FreeTM Digital Step Attenuator
Lot Code
16
Rev2 April 2013
IDTF1951
DATASHEET
6-bit 0.5 dB Digital Step Attenuator
100 MHz to 4000 MHz
EVKIT THROUGH-REFLECT-LINE (TRL) CALIBRATION
The “Through-Reflect-Line” (TRL) method [1] is used to de-embed the evaluation board losses from the S-parameter measurements of the
F1951. This method requires the use of three standards: a through, a reflection, and a line. The TRL method has the advantage over other
calibration methods in that it requires only one of these three standards to be well defined.
The TRL through which is used for the F1951 TRL calibration was constructed identically to the evaluation board, minus the DUT and its
corresponding length. Therefore, the through corresponds to a precise zero length connection between the input and output reference
planes of the DUT. This through satisfies the requirement of the TRL method that one of the three standards be precisely specified.
The TRL reflection standard used is constructed identically to the input and output lines of the evaluation board, with a short placed at the
reference plane of the DUT. In accordance with the TRL method’s requirements, the actual magnitude and phase were not accurately
specified, but the phase was known to within 90 degrees and the TRL reflection standard has a magnitude close to one.
The TRL line standard is identical to the TRL through, but with an additional length of 0.8 inches (2 cm). This satisfies the TRL method’s
requirement that the TRL be a different length than the TRL through, that it have the same impedance and propagation constant as the
through, and that the phase difference between the through and the line be between 20 degrees and 160 degrees. The difference in length
yields a phase difference of approximately 20 degrees at 500 MHz, and a phase difference of 160 degrees at 4 GHz.
For characterization of performance from 150 to 500 MHz a separate TRL board with different “Line” length is used.
Standards used for F195x TRL calibration
F1951 evaluation circuit
Engen, G.F.; Hoer, C.A.; “Thru-Reflect-Line: An Improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer,” IEEE
Transactions on Microwave Theory and Techniques, Volume: 27 Issue:12, pp. 987 – 993, Dec 1979.
Glitch-FreeTM Digital Step Attenuator
17
Rev2 April 2013