TI CDCVF2310PWRG4 2.5-v to 3.3-v high-performance clock buffer Datasheet

CDCVF2310
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SCAS666C – JUNE 2001 – REVISED JANUARY 2008
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
FEATURES
1
•
•
•
•
•
•
•
•
•
High-Performance 1:10 Clock Driver
Operates up to 200 MHz at VDD 3.3 V
Pin-to-Pin Skew < 100 ps at VDD 3.3 V
VDD Range: 2.3 V to 3.6 V
Operating Temperature Range –40°C to 85°C
Output Enable Glitch Suppression
Distributes One Clock Input to Two Banks of
Five Outputs
25-Ω On-Chip Series Damping Resistors
Packaged in 24-Pin TSSOP
APPLICATIONS
•
PW PACKAGE
(TOP VIEW)
GND
VDD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
1G
2Y4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
VDD
VDD
2Y0
2Y1
GND
GND
2Y2
2Y3
VDD
VDD
2G
General-Purpose Applications
DESCRIPTION
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a
2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –40°C to 85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2008, Texas Instruments Incorporated
CDCVF2310
www.ti.com
SCAS666C – JUNE 2001 – REVISED JANUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
3
25 Ω
4
25 Ω
5
25 Ω
8
25 Ω
9
25 Ω
1G
2G
11
Logic Control
13
Logic Control
21
CLK
24
25 Ω
20
25 Ω
17
25 Ω
16
25 Ω
12
25 Ω
2
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1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
2Y4
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SCAS666C – JUNE 2001 – REVISED JANUARY 2008
FUNCTION TABLE
INPUT
(1)
OUTPUT
1G
2G
CLK
1Y[0:4]
2Y[0:4]
L
L
↓
L
L
(1)
H
L
↓
CLK
L
H
↓
L
CLK (1)
H
H
↓
CLK (1)
CLK (1)
L
After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
1G
11
I
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
2G
13
I
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4]
3, 4, 5, 8, 9
O
Buffered output clocks
2Y[0:4]
21, 20, 17, 16, 12
O
Buffered output clocks
CLK
24
I
Input reference frequency
GND
1, 6, 7, 18, 19
VDD
2, 10, 14, 15, 22, 23
Ground
DC power supply, 2.3 V – 3.6 V
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DETAILED DESCRIPTION
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
CLK
Gn
Yn
tsu(en)
th(en)
a) Enable Mode
CLK
Gn
Yn
tsu(dis)
th(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
4
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage range, VDD
Input voltage range, VI
–0.5 V to 4.6 V
(2) (3)
Output voltage range, VO
–0.5 V to VDD + 0.5 V
(2) (3)
–0.5 V to VDD + 0.5 V
Input clamp current, IIK (VI < 0 or VI> VDD)
±50 mA
Output clamp current, IOK (VO < 0 or VO > VDD)
±50 mA
Continuous total output current, IO (VO = 0 to VDD)
±50 mA
Package thermal impedance, θJA
(4)
: PW package
120°C/W
Storage temperature range Tstg
(1)
(2)
(3)
(4)
–65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS
(1)
Supply voltage, VDD
Low-level input voltage, VIL
High-level input voltage, VIH
Low-level output current, IOL
2.5
MAX
3.6
VDD = 3 V to 3.6 V
0.8
VDD = 2.3 V to 2.7 V
0.7
VDD = 3 V to 3.6 V
2
VDD = 2.3 V to 2.7 V
UNIT
V
V
V
1.7
0
VDD
VDD = 3 V to 3.6 V
12
VDD = 2.3 V to 2.7 V
6
VDD = 3 V to 3.6 V
12
VDD = 2.3 V to 2.7 V
6
Operating free-air temperature, TA
(1)
NOM
2.3
3.3
Input voltage, VI
High-level output current, IOH
MIN
–40
85
V
mA
mA
°C
Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
UNIT
Input voltage
VDD = 3 V,
II
Input current
VI = 0 V or VDD
IDD (2)
Static device current
CLK = 0 V or VDD,
IO = 0 mA
CI
Input capacitance
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
2.5
pF
CO
Output capacitance
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
2.8
pF
(1)
(2)
II = –18 mA
MAX
VIK
–1.2
V
±5
µA
80
µA
All typical values are at respective nominal VDD.
For ICC over frequency, see Figure 6.
VDD = 3.3 V ±0.3 V
PARAMETER
TEST CONDITIONS
VDD = min to max,
VOH
(1)
High-level output voltage
VDD = 3 V
MIN
IOH = –100 µA
VDD – 0.2
IOH = –12 mA
2.1
IOH = –6 mA
2.4
TYP (1)
MAX
UNIT
V
All typical values are at respective nominal VDD.
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VDD = 3.3 V ±0.3 V (continued)
PARAMETER
TEST CONDITIONS
VDD = min to max,
VOL
IOH
IOL
Low-level output voltage
High-level output current
Low-level output current
VDD = 3 V
MIN
TYP (1)
IOL = –100 µA
MAX
IOL = 12 mA
0.8
IOL = 6 mA
0.55
VDD = 3 V,
VO = 1 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3.6 V,
VO = 3.135 V
VDD = 3 V,
VO = 1.95 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3.6 V,
VO = 0.4 V
UNIT
0.2
V
–28
–36
mA
–14
28
36
mA
14
VDD = 2.5 V ±0.2 V
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
Low-level output voltage
IOH
IOL
(1)
High-level output current
Low-level output current
VDD = min to max,
IOH = –100 µA
VDD = 2.3 V
IOH = –6 mA
VDD = min to max,
IOL = 100 µA
VDD = 2.3 V
IOL = 6 mA
VDD = 2.3 V,
VO = 1 V
VDD = 2.5 V,
VO = 1.25 V
VDD = 2.7 V,
VO = 2.375 V
VDD = 2.3 V,
VO = 1.2 V
VDD = 2.5 V,
VO = 1.25 V
VDD = 2.7 V,
VO = 0.3 V
MIN
TYP (1)
MAX
VDD – 0.2
UNIT
V
1.8
0.2
0.55
V
–17
–25
mA
–10
17
25
mA
10
All typical values are at respective nominal VDD.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
MIN NOM
fclk
Clock frequency
MAX
VDD = 3 V to 3.6 V
0
200
VDD = 2.3 V to 2.7 V
0
170
UNIT
MHz
JITTER CHARACTERISTICS
Characterized using CDCVF2310 Performance EVM when VDD=3.3 V. Outputs not under test are terminated to 50 Ω.
PARAMETER
tjitter
6
TEST CONDITIONS
Additive phase jitter from input to output 1Y0
MIN
TYP
12 kHz to 5 MHz, fout = 30.72 MHz
52
12 kHz to 20 MHz, fout = 125 MHz
45
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MAX
UNIT
fs rms
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SCAS666C – JUNE 2001 – REVISED JANUARY 2008
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
VDD = 3.3 V ±0.3 V (see Figure 2)
PARAMETER
tPLH
TEST CONDITIONS
f = 0 MHz to 200 MHz
For circuit load, see Figure 2.
CLK to Yn
tPHL
MIN
(1)
TYP
1.3
UNIT
2.8
ns
tsk(o)
Output skew (Ym to Yn)
100
ps
tsk(p)
Pulse skew (see Figure 5)
250
ps
tsk(pp)
Part-to-part skew
500
ps
tr
Rise time (see Figure 3)
VO = 0.4 V to 2 V
0.7
2
V/ns
tf
Fall time (see Figure 3)
VO = 2 V to 0.4 V
0.7
2
V/ns
tsu(en)
Enable setup time, G_high before CLK ↓
0.1
ns
tsu(dis)
Disable setup time, G_low before CLK ↓
0.1
ns
th(en)
Enable hold time, G_high after CLK ↓
0.4
ns
th(dis)
Disable hold time, G_low after CLK ↓
0.4
ns
(1)
(see Figure 4)
MAX
The tsk(o) specification is only valid for equal loading of all outputs.
VDD = 2.5 V ±0.2 V (see Figure 2)
PARAMETER
tPLH
TEST CONDITIONS
f = 0 MHz to 170 MHz
For circuit load, see Figure 2.
CLK to Yn
tPHL
MIN
(1)
1.5
MAX
UNIT
3.5
ns
tsk(o)
Output skew (Ym to Yn)
170
ps
tsk(p)
Pulse skew (see Figure 5)
400
ps
tsk(pp)
Part-to-part skew
600
ps
tr
Rise time (see Figure 3)
VO = 0.4 V to 1.7 V
0.5
1.4
V/ns
tf
Fall time (see Figure 3)
VO = 1.7 V to 0.4 V
0.5
1.4
V/ns
tsu(en)
Enable setup time, G_high before CLK ↓
0.1
ns
tsu(dis)
Disable setup time, G_low before CLK ↓
0.1
ns
th(en)
Enable hold time, G_high after CLK ↓
0.4
ns
th(dis)
Disable hold time, G_low after CLK ↓
0.4
ns
(1)
(see Figure 4 )
TYP
The tsk(o) specification is only valid for equal loading of all outputs.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 25 pF on Yn
500 Ω
A.
CL includes probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50 Ω,
tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
VDD
50% VDD
0V
CLK
tPLH
tPHL
1.7 V or 2 V
Yn
0.4 V
0.4 V
tr
VOH
50% VDD
VOL
tf
Figure 3. Voltage Waveforms Propagation Delay Times
VDD
CLK
0V
VOH
50% VDD
Any Y
VOL
VOH
50% VDD
Any Y
VOL
tsk(o)
tsk(o)
Figure 4. Output Skew
VDD
50% VDD
CLK
0V
tPLH
tPHL
VOH
Yn
50% VDD
VOL
NOTE: tsk(p) = | tPLH − tPHL |
Figure 5. Pulse Skew
8
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PARAMETER MEASUREMENT INFORMATION (continued)
SUPPLY CURRENT
vs
FREQUENCY
220
VDD = 2.3 V to 3.6 V
CL(Yn) = 25 pF || 500 Ω
All Outputs Switching
TA = –40°C to 85°C
200
ICC – Supply Current – mA
180
VDD = 3.6 V
TA = –40°C
VDD = 3.6 V
TA = 85°C
160
140
120
100
80
VDD = 2.3 V
TA = 85°C
60
VDD = 2.3 V
TA = –40°C
40
20
0
0
20
40
60
80
100
120
140
160
180
200
f – Frequency – MHz
Figure 6.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CDCVF2310PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
CDCVF2310PWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
CDCVF2310PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
CDCVF2310PWRG4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF CDCVF2310 :
• Enhanced Product: CDCVF2310-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCVF2310PWR
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCVF2310PWR
TSSOP
PW
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
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