HD74AC280/HD74ACT280 9-bit Parity Generator/Checker Description The HD74AC280/HD74ACT280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is High. If an even number of inputs is High, the Sum Even output is High. If an odd number is High, the Sum Even output is Low. The Sum Odd output is the complement of the Sum Even output. Features • Outputs Source/Sink 24 mA • HD74ACT280 has TTL-Cmpatible Inputs Pin Arrangement I6 1 14 VCC I7 2 13 I5 NC 3 12 I4 I8 4 11 I3 ΣE 5 10 I2 ΣO 6 9 I1 GND 7 8 I0 (Top view) HD74AC280/HD74ACT280 Logic Symbol I0 I1 I2 I3 ΣO I4 I5 I6 I7 I8 ΣE Pin Names I0 – I8 O E Data Inputs Odd Parity Output Even Parity Output Truth Table Outputs Number of High Inputs I0 – I 8 ∑ Even ∑ Odd 0, 2, 4, 6, 8 H L 1, 3, 5, 7, 9 L H H : L : 2 High Voltage Level Low Voltage Level HD74AC280/HD74ACT280 Logic Diagram I8 I7 I6 I5 ΣO I4 I3 I2 I1 I0 ΣE Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 HD74AC280/HD74ACT280 DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum ICC/input (HD74ACT280) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V, Ta = Worst case AC Characteristics: HD74AC280 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Propagation delay t PLH 3.3 1.0 14.5 17.0 1.0 18.5 ns 5.0 1.0 11.0 13.0 1.0 14.5 3.3 1.0 14.5 17.0 1.0 18.5 5.0 1.0 11.0 13.0 1.0 14.5 Propagation delay Note: t PHL ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Characteristics: HD74ACT280 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Propagation delay t PLH 5.0 1.0 12.5 15.0 1.0 16.5 ns Propagation delay t PHL 5.0 1.0 12.5 15.0 1.0 16.5 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 60.0 pF VCC = 5.0 V 4 Unit: mm 19.20 20.32 Max 8 6.30 7.40 Max 14 1.30 7 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.39 Max 2.54 Min 5.06 Max 1 7.62 + 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 8 5.5 14 1 0.10 ± 0.10 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7 + 0.20 7.80 – 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 *0.40 ± 0.06 0.11 0.14 +– 0.04 0° – 8° 1.27 0.67 0.60 +– 0.20 0.15 0.25 M *Pd plating Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.83 Max 0.07 +0.03 –0.04 *0.22+0.08 –0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-14D — — 0.05 g Cautions 1. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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