ICSSSTV32852 Integrated Circuit Systems, Inc. DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Supports SSTL_2 class II specifications on inputs and outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 114 ball BGA package. Pin Configuration 1 2 3 4 5 6 A B C D E F G H J Truth Table 1 K L Inputs Q Outputs M RESET# CLK CLK# D Q N L X or Floating X or Floating X or Floating L R H ↑ ↓ H H U H ↑ ↓ L L L or H L or H X H P T V W Q0(2) Notes: 1. 2. 114-Pin Ball BGA H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care Pin Configuration Assignments A B C D E F G Output level before the indicated steady state input conditions were established. Block Diagram CLK CLK# RESET# D1 VREF R Q1A CLK D1 Q1B To 23 Other Channels 0513F—05/13/03 H J K L M N P R T U V W 1 Q2A Q3A Q5A Q7A Q8A Q10A 2 Q1A VDDQ Q4A Q6A GND Q9A Q12A Q13A Q14A Q17A Q18A Q20A Q22A Q23A Q24A D2 D4 D5 D8 Q11A VDD Q15A Q16A Q19A VDDQ Q21A VDDQ VDD D1 D3 D7 D9 3 CLK GND VDDQ GND VDDQ VDDQ 4 CLK# GND VDDQ GND VDDQ VDDQ 5 Q1B VDDQ Q4B Q6B GND Q9B 6 Q2B Q3B Q5B Q7B Q8B Q10B GND GND Q11B Q12B VDDQ GND VDDQ GND GND VDDQ GND RESET# D6 D10 D11 D12 VDDQ GND VDDQ GND GND VDDQ GND VREF D18 D22 D23 D24 VDD Q15B Q16B Q19B VDDQ Q21B VDDQ VDD D13 D15 D19 D21 Q13B Q14B Q17B Q18B Q20B Q22B Q23B Q24B D14 D16 D17 D20 ICSSSTV32852 General Description The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/ O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV32852 supports low-power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during powerup. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic “Low” level during power up. In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power standby state, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level. Pin Configuration PIN NUMBER PIN NAME TYPE DESCRIPTION R1,P1, N1, N2, M1, L2, L1, K1, K2, J2, J1, H1, G1, G2, F1, F2, E1, D1, D2, C1, C2, B1, A1, A2 Q (24:1)A OUTPUT Data output R6, P6, N6, N5, M6, L5, L6, K6, K5, J5, J6, H6, G6, G5, F6, F5, E6, D6, D5, C6, C5, B6, A6, A5 Q (24:1)B OUTPUT Data output E2, B3, D3, G3, J3, L3, M3, P3, B4, D4, G4, J4, L4, M4, P4, E5 GND PWR Ground B2, M2, P2, C3, E3, F3, H3, K3, N3, C4, E4, F4, H4, K4, N4, B5, M5, P5 VDDQ PWR Output supply voltage, 2.5V nominal W4, V4, U4, W5, W6, V5, T4, V6, U6, U5, T6, T5, W3, V3, U3, W2, W1, V2, T3, V1, U1, U2, T1, T2 D (24:1) INPUT Data input A3 CLK INPUT Positive master clock input A4 CLK# INPUT Negative master clock input H2, H5, R2, R5 VDD PWR R3 RESET# INPUT Reset (active low) R4 VREF INPUT Input reference voltage, 1.25V nominal 0513F—05/13/03 2 Core supply voltage, 2.5V nominal ICSSSTV32852 Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD, VDDQ or GND Current/Pin . . . . . . . . . . –65°C to +150°C -0.5 to 3.6V -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 ±50 mA ±50mA ±50mA ±100mA Package Thermal Impedance 3 55°C/W ............... Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAMETER V DD V DDQ VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (DC) VIH VIL VICR VID VIX IOH IOL TA DESCRIPTION Supply Voltage I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET# Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage Cross Point Voltage of Differential Clock Pair High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 1 Guarenteed by design, not 100% tested in production. 0513F—05/13/03 3 MIN 2.3 2.3 1.15 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 TYP 2.5 2.5 1.25 V REF MAX 2.7 2.7 1.35 V REF + 0.04 V DDQ UNITS VREF - 0.15 VREF - 0.31 V 1.7 0.97 0.36 0.7 1.53 (V DDQ/2) - 0.2 (VDDQ/2) + 0.2 0 19 19 70 mA °C ICSSSTV32852 Electrical Characteristics - DC TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL VIK VOH VOL II IDD IDDD rOH rOL rO(D) Ci PARAMETERS CONDITIONS VDDQ II = -18mA IOH = -100µA IOH = -16mA IOL = 100µA IOL = 16mA All Inputs VI = VDD or GND Standby (Static) RESET# = GND VI = VIH(AC) or VIL(AC), Operating (Static) RESET# = VDD RESET# = VDD, Dynamic operating VI = VIH(AC) or VIL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 RESET# = VDD, VI = VIH(AC) or VIL (AC), Dynamic Operating CLK and CLK# switching (per each data input) 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle IOH = -20mA Output High Output Low IOL = 20mA [rOH - rOL] each IO = 20mA, TA = 25°C separate bit Data Inputs VI = VREF ±350mV CLK and CLK# VICR = 1.25V, VI(PP) = 360mV Notes: 1. Guaranteed by design, not 100% tested in production. 0513F—05/13/03 4 2.3V 2.3V - 2.7V 2.3V 2.3V - 2.7V 2.3V 2.7V MIN TYP MAX UNITS -1.2 VDDQ - 0.2 2.05 V 0.2 0.20 ±5 0.01 µA µA 40 mA 35 µA/clock MHz 7 µA/ clock MHz/data 12 10 Ω Ω 2.5V 2.3V - 2.7V 2.3V - 2.7V 2.5V 2.5V 2.5 2.5 4 Ω 3.5 3.5 pF ICSSSTV32852 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) VDD = 2.5V ±0.2V PARAMETERS SYMBOL MIN MAX Clock frequency 200 fclock tPD Clock to output time 1.9 2.7 tRST Reset to output time 4.5 tSL Output slew rate 1 4 2, 4 0.50 Setup time, fast slew rate Data before CLK↑, CLK#↓ tS 0.70 Setup time, slow slew rate 3, 4 Th Notes: Hold time, fast slew rate 2, 4 Data after CLK↑, CLK#↓ Hold time, slow slew rate 3, 4 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns. 0.30 0.50 Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) V DD = 2.5V ±0.2V From To SYMBOL UNITS MIN TYP MAX (Input) (Output) fmax 200 MHz CLK, CLK# Q 1.9 2.7 ns tPD RESET# Q 4.5 ns tphl 0513F—05/13/03 5 UNITS MHz ns ns V/ns ns ns ns ns ICSSSTV32852 VTT RL=50Ω From Output Under Test Test Point CL = 30 pF (see Note 1) Load Circuit LVCMOS RESET# Input VDD VDD/2 VDD/2 tinact VI(pp) 0V Timing Input tact IDD (see note 2) tPHL 90% IDDH 10% VICR VICR IDDL tPHL VTT Voltage and Current Waveforms Inputs Active and Inactive Times VTT VOH VOL Output Voltage Waveforms - Propagation Delay Times tw VIH VREF Input VREF VIL Voltage Waveforms - Pulse Duration LVCMOS RESET# Input VI(pp) Timing Input VIL VICR tPHL tSU Input VIH VDD/2 VREF VOH Output th VTT VOL VIH VREF Voltage Waveforms - Propagation Delay Times VIL Voltage Waveforms - Setup and Hold Times Parameter Measurement Information (VDD = 2.5V ±0.2V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tpd 0513F—05/13/03 6 ICSSSTV32852 D 16.00 Bsc E 5.50 Bsc T Min/Max 1.30/1.50 e 0.80 Bsc ----- BALL GRID ----HORIZ VERT TOTAL 6 19 114 d 0.46 h Min/Max 0.31/0.41 REF. DIMENSIONS b c 0.80 0.75 ALL DIMENSIONS IN MILLIMETERS 10-0055 Ordering Information ICSSSTV32852yHT Example: ICS XXXX y H - T Designation for tape and reel packaging Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0513F—05/13/03 7