2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 FEATURES GENERAL DESCRIPTION AD5330: single 8-bit DAC in 20-lead TSSOP AD5331: single 10-bit DAC in 20-lead TSSOP AD5340: single 12-bit DAC in 24-lead TSSOP AD5341: single 12-bit DAC in 20-lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 × VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Low power parallel data interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input. The AD5330/AD5331/AD5340/AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF. Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control The AD5330/AD5331/AD5340/AD5341 are available in thin shrink small outline packages (TSSOP). 1 Protected by U.S. Patent Number 5,969,657. FUNCTIONAL BLOCK DIAGRAM VREF VDD 3 12 POWER-ON RESET AD5330 BUF 1 INPUT REGISTER DB .. 7 20 DB0 13 CS 6 WR 7 CLR 9 INTERFACE LOGIC GAIN 8 DAC REGISTER 8-BIT DAC RESET BUFFER 4 VOUT POWER-DOWN LOGIC 11 5 PD GND 06852-001 LDAC 10 Figure 1. AD5330 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved. AD5330/AD5331/AD5340/AD5341 TABLE OF CONTENTS Features .............................................................................................. 1 Double-Buffered Interface ........................................................ 18 Applications ....................................................................................... 1 Clear Input (CLR) ...................................................................... 18 General Description ......................................................................... 1 Chip Select Input (CS) ............................................................... 18 Functional Block Diagram .............................................................. 1 Write Input (WR) ....................................................................... 18 Revision History ............................................................................... 2 Load DAC Input (LDAC) .......................................................... 18 Specifications..................................................................................... 3 High-Byte Enable Input (HBEN) ............................................. 18 AC Characteristics........................................................................ 4 Power-On Reset .......................................................................... 18 Timing Characteristics ................................................................ 5 Power-Down Mode ........................................................................ 19 Absolute Maximum Ratings............................................................ 6 Suggested Databus Formats .......................................................... 20 ESD Caution .................................................................................. 6 Applications Information .............................................................. 21 Pin Configurations and Function Descriptions ........................... 7 Typical Application Circuits ..................................................... 21 Terminology .................................................................................... 11 Driving VDD From the Reference Voltage ............................... 21 Typical Performance Characteristics ........................................... 13 Theory of Operation ...................................................................... 17 Bipolar Operation Using the AD5330/AD5331/ AD5340/AD5341 ......................................................................... 21 Digital-to-Analog Section ......................................................... 17 Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21 Resistor String ............................................................................. 17 Programmable Current Source ................................................ 22 DAC Reference Input ................................................................. 17 Power Supply Bypassing and Grounding ................................ 22 Output Amplifier ........................................................................ 17 Outline Dimensions ....................................................................... 24 Parallel Interface ............................................................................. 18 Ordering Guide .......................................................................... 25 REVISION HISTORY 2/08—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Table 4 .......................................................................... 16 Replaced Driving VDD from the Reference Voltage Section ..... 21 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 25 4/00—Revision 0: Initial Version Rev. A | Page 2 of 28 AD5330/AD5331/AD5340/AD5341 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter DC PERFORMANCE 3, 4 AD5330 Resolution Relative Accuracy Differential Nonlinearity AD5331 Resolution Relative Accuracy Differential Nonlinearity AD5340/AD5341 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband 5 Upper Deadband Offset Error Drift 6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DAC REFERENCE INPUT6 VREF Input Range Min Conditions/Comments 8 ±0.15 ±0.02 ±1 ±0.25 Bits LSB LSB Guaranteed monotonic by design over all codes ±4 ±0.5 Bits LSB LSB Guaranteed monotonic by design over all codes 12 ±2 ±0.2 ±0.4 ±0.15 10 10 −12 −5 −60 1 0.25 Reference Feedthrough OUTPUT CHARACTERISTICS6 Minimum Output Voltage4, 7 Maximum Output Voltage4, 7 DC Output Impedance Short-Circuit Current Power-Up Time LOGIC INPUTS6 Input Current Input Low Voltage, VIL Pin Capacitance Unit 10 ±0.5 ±0.05 VREF Input Impedance Input High Voltage, VIH B Version 2 Typ Max ±16 ±1 ±3 ±1 60 60 VDD VDD Bits LSBs LSB % of FSR % of FSR mV mV ppm of FSR/°C ppm of FSR/°C dB Guaranteed monotonic by design over all codes Lower deadband exists only if offset error is negative VDD = 5 V; upper deadband exists only if VREF = VDD ΔVDD = ±10% >10 180 90 −90 V V MΩ kΩ kΩ dB Buffered reference (AD5330, AD5340, and AD5341) Unbuffered reference Buffered reference (AD5330, AD5340, and AD5341) Unbuffered reference; gain = 1, input impedance = RDAC Unbuffered reference; gain = 2, input impedance = RDAC Frequency = 10 kHz 0.001 VDD − 0.001 0.5 25 15 2.5 5 V min V max Ω mA mA μs μs Rail-to-rail operation ±1 0.8 0.6 0.5 2.4 2.1 2.0 3 μA V V V V V V pF Rev. A | Page 3 of 28 VDD = 5 V VDD = 3 V Coming out of power-down mode; VDD = 5 V Coming out of power-down mode; VDD = 3 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V AD5330/AD5331/AD5340/AD5341 1 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V Min B Version 2 Typ Max 2.5 Unit 5.5 V 140 115 250 200 μA μA 0.2 0.08 1 1 μA μA Conditions/Comments DACs active and excluding load currents. Unbuffered Reference, VIH = VDD, VIL = GND IDD increases by 50 μA at VREF > VDD − 100 mV. In buffered mode, extra current is (5 + VREF/RDAC) μA, where RDAC is the resistance of the resistor string. 1 See the Terminology section. Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C. Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095). 4 DC specifications tested with output unloaded. 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 2 3 AC CHARACTERISTICS 1 VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 2 Parameter Output Voltage Settling Time AD5330 AD5331 AD5340 AD5341 Slew Rate Major Code Transition Glitch Energy Digital Feedthrough Multiplying Bandwidth Total Harmonic Distortion B Version 3 Min Typ Max Unit 6 7 8 8 0.7 6 0.5 200 −70 μs μs μs μs V/μs nV/s nV/s kHz dB 8 9 10 10 Conditions/Comments VREF = 2 V; see Figure 29 ¼ scale to ¾ scale change (0x40 to 0xC0) ¼ scale to ¾ scale change (0x100 to 0x300) ¼ scale to ¾ scale change (0x400 to 0xC00) ¼ scale to ¾ scale change (0x400 to 0xC00) 1 LSB change around major carry VREF = 2 V ± 0.1 V p-p; unbuffered mode VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz 1 Guaranteed by design and characterization, not production tested. See the Terminology section. 3 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C. 2 Rev. A | Page 4 of 28 AD5330/AD5331/AD5340/AD5341 TIMING CHARACTERISTICS 1, 2, 3 VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 Limit at TMIN, TMAX 0 Unit ns min Condition/Comments CS to WR setup time. t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 0 20 5 4.5 5 5 4.5 5 4.5 20 20 50 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min CS to WR hold time. WR pulse width. Data, GAIN, BUF, HBEN setup time. Data, GAIN, BUF, HBEN hold time. Synchronous mode; WR falling to LDAC falling. Synchronous mode; LDAC falling to WR rising. Synchronous mode; WR rising to LDAC rising. Asynchronous mode; LDAC rising to WR rising. Asynchronous mode; WR rising to LDAC falling. LDAC pulse width. CLR pulse width. Time between WR cycles. 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. 2 t1 t2 CS t3 t13 WR t4 DATA, GAIN, BUF, HBEN t6 t7 t5 t8 LDAC1 t9 t10 t11 LDAC2 t12 NOTES: 1SYNCHRONOUS LDAC UPDATE MODE 2ASYNCHRONOUS LDAC UPDATE MODE Figure 2. Parallel Interface Timing Diagram Rev. A | Page 5 of 28 06852-002 CLR AD5330/AD5331/AD5340/AD5341 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND VOUT to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature TSSOP Package Power Dissipation θJA Thermal Impedance (20-Lead TSSOP)1 θJA Thermal Impedance (24-Lead TSSOP)1 Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +105°C −65°C to +150°C 150°C (TJ max – TA)/θJA mW 85°C/W 80°C/W 260°C 20 sec to 40 sec Thermal resistance (JEDEC 4-layer (2S2P) board). Rev. A | Page 6 of 28 AD5330/AD5331/AD5340/AD5341 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VREF VDD 3 12 POWER-ON RESET AD5330 INPUT REGISTER CS 6 WR 7 CLR 9 INTERFACE LOGIC DB .. 7 20 DB0 13 DAC REGISTER 8-BIT DAC BUFFER 4 VOUT BUF 1 20 DB7 NC 2 19 DB6 VREF 3 VOUT 4 GND 5 CS 6 RESET POWER-DOWN LOGIC 11 5 PD GND Figure 3. AD5330 Functional Block Diagram 06852-003 LDAC 10 18 DB5 8-BIT 17 DB4 TOP VIEW (Not to Scale) 16 DB3 AD5330 15 DB2 WR 7 14 DB1 GAIN 8 13 DB0 CLR 9 12 V DD LDAC 10 11 PD NC = NO CONNECT Figure 4. AD5330 Pin Configuration Table 5. AD5330 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Mnemonic BUF NC VREF VOUT GND CS WR GAIN CLR LDAC PD VDD 13 to 20 DB0 to DB7 Description Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. No Connect. Reference Input. Output of DAC. Buffered output with rail-to-rail operation. Ground reference point for all circuitry on the part. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. Rev. A | Page 7 of 28 06852-004 BUF 1 GAIN 8 AD5330/AD5331/AD5340/AD5341 VREF VDD 3 12 POWER-ON RESET AD5331 DB8 1 CS 6 WR 7 CLR 9 INPUT REGISTER DAC REGISTER 10-BIT DAC BUFFER 4 VOUT DB8 1 20 DB7 DB9 2 19 DB6 VREF 3 VOUT 4 GND 5 RESET CS 6 POWER-DOWN LOGIC 11 5 PD GND Figure 5. AD5331 Functional Block Diagram 06852-005 LDAC 10 18 DB5 10-BIT 17 DB4 TOP VIEW (Not to Scale) 16 DB3 AD5331 15 DB2 WR 7 14 DB1 GAIN 8 13 DB0 CLR 9 12 V DD LDAC 10 11 PD Figure 6. AD5331 Pin Configuration Table 6. AD5331 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Mnemonic DB8 DB9 VREF VOUT GND CS WR GAIN CLR LDAC PD VDD 13 to 20 DB0 to DB7 Description Parallel Data Input. Most Significant Bit of Parallel Data Input. Unbuffered Reference Input. Output of DAC. Buffered output with rail-to-rail operation. Ground reference point for all circuitry on the part. Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. Active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Eight Parallel Data Inputs. Rev. A | Page 8 of 28 06852-006 DB .. 7 20 DB0 13 INTERFACE LOGIC DB9 2 GAIN 8 AD5330/AD5331/AD5340/AD5341 VREF VDD 4 14 POWER-ON RESET AD5340 DB11 2 GAIN 10 DB .. 9 24 DB0 15 CS 8 WR 9 INTERFACE LOGIC BUF 3 CLR 11 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER RESET 5 VOUT POWER-DOWN LOGIC 13 PD Figure 7. AD5340 Functional Block Diagram 7 GND 06852-007 LDAC 12 DB10 1 24 DB9 DB11 2 23 DB8 BUF 3 22 DB7 VREF 4 21 DB6 VOUT 5 20 DB5 NC 6 19 DB4 GND 7 18 DB3 CS 8 17 DB2 WR 9 16 DB1 GAIN 10 15 DB0 CLR 11 14 VDD LDAC 12 13 PD 12-BIT AD5340 TOP VIEW (Not to Scale) Figure 8. AD5340 Pin Configuration Table 7. AD5340 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic DB10 DB11 BUF VREF VOUT NC GND Description Parallel Data Input. Most Significant Bit of Parallel Data Input. Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. Reference Input. Output of DAC. Buffered output with rail-to-rail operation. No Connect. Ground reference point for all circuitry on the part. 8 9 10 11 12 13 14 CS WR GAIN CLR LDAC PD VDD 15 to 24 DB0 to DB9 Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Ten Parallel Data Inputs. Rev. A | Page 9 of 28 06852-008 DB10 1 AD5330/AD5331/AD5340/AD5341 VREF VDD 3 12 POWER-ON RESET HBEN 1 CS 6 WR 7 LOW BYTE REGISTER 20 DB7 HBEN 1 12-BIT DAC BUFFER 4 VOUT BUF VREF 3 VOUT 4 GND RESET 5 CS 6 POWER-DOWN LOGIC 19 DB6 2 18 DB5 10-BIT 17 DB4 TOP VIEW (Not to Scale) 16 DB3 AD5341 15 DB2 14 DB1 CLR 9 GAIN 8 13 DB 0 LDAC 10 CLR 9 12 V DD 11 5 PD GND Figure 9. AD5341 Functional Block Diagram 06852-009 WR 7 LDAC 10 11 PD Figure 10. AD5341 Pin Configuration Table 8. AD5341 Pin Function Descriptions Pin No. 1 Mnemonic HBEN 2 3 4 5 6 7 8 9 10 11 12 BUF VREF VOUT GND CS WR GAIN CLR LDAC PD VDD 13 to 20 DB0 to DB7 Description High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. Reference Input. Output of DAC. Buffered output with rail-to-rail operation. Ground reference point for all circuitry on the part. Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. Rev. A | Page 10 of 28 06852-010 DB .. 7 20 DB0 13 INTERFACE LOGIC GAIN 8 DAC REGISTER HIGH BYTE REGISTER BUF 2 AD5341 AD5330/AD5331/AD5340/AD5341 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 14, Figure 15, and Figure 16. OUTPUT VOLTAGE ACTUAL IDEAL POSITIVE OFFSET Gain Error This is a measure of the span error of the DAC (including any error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. This is illustrated in Figure 11. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage is still positive at zero input code. This is shown in Figure 12. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code, there is a deadband over which the output voltage does not change. This is illustrated in Figure 13. 06852-012 Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 17, Figure 18, and Figure 19. GAIN ERROR AND OFFSET ERROR DAC CODE Figure 12. Positive Offset Error and Gain Error GAIN ERROR AND OFFSET ERROR OUTPUT VOLTAGE ACTUAL IDEAL NEGATIVE OFFSET DAC CODE POSITIVE GAIN ERROR NEGATIVE GAIN ERROR DEADBAND CODES OUTPUT VOLTAGE AMPLIFIER FOOTROOM (~1mV) ACTUAL IDEAL Figure 11. Gain Error Rev. A | Page 11 of 28 06852-013 DAC CODE 06852-011 NEGATIVE OFFSET Figure 13. Negative Offset Error and Gain Error AD5330/AD5331/AD5340/AD5341 Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Power-Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2 V and VDD is varied ±10%. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV/s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 … 11 to 100 … 00 or 100 … 00 to 011 … 11). Digital Feedthrough Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device; it is measured when the DAC is not being written to (CS held high). It is specified in nV/s and is measured with a fullscale change on the digital input pins, that is, from all 0s to all 1s and vice versa. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with a full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Rev. A | Page 12 of 28 AD5330/AD5331/AD5340/AD5341 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 1.0 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSBs) INL ERROR (LSBs) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 250 CODE –0.3 06852-015 0 150 200 250 800 1000 Figure 17. AD5330 Typical DNL Plot 3 0.6 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 2 0.4 DNL ERROR (LSBs) INL ERROR (LSBs) 100 CODE Figure 14. AD5330 Typical INL Plot 1 0 –1 –2 0.2 0 –0.2 –0.4 0 200 400 500 800 1000 CODE –0.6 06852-016 –3 50 0 200 400 600 CODE Figure 15. AD5331 Typical INL Plot 06852-019 –1.0 06852-018 –0.2 Figure 18. AD5331 Typical DNL Plot 12 1.0 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 8 DNL ERROR (LSBs) 0 –4 0 –0.5 –12 0 1000 2000 3000 CODE 4000 Figure 16. AD5340/AD5341 Typical INL Plot –1.0 0 1000 2000 3000 CODE Figure 19. AD5340/AD5341 Typical DNL Plot Rev. A | Page 13 of 28 4000 06852-020 –8 06852-017 INL ERROR (LSBs) 0.5 4 AD5330/AD5331/AD5340/AD5341 0.2 TA = 25°C VDD = 5V 0.75 GAIN ERROR 0 0.25 ERROR (%) MAX INL MAX DNL 0 MIN DNL –0.25 MIN INL –0.1 –0.2 –0.3 –0.50 –0.4 –0.75 –0.5 2 3 4 5 VREF (V) –0.6 06852-021 ERROR (LSBs) 0.50 –1.00 TA = 25°C VREF = 2V 0.1 OFFSET ERROR 0 0.75 2 3 4 5 6 VDD (V) Figure 20. AD5330 INL and DNL Error vs. VREF 1.00 1 06852-024 1.00 Figure 23. Offset Error and Gain Error vs. VDD 5 VDD = 5V VREF = 3V 5V SOURCE 4 0.50 3V SOURCE MAX INL VOUT (V) ERROR (LSBs) MAX DNL 0.25 0 –0.25 3 2 MIN DNL MIN INL –0.50 1 3V SINK 5V SINK 0 40 80 120 TEMPERATURE (°C) 0 06852-022 –1.00 –40 0 2 3 4 5 6 SINK/SOURCE CURRENT (mA) Figure 21. AD5330 INL Error and DNL Error vs. Temperature 1.0 1 06852-025 –0.75 Figure 24. VOUT Source and Sink Current Capability 300 VDD = 5V VREF = 2V TA = 25°C VREF = 2V 250 VDD = 5.5V 200 IDD (µA) GAIN ERROR 0 150 VDD = 3.6V 100 OFFSET ERROR –0.5 –1.0 –40 0 40 80 120 TEMPERATURE (°C) Figure 22. AD5330 Offset Error and Gain Error vs. Temperature 0 ZERO-SCALE FULL-SCALE DAC CODE Figure 25. Supply Current vs. DAC Code Rev. A | Page 14 of 28 06852-026 50 06852-023 ERROR (%) 0.5 AD5330/AD5331/AD5340/AD5341 300 TA = 25°C TA = 25°C VDD = 5V CH2 5V CLK IDD (µA) 200 VOUT 100 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Figure 26. Supply Current vs. Supply Voltage TIME BASE = 5µs/DIV 06852-030 0 2.5 06852-027 CH1 1V Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change) 0.5 TA = 25°C TA = 25°C VDD = 5V VREF = 2V 0.4 IDD (µA) CH1 2V VDD 0.3 0.2 VOUTA 0.1 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) TIME BASE = 200µs/DIV Figure 27. Power-Down Current vs. Supply Voltage 06852-031 0 2.5 06852-028 CH2 200mV Figure 30. Power-On Reset to 0 V 1800 TA = 25°C 1600 TA = 25°C VDD = 5V VREF = 2V 1400 CH1 500mV 1200 VOUTA 800 600 PD 400 0 VDD = 3V 0 1 2 3 4 VLOGIC (V) 5 Figure 28. Supply Current vs. Logic Input Voltage TIME BASE = 1µs/DIV Figure 31. Exiting Power-Down to Midscale Rev. A | Page 15 of 28 06852-032 200 CH2 5V 06852-029 IDD (µA) VDD = 5V 1000 AD5330/AD5331/AD5340/AD5341 10 0 –10 FREQUENCY VDD = 3V VDD = 5V (dB) –20 –30 –40 90 100 110 120 130 140 150 160 170 180 190 200 IDD (µA) –60 0.01 06852-033 80 1 10 100 1k 10k FREQUENCY (kHz) Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 34. Multiplying Bandwidth (Small-Signal Frequency Response) 0.4 0.917 TA = 25°C VDD = 5V 0.916 FULL-SCALE ERROR (%FSR) 0.915 0.914 0.913 0.912 0.911 0.910 0.909 0.908 0.907 0.2 0 0.906 0.904 0.903 250ns/DIV Figure 33. AD5340 Major-Code Transition Glitch Energy –0.2 0 1 2 3 VREF (V) Figure 35. Full-Scale Error vs. VREF Rev. A | Page 16 of 28 4 5 06852-036 0.905 06852-034 VOLTS 0.1 06852-035 –50 AD5330/AD5331/AD5340/AD5341 THEORY OF OPERATION VREF The AD5330/AD5331/AD5340/AD5341 are single resistorstring DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers offer rail-to-rail output swing. The AD5330, AD5340, and AD5341 have a reference input that can be buffered to draw virtually no current from the reference source. The reference input of the AD5331 is unbuffered. The devices have a power-down feature that reduces current consumption to only 80 nA @ 3 V. R R R R The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 36 shows a block diagram of the DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by D × Gain 2N where: D is the decimal equivalent of the binary code, which is loaded to the DAC register: 0 to 255 for AD5330 (8 Bits) 0 to 1023 for AD5331 (10 Bits) 0 to 4095 for AD5340/AD5341 (12 Bits) VREF DAC REFERENCE INPUT There is a reference input pin for the DAC. The reference input is buffered on the AD5330, AD5340, and AD5341 but can be configured as unbuffered also. The reference input of the AD5331 is unbuffered. The buffered/unbuffered option is controlled by the BUF pin. In buffered mode (BUF = 1), the current drawn from an external reference voltage is virtually zero because the impedance is at least 10 MΩ. The reference input range is 1 V to 5 V with a 5 V supply. BUF REFERENCE BUFFER OUTPUT AMPLIFIER GAIN RESISTOR STRING VOUT OUTPUT BUFFER AMPLIFIER 06852-037 DAC REGISTER Figure 37. Resistor String In unbuffered mode (BUF = 0), the user can have a reference voltage as low as 0.25 V and as high as VDD because there is no restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 180 kΩ for 0 V to VREF mode and 90 kΩ for 0 V to 2 × VREF mode. If there is an external buffered reference (for example, REF192), there is no need to use the on-chip buffer. N is the DAC resolution. Gain is the output amplifier gain (1 or 2). INPUT REGISTER 06852-038 DIGITAL-TO-ANALOG SECTION VOUT = V REF × TO OUTPUT AMPLIFIER R Figure 36. Single DAC Channel Architecture RESISTOR STRING The resistor-string section is shown in Figure 37. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on VREF, GAIN, the load on VOUT, and offset error. If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 × VREF. However, because of clamping, the maximum output is limited to VDD – 0.001 V. The output amplifier is capable of driving a load of 2 kΩ to GND or 2 kΩ to VDD in parallel with 500 pF to GND or 500 pF to VDD. The source and sink capabilities of the output amplifier can be seen in Figure 24. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs with the output unloaded (see Figure 29). Rev. A | Page 17 of 28 AD5330/AD5331/AD5340/AD5341 PARALLEL INTERFACE DOUBLE-BUFFERED INTERFACE The AD5330/AD5331/AD5340/AD5341 DACs all have doublebuffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the input register under the control of chip select (CS) and write (WR). Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are only updated when LDAC is taken low. Double-buffering is also useful where the DAC data is loaded in two bytes, as in the AD5341, because it allows the whole data word to be assembled in parallel before updating the DAC register. This prevents spurious outputs that can occur if the DAC register is updated with only the high byte or the low byte. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC register is filled with the contents of the input register. In the case of the AD5330/ AD5331/AD5340/AD5341, the parts only update the DAC register if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk. LOAD DAC INPUT (LDAC) LDAC transfers data from the input register to the DAC register (and therefore updates the outputs). Use of the LDAC function enables double-buffering of the DAC data, GAIN, and BUF. There are two LDAC modes: synchronous mode and asynchronous mode. In synchronous mode, the DAC register is updated after new data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed, as shown in Figure 2. In asynchronous mode, the outputs are not updated at the same time that the input register is written to. When LDAC goes low, the DAC register is updated with the contents of the input register. HIGH BYTE ENABLE INPUT (HBEN) High byte enable is a control input on the AD5341 only. It determines if data is written to the high byte input register or the low byte input register. The low data byte of the AD5341 consists of Data Bits [0:7] at the data inputs DB0 to DB7, whereas the high byte consists of Data Bits [8:11] at the data inputs DB0 to DB3, as shown in Figure 38. DB4 to DB7 are ignored during a high byte write, but they can be used for data to set up the reference input as buffered/ unbuffered, and buffer amplifier gain (see Figure 42). HIGH BYTE X X DB7 DB6 X X DB11 DB10 DB9 DB8 DB2 DB1 DB0 LOW BYTE DB5 DB4 DB3 X = UNUSED BIT 06852-039 The AD5330, AD5331, and AD5340 load their data as a single 8-, 10-, or 12-bit word, while the AD5341 loads data as a low byte of eight bits and a high byte containing four bits. Figure 38. Data Format for AD5341 CLEAR INPUT (CLR) CLR is an active low, asynchronous clear that resets the input and DAC registers. CHIP SELECT INPUT (CS) CS is an active low input that selects the device. WRITE INPUT (WR) WR is an active low input that controls writing of data to the device. Data is latched into the input register on the rising edge of WR. POWER-ON RESET The AD5330/AD5331/AD5340/AD5341 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is • • • • Normal operation Reference input unbuffered 0 V to VREF output range Output voltage set to 0 V Both input and DAC registers are filled with zeros and remain as such until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. Rev. A | Page 18 of 28 AD5330/AD5331/AD5340/AD5341 POWER-DOWN MODE When the PD pin is high, the DAC works normally with a typical power consumption of 140 μA at 5 V (115 μA at 3 V). In power-down mode, however, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when the DAC is powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 39. RESISTOR STRING DAC AMPLIFIER POWER-DOWN CIRCUITRY Figure 39. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when VDD = 3 V. This is the time from a rising edge on the PD pin to when the output voltage deviates from its power-down voltage (see Figure 31). Table 9. AD5330/AD5331/AD5340 Truth Table1 CLR LDAC CS WR Function 1 1 0 1 1 1 1 1 X 1 0 0 1 X X 0 0 X X 1 X 0→1 0→1 X No data transfer No data transfer Clear all registers Load input register Load input register and DAC register Update DAC register 1 X = don’t care. Table 10. AD5341 Truth Table1 CLR LDAC CS WR HBEN Function 1 1 0 1 1 1 1 1 1 1 X 1 1 0 0 0 1 X X 0 0 0 0 X X 1 X 0→1 0→1 0→1 0→1 X X X X 0 1 0 1 X No data transfer No data transfer Clear all registers Load low byte input register Load high byte input register Load low byte input register and DAC register Load high byte input register and DAC register Update DAC register 1 VOUT 06852-040 The AD5330/AD5331/AD5340/AD5341 have low power consumption, dissipating only 0.35 mW with a 3 V supply and 0.7 mW with a 5 V supply. Power consumption can be further reduced when the DAC is not in use by putting it into powerdown mode, which is selected by taking Pin PD low. X = don’t care. Rev. A | Page 19 of 28 AD5330/AD5331/AD5340/AD5341 SUGGESTED DATABUS FORMATS The AD5341 is a 12-bit device that uses byte load, so only four bits of the high byte are actually used as data. Two of the unused bits can be used for GAIN and BUF data by connecting them to the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as shown in Figure 41 and Figure 42. 8-BIT DATA BUS DB6 DB7 BUF GAIN X X X X X X DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AD5331 BUF GAIN X X X X DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 06852-041 AD5340 BUF GAIN X X DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X = UNUSED BIT CLR CS WR HBEN Figure 41. AD5341 Data Format for Byte Load with GAIN and BUF Data on 8-Bit Bus In this case, the low byte is written to first in a write operation with HBEN = 0. Bit 6 and Bit 7 of DAC data are written into GAIN and BUF registers but have no effect. The high byte is then written to. Only the lower four bits of data are written into the DAC high byte register, so Bit 6 and Bit 7 can be GAIN and BUF data. LDAC is used to update the DAC, GAIN, and BUF values. BUF GAIN DB7 DB6 Figure 40. GAIN and BUF Data on a 16-Bit Bus X DB5 HIGH BYTE X DB11 LOW BYTE DB4 DB3 DB10 DB9 DB8 DB2 DB1 DB0 X = UNUSED BIT Figure 42. AD5341 with GAIN and BUF Data on 8-Bit Bus Rev. A | Page 20 of 28 06852-043 AD5330 BUF GAIN AD5341 LDAC In the case of the AD5330, this means that the databus must be wider than eight bits. The AD5331 and AD5340 databuses must be at least 10 bits and 12 bits wide, respectively, and are best suited to a 16-bit databus system. Examples of data formats for putting GAIN and BUF on a 16-bit databus are shown in Figure 40. Note that any unused bits above the actual DAC data can be used for BUF and GAIN. DAC devices can be controlled using common GAIN and BUF lines. DATA INPUTS 06852-042 In most applications, GAIN and BUF are hard-wired. However, if more flexibility is required, they can be included in a databus. This enables the user to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system, GAIN and BUF can be treated as data inputs because they are written to the device during a write operation and take effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines. AD5330/AD5331/AD5340/AD5341 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUITS The AD5330/AD5331/AD5340/AD5341 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices can be used with a fixed, precision reference voltage. Figure 43 shows a typical setup for the devices when using an external reference connected to the unbuffered reference inputs. If the reference inputs are unbuffered, the reference input range is from 0.25 V to VDD, but if the on-chip reference buffers are used, the reference range is reduced. Suitable references for 5 V operation are the AD780 and REF192. For 2.5 V operation, a suitable external reference is the AD589, a 1.23 V band gap reference. VDD = 2.5V TO 5.5V VOUT VREF GND The output voltage for any input code can be calculated as follows: VO = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] – R4 × VREF/R3 where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. VREF is the reference voltage input. with: VREF = 2.5 V. R1 = R3 = 10 kΩ. R2 = R4 = 20 kΩ and VDD = 5 V. VO = (10 × D/2N) − 5. 10µF VIN VDD VOUT AD5330/AD5331/ AD5340/AD5341 AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V VDD = 5V 0.1µF GND 06852-044 EXT REF The AD5330/AD5331/AD5340/AD5341 are designed for single-supply operation, but bipolar operation is achievable using the circuit shown in Figure 45. The circuit shown has been configured to achieve an output voltage range of –5 V < VO < +5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier. Figure 43. AD5330/AD5331/AD5340/AD5341 Using External Reference EXT REF 0.1µF + 10µF VDD VREF VOUT AD5330/AD5331/ AD5340/AD5341 GND Figure 44. Using an ADP667 as Power and Reference to AD5330/AD5331/AD5340/AD5341 06852-045 0.1µF AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V 0.1µF VREF VDD AD5330/AD5331/ AD5340/AD5341 VOUT –5V R1 10kΩ R2 20kΩ GND Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341 The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and WR pulses, but only CS to one of the DACs is active at any one time, so data is only written to the DAC whose CS is low. If multiple AD5341s are being used, a common HBEN line is also required to determine if the data is written to the high byte or low byte register of the selected DAC. ADP667 VSET GND SHDN VO = ±5V VOUT DECODING MULTIPLE AD5330/AD5331/ AD5340/AD5341 VIN VOUT +5V R3 10kΩ GND 6V TO 16V R4 20kΩ 10µF VIN DRIVING VDD FROM THE REFERENCE VOLTAGE If an output range of 0 V to VDD is required, the simplest solution is to connect the reference inputs to VDD. Because this supply may not be very accurate and may be noisy, the devices can be powered from the reference voltage, for example using a 5 V reference such as the ADP667, as shown in Figure 44. + 06852-046 + 0.1µF BIPOLAR OPERATION USING THE AD5330/AD5331/ AD5340/AD5341 The 74HC139 is used as a 2-line to 4-line decoder to address any of the DACs in the system. To prevent timing errors, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 46 shows a diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in Rev. A | Page 21 of 28 AD5330/AD5331/AD5340/AD5341 VDD = 5V a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to reset all DAC outputs to zero. 0.1µF VSOURCE EXT REF DATA INPUTS GND AD780/REF192 WITH VDD = 5V CODED ADDRESS G1 74HC139 1Y0 A1 1Y1 B1 1Y2 1Y3 DGND AD820/ OP295 POWER SUPPLY BYPASSING AND GROUNDING DATA INPUTS 06852-047 DATA INPUTS *AD5341 ONLY Figure 46. Decoding Multiple DAC Devices PROGRAMMABLE CURRENT SOURCE Figure 47 shows the AD5330/AD5331/AD5340/AD5341 used as the control element of a programmable current source. In this example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, which gives an adjustment of about ±5%. Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having rail-to-rail operation on their outputs. The current for any digital input code and resistor value can be calculated as follows: I = G × VREF × AD5330/AD5331/ AD5340/AD5341 Figure 47. Programmable Current Source AD5330/AD5331/ AD5340/AD5341 HBEN* WR LDAC CLR CS LOAD 470Ω AD5330/AD5331/ AD5340/AD5341 HBEN* WR LDAC CLR CS 5V VOUT DATA INPUTS VCC ENABLE VDD GND DATA BUS VDD 0.1µF VREF 4.7kΩ AD5330/AD5331/ AD5340/AD5341 HBEN* WR LDAC CLR CS VOUT D mA (2 × R) N where: G is the gain of the buffer amplifier (1 or 2). D is the digital equivalent of the digital input code. N is the DAC resolution (8, 10, or 12 bits). R is the sum of the resistor plus adjustment potentiometer in kilo ohms. 06852-048 HBEN* WR LDAC CLR CS 10µF VIN AD5330/AD5331/ AD5340/AD5341 HBEN* WR LDAC CLR + In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5330/AD5331/AD5340/AD5341 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the device is in a system where multiple devices require an AGNDto-DGND connection, the connection should be made at one point only. The star ground point should be established as closely as possible to the device. The AD5330/AD5331/ AD5340/AD5341 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. Rev. A | Page 22 of 28 AD5330/AD5331/AD5340/AD5341 Table 11. Overview of AD53xx Parallel Devices Additional Pin Functions Part No. Singles AD5330 AD5331 AD5340 AD5341 Resolution Bits DNL No. of VREF Pins Settling Time BUF GAIN 8 10 12 12 ±0.25 ±0.5 ±1.0 ±1.0 1 1 1 1 6 μs 7 μs 8 μs 8 μs BUF BUF BUF GAIN GAIN GAIN GAIN Duals AD5332 AD5333 AD5342 AD5343 8 10 12 12 ±0.25 ±0.5 ±1.0 ±1.0 2 2 2 1 6 μs 7 μs 8 μs 8 μs BUF BUF GAIN GAIN Quads AD5334 AD5335 AD5336 AD5344 8 10 10 12 ±0.25 ±0.5 ±0.5 ±1.0 2 2 4 4 6 μs 7 μs 7 μs 8 μs HBEN CLR Package No. of Pins HBEN CLR CLR CLR CLR TSSOP TSSOP TSSOP TSSOP 20 20 24 20 HBEN CLR CLR CLR CLR TSSOP TSSOP TSSOP TSSOP 20 24 28 20 CLR CLR CLR TSSOP TSSOP TSSOP TSSOP 24 24 28 28 GAIN HBEN GAIN Table 12. Overview of AD53xx Serial Devices Part No. Singles AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 Resolution Bits No. of DACs DNL Interface Settling Time Package No of Pins 8 10 12 8 10 12 1 1 1 1 1 1 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI 2-Wire 2-Wire 2-Wire 4 μs 6 μs 8 μs 6 μs 7 μs 8 μs SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 Duals AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 8 10 12 8 10 12 2 2 2 2 2 2 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI SPI SPI SPI 6 μs 7 μs 8 μs 6 μs 7 μs 8 μs MSOP MSOP MSOP TSSOP TSSOP TSSOP 10 10 10 16 16 16 Quads AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 8 10 12 8 10 12 8 10 12 8 10 12 4 4 4 4 4 4 4 4 4 4 4 4 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI 6 μs 7 μs 8 μs 6 μs 7 μs 8 μs 6 μs 7 μs 8 μs 6 μs 7 μs 8 μs MSOP, LFCSP MSOP, LFCSP MSOP, LFCSP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP 10 10 10 10 10 10 16 16 16 16 16 16 Rev. A | Page 23 of 28 AD5330/AD5331/AD5340/AD5341 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 6.40 BSC 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters Rev. A | Page 24 of 28 AD5330/AD5331/AD5340/AD5341 ORDERING GUIDE Model AD5330BRU AD5330BRU-REEL AD5330BRU-REEL7 AD5330BRUZ 1 AD5330BRUZ-REEL1 AD5330BRUZ-REEL71 AD5331BRU AD5331BRU-REEL AD5331BRU-REEL7 AD5331BRUZ1 AD5331BRUZ-REEL1 AD5331BRUZ-REEL71 AD5340BRU AD5340BRU-REEL AD5340BRU-REEL7 AD5340BRUZ1 AD5340BRUZ-REEL1 AD5340BRUZ-REEL71 AD5341BRU AD5341BRU-REEL AD5341BRU-REEL7 AD5341BRUZ1 AD5341BRUZ-REEL1 AD5341BRUZ-REEL71 1 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] Z = RoHS Compliant Part. Rev. A | Page 25 of 28 Package Option RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 AD5330/AD5331/AD5340/AD5341 NOTES Rev. A | Page 26 of 28 AD5330/AD5331/AD5340/AD5341 NOTES Rev. A | Page 27 of 28 AD5330/AD5331/AD5340/AD5341 NOTES ©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06852-0-2/08(A) Rev. A | Page 28 of 28