MSU2051/U2031
MOSEL VITELIC
Product List
MSU2031L16, low working voltage 16 MHz ROM less MCU
MSU2031S16, small sink current 16 MHz ROM less MCU
MSU2031C16, 16 MHz ROM less MCU
MSU2031C25, 25 MHz ROM less MCU
MSU2031C40, 40 MHz ROM less MCU
MSU2051L16, low working voltage 16 MHz 4 KB internal ROM MCU
MSU2051S16, small sink current 16 MHz 4 KB internal ROM MCU
MSU2051C16, 16 MHz 4 KB internal ROM MCU
MSU2051C25, 25 MHz 4 KB internal ROM MCU
MSU2051C40, 40 MHz 4 KB internal ROM MCU
Description
Features
Working voltage : L series at 2.7V through 4.5V
while S & C series at 4.5 V through 5.5 V
General 80C51 family compatible
64 K byte External Memory Space
4 K byte ROM
128 byte data RAM
Two 16 bit Timers/Counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Working at 16/25/40 MHz Clock
The MVI MSU2051 series product is an 8 - bit
single chip microcontroller. It provides hardware
features and a powerful instruction set,
necessary to make it a versatile and cost
effective controller for those applications
demand up to 32 I/O pins or need up to 64 K
byte external memory either for program or for
data or mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications,
and full duplex UART.
Ordering Information
MSU2031ihhk
MSU2051ihh - yyyk
i: process identifier {S, L, C}.
hh: working clock in MHz {16, 25, 40}.
yyy: production code {001, ..., 999}
k: package type postfix {as below table}.
Postfix
blank
Package
dice
Pin/Pad
Configuration
Dimension
Logo Size at
Top Marking
page 18
page 18
-
P
40L PDIP
page 2
page 14
5.0 x 4.2 mm
J
44L PLCC
page 2
page 15
4.5 x 3.8 mm
Q
44L PQFP
page 2
page 16
2.8 x 2.4 mm
U
44L LQFP
page 2
page 17
2.8 x 2.4 mm
Cross Reference
M.V.I.
W.B.
MSU2051
W78C51
MSU2031
W78C31
Philips
L.G.
80C51
GMS80C501
80C31
GMS80C301
Intel
80C51
80C31
CCL. itri
Atmel
CIC80510
AT80C51
----AT80C31
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Rev. 1.0 February 1998
1
MSU2051/U2031
MOSEL VITELIC
AD2/P 0.2
AD1/P 0.1
AD0/P 0.0
VDD
NC
P 1 .0
P 1 .1
P 1 .2
P 1 .3
P 1 .4
AD3/P 0.3
#E A
28
NC
27
AL E
26
#P SEN
A1 5/P 2.7
24
A1 4/P 2.6
23
A1 3/P 2.5
A14 /P 2 .6
T0 /P 3 .4
10
A13 /P 2 .5
T1 /P 3 .5
11
(Top View)
A11/P 2.3
A12.P 2.4
AD2/P 0.2
AD3/P 0.3
20 2 1 2 2
A10/P 2.2
12 1 3 14 1 5 16 17 1 8 19
A12.P 2.4
A11/P 2.3
A10/P 2.2
A9/P 2.1
A8/P 2.0
NC
VSS
XTAL1
XTAL2
#RD/P 3.7
#WR/P 3.6
29
1 8 1 9 2 0 21 22 2 3 24 25 2 6 2 7 28
XT L1
AD7 /P 0 .7
29
# INT1 /P 3 .3
AD1/P 0.1
(Top View)
AD6 /P 0 .6
30
25
A9/P 2.1
T1/P 3.5
17
A15 /P 2 .7
AD5 /P 0 .5
31
9
AD0/P 0.0
30
AD4 /P 0 .4
32
8
A8/P 2.0
T0/P 3.4
16
33
# INT0 /P 3 .2
VDD
15
#PSE N
44L PQFP
NC
#INT1/P 3.3
31
7
NC
32
TXD/P 3 .1
ALE
6
VSS
14
NC
NC
5
P 1 .0
33
44L PLCC
RXD/P 3 .0
#EA
4
VDD
39
AD0 /P0.0
P 1.2
3
38
AD1 /P0.1
P 1 .5
1
33
AD4 /P 0 .4
P 1.3
4
37
AD2 /P0.2
P 1 .6
2
32
AD5 /P 0 .5
P 1.4
5
36
AD3 /P0.3
P 1 .7
3
31
AD6 /P 0 .6
P 1.5
6
35
AD4 /P0.4
RES
4
30
AD7 /P 0 .7
P 1.6
7
34
AD5 /P0.5
RXD/P 3 .0
5
29
#E A
P 1.7
8
33
AD6 /P0.6
NC
28
NC
RES
9
32
AD7 /P0.7
TXD/P 3 .1
7
27
AL E
31
# EA
# INT0 /P 3 .2
8
26
#P SEN
30
AL E
# INT1 /P 3 .3
25
A1 5/P 2.7
29
# PSEN
T0 /P 3 .4
10
24
A1 4/P 2.6
28
A1 5/P2 .7
T1 /P 3 .5
11
23
A1 3/P 2.5
27
A1 4/P2 .6
26
A1 3/P2 .5
25
A1 2/P2 .4
24
A1 1/P2 .3
23
A1 0/P2 .2
22
A9 /P2.1
21
A8 /P2.0
# INT1 /P 3.3
13
T0 /P 3.4
14
T1 /P 3.5
15
# WR/P 3.6
16
# RD/P 3.7
17
XTAL 2
18
XTAL 1
19
VSS
20
Rev. 1.0 February 1998
44L LQFP
9
12 13 14
2
15 16
17 18 19
20 21 22
A12.P 2.4
12
A11/P 2.3
# INT0 /P 3.2
MSU2031ihhU,
MSU2051ihhyyyU
6
A10/P 2.2
11
39 38 37 34
A9/P 2.1
TXD/P 3.1
41 40 41 40
A8/P 2.0
10
4 4 43 42
NC
R XD/P 3.0
(Top V iew)
40
2
MSU2031ihhP, MSU2051ihh- yyyP
1
P 1.1
40L PDIP
P 1.0
VSS
#INT0/P 3.2
13
34
RES
AD7/P 0 .7
MSU2031ihhQ,
MSU2051ihhyyyQ
XTAL1
TXD/P 3.1
12
35
3
XTAL2
NC
11
36
P 1 .7
#RD/P 3.7
RXD/P 3.0
MSU2031ihhJ,
MSU2051ihhyyyJ
10
AD6/P 0 .6
#WR/P 3.6
RES
AD5/P 0 .5
XTAL1
37
2
P 1 .1
9
P 1 .6
XTAL2
P 1.7
AD4/P 0 .4
P 1 .2
38
1
#RD/P 3.7
P 1.6
8
4 4 4 3 42 41 4 0 4 1 40 3 9 3 8 3 7 34
P 1 .5
P 1 .3
P 1.5
44 4 3 4 2 41 40
39
#WR/P 3.6
1
7
P 1 .4
NC
2
AD3/P 0.3
P 1 .0
3
AD2/P 0.2
P 1 .1
4
AD1/P 0.1
P 1 .2
5
AD0/P 0.0
P 1 .3
6
VDD
P 1 .4
Pin Configurations
MSU2051/U2031
MOSEL VITELIC
Block Diagram
Timer 1
Timer 0
Stack
Decoder &
128 bytes
4K bytes
Pointer
Register
RAM
ROM
Register
RES
Reset
to pertinent blocks
Circuit
to whole chip
Vdd
Vss
Buffer
Acc
Power
Circuit
Buffer2
Interrupt
Circuit
DPTR
Buffer1
to pertinent blocks
PC
Increamenter
ALU
XTAL2
XTAL1
#EA
#PSEN
Timming
to whole system
Program
PSW
Counter
Generator
ALE
Instruction
Register
Rev. 1.0 February 1998
Port 3
Port 1
Port 2
Port 0
Latch
Latch
Latch
Latch
Port 3
Driver
Port 1
Driver
Port 2
Driver
Port 0
Driver
8
8
8
3
8
MSU2051/U2031
MOSEL VITELIC
Pin Descriptions
40 PDIP Dice
44 LQFP 44 PQFP 44 PLCC Symbol
Active I/O
Names
Pin#
Pad#
Pin#
Pin#
Pin#
1
1
40
40
2
P1.0
i/o
bit 0 of Port 1
2
3
2
3
41
42
41
42
3
4
P1.1
P1.2
i/o
i/o
bit 1 of Port 1
bit 2 of Port 1
4
4
43
43
5
P1.3
i/o
bit 3 of Port 1
5
6
5
6
44
1
44
1
6
7
P1.4
P1.5
i/o
i/o
bit 4 of Port 1
bit 5 of Port 1
7
7
2
2
8
P1.6
i/o
bit 6 of Port 1
8
8
3
3
9
P1.7
i/o
bit 7 of Port 1
9
10
9
10
4
5
4
5
10
11
RES
RXD/P3.0
i
i/o
Reset
bit 0 of Port 3 & Receive data
11
11
7
7
13
TXD/P3.1
i/o
bit 1 of Port 3 & Transmit data
12
13
12
13
8
9
8
9
14
15
#INT0/P3.2
#INT1/P3.3
i/o
i/o
bit 2 of Port 3 & low true Interrupt 0
bit 3 of Port 3 & low true Interrupt 1
14
14
10
10
16
T0/P3.4
i/o
bit 4 of Port 3 & Timer 0
15
16
15
16
11
12
11
12
17
18
T1/P3.5
#WR/P3.6
i/o
i/o
bit 5 of Port 3 & Timer 1
bit 6 of Port 3 & Write (low enable)
17
17
13
13
19
#RD/P3.7
i/o
bit 7 of Port 3 & Read (low enable)
18
18
14
14
20
XTAL2
o
Crystal out
19
20
19
20-22
15
16
15
16
21
22
XTAL1
VSS
i
Crystal in
Sink Voltage, Ground
21
23
18
18
24
A8/P2.0
i/o
bit 0 of Port 2 & Address 8
22
23
24
25
19
20
19
20
25
26
A9/P2.1
A10/P2.2
i/o
i/o
bit 1 of Port 2 & Address 9
bit 2 of Port 2 & Address 10
24
26
21
21
27
A11/P2.3
i/o
bit 3 of Port 2 & Address 11
25
26
27
28
22
23
22
23
28
29
A12/P2.4
A13/P2.5
i/o
i/o
bit 4 of Port 2 & Address 12
bit 5 of Port 2 & Address 13
27
29
24
24
30
A14/P2.6
i/o
bit 6 of Port 2 & Address 14
28
30
25
25
31
A15/P2.7
i/o
bit 7 of Port 2 & Address 15
29
30
31
32
26
27
26
27
32
33
#PSEN
ALE
o
o
Program store enable (low enable)
Address latch enable
31
33
29
29
35
#EA
i
External access first 4K memory
32
33
34
35
30
31
30
31
36
37
AD7/P0.7
AD6/P0.6
i/o
i/o
bit 7 of Port 0 & Address or Data 7
bit 6 of Port 0 & Address or Data 6
34
36
32
32
38
AD5/P0.5
i/o
bit 5 of Port 0 & Address or Data 5
35
36
37
38
33
34
33
34
39
40
AD4/P0.4
AD3/P0.3
i/o
i/o
bit 4 of Port 0 & Address or Data 4
bit 3 of Port 0 & Address or Data 3
37
39
35
35
41
AD2/P0.2
i/o
bit 2 of Port 0 & Address or Data 2
38
40
36
36
42
AD1/P0.1
i/o
bit 1 of Port 0 & Address or Data 1
39
40
41
42,43
37
38
37
38
43
44
AD0/P0.0
VDD
i/o
bit 0 of Port 0 & Address or Data 0
Drive Voltage, +3 Vcc (or +5 Vcc)
Rev. 1.0 February 1998
L/L/-
L/L/-
L
H
L
4
MSU2051/U2031
MOSEL VITELIC
Pin Descriptions
#EA
When held at a TTL high level, the MSU2051 executes
instructions from the internal ROM when the PC is less
than 4096. When held at a TTL low level, the
MSU2051 fetches all instuctions from external Program
Memory.
Vss
Circuit ground potential.
V DD
+3V (or +5 V) power supply during operation.
XTAL 1
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
PORT 0
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data
bus when using external memory.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance.
Terms
PORT 2
Port 2 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance. It also emit the high-order
address byte when accessing external memory.
Idle Mode
During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/
counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing
instructions. In Idle mode (IDL=1), the oscillator
continues to run and the interrput, and timer blocks
continue to be clocked but the clock signal is gated off
to the CPU. The activities of the CPU no longer exist
unless waiting for an interrupt request.
-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.
-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.
-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.
-There are three ways to terminate the Idle Mode.
1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.
2) By hardware reset
Since the clock oscillator is still running, the hardware
reset needs to be held active for only two machine
cycles (24 oscillator periods) to complete the reset. All
SFR and PC value will be cleared to reset value.
3) By one of CLK, DATA, PORT 2.0-2.7 transition to
low (falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
PORT 3
Port 3 is an 8-bit quasi-bidirectinal I/O port with internal
pull-up resistance. It also contains the interrupt, timer,
serial port and #RD as well as #WR pins that are used
by various options. The output latch corresponding to a
secondary function must be programmed to one (1) for
that function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
- RXD/data (P3.0). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data
output (asynchronous) or data output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.4). Input to counter 1.
- #WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.
- #RD (P3.7). The read control signal enables External
Data Memory to Port 0.
RES
A high on this pin for two machine cycles (24 clocks)
while the oscillator is running, resets the device. The
data in RAM is preserved when reset signals - reset
does not clear the data in RAM.
ALE
Provides Address Latch Enable output used for latching
the address into external memory during normal operation.
#PSEN
The Program Store Enable output is a control signal that
enables the external Program Memory to the bus during
normal fetch operations.
Rev. 1.0 February 1998
5
MSU2051/U2031
MOSEL VITELIC
Power Down Mode
It saves the RAM content, stops the clock generator
and disables every other blocks' function until the
coming hardware reset. To save even more power
consumption, user's software program can invoke this
mode. The SFRs and the on-chip data RAM retain
their values during this mode, but the porcessor stops
executing instructions. In Power-Down mode (PD=1)
the oscillator is frozen.
-An instruction that sets flag (PCON.1) causes that to
be the last instruction executed before going into the
Power Down Mode.
-In the Power Down Mode, the on-chip oscillator is
stopped.
With the clock frozen, all functions are stopped, but
the on-chip RAM and Special Function Registers are
held.
-Reset redefines all the SFRs, but does not change the
on-chip RAM.
-There are two ways to terminate the Power Down
Mode.
1) By hardware reset
All SFR and PC value will be cleared to reset value.
2) One of CLK, DATA, PORT 2.0-2.7 transition to low
(falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
-Care must be taken, however, to ensure that VCC is
not reduced before the Power Down Mode is invoked,
and that VCC is restored to its normal operating level
before the Power Down Mode is terminated.
-The hardware reset must be held active long enough
to allow the oscillator to restart and stabilize.
General of above
User should fix the attention on using wake up from
port 2:
-The user should write the power down or idle mode
flag value to one RAM address before write PCON to
distinguish waking up from power down mode or idle
mode.
-After idle mode or power down mode wakes up, the
interrupt service routine will be executed first and then
executes PC+1 address if the IE register is enabled
before entering power down mode or idle mode. The
interrupt service routine will not be executed but CPU
executes PC+1 address program if disable IE register.
-After wake up power down or idle mode the IDF flag
will be set by hardware. The IDF flag be cleared at
the ISR execution time. If IE register is disable, the
IDF flag will not be cleared when power down or idle
mode wakes up.
The state of pins during Idle and Power-Down Mode
Mode
Program
memory
ALE
#PSEN
Port 0
Port 1
Port 2
Port 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
Power Down
External
Internal
1
0
1
0
Float
Data
Data
Data
Address
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
Absolute Maximal Rating
Symbol
Name
Rating
Unit
Vdd - Vss
DC supply Voltage
-0.5 ~ +5.0
-0.5 ~ +7.0
V
V
VIN
VOUT
Input voltage
Vss-0.3 ~ V dd +0.3
V
output voltage
Vss ~ Vdd
T (Operating) Operating Temperature
T (Storage) Storage Temperature
Rev. 1.0 February 1998
0 ~ +70
-55 ~ +125
Remark
U20x1L
U20x1S,U20x1C
°C
°C
6
* Note:
Operation beyond Absolute Maximal Rating
can adversely affect device reliability.
MSU2051/U2031
MOSEL VITELIC
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit
Remarks
t A
V CC3
Ambient temperature under bias
Supply voltage
0
2.7
25
3.0
70
4.5
°C
V
U20x1L
4.5
5.0
5.5
V
3.0
16
16
25
16
25
MHz
MHz
U20x1i16
U20x1i25
25
40
40
MHz
U20x1i40
V CC5
f osc 16
f osc 25
Oscillator Frequency
f osc 40
U20x1S, U20x1C
AC Characteristics
(16/25/40 MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Outputs=80pF)
f osc 16
Valid
Parameter
Cycle
Min.
ALE pulse width
Address Valid to ALE low
RD/WRT
RD/WRT
115
43
Address Hold after ALE low
RD/WRT
53
T LLPL
ALE low to Valid Instruction In
ALE low to #PSEN low
RD
RD
53
T PLPH
#PSEN pulse width
RD
173
T PLIV
T PXIX
#PSEN low to Valid Instruction In
RD
Instruction Hold after #PSEN
Instruction Float after #PSEN
RD
RD
Address to Valid Instruction In
T RLRH
#PSEN low to Address Float
#RD pulse width
T WLWH
T RLDV
T RHDX
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
Variable f osc
Typ. Max
Min.
Typ.
Max.
Unit
nS
nS
2xT - 10
T - 20
T - 10
nS
240
4xT - 10
T - 10
3xT - 15
nS
nS
nS
177
3xT - 10
nS
87
T + 25
nS
nS
RD
292
5xT - 20
nS
RD
RD
10
10
365
nS
nS
#WR pulse width
WRT
365
#RD low to Valid Data in
RD
Data Hold after #RD
Data Float after #RD
RD
RD
ALE low to Valid Data In
T LLYL
Address to Valid Data In
ALE low to #WR or #RD low
T AVYL
T QVWH
T QVWX
T PXIZ
T AVIV
T PLAZ
0
0
6xT - 10
6xT - 10
nS
302
5xT - 10
nS
145
2xT + 20
nS
nS
RD
490
8xT - 10
nS
RD
RD/WRT
178
542
197
nS
nS
Address Valid to #WR or #RD low
RD/WRT
230
3xT - 10
4xT - 20
9xT - 20
3xT + 10
Data Valid to #WR High
WRT
403
7xT - 35
nS
Data Valid to #WR transition
Data hold after #WR
WRT
WRT
38
73
T - 25
nS
nS
#RD low to Address Float
RD
RD/WRT
T CHCL
#WR or #RD high to ALE high
Clock fall time
T CLCX
Clock low time
nS
T CLCH
T CHCX
Clock rise time
nS
T RHDZ
T LLDV
T AVDV
T WHQX
T RLAZ
T YHLH
T, T CLCL
0
72
63
7
nS
T + 10
53
Clock high time
Clock period
Rev. 1.0 February 1998
0
T - 10
1/ fosc
5
nS
T + 10
nS
nS
nS
nS
Remarks
MSU2051/U2031
MOSEL VITELIC
DC Characteristics
(16/25/40 MHz, typical operating conditons, valid for U20x1C series)
Symbol
V ILX
V ILE
V ILR
V IHX
V IHE
V IHR
Parameter
Input Low Voltage
"
"
Input High Voltage
"
"
V OLA
V OL0
Output Low Voltage
V OL1
"
Output High Voltage
V OHA
"
Valid
XTAL1
#EA
RES
Typ.
Max
20%Vcc-0.1
20%Vcc-0.3
-0.5
20%Vcc-0.1
70%Vcc
20%Vcc+0.9
Vcc+0.5
Vcc+0.5
70%Vcc
Vcc+0.5
ALE, #PSEN
ports 0,3
ports 1,2
ALE, #PSEN
"
"
port 0
V OH1
"
ports 1,3
V OH2
"
"
Unit
-0.5
0
#EA
RES
"
V OH0
Min.
XTAL1
I OL = 3.2 mA
I OL = 3.2 mA
450
mV
V
I OL = 1.6 mA
I OH = -60 uA
V
I OH = -10 uA
V
V
I OH = -800 uA
I OH = -80 uA
V
I OH = -60 uA
V
V
I OH = -10 uA
I OH = -60 uA
V
I OH = -10 uA
90%Vcc
2.4
2.4
90%Vcc
2.4
90%Vcc
ports 0,3
Logical 0 Input Current
Logical 1 Input Current
ports 1,2,3
port 0
-50
Logic Transition Current
Input Leakage Current
ports 1,2,3
port 0
-650
R RES
RX
Reset Pulldown Resistance
RES
Crystal feedback Resistance
XTAL1,2
C IO
Pin Capacitance
Power Supply Current
I IH
I TL
I LI
I CC
18
1.5
10
50
90
mA
V OL = 0.45V, note 1
uA
uA
V in = 0.45 V
V in = 5.0 V
uA
uA
V in = 2.0 V
0.45V < Vin < Vcc
150
330
Kohm
10
pF
mA
Freq=1MHz, Ta=25 ¢J
Active mode, 16 MHz
mA
Idle mode, 16MHz
uA
Power down mode
Unit
mA
Test conditions
V OL = 0.45V
Vdd
5
8
Vdd
3
10
5
45
Vdd
V
V
mV
90%Vcc
"
V
mV
Output Low Current
I OL0
I IL
V
V
450
450
2.4
port 2
Test Conditions
V
Kohm
note 1 : no more than 80 mA I OLs for all 16-bit ports 0 & 3 output pins.
DC Characteristics
(16 MHz, typical operating conditons, valid for U20x1S series)
Symbol
I OL0
Parameter
Output Low Current
others
Rev. 1.0 February 1998
Valid
ports 0 & 3
Min.
Typ.
3
Max.
identical to U20x1C series'
8
MSU2051/U2031
MOSEL VITELIC
DC Characteristics
(16 MHz, typical operating conditons, valid for U20x1L series)
Symbol
V ILX
V ILE
V ILR
V IHX
V IHE
V IHR
V OLA
V OL0
V OL1
V OHA
V OH0
Parameter
Input Low Voltage
"
"
Input High Voltage
"
"
Output Low Voltage
"
"
Output High Voltage
"
"
Valid
"
V OH2
"
"
Typ.
Max
#EA
RES
mV
mV
XTAL1
Vcc+0.3
V
#EA
RES
Vcc+0.3
Vcc+0.3
V
V
I OL = 3.2 mA
mV
mV
I OL = 3.2 mA
I OL = 1.6 mA
V
I OH = -60 uA
2.2
V
V
I OH = -10 uA
I OH = -800 uA
2.4
V
I OH = -80 uA
1.8
2.4
V
I OH = -60 uA
1.8
V
V
I OH = -10 uA
I OH = -60 uA
2.4
V
I OH = -10 uA
45
uA
V in = 0.45 V
1
uA
V in = 3.0 V
250
uA
V in = 1.4 V
uA
0.45V < Vin < Vcc
400
400
ports 0,3
ports 1,2
ALE, #PSEN
port 0
ports 1,3
port 2
Test Conditions
mV
ALE, #PSEN
"
400
1.8
2.4
I IL
Logical 0 Input Current
ports 1,2,3
I IH
Logical 1 Input Current
port 0
I TL
Logic Transition Current
ports 1,2,3
I LI
R RES
Input Leakage Current
port 0
Reset Pulldown Resistance
RES
50
8
150
RX
Crystal feedback Resistance
Pin Capacitance
XTAL1,2
90
330
C IO
I CC
Power Supply Current
Vdd
10
Vdd
Vdd
Rev. 1.0 February 1998
Unit
mV
"
V OH1
Min.
XTAL1
9
2
1
7
4.5
10
45
Kohm
Kohm
pF
Freq=1MHz, Ta=25 ¢J
mA
Active mode, 16 MHz
mA
uA
Idle mode, 16MHz
Power down mode
MSU2051/U2031
MOSEL VITELIC
Data Memory Read Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
1
2
ALE
#PSEN
5
#RD
7
3
ADDRESS A - A
15
8
PORT2
3
INST in Float
PORT0
4
A 7 -A0
6
8
Float
DATA in
Float
Program Memory Read Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
OSC
1
2
ALE
5
7
#PSEN
#RD, #WR
3
ADDRESS A15 - A 8
PORT2
3
PORT0
Rev. 1.0 February 1998
Float
A 7 -A0
4
Float
ADDRESS A 15-A 8
6
8
INST in
10
Float
A 7 -A0
Float
INST in
Float
ADDRESS
or Flloat
MSU2051/U2031
MOSEL VITELIC
Data Memory Write Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
1
ALE
#PSEN
5
#WR
6
2
ADDRESS A15 - A 8
PORT2
2
INST
PORT0
Float
3
4
A 7-A 0
DATA OUT
ADDRESS
or Floa
I/O Ports Timing
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
X1
sampled
inputs P0, P1
sampled
inputs P2, P3
Output by
MOV Px,Src
RxD at Serial Port
Shift Clock
(Mode 0)
Rev. 1.0 February 1998
current data
next data
sampled
11
T4
T5
T6
T7
T8
MSU2051/U2031
MOSEL VITELIC
Timing Critical, Requirement of External Clock
(Vss=0.0V is assumed)
T CLCL
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V
T CHCX
T CLCX
T CHCL
T CLCH
Tm.I External Program Memory Read Cycle
T PLPH
#PSEN
ALE
T LHLL
T LLPL
T AVLL
T LLAX
PORT 0
T LLIV
T PLAZ
T PXIZ
T PXIX
T PLIV
A0 - A7
Instruction. IN
A0 - A7
T AVIV
PORT 2
A8 - A15
A8 - A15
Tm.II External Data Memory Read Cycle
#PSEN
T YHLH
ALE
T LLDV
T LLYL
T RLRH
#RD
T AVLL
T LLAX
T RHDZ
T RLDV
T RHDX
T RLAZ
PORT 0
A0-A7
from Ri or
DATA IN
A0-A7
From
T AVYL
T AVDV
PORT 2
Rev. 1.0 February 1998
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
12
INSTR.
IN
MSU2051/U2031
MOSEL VITELIC
Tm.III External Data Memory Write Cycle
#PSEN
T YHLH
ALE
T LHLL
T LLYL
#WR
T WLWH
T QVWX
T AVLL
T LLAX
A0-A7
from Ri or
DPL
PORT 0
T WHQX
T QVWH
A0-A7
From
PCL
DATA OUT
T AVYL
PORT 2
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
Application Reference
Valid for U2051L16/ U2031L16/
U2051S16/ U2031S16
X'tal
C1
3 MHz
15 pF
6 MHz
12 MHz
16 MHz
15 pF
30 pF
30 pF
C2
15 pF
R
open
15 pF
open
30 pF
open
30 pF
open
X1
X'tal
Valid for U2051C16/ U2031C16/
U2051C25/ U2031C25/
U2051C40/ U2031C40
R
X2
X'tal
C1
12 MHz
30 pF
16 MHz
25 MHz
40 MHz
30 pF
15 pF
5 pF
C2
30 pF
R
open
30 pF
open
Rev. 1.0 February 1998
MSU2051/U2031
C1
15 pF
5 pF
62 Kohm 4.7 Kohm
13
C2
INSTR.
IN
MSU2051/U2031
MOSEL VITELIC
40L 600mil PDIP Information
E
D
S
E1
A1
A2
C
A
L
e1
eA
B1
B
£\
Note:
1.Dimension D Max & S include mold flash or tie bar
burrs.
2.Dimension E1 does not include interlead flash.
3.Dimenseion D & E1 include mold mismatch and are
determined at the mold parting line.
4.Dimension B1 does not include dambar protrusion/
infrusion.
5.Controlling dimension is inch.
6.General appearance spec. should base on final
visual inspection spec.
Symbol
A
A1
- / 0.210
0.010 / -
- / 5.33
0.150 / 0.160
0.25 / 3.81 / 4.06
0.016 / 0.022
0.41 / 0.56
B1
0.048 / 0.054
0.008 / 0.014
1.22 / 1.37
C
D
E
E1
e1
L
eA
S
14
Dimension in mm
minimal/maximal
A2
B
£\
Rev. 1.0 February 1998
Dimension in Inch
minimal/maximal
- / 2.070
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.20 / 0.36
- / 52.58
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
0.120 / 0.140
0° / 15°
3.05 / 3.56
0.630 / 0.670
/ 0.090
16.00 / 17.02
- / 2.29
0° / 15°
MSU2051/U2031
MOSEL VITELIC
44L Plastic Leaded Chip Carrier (PLCC)
L
6
7
E HE
GE
y
A2
D
A1
A
HD
C
b1
b
e
0
GD
Note:
1.Dimension D & E does not include interlead flash.
2.Dimension b1 does not include dambar protrusion/
intrusion.
3.Controlling dimension:Inch
4.General appreance spec. should base on final visual
inspection spec.
Rev. 1.0 February 1998
15
Symbol
Dimension in Inch
minimal/maximal
Dimension in mm
minimal/maximal
A
- / 0.185
A1
A2
0.020 / 0.145 / 0.155
b1
0.026 / 0.032
3.68 / 3.94
0.66 / 0.81
b
0.016 / 0.022
0.41 / 0.56
C
D
0.008 / 0.014
0.648 / 0.658
E
0.648 / 0.658
e
GD
0.050 BSC
0.590 / 0.630
GE
0.590 / 0.630
HD
HE
0.680 / 0.700
0.680 / 0.700
17.27 / 17.78
L
y
θ
0.090 / 0.110
- / 0.004
2.29 / 2.79
- / 0.10
/
/
- / 4.70
0.51 / -
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27BSC
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
MSU2051/U2031
MOSEL VITELIC
44L Plastic Quad Flat Package
C
L
L1
S
θ2
e
R1
D2 D1 D
Gage Plane
0.25 mm
b
A2
θ3
R2
A1
E2
E1
E
A
01
seating plane
C
θ
Note:
Symbol
1. Dimension D1 and E1 do not include mold
protrustion. Allowance protrusion is 0.25mm per side.
Dimensions D1 and E1 do include mold mismatch
and are determined at datum plane.
2. Dimension b does not include dambar protrusion.
Allowance dambar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius or the lead foot.
A
A1
A2
b
c
D
minimal/maximal
0.071 / 0.087
1.80 / 2.20
0.012 / 0.018
0.004 / 0.009
0.30 / 0.45
0.09 / 0.20
- / 2.55
0.15 / 0.35
0.520 BSC
13.20 BSC
0.394 BSC
D2
0.315
0.520 BSC
10.00 BSC
8.00
E
E1
e
L
L1
R1
R2
S
16
Dimension in mm
minimal/maximal
- / 0.100
0.006 / 0.014
D1
E2
Rev. 1.0 February 1998
Dimension in Inch
13.20 BSC
0.394 BSC
10.00 BSC
0.315
0.031 BSC
8.00
0.80 BSC
0.029 / 0.041
0.73 / 1.03
0.063
0.005 / -
1.60
0.13 / -
0.005 / 0.012
0.008 / -
0.13 / 0.30
0.20 / as left
θ
θ1
0° / 7°
0° / -
θ2
10° REF
as left
θ3
7° REF
C
0.004
as left
0.10
as left
MSU2051/U2031
MOSEL VITELIC
44L Low profile Quad Flat Package
C
L
L1
S
θ2
e
R1
D2 D1 D
Gage Plane
0.25 mm
b
A2
θ3
R2
A1
E2
E1
E
A
01
seating plane
C
θ
Note:
1. Dimension D1 and E1 do not include mold
protrustion. Allowance protrusion is 0.25mm per side.
D1 and E1 are maximal plastic body size dimensions
including mold mismatch.
2. Dimension b does not include dambar protrusion.
Allowance dambar protrusion shall not cause the
lead width to exceed the maximal b dimension by
more than 0.08 mm.
3. Dambar can not be located on the lower radius or the
foot. Minimal space between protrusion and an
adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm
pitch packages.
Dimension in Inch
minimal/maximal
Dimension in mm
Symbol
A
- / 0.063
A1
0.002 / 0.006
0.053 / 0.057
- / 1.60
0.05 / 0.15
A2
b
c
D
D1
D2
E
E1
0.30 / 0.45
0.004 / 0.008
0.472 BSC
0.393 BSC
0.09 / 0.20
12.00 BSC
0.315
0.472 BSC
8.00
12.00 BSC
0.393 BSC
10.00 BSC
10.00 BSC
0.315
8.00
e
0.031 BSC
0.018 / 0.030
0.80 BSC
0.45 / 0.75
0.039 REF
1.00 REF
0.003 / 0.003 / 0.008
0.08 / 0.08 / 0.20
R1
R2
S
17
1.35 / 1.45
0.012 / 0.018
E2
L
L1
Rev. 1.0 February 1998
minimal/maximal
0.008 / -
0.20 / -
θ
0° / 7°
θ1
0° / -
as left
as left
θ2
θ3
C
11°/13°
11°/13°
0.004
as left
as left
0.10
MSU2051/U2031
MOSEL VITELIC
Bonding Information
PAD-NAME
ORDER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Y-COORD
X-COORD
186
186
186
186
186
270
432
592
754
914
1077
1236
1399
1558
1721
1964
1964
1964
1964
1964
1964
1964
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
RES
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
XTAL2
XTAL1
GND
GND
GND
ORDER
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
1080
921
758
599
436
186
186
186
186
186
186
186
186
186
186
255
418
577
839
1000
1151
1302
PAD-NAME
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
#PSEN
ALE
#EA
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
VDD
VDD
X-COORD
1964
1964
1964
1964
1964
1721
1558
1399
1236
1077
914
754
592
432
270
186
186
186
186
186
186
Y-COORD
1463
1623
1786
1945
2108
2281
2281
2281
2281
2281
2281
2281
2281
2281
2281
2038
1876
1716
1554
1393
1241
Logo
37
36
35
34
33
32
31
30
29
27
38
26
39
25
40
24
41
MSU2051/U2031
42
23
2570 x 2250 (µm)
22
43
PAD SIZE : 96 x 96 (µm)
1
substrate should be bonded to Vss
2
(Gnd)
21
pid 251*
pid 251**
pid 251***
pid 251****
pid 251*****
pid 251A
pid 263*
pid 251B
20
19
3
18
4
5
6
28
17
7
Rev. 1.0 February 1998
8
9
10
11
12
13
14
15 16
18
11/95
01/96
03/96
08/96
10/96
11/96
11/97
01/98
MSU2051/U2031
MOSEL VITELIC
To:
Mosel Vitelic Inc.
886-3-578-4732 (fax #)
Attn: Sales & Marketing Department
Product Request Form
We hereby request MVI to start producing MSU2051 which is specified below.
Please send us the product code and a hardcopy of data code as well as data code file duplicated on floppy
diskette. No further confirmation is necessary.
Production will start automatically once you receive our data code and verify that the checksum is match.
Mass Production of the captioned device shall be done in accordance with the purchase order(s) issued by
us or a company specified by us. All terms and conditions are based on the development agreement and/or
contract signed between MVI and us.
IC descriptions
Data Code Descriptions
Code Length
U2051S16, 16 MHz small current
Dice form
P type = 40L-PDIP
File Length
U2051L16, 16 MHz low working voltage
U2051C16, 16 MHz
J type = 44L-PLCC
U2051C25, 25 MHz
Q type = 44L-PQFP
L type = 44L-LQFP
File Name
Checksum
h
00h filled
Unused
Data Byte
FFh filled
HEX format
Format
Binary code format
EPROM
Media
8751 chip
File on Floppy
E-mail file
U2051C40, 40 MHz
Top Marking (fill only for packaged)
Use MVI logo, date code and part number
Use my specifications as described below
Specify below fields only for customer top marking
Date code location descriptions
Use regular date code as MVI's
Leave it as blank
use right side five letters
Logo Specifications
Leave it blank
Use my specifications as attachment
Part number specified, less than 15 digits
Phone # :
Fax # :
Company Name :
Signature :
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Rev. 1.0 February 1998
19
MSU2051/U2031
MOSEL VITELIC
To:
Mosel Vitelic Inc.
886-3-578-4732 (fax#)
Attn: Sales & Marketing Department
Logo Top Marking Request & spec.
We hereby request MVI to have our logo printed on top of the device package. Below is the
specification of our logo in 20:1 scale base. This logo diagram is clear enough and is able to be
shrunk directly to fit into available top marking area described on page.
Phone # :
Fax # :
Company Name :
Signature :
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Rev. 1.0 February 1998
20
MOSEL VITELIC
WORLDWIDE OFFICES
MSU2051/U2031
U.S.A.
TAIWAN
JAPAN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
WBG MARINE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-71
PHONE: 81-43-299-6000
FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2665-4883
FAX: 852-2664-7535
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-578-3344
FAX: 886-3-579-2838
GERMANY
(CONTINENTAL
EUROPE & ISRAEL )
71083 HERRENBERG
BENZSTR. 32
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
IRELAND & UK
BLOCK A UNIT 2
BROOMFIELD BUSINESS PARK
MALAHIDE
CO. DUBLIN, IRELAND
PHONE: +353 1 8038020
FAX: +353 1 8038049
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
CENTRAL & SOUTHEASTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
FAX: 562-597-2174
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
1/98
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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