IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES LOW SKEW PLL CLOCK DRIVER TURBOCLOCK™ JR. FEATURES: • • • • • • DESCRIPTION: Eight zero delay outputs Selectable positive or negative edge synchronization Synchronous output enable Output frequency: 15MHz to 100MHz TTL outputs 3 skew grades: IDT59910A-2: tSKEW0<250ps IDT59910A-5: tSKEW0<500ps IDT59910A-7: tSKEW0<750ps 3-level inputs for PLL range control PLL bypass for DC testing External feedback, internal loop filter 46mA IOL high drive outputs Low Jitter: <200ps peak-to-peak Ω terminated lines Outputs drive 50Ω Pin-compatible with Cypress CY7B9910 Available in SOIC package • • • • • • • • IDT59910A The IDT59910A is a high fanout phase lock loop clock driver intended for high performance computing and data-communications applications. The IDT59910A has eight zero delay TTL outputs. The IDT59910A maintains Cypress CY7B9910 compatibility while providing two additional features: Synchronous Output Enable (GND/sOE), and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/ sOE pin is held low, all the outputs are synchronously enabled (CY7B9910 compatibility). However, if GND/sOE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input (CY7B9910 compatibility). When VCCQ/PE is held low, all the outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. FUNCTIONAL BLOCK DIAGRAM V CCQ /PE GND/sOE Q0 Q1 Q2 Q3 FB PLL REF Q4 Q5 FS Q6 Q7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SEPTEMBER 2001 1 c 2001 Integrated Device Technology, Inc. DSC 5845/1 IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol REF 1 24 GND VCCQ 2 23 TEST FS 3 22 NC NC 21 GND/sOE VCCQ/PE 4 5 20 VCCN VCCN 6 19 Q7 Q0 7 18 Q6 Q1 8 17 GND GND 9 16 Q5 Q2 10 15 Q4 Q3 11 14 VCCN VCCN 12 13 FB VI Description Max Unit Supply Voltage to Ground –0.5 to +7 V DC Input Voltage –0.5 to +7 V 530 mW –65 to +150 °C Maximum Power Dissipation (TA = 85°C) TSTG Storage Temperature NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) Parameter CIN Description Input Capacitance Typ. Max. Unit 5 7 pF NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested. SOIC TOP VIEW PIN DESCRIPTION Pin Name Type REF IN Description Reference Clock Input FB IN Feedback Input TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. GND/ sOE(1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the VCCQ/PE IN feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. FS(2) IN Frequency range select. 3 level input. FS = GND: 15 to 35MHz FS = MID (or open): 25 to 60MHz FS = VCC: 40 to 100MHz Q0 - Q7 OUT Eight clock output VCCN PWR Power supply for output buffers VCCQ PWR Power supply for phase locked loop and other internal circuitry GND PWR Ground NOTES: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active. 2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved. 2 IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RECOMMENDED OPERATING RANGE Symbol IDT59910A-5, -7 IDT59910A-2 (Industrial) (Commercial) Description Min. Max. Min. Max. Unit VCC Power Supply Voltage 4.5 5.5 4.75 5.25 V TA Ambient Operating Temperature -40 +85 0 +70 °C DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Conditions Min. Max. Unit 2 — V — 0.8 V VCC−1 — V VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) VIHH Input HIGH Voltage(1) 3-Level Inputs Only VIMM Input MID Voltage 3-Level Inputs Only VCC/2−0.5 VCC/2+0.5 V VILL Input LOW Voltage(1) 3-Level Inputs Only — 1 V IIN Input Leakage Current VIN = VCC or GND — ±5 µA (REF, FB Inputs Only) VCC = Max. HIGH Level — ±200 VIN = VCC/2 MID Level — ±50 VIN = GND LOW Level — ±200 — ±100 µA (1) VIN = VCC I3 3-Level Input DC Current (TEST, FS) IPU Input Pull-Up Current (VCCQ/PE) VCC = Max., VIN = GND µA IPD Input Pull-Down Current (GND/sOE) VCC = Max., VIN = VCC — ±100 µA VOH Output HIGH Voltage VCC = Min., IOH = −16mA VCC = Min., IOH = −40mA 2.4 — V — — VOL Output LOW Voltage VCC = Min., IOL = 46mA — 0.45 V IOS Output Short Circuit Current VCC = Max., VO = GND — −250 mA (2) NOTES: 1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 2. This is to be measured at 25°C with 10:1 duty cycle, one output at a time, and one second maximum. POWER SUPPLY CHARACTERISTICS Symbol Parameter ICCQ Quiescent Power Supply Current Test Conditions(1) VCC = Max., TEST = MID, REF = LOW, Typ.(2) Max. Unit 10 40 mA GND/sOE = LOW, All outputs unloaded ∆ICC Power Supply Current per Input HIGH VCC = Max., VIN = 3.4V 0.4 1.5 mA ICCD Dynamic Power Supply Current per Output VCC = Max., CL = 0pF 100 160 µA/MHz ITOT Total Power Supply Current VCC = 5V, FREF = 25MHz, CL = 240pF(1) 53 — VCC = 5V, FREF = 33MHz, CL = 240pF(1) 63 — 240pF(1) 117 — VCC = 5V, FREF = 66MHz, CL = NOTE: 1. For eight outputs, each loaded with 30pF. 3 mA IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES INPUT TIMING REQUIREMENTS Description (1) Symbol Min. Max. Unit — 10 ns/V tR, tF Maximum input rise and fall times, 0.8V to 2V tPWC Input clock pulse, HIGH or LOW 3 — ns DH Input duty cycle 10 90 % REF Reference clock input 15 100 MHz NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. SWITCHING CHARACTERISTICS OVER OPERATING RANGE IDT59910A-2 Symbol Parameter Min. Typ. IDT59910A-5 Max. Min. Typ. IDT59910A-7 Max. Min. Typ. Max. Unit FS = LOW 15 — 35 15 — 35 15 — 35 FS = MED 25 — 60 25 — 60 25 — 60 FS = HIGH 40 — 100 40 — 100 40 — 100 REF Pulse Width HIGH 3 — — 3 — — 3 — — ns REF Pulse Width LOW(1,8) 3 — — 3 — — 3 — — ns — 0.1 0.25 — 0.25 0.5 — 0.3 0.75 ns — — 0.75 — — 1.25 — — 1.65 ns −0.25 −1.2 0 0.25 0 0.5 0.7 ns 1.2 0 1.2 −0.7 −1.2 0 0 −0.5 −1.2 0 1.2 ns 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns FREF REF Frequency Range tRPWH tRPWL tSKEW0 Zero Output Skew (All Outputs) (1,8) (1,3,4) tDEV Device-to-Device Skew(1,2,5) tPD REF Input to FB Propagation Delay(1,7) MHz tODCV Output Duty Cycle Variation from 50% tORISE Output Rise Time(1) 0.15 tOFALL Output Fall Time 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tLOCK PLL Lock Time(1,6) — — 0.5 — — 0.5 — — 0.5 ms RMS — — 25 — — 25 — — 25 ps Peak-to-Peak — — 200 — — 200 — — 200 tJR (1) (1) Cycle-to-Cycle Output Jitter(1) NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. tSKEW is the skew between all outlets. See AC TEST LOADS. 4. For IDT59910A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max. 5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 7. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns. 8. Refer to INPUT TIMING REQUIREMENTS for more detail. 4 IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC TEST LOADS AND WAVEFORMS ≤ 1ns ≤ 1ns VCC 3.0V 2.0V Vth =1.5V 130 Ω 0.8V 0V Output TTL Input Test Waveform 91 Ω CL t OF AL L t O R ISE C L = 50pF (C L = 30pF for -2 and -5 devices) Test Load 2.0V 0.8V TTL Output Waveform AC TIMING DIAGRAM t RP W L t R EF t R PW H REF t PD t OD CV t O D CV FB t JR Q t S KE W tS K EW OTHER Q NOTES: Skew: tSKEW: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with 50Ω to 2.06V. The skew between all outputs. tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 5 IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) SO Small Outline IC (300-mil) 59910A-2 Low Skew PLL Clock Driver TurboClock Jr. 59910A-5 59910A-7 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459