CY5057 High-Frequency Flash Programmable PLL Die with Spread Spectrum Features Benefits ■ Flash programmable die for in-package programming of crystal oscillators ■ ■ High resolution phase-locked loop (PLL) with 10-bit multiplier and 7-bit divider Enables quick turnaround of custom oscillators and lowers inventory costs through stocking blank parts. In addition, the part may be Flash programmed up to 100 times. This reduces programming errors and provides an easy upgrade path for existing designs. ■ Flash programmable capacitor tuning array ■ ■ Simple two-pin programming interface (excluding VDD and VSS pins) Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM. ■ ■ On-chip oscillator used with external 25.1 MHz fundamental tuned crystal Enables fine tuning of output clock frequency by adjusting the load capacitance of the crystal. ■ Allows the device to go into standard 4 or 6-pin packages. ■ Flash programmable spread spectrum with spread percentages between ± 0.25% and ± 2.00% ■ Lowers cost of oscillator, because PLL may be programmed to a high frequency using a low frequency, low cost crystal. ■ Spread spectrum on/off function ■ Provides various spread percentage. ■ Operating frequency: 5 MHz to 170 MHz at 3.3 V ± 10% ■ ■ Seven-bit linear post divider with divide options from divide-by-2 to divide-by-127 Provides the ability to enable or disable spread spectrum with an external pin. ■ Provides flexibility in output configurations and testing. ■ Programmable PD# or OE pin ■ Enables low power operation or output enable function. ■ Provides flexibility for system applications through selectable instantaneous or synchronous change in outputs. ■ Suitable for most PC, consumer, and networking applications. ■ Has lower EMI than oscillators. ■ Easy to use software support for design entry. ■ Programmable asynchronous or synchronous OE and PD# modes ■ Low jitter output: < 200 ps (pk-pk) at 3.3 V ± 10% ■ Controlled rise and fall times and output slew rate ■ Software configuration support Logic Block Diagram XIN XOUT SSON# Crystal Osc with 8-bit Cap Array 7-bit ÷Q 10-bit ÷P 7-bit Output Divider Block 100- to 400-MHz PLL OUT Spread Spectrum PD#/OE Cypress Semiconductor Corporation Document #: 38-07363 Rev. *I Flash Configuration/ Spread Spectrum Storage • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 21, 2011 [+] Feedback CY5057 Die Pad Figure 1. Die Pad Diagram Note Active die size: X = 75.0 mils / 1907 μm Y = 56.2 mils / 1428 μm Scribe: X (vertical) = 3.4 mils / 86.2 μm Y (horizontal) = 2.8 mils / 71 μm Bond pad opening: 85 μm x 85 μm Pad pitch: 125 μm x 125 μm (pad center to pad center) Wafer thickness: 11 mils typical Table 1. Die Pad Definitions [Pad coordinates are referenced from the center of the die (X = 0, Y = 0)] Name Die Pad Description X Coordinate Y Coordinate –843.612 597.849, 427.266 883.743, 887.355 –563.304, –369.957 –843.612 –1.806 VDD 1,2 Power supply VSS 6,7 Ground XIN 4 Crystal gate pin XOUT 3 Crystal drain pin –843.612 236.565 5 Flash programmable to function as power down or output enable in normal operating mode. Weak pull up is enabled by default. –843.612 –424.662 834.183 589.848 PD#/OE VPP Super voltage when going into programming mode. SDA SSON# Data pin when going into and when in programming mode. 10 SCL Active low spread spectrum control. Asserting LOW turns the internal modulation waveform on. Strong pull down is enabled by default. Pull down is disabled in power down mode. Clock pin in programming mode. Must be double bonded to the OUT pad for pinouts not using the SSON# function. There is an internal pull down resistor on this pad. OUT 9 Clock output. There is an internal pull down resistor on this pad. Weak pull down is enabled by default. Default output is from the reference. 834.183 462.840 NC 8 No connect pin (do not connect this pad). 834.183 335.832 Document #: 38-07363 Rev. *I Page 2 of 11 [+] Feedback CY5057 Functional Description PLL Output Frequency CY5057 is a Flash programmable, high accuracy, PLL-based die designed for the crystal oscillator market. It also contains spread spectrum circuitry that is enabled or disabled with an external pin. The die is integrated with a low cost 25.1 MHz fundamental tuned crystal in a 4 or 6-pin through hole or surface mount package. The oscillator devices may be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables faster manufacturing of custom and standard crystal oscillators without the need for dedicated and expensive crystals. CY5057 contains a high resolution PLL with a 10-bit multiplier and a 7-bit divider. The output frequency of the PLL is determined by the following equation: CY5057 contains an on-chip oscillator and unique oscillator tuning circuit for fine tuning the output frequency. The crystal Cload is selectively adjusted by programming a set of Flash memory bits. This feature is used to compensate for crystal variations or to obtain a more accurate synthesized frequency. CY5057 uses a simple two-pin programming interface, excluding the VSS and VDD pins.. Clock outputs are generated from 5 MHz to 170 MHz at 3.3 V ± 10% operating voltage. You can reprogram the entire Flash configuration multiple times to alter or reuse the programmed inventory. CY5057 PLL die is designed for very high resolution. It has a 10-bit feedback counter multiplier and a 7-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The output of the PLL or the oscillator is further modified by a 7-bit linear post divider with a total of 126 divider options (2 to 127). CY5057 also contains flexible power management controls. These parts include both power down mode (PD# = 0) and output enable mode (OE = 1). The power down and output enable modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enables CY5057 to have low jitter and accurate outputs. This makes it suitable for most PC, networking, and consumer applications. CY5057 also has an additional spread spectrum feature that is disabled or enabled with an external pin. For more information, refer the section Spread Spectrum. Flash Configuration and Spread Spectrum Storage Block Table 2 summarizes the features configurable by the Flash memory bits. Refer to “CY5057 Programming Specification” for programming details. The specification can be obtained from your Cypress factory representative. Table 2. Flash Programmable Features Adjust Frequency Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator tuning (load capacitance values) Oscillator direct output Power management mode (OE or PD#) Power management timing (synchronous or asynchronous) Spread spectrum Pull up and Pull down resistors Document #: 38-07363 Rev. *I 2 • ( P BL + 4 ) + Po F PLL = ---------------------------------------------- • F REF (QL + 2) Equation (1) In this equation: ■ QL is the loaded or programmed reference counter value (Q counter) ■ PBL is the loaded or programmed feedback counter value (P counter) ■ Po is the P offset bit (is only 0 or 1) In spread spectrum mode, the time averaged P value is used to calculate the average frequency. Power Management Features CY5057 contains Flash programmable PD# (active LOW) and OE (active HIGH) functions. If power down mode is selected (PD# = 0), the oscillator and PLL are placed in a low supply current standby mode and the output is tri-stated and weakly pulled low. The oscillator and PLL circuits must relock when the part leaves power down mode. If output enable mode is selected (OE = 0), the output is tri-stated and weakly pulled low. In this mode, the oscillator and PLL circuits continue to operate allowing a rapid return to normal operation when the output is enabled. In addition, the PD# and OE modes may be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the power down or output disable occurs immediately (allowing for logic delays) irrespective of the position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before power down or output enable signal is initiated. This prevents output glitches. In asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of the output. Spread Spectrum CY5057 contains spread spectrum with Flash programmable spread percentage and modulation frequency. Center spread nonlinear “hershey kiss” modulation is obtained. Spread percentage is programmed to values between ±0.25% and ±2.00%, in 0.25% intervals. Only one spread profile (for one specific percentage spread and for one output frequency) may be programmed into the device at a time. CY5057 has a spread spectrum on and off function. The spread spectrum is enabled or disabled through an external pin. Timing this feature is explained in the section Switching Waveforms on page 7. Page 3 of 11 [+] Feedback CY5057 Figure 2. Crystal Oscillator Tuning Circuit RF XIN XOUT CXOUT CXIN C7 C6 C5 C4 C3 C2 C1 C0 Table 3. Crystal Oscillator Tuning Cap Values Bit[1] Capacitance per Bit (pF) C7 (MSB) 24.32 C6 12.16 C5 6.08 C4 3.04 C3 1.52 C2 0.76 C1 0.38 C0 (LSB) 0.19 C0 C1 C2 C3 C4 C5 C6 C7 Inkless Die Pick Map (DPM) Format Cypress ships inkless wafers to customers with an accompanying die pick map, which is used to determine the good die for assembly and programming. Customers can also access individual DPM files at their convenience through ftp.cypress.com with a valid user account login and password. Contact your local Cypress Field Application Engineer (FAE) or sales representative for a customer FTP account. The DPM files are named using the fab lot number and wafer number scribed on the wafer. The DPM files are transferred to the FTP account of the customer when the factory ships out the wafers against their purchase order (PO). Note 1. CXIN, CXOUT, and parasitic capacitance due to fixture and package must be included when calculating the total capacitance. Document #: 38-07363 Rev. *I Page 4 of 11 [+] Feedback CY5057 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Data retention at Tj = 125°C..................................> 10 years Supply voltage .................................................. –0.5 to 7.0 V Input voltage ............................................–0.5 V to VDD + 0.5 Static discharge voltage.......................................... > 2000 V (per MIL-STD-883, method 3015) Storage temperature (noncondensing) ......... –55°C to 125°C Output (pad 9) sink or sources current ........20 mA maximum Maximum non volatile programming cycles......................100 Junction temperature................................... –40°C to 125°C Operating Conditions Parameter VDD [2] Description Min Max Unit Supply voltage (3.3 V) 3.0 3.6 V –40 100 °C – 15 pF 25.1 25.1 MHz TAJ Operating temperature, junction CLC Maximum capacitive load on the output (CMOS levels spec) VDD = 3.0 V to 3.6 V, output frequency = 5 MHz to 170 MHz XREF Reference frequency with spread spectrum disabled. Fundamental tuned crystals only Cin Input capacitance (except crystal pins) – 7 pF CXIN Crystal input capacitance (all internal caps off) 10 14 pF CXout Crystal output capacitance (all internal caps off) 10 14 pF TPSRT Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.005 500 ms Min Max Unit DC Electrical Characteristics (Tj = -40 to 100°C) Parameter Description Test Conditions VIL Input low voltage PD#/OE and SSON# pins VDD = 3.0 V–3.6 V – 0.3*VDD V VIH Input high voltage PD#/OE and SSON# pins VDD = 3.0 V–3.6 V 0.7*VDD – V VOL Output low voltage, OUT pin VDD = 3.0 V–3.6 V, IOL = 8 mA – 0.4 V VOH Output high voltage, CMOS levels VDD = 3.0 V–3.6 V, IOH = –8 mA VDD – 0.4 – V IILPDOE Input low current, PD#/OE pin VIN = VSS (Internal pull up = 3 MΩ typical) – 10 μA IIHPDOE Input high current, PD#/OE pin VIN = VDD (Internal pull up = 100 kΩ typical) – 10 μA IILSR Input low current, SSON# pin VIN = VSS (Internal pull down = 100 kΩ typical) – 10 μA IIHSR Input high current, SSON# pin VIN = VDD (Internal pull down = 100 kΩ typical) – 50 μA IDD Supply current No load, VDD = 3.0 V–3.6 V, Fout = 170 MHz – 50 mA IOZ Output leakage current, OUT pin VDD = 3.0 V–3.6 V, output disabled with OE – 50 μA IPD Standby current VDD = 3.0 V–3.6 V, device powered down with PD# – 50 μA RUP Pull up resistor on PD#/OE pin VDD = 3.0 V–3.6 V, measured at VIN =VSS VDD = 3.0 V–3.6 V, measured at VIN = 0.7 VDD 1 80 6 150 MΩ kΩ RDN Pull down resistor on SSON# and OUT pins VDD = 3.0 V–3.6 V, measured at VIN = 0.5 VDD 80 150 kΩ Rf Crystal feedback resistor VDD = 3.0 V–3.6 V, measured at XIN = 0 100 – kΩ Document #: 38-07363 Rev. *I Page 5 of 11 [+] Feedback CY5057 AC Electrical Characteristics (Tj = –40 to 100°C) Parameter[2] Description Test Conditions Min Max Unit Fout Output frequency VDD = 3.0 V–3.6 V, CL = 15 pF 5 170 MHz tr OUT rise time VDD = 3.0 V–3.6 V, 20% to 80% VDD, CL = 15 pF – 2.7 ns tf OUT fall time VDD = 3.0 V–3.6 V, 80% to 20% VDD, CL = 15 pF – 2.7 ns DC OUT duty cycle Divider output, measured at VDD/2 Crystal direct output, measured at VDD/2 45 40 55 60 % % tJ1 Peak-to-peak period jitter Fout >133 MHz, VDD/2, SS off 25 MHz < Fout< 133 MHz, VDD/2, SS off – 200 ps 400 ps 1% of 1/Fout s Fout< 25 MHz, VDD/2, SS off tJ2 Cycle-to-cycle jitter Fout >133 MHz, VDD/2, SS on – 25 MHz < Fout< 133 MHz, VDD/2, SS on Fout< 25 MHz, VDD/2, SS on FMOD Modulation frequency DL Crystal drive level –R Negative resistance 200 ps 400 ps 1% of 1/Fout s 30 33 kHz Measured at 25.1 MHz, with crystal ESR = 20Ω, cap setting = hex16, DL = program code [1,0] – 540 μW Measured at 25.1 MHz, cap setting = hex 3F – –200 Ω Min Max Unit Timing Parameters Parameter[2] Description TSSON1 Time from steady state spread to steady state nonspread -- 600 μs TSSON2 Time from steady state non spread to steady state spread -- 100 μs TSSON3 Minimum SSON# pulse width (positive or negative) 250 – μs TMOD Spread spectrum modulation period 30 33.33 μs TSTP,SYNC Time from falling edge on PD# to stopped outputs, synchronous mode, T = 1/Fout -- 1.5T + 350 ns TSTP,ASYNC Time from falling edge on PD# to stopped outputs, asynchronous mode -- 350 ns TPU,SYNC Time from rising edge on PD# to outputs at valid frequency, synchronous mode -- 3 ms TPU,ASYNC Time from rising edge on PD# to outputs at valid frequency, asynchronous mode -- 3 ms TPXZ,SYNC Time from falling edge on OE to high impedance outputs, synchronous mode, T = 1/Fout -- 1.5T+350 ns TPXZ,ASYNC Time from falling edge on OE to high impedance outputs, asynchronous mode -- 350 ns TPZX,SYNC Time from rising edge on OE to running outputs, synchronous mode, T=1/Fout -- 1.5T + 350 ns TPZX,ASYNC Time from rising edge on OE to running outputs, asynchronous mode -- 350 ns TLOCK PLL lock time (from 0.9 VDD to valid output clock frequency) -- 10 ms Note 2. In Cypress standard TSSOP packages with external crystal. Document #: 38-07363 Rev. *I Page 6 of 11 [+] Feedback CY5057 Switching Waveforms Figure 3. Duty Cycle Timing (dc) t1A t1B t 1A Duty = -------- × [ 100% ] t 1B OUTPUT Figure 4. Output Rise/Fall Time VDD OUTPUT 0V tr tf Figure 5. Power Down Timing (Synchronous and Asynchronous Modes) VDD POWER DOWN (PD#) VIH VIL High Impedance Weakly Pulled Low CLKOUT (synchronous) TSTP CLKOUT (asynchronous) TPU High Impedance Weakly Pulled Low TPU TSTP Figure 6. Output Enable Timing (Synchronous and Asynchronous Modes) VDD VIH OUTPUT ENABLE (OE) VIL High Impedance Weakly Pulled Low CLKOUT (synchronous) TPXZ CLKOUT (asynchronous) TPZX High Impedance Weakly Pulled Low TPZX TPXZ Document #: 38-07363 Rev. *I Page 7 of 11 [+] Feedback CY5057 Figure 7. Power Up Timing VDD 0.9VDD Power Up 0V TPSRT TLOCK CLKOUT Valid CLKOUT Figure 8. Spread Spectrum On and OFF Timing SSON# T SSON3 +100% Internal Modulation W aveform T SSON1 T SSON2 0% -100% Ordering Information Ordering Code CY5057-11WAF-IL Status Active Type Inkless wafer (background to 11 mils) Operating Range –40 °C to 100 °C Ordering Code Definitions CY5057 -11WAF -IL Inkless Wafer background to 11 mils Base part number Document #: 38-07363 Rev. *I Page 8 of 11 [+] Feedback CY5057 Acronyms Acronym Description CLKOUT Clock output CMOS Complementary metal oxide semiconductor DPM Die pick map EMI Electromagnetic interference EPROM Erasable programmable read only memory FAE Field Application Engineer FTP File transfer protocol OE Output enable PAL Phase alternate line PD Power down PLL Phase locked loop PPM Parts per million TSSOP Thin shrunk small outline package TTL Transistor transistor logic Document Conventions Units of Measure Symbol Unit of Measure °C degrees Celsius mA milli Amperes mm milli meters ms milli seconds ns nano seconds ps pico seconds ppm parts per million Ω ohms kΩ kilo ohms MHz Mega Hertz MΩ Mega Ohms µA micro Amperes µF micro Farads µm micro meters pF pico Farads pp peak-to-peak V Volts % percent Document #: 38-07363 Rev. *I Page 9 of 11 [+] Feedback CY5057 Document History Page Document Title: CY5057 High-Frequency Flash Programmable PLL Die with Spread Spectrum Document Number: 38-07363 Revision ECN Orig. of Change Submission Date Description of Change ** 112486 CKN See ECN New data sheet *A 121373 CKN See ECN Added scribe lines to die pad description Added wafer thickness to die pad description Added X and Y coordinates to die pad description Removed list of discrete frequencies and discrete spread percentages Removed references to discrete frequencies and profile tables Replaced with description of software for full programmability Operating frequency changed to 5 MHz–170 MHz Removed C0 and C1 from crystal oscillator tuning circuit; renumbered other capacitors Changed maximum junction temperature to 125°C Changed PDOE internal pull up value to 1–6 Mohm when VIN = VSS Changed IILPDOE to 10 μA Changed Rf spec to 100 kohm, at condition XIN = 0 Change DL spec to 540 μW, at condition cap setting = hex16, DL=10 Added power up timing diagram separate from power down timing diagram Removed die information table *B 127414 RGL See ECN Added –11 and other details to ordering Information Added tPU details to operating conditions Changed max TSSON1 value to 600 in timing parameters table Changed parameter TPU under timing parameters to TLOCK with the description “PLL lock time” Altered minimum and maximum values in power up timing figure *C 2143928 FGA/PYRS See ECN Modified power down timing diagram Changed power up timing from min. of 50 μs to 5 μs Added output sink/source current specification in the absolute max ratings Change cap array from 10 to 8-bit Add MSB and LSB in the crystal oscillator tuning cap values table Fixed power up timing diagram Added -R cap setting value FF Added Inkless die information before Absolute Maximum Ratings Added new part number (CY5057-11WAF-IL) with note *D 2541797 AESA 07/24/08 Updated template. Added Note “Not recommended for new designs.” Added part number CY5057K-11WAF-IL in ordering information table. *E 2600816 KVM/AESA 11/04/08 Updated to match data sheet labeled “Rev *C November 16, 2004” (added logo and die number to die drawing; added pull up & pull down resistors to features table; revised –R spec and conditions; added missing labels to waveform drawings) Removed CY5057K-11WAF-IL from ordering information table. Updated die dimensions (page 2) with 29 mil thickness; corrected scribe variables *F 2621902 KVM/AESA *G 2897373 CXQ *H 3068367 CXQ 10/21/2010 Removed CY5057-11WAF part from Ordering Information. Added Ordering Code Definitions. *I 3201346 CXQ 03/21/2011 Sunset review. No material changes to document. Fixed various typos. Included Acronyms and units tables. Updated template and styles. Document #: 38-07363 Rev. *I 12/15/2008 Corrected typos on p. 1 (spread amount) & p. 5 (VIL & VIH test conditions). Connected text frames. 03/22/10 Removed part number CY5057-29WAF-IL from Ordering information table. Updated copyright section. Page 10 of 11 [+] Feedback CY5057 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07363 Rev. *I Revised March 21, 2011 Page 11 of 11 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback