Infineon HYS64D16301HU-5-C 184-pin unbuffered dual-in-line memory module Datasheet

D a t a S he et , V 1. 0, J u l y 2 00 3
HYS[64/72]D64x20HU-[5/6]-C
HYS[64/72]D32x00HU-[5/6]-C
H Y S 64 D 1 6 x 0 1 H U - [ 5 / 6 ] - C
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es
Reg DIMM
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2003-07
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
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Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
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approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S he et , V 1. 0, J u l y 2 00 3
HYS[64/72]D64x20HU-[5/6]-C
HYS[64/72]D32x00HU-[5/6]-C
H Y S 64 D 1 6 x 0 1 H U - [ 5 / 6 ] - C
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es
Reg DIMM
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYS[64/72]D64x20HU-[5/6]-C, HYS[64/72]D32x00HU-[5/6]-C, HYS64D16x01HU-[5/6]-C
Revision History:
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Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet
5
17
17
19
22
V1.0, 2003-07
184-Pin Unbuffered Dual-In-Line Memory Modules
Reg DIMM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
HYS[64/72]D64x20HU-[5/6]-C
HYS[64/72]D32x00HU-[5/6]-C
HYS64D16x01HU-[5/6]-C
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Server main memory
applications
One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 Speed Grade supported
Lead-free
Table 1
Performance
Part Number Speed Code
–5
–6
Unit
Module Speed Grade
DDR400B
DDR333B
–
Component Module
PC3200-3033
PC2700-2533
–
200
166
MHz
166
166
MHz
133
133
MHz
max. Clock Frequency
@ CL = 3
@ CL = 2.5
@ CL = 2
1.2
fCK3
fCK2.5
fCK2
Description
The HYS[64/72]D64x20HU-[5/6]-C, HYS[64/72]D32x00HU-[5/6]-C, and HYS64D16x01HU-[5/6]-C are industry
standard 184-Pin Unbuffered Dual-In-Line Memory Modules (Reg DIMM) organized as 16M × 64, 32M × 64 and
64M × 64 for non-parity and 32M × 72 and 64M × 72 for ECC main memory applications. The memory array is
designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted
on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device
using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes
are available to the customer
Data Sheet
6
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
HYS64D16301HU-5-C
PC3200U-30330-C0
one rank 128MB DIMM
256 Mbit (× 16)
HYS64D32300HU-5-C
PC3200U-30330-A0
one rank 256MB DIMM
256 Mbit (× 8)
HYS72D32300HU-5-C
PC3200U-30330-A0
one rank 256MB ECC-DIMM
256 Mbit (× 8)
256 Mbit (× 8)
PC3200 (CL=3)
HYS64D64320HU-5-C
PC3200U-30330-B0
two ranks 512MB DIMM
HYS72D64320HU-5-C
PC3200U-30330-B0
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
HYS64D16301HU-6-C
PC2700U-25330-C0
one rank 128MB DIMM
256 Mbit (× 16)
HYS64D32300HU-6-C
PC2700U-25330-A0
one rank 256MB DIMM
256 Mbit (× 8)
HYS72D32300HU-6-C
PC2700U-25330-A0
one rank 256MB ECC-DIMM
256 Mbit (× 8)
HYS64D64320HU-6-C
PC2700U-25330-B0
two ranks 512MB DIMM
256 Mbit (× 8)
HYS72D64320HU-6-C
PC2700U-25330-B0
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
PC2700 (CL=2.5)
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D32000HU-6-C, indicating rev. C dies are used for SDRAM components. The
Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3
Pin Definitions and Functions
Symbol
Type1)
Function
A0 - A12
I
Address Inputs
BA0, BA1
I
Bank Selects
DQ0 - DQ63
I/O
Data Input/Output
CB0 - CB7
I/O
Check Bits (× 72 organization only)
RAS, CAS, WE
I
Command Inputs
CKE0 - CKE1
I
Clock Enable
DQS0 - DQS8
I/O
SDRAM low data strobes
CK0 - CK2,
I
SDRAM clock (positive lines)
CK0 - CK2
I
SDRAM clock (negative lines)
DM0 - DM8
DQS9 - DQS17
I
I/O
SDRAM low data mask/
high data strobes
S0, S1
I
Chip Selects for Rank0 and Rank1
VDD
PWR
Power (+2.5 V)
VSS
GND
Ground
VDDQ
PWR
I/O Driver power supply
VDDID
PWR
VDD Indentification flag
VREF
AI
I/O reference supply
VDDSPD
PWR
Serial EEPROM power supply
SCL
I
Serial bus clock
SDA
I/O
Serial bus data line
SA0 - SA2
I
slave address select
NC
NC
Not Connected
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4
Pin Configuration
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
93
VSS
140
NC /
DM8/DQS17
2
DQ0
49
NC / CB2
94
DQ4
141
A10
3
VSS
50
VSS
95
DQ5
142
NC / CB6
4
DQ1
51
NC / CB3
96
VDDQD
143
VDDQD
5
DQS0
52
BA1
97
DM0/DQS9
144
NC / CB7
6
DQ2
98
DQ6
7
VDD
99
DQ7
8
DQ3
53
DQ32
100
VSS
145
VSS
9
NC
54
VDDQ
101
NC
146
DQ36
10
NC
55
DQ33
102
NC
147
DQ37
11
VSS
56
DQS4
103
NC
148
VDD
12
DQ8
57
DQ34
104
VDDQ
149
DM4/DQS13
Key
Key
13
DQ9
58
VSS
105
DQ12
150
DQ38
14
DQS1
59
BA0
106
DQ13
151
DQ39
15
VDDQ
60
DQ35
107
DM1/DQS10
152
VSS
16
CK1
61
DQ40
108
VDD
153
DQ44
17
CK1
62
VDDQ
109
DQ14
154
RAS
18
VSS
63
WE
110
DQ15
155
DQ45
19
DQ10
64
DQ41
111
CKE1
156
VDDQ
20
DQ11
65
CAS
112
VDDQ
157
S0
21
CKE0
66
VSS
113
NC (BA2)
158
S1
22
VDDQ
67
DQS5
114
DQ20
159
DM5/DQS14
23
DQ16
68
DQ42
115
NC / A12
160
VSS
24
DQ17
69
DQ43
116
VSS
161
DQ46
25
DQS2
70
VDD
117
DQ21
162
DQ47
26
VSS
71
NC
118
A11
163
NC
27
A9
72
DQ48
119
DM2/DQS11
164
VDDQ
28
DQ18
73
DQ49
120
VDD
165
DQ52
29
A7
74
VSS
121
DQ22
166
DQ53
30
VDDQ
75
CK2
122
A8
167
NC (A13)
31
DQ19
76
CK2
123
DQ23
168
VDD
32
A5
77
VDDQ
124
VSS
169
DM6/DQS15
33
DQ24
78
DQS6
125
A6
170
DQ54
34
VSS
79
DQ50
126
DQ28
171
DQ55
35
DQ25
80
DQ51
127
DQ29
172
VDDQ
36
DQS3
81
128
VDDQ
173
NC
37
A4
82
VSS
VDDID
129
DM3/DQS12
174
DQ60
38
VDD
83
DQ56
130
A3
175
DQ61
39
DQ26
84
DQ57
131
DQ30
176
VSS
Data Sheet
9
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4
Pin Configuration (cont’d)
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
40
DQ27
85
VDD
132
VSS
177
DM7/DQS16
41
A2
86
DQS7
133
DQ31
178
DQ62
42
VSS
87
DQ58
134
NC / CB4
179
DQ63
43
A1
88
DQ59
135
NC / CB5
180
VDDQ
44
NC / CB0
89
VSS
136
VDDQ
181
SA0
45
NC / CB1
90
NC
137
CK0
182
SA1
46
VDD
91
SDA
138
CK0
183
SA2
47
NC / DQS8
92
SCL
139
VSS
184
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on × 64 organised non-ECC
modules.
Table 5
Density
128MB
Address Format
Organization Memory SDRAMs # of
# of row/bank/
Ranks
SDRAMs columns bits
Refresh
Period Interval
16M × 64
13/2/10
8K
64 ms
7.8 µs
1
16M × 1 4
6
256MB
32M × 64
1
32M × 8 8
13/2/11
8K
64 ms
7.8 µs
256MB
32M × 72
1
32M × 8 9
13/2/11
8K
64 ms
7.8 µs
512MB
64M × 64
2
32M × 8 16
13/2/11
8K
64 ms
7.8 µs
512MB
64M × 72
2
32M × 8 18
13/2/11
8K
64 ms
7.8 µs
Data Sheet
10
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS1
DM1/DQS10
LDQS
LDM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS3
DM3/DQS12
DQS2
DM2/DQS11
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS5
DM5/DQS14
S
D0
DQS4
DM4/DQS13
LDQS
LDM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS7
DM7/DQS16
S
D1
DQS6
DM6/DQS15
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SCL
SPD
VDD /VDDQ
D0 - D3
VREF
D0 - D3
VSS
D0 - D3
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D2
S
D3
* Clock Wiring
Clock
SDRAMs
Input
Serial PD
VDD SPD
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
SDA
WP
A0
A1
A2
SA0
SA1
SA2
*CK0/CK0
*CK1/CK1
*CK2/CK2
NC
2 SDRAMs
2 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
CAS
CAS: SDRAMs D0 - D3
CKE0
CKE: SDRAMs D0 - D3
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ ):
STRAP OUT (OPEN): V DD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
WE
WE: SDRAMs D0 - D3
5. BAx, Ax, RAS, CAS, WE resistors: 7.5 ohms ± 5%
VDDID
BA0 - BA1
A0 - A13
RAS
Figure 1
Data Sheet
Strap: see Note 4
BA0-BA1: SDRAMs D0 - D3
A0-A13: SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
Block Diagram - One Rank 16M × 64 DDR SDRAM DIMM HYS64D16301GU using × 16
organized SDRAMs
11
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS0
DM0/DQS9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
S
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
S
D1
D4
S
DQS
D5
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
S
DQS
D2
S
DQS
D6
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S
DQS
D3
Serial PD
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
S
DQS
D7
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
BA0 - BA1
BA0-BA1: SDRAMs D0 - D7
A0 - A13
A0-A13: SDRAMs D0 - D7
RAS
RAS: SDRAMs D0 - D7
CAS
CAS: SDRAMs D0 - D7
VDD SPD
CKE0
CKE: SDRAMs D0 - D7
VDD/VDDQ
D0 - D7
WE
WE: SDRAMs D0 - D7
VREF
D0 - D7
SPD
VSS
D0 - D7
VDDID
Data Sheet
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
Figure 2
S
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%
4. VDDID strap connections
(for memory device VDD , V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ .
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohms
+5%
Block Diagram - One Rank 32M × 64 DDR-I SDRAM DIMM HYS64D32× 00GU / HYS64D32300EU
using × 8 organized SDRAMs
12
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
VDD SPD
VDD/VDDQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D3
VSS
D0 - D15
BA0-BA1: SDRAMs D0 - D15
A0 - A13
A0-A13: SDRAMs D0 - D15
CKE: SDRAMs D8 - D15
RAS: SDRAMs D0 - D15
CAS
CAS: SDRAMs D0 - D15
CKE0
CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D15
Data Sheet
S
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
S
DQS
D12
DQS
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D13
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
D7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D15
Serial PD
SCL
Strap: see Note 4
BA0 - BA1
Figure 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0 - D15
D0 - D15
CKE1
RAS
S
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SPD
VREF
VDDID
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
SDA
WP
A0
A1
A2
SA0
SA1
SA2
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 SDRAMs
6 SDRAMs
6 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
(for memory device VDD, V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Block Diagram - Two Rank 64M × 64 DDR-I SDRAM DIMM HYS64D64× 20GU using × 8
Organized SDRAMs
13
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DM4/DQS13
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D2
S
DQS
D5
S
DQS
D6
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D3
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
RAS
D4
DQS6
DM6/DQS15
DQS2
DM2/DQS11
A0 - A13
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
BA0 - BA1
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
SCL
D8
RAS: SDRAMs D0 - D8
CAS
CAS: SDRAMs D0 - D8
CKE0
CKE: SDRAMs D0 - D8
WE
WE: SDRAMs D0 - D8
D7
SDA
WP
A0
A1
A2
SA0
SA1
SA2
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
SPD
maintained as shown.
D0 - D8 3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
D0 - D8
(for memory device VDD, V DDQ ):
D0 - D8
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ.
Strap: see Note 4
BA0-BA1: SDRAMs D0 - D8
A0-A13: SDRAMs D0 - D8
DQS
* Clock Wiring
Clock
SDRAMs
Input
Serial PD
DQS
S
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm
+5%
Figure 4
Data Sheet
Block Diagram - One Rank 32M × 72 DDR-I SDRAM DIMM HYS72D32× 00GU using × 8
organized SDRAMs
14
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
S
DQS
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS
S
D10
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
A0 - A13
CKE1
RAS
CAS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
S
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D8
DQS
S
D17
DQS
D7
D0 - D17
D0 - D17
VSS
D0 - D17
VDDID
Strap: see Note 4
A0-A13: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
S
VREF
BA0-BA1: SDRAMs D0 - D17
CKE: SDRAMs D9 - D17
RAS: SDRAMs D0 - D17
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SPD
VDD/VDDQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS
S
D13
S
DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D15
DQS7
DM7/DQS16
VDD SPD
DQS8
DM8/DQS17
BA0 - BA1
S
DQS
S
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Serial PD
SCL
CKE0
CKE: SDRAMs D0 - D8
WP
A0
A1
A2
WE
WE: SDRAMs D0 - D17
SA0
SA1
SA2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D16
* Clock Wiring
Clock
SDRAMs
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 SDRAMs
6 SDRAMs
6 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
SDA
(for memory device VDD, V DDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): V DD ≠ VDDQ
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Figure 5
Data Sheet
Block Diagram - Two Rank 64M × 72 DDR-I SDRAM DIMM HYS72D64× 20GU using × 8
Organized SDRAMs
15
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
DRAM1
DRAM2
CK R = 120 Ω ± 5%
DIMM
Connector
DRAM3
4 DRAM Loads
DRAM4
CK
DRAM1
DRAM5
DRAM2
R = 120 Ω ± 5%
DRAM6
DIMM
Connector
Cap.
Cap.
3 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
DRAM1
DRAM5
Cap.
DRAM6
DRAM3
Cap.
2 DRAM Loads
DRAM5
Cap.
Cap.
1 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
Cap.
R = 120 Ω ± 5%
Cap.
Cap.
DRAM5
Cap.
DIMM
Connector
DRAM1
DRAM3
Cap.
Cap.
Cap.
Cap.
Cap. = 1/2 DDR SDRAM input capacitance; 1.0 pF ± 20%
Figure 6
Data Sheet
Clock Net Wiring
16
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 6
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
Values
min.
typ.
max.
Unit Note/ Test
Condition
–0.5
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
–1
–
+3.6
V
–
–1
–
+3.6
V
–
–1
–
+3.6
V
–
0
–
+70
°C
–
Storage temperature (plastic)
VIN
VDD
VDDQ
TA
TSTG
-55
–
+150
°C
–
Power dissipation (per SDRAM component)
PD
–
1
–
W
–
Short circuit output current
IOUT
–
50
–
mA
–
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 7
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
VDD
Device Supply Voltage
VDD
Output Supply Voltage
VDDQ
Output Supply Voltage
VDDQ
EEPROM supply voltage
VDDSPD
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
VREF
Input Reference Voltage
Input Reference Voltage
VREF
Device Supply Voltage
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤166 MHz
fCK > 166 MHz 2)
fCK ≤166 MHz 3)
fCK > 166 MHz 2)3)
2.3
2.5
3.6
V
—
0
V
—
0
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V
VDDQ / 2
– 50 mV
VDDQ
/2
VDDQ / 2
V
fCK ≤166 MHz 4)
fCK > 166 MHz 2)4)
+ 50 mV
VREF – 0.04
VREF + 0.04 V
5)
Input High (Logic1) Voltage VIH(DC)
VREF + 0.15
8)
Input Low (Logic0) Voltage VIL(DC)
–0.3
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6
8)6)
I/O Termination Voltage
(System)
Data Sheet
VTT
17
V
8)
8)
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 7
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
7)
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤VIN ≤VDD;
All other pins not under test
= 0 V 8)9)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤VOUT ≤VDDQ 8)
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 8)
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V 8)
1) 0 ° C ≤TA ≤70 ° C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Data Sheet
18
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
Table 8
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, distributed refresh
IDD5
Self-Refresh Current
CKE ≤0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
19
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS64D32000HU-6-C
HYS72D32000HU-6-C
HYS64D64020HU-6-C
HYS72D64020HU-6-C
IDD Specification (PC2700, –6)
HYS64D16301HU-6-C
Part Number & Organization
Table 9
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
–6
–6
–6
–6
–6
Unit
Note 1)2)
typ.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
260
300
480
600
540
675
736
904
828
1017
mA
3)
320
380
560
680
630
765
816
984
918
1107
mA
3)4)
14
18
28
36
31.5
40.5
56
72
63
81
mA
5)
100
340
200
240
225
270
400
480
450
540
mA
5)
68
96
136
192
153
216
272
384
306
432
mA
5)
44
60
88
120
99
135
176
240
198
270
mA
5)
136
160
256
304
288
342
512
608
576
684
mA
5)
340
400
560
680
630
765
816
984
918
1107
mA
3)4)
360
440
600
720
675
810
856
1024
963
1152
mA
3)
540
640
1080
1280
1215
1440
1336
1584
1503
1782
mA
3)
5.6
11.2
11.2
22.4
12.6
25.2
44.8
22.4
25.2
25.2
mA
5)
820
960
1440
1720
1620
1935
1696
2024
1908
2277
mA
3)4)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
20
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS64D32000HU-5-C
HYS72D32000HU-5-C
HYS64D64020HU-5-C
HYS72D64020HU-5-C
IDD Specification (PC3200, –5)
HYS64D16301HU-5-C
Part Number & Organization
Table 10
128MB
256MB
256MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
–5
–5
–5
–5
–5
Unit
Note 1)2)
typ.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
280
340
560
640
630
720
848
984
954
1107
mA
3)
340
420
640
760
720
855
928
1104
1044
1242
mA
3)4)
14
18
28
36
31.5
40.5
56
72
63
81
mA
5)
120
144
240
288
270
324
480
576
540
648
mA
5)
76
104
152
208
171
234
304
416
342
468
mA
5)
48
64
96
128
108
144
192
256
216
288
mA
5)
152
184
288
344
324
387
576
688
648
774
mA
5)
400
480
680
800
765
900
968
1144
1089
1287
mA
3)4)
420
520
720
840
810
945
1008
1184
1134
1332
mA
3)
600
720
1200
1440
1350
1620
1488
1784
1674
2007
mA
3)
6
11.6
12
23.2
13.5
26.1
24
46.4
27
52.2
mA
5)
900
1060
1600
1920
1800
2160
1888
2264
2124
2547
mA
3)4)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
21
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.3
AC Characteristics
Table 11
AC Timing - Absolute Specifications –6/–5
Parameter
Symbol
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each
input)
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
st
Write command to 1 DQS latching transition
DQS-DQ skew (DQS and associated DQ
signals)
Data hold skew factor
DQ/DQS output hold time
tAC
tDQSCK
tCH
tCL
tHP
tCK
–6
–5
DDR333
DDR400B
Unit Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)
–0.6
+0.6
–0.5
+0.5
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
min. (tCL, tCH)
min. (tCL, tCH) ns
2)3)4)5)
2)3)4)5)
6
12
5
12
ns
CL = 3.0 2)3)4)5)
6
12
6
12
ns
CL = 2.5 2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
tDH
tDS
tIPW
0.45
—
0.4
—
ns
2)3)4)5)
0.45
—
0.4
—
ns
2)3)4)5)
2.2
—
tbd
—
ns
2)3)4)5)6)
tDIPW
tHZ
tLZ
tDQSS
tDQSQ
1.75
—
tbd
—
ns
2)3)4)5)6)
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
—
+0.40
—
+0.40
ns
TFBGA 2)3)4)5)
—
+0.45
—
+0.40
ns
TSOPII 2)3)4)5)
—
+0.50
—
+0.50
ns
TFBGA 2)3)4)5)
—
+0.55
—
+0.50
ns
TSOPII 2)3)4)5)
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
0.35
—
0.35
—
2)3)4)5)
0.2
—
0.2
—
0.2
—
0.2
—
tCK
tCK
tCK
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
0.75
—
0.6
—
ns
tQHS
tQH
tDQSL,H
DQS falling edge to CK setup time (write cycle) tDSS
DQS falling edge hold time from CK (write
tDSH
DQS input low (high) pulse width (write cycle)
2)3)4)5)
2)3)4)5)
cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
tMRD
tWPRES
tWPST
tWPRE
tIS
2)3)4)5)
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75
—
0.6
—
ns
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
Data Sheet
tRPRE
0.9
22
1.1
0.9
1.1
tCK
2)3)4)5)
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 11
AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Symbol
–6
–5
DDR333
DDR400B
Unit Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
0.40
0.60
0.40
0.60
42
70E+3 40
70E+3 ns
2)3)4)5)
60
—
55
—
ns
2)3)4)5)
72
—
65
—
ns
2)3)4)5)
tRCD
tRP
tRAP
tRRD
tWR
tDAL
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
12
—
10
—
ns
2)3)4)5)
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)11)
tWTR
tXSNR
tXSRD
tREFI
1
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)12)
tRPST
Active to Precharge command
tRAS
Active to Active/Auto-refresh command period tRC
Auto-refresh to Active/Auto-refresh command tRFC
Read postamble
tCK
2)3)4)5)
period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
1) 0 ° C ≤TA ≤70 ° C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
23
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
HYS72D64320HU–6–C
HYS64D64320HU–6–C
SPD Codes for PC2700 Modules “–6”
HYS72D32300HU–6–C
Table 12
HYS64D32300HU–6–C
SPD Contents
Part Number & Organization
4
HYS64D16301HU–6–C
SPD Contents
128MB 256MB 256MB 512MB
512MB
× 64
× 72
× 64
× 72
× 64
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
–6
–6
–6
–6
–6
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in
E2PROM
128
80
80
80
80
80
1
Total number of Bytes in
E2PROM
256
08
08
08
08
08
2
Memory Type DDR-I = 07h DDR SDRAM
07
07
07
07
07
3
# of Row Addresses
13
0D
0D
0D
0D
0D
4
# Number of Column
Addresses
9/10
09
0A
0A
0A
0A
5
# of DIMM Banks
1/2
01
01
01
02
02
6
Data Width (LSB)
× 64/× 72
40
40
48
40
48
7
Data Width (MSB)
0
00
00
00
00
00
8
Interface Voltage Levels
SSTL_2.5
04
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns] 6 ns
60
60
60
60
60
10
tAC SDRAM @ CLmax
(Byte 18) [ns]
0.75 ns
70
70
70
70
70
11
DIMM Configuration Type
(non- / ECC)
non-ECC/ECC
00
00
02
00
02
12
Refresh Rate
Self-Refresh 7.8 µs
82
82
82
82
82
13
Primary SDRAM width
× 16/ × 8
10
08
08
08
08
14
Error Checking SDRAM
width
na/ × 8
00
00
08
00
08
15
tCCD [cycles]
tCCD = 1 CLK
01
01
01
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
0E
0E
0E
17
Number of Banks on
SDRAM
4
04
04
04
04
04
18
CAS Latency
CAS latency = 2 & 2.5
0C
0C
0C
0C
0C
19
CS Latency
CS latency = 0
01
01
01
01
01
20
WE (Write) Latency
Write latency = 1
02
02
02
02
02
21
DIMM Attributes
unbuffered
20
20
20
20
20
Data Sheet
24
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D64320HU–6–C
HYS64D64320HU–6–C
HYS72D32300HU–6–C
HYS64D32300HU–6–C
HYS64D16301HU–6–C
SPD Codes for PC2700 Modules “–6” (cont’d)
Part Number & Organization
Table 12
128MB 256MB 256MB 512MB
512MB
× 64
× 72
× 64
× 72
× 64
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
–6
–6
–6
–6
–6
HEX
HEX
HEX
HEX
HEX
C1
C1
C1
C1
C1
tCK @ CLmax -0.5 (Byte 18) 7.5 ns
[ns]
75
75
75
75
75
24
tAC SDRAM @ CLmax -0.5 0.70 ns
[ns]
70
70
70
70
70
25
tCK @ CLmax -1 (Byte 18)
[ns]
not supported
00
00
00
00
00
26
tAC SDRAM @ CLmax -1
[ns]
not supported
00
00
00
00
00
27
tRPmin (ns)
18 ns
48
48
48
48
48
28
tRRDmin [ns]
12 ns
30
30
30
30
30
29
tRCDmin [ns]
18 ns
48
48
48
48
48
30
tRASmin [ns]
42 ns
2A
2A
2A
2A
2A
31
Module Density per Bank
128 MByte/ 256 MByte 20
40
40
40
40
32
tAS, tCS [ns]
0.75 ns
75
75
75
75
75
33
tAH, TCH [ns]
0.75 ns
75
75
75
75
75
34
tDS [ns]
0.45 ns
45
45
45
45
45
35
tDH [ns]
0.45 ns
45
45
45
45
45
36 to 40
not used
—
00
00
00
00
00
Byte#
Description
22
Component Attributes
23
—
41
tRCmin [ns]
60 ns
3C
3C
3C
3C
3C
42
tRFCmin [ns]
72 ns
48
48
48
48
48
43
tCKmax [ns]
12 ns
30
30
30
30
30
44
tDQSQmax [ns]
0.45 ns
2D
2D
2D
2D
2D
45
tQHSmax [ns]
0.55 ns
55
55
55
55
55
46 to 61
not used
—
00
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
00
63
Checksum of Byte 0-62
(LSB only)
—
E8
01
13
02
14
64
JEDEC ID Code for Infineon —
C1
C1
C1
C1
C1
65 to 71
JEDEC ID Code for Infineon —
00
00
00
00
00
Data Sheet
25
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D64320HU–6–C
HYS64D64320HU–6–C
HYS72D32300HU–6–C
HYS64D32300HU–6–C
HYS64D16301HU–6–C
SPD Codes for PC2700 Modules “–6” (cont’d)
Part Number & Organization
Table 12
128MB 256MB 256MB 512MB
512MB
× 64
× 72
× 64
× 72
× 64
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
–6
–6
–6
–6
–6
HEX
HEX
HEX
HEX
HEX
—
xx
xx
xx
xx
xx
Part Number, Char 1
—
36
36
37
36
37
74
Part Number, Char 2
—
34
34
32
34
32
75
Part Number, Char 3
—
44
44
44
44
44
76
Part Number, Char 4
—
31
33
33
36
36
77
Part Number, Char 5
—
36
32
32
34
34
78
Part Number, Char 6
—
33
33
33
33
33
79
Part Number, Char 7
—
30
30
30
32
32
80
Part Number, Char 8
—
31
30
30
30
30
81
Part Number, Char 9
—
48
48
48
48
48
82
Part Number, Char 10
—
55
55
55
55
55
83
Part Number, Char 11
—
36
36
36
36
36
84
Part Number, Char 12
—
43
43
43
43
43
85
Part Number, Char 13
—
20
20
20
20
20
86
Part Number, Char 14
—
20
20
20
20
20
87
Part Number, Char 15
—
20
20
20
20
20
88
Part Number, Char 16
—
20
20
20
20
20
89
Part Number, Char 17
—
20
20
20
20
20
90
Part Number, Char 18
—
20
20
20
20
20
91
Module Revision Code
—
xx
xx
xx
xx
xx
92
Test Program Revision
Code
—
xx
xx
xx
xx
xx
93
Module Manufacturing Date —
Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date —
Week
xx
xx
xx
xx
xx
95 to 98
Module Serial Number
—
xx
xx
xx
xx
xx
—
00
00
00
00
00
Byte#
Description
72
Module Manufacturer
Location
73
99 to 127 not used
Data Sheet
26
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D64320HU–5–C
HYS64D64320HU–5–C
HYS72D32300HU–5–C
HYS64D32300HU–5–C
HYS64D16301HU–5–C
SPD Codes for PC3200 Modules “–5”
Part Number & Organization
Table 13
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
–5
–5
–5
–5
–5
HEX
HEX
HEX
HEX
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
128
80
80
80
80
80
1
Total number of Bytes in E2PROM
256
08
08
08
08
08
2
Memory Type DDR-I = 07h
DDR SDRAM 07
07
07
07
07
3
# of Row Addresses
13
0D
0D
0D
0D
0D
4
# Number of Column Addresses
9/10
09
0A
0A
0A
0A
5
# of DIMM Banks
1/2
01
01
01
02
02
6
Data Width (LSB)
× 64/× 72
40
40
48
40
48
7
Data Width (MSB)
0
00
00
00
00
00
8
Interface Voltage Levels
SSTL_2.5
04
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
5 ns
50
50
50
50
50
10
tAC SDRAM @ CLmax (Byte 18) [ns]
0.50 ns
50
50
50
50
50
11
DIMM Configuration Type (non- / ECC) nonECC/ECC
00
00
02
00
02
12
Refresh Rate
Self-Refresh
7.8 µs
82
82
82
82
82
13
Primary SDRAM width
× 16/ × 8
10
08
08
08
08
14
Error Checking SDRAM width
na/ × 8
00
00
08
00
08
15
tCCD [cycles]
tCCD = 1 CLK
01
01
01
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
0E
0E
0E
17
Number of Banks on SDRAM
4
04
04
04
04
04
18
CAS Latency
CAS
latency = 2,
2.5, 3
1C
1C
1C
1C
1C
19
CS Latency
CS
latency = 0
01
01
01
01
01
20
WE (Write) Latency
Write
latency = 1
02
02
02
02
02
21
DIMM Attributes
unbuffered
20
20
20
20
20
22
Component Attributes
—
C1
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
6.0 ns
60
60
60
60
60
Data Sheet
27
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D64320HU–5–C
HYS64D64320HU–5–C
HYS72D32300HU–5–C
HYS64D32300HU–5–C
HYS64D16301HU–5–C
SPD Codes for PC3200 Modules “–5” (cont’d)
Part Number & Organization
Table 13
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
–5
–5
–5
–5
–5
HEX
HEX
HEX
HEX
HEX
0.50 ns
50
50
50
50
50
tCK @ CLmax -1 (Byte 18) [ns]
7.5 ns
75
75
75
75
75
26
tAC SDRAM @ CLmax -1 [ns]
0.50 ns
50
50
50
50
50
27
tRPmin (ns)
15 ns
3C
3C
3C
3C
3C
28
tRRDmin [ns]
10 ns
28
28
28
28
28
29
tRCDmin [ns]
15 ns
3C
3C
3C
3C
3C
30
tRASmin [ns]
40 ns
28
28
28
28
28
31
Module Density per Bank
128 MByte/
256 MByte
20
40
40
40
40
32
tAS, tCS [ns]
0.60 ns
60
60
60
60
60
33
tAH, TCH [ns]
0.60 ns
60
60
60
60
60
34
tDS [ns]
0.40 ns
40
40
40
40
40
35
tDH [ns]
0.40 ns
40
40
40
40
40
36 to 40
not used
—
00
00
00
00
00
41
tRCmin [ns]
55 ns
37
37
37
37
37
42
tRFCmin [ns]
65 ns
41
41
41
41
41
43
tCKmax [ns]
10 ns
28
28
28
28
28
44
tDQSQmax [ns]
0.40 ns
28
28
28
28
28
45
tQHSmax [ns]
0.50 ns
50
50
50
50
50
46 to 61
not used
—
00
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
00
63
Checksum of Byte 0-62 (LSB only)
—
E4
FD
0F
FE
10
64
JEDEC ID Code for Infineon
—
C1
C1
C1
C1
C1
Byte#
Description
24
tAC SDRAM @ CLmax -0.5 [ns]
25
65 to 71
JEDEC ID Code for Infineon
—
00
00
00
00
00
72
Module Manufacturer Location
—
xx
xx
xx
xx
xx
73
Part Number, Char 1
—
36
36
37
36
37
74
Part Number, Char 2
—
34
34
32
34
32
75
Part Number, Char 3
—
44
44
44
44
44
76
Part Number, Char 4
—
31
33
33
36
36
77
Part Number, Char 5
—
36
32
32
34
34
Data Sheet
28
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
SPD Contents
HYS72D64320HU–5–C
HYS64D64320HU–5–C
HYS72D32300HU–5–C
HYS64D32300HU–5–C
HYS64D16301HU–5–C
SPD Codes for PC3200 Modules “–5” (cont’d)
Part Number & Organization
Table 13
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
–5
–5
–5
–5
–5
HEX
HEX
HEX
HEX
HEX
—
33
33
33
33
33
Part Number, Char 7
—
30
30
30
32
32
80
Part Number, Char 8
—
31
30
30
30
30
81
Part Number, Char 9
—
48
48
48
48
48
82
Part Number, Char 10
—
55
55
55
55
55
83
Part Number, Char 11
—
35
35
35
35
35
84
Part Number, Char 12
—
43
43
43
43
43
85
Part Number, Char 13
—
20
20
20
20
20
86
Part Number, Char 14
—
20
20
20
20
20
87
Part Number, Char 15
—
20
20
20
20
20
88
Part Number, Char 16
—
20
20
20
20
20
89
Part Number, Char 17
—
20
20
20
20
20
90
Part Number, Char 18
—
20
20
20
20
20
91
Module Revision Code
—
xx
xx
xx
xx
xx
92
Test Program Revision Code
—
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
—
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
—
xx
xx
xx
xx
xx
95 to 98
Module Serial Number
—
xx
xx
xx
xx
xx
—
0
0
0
0
0
Byte#
Description
78
Part Number, Char 6
79
99 to 127 not used
Data Sheet
29
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Package Outlines
5
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 7
Data Sheet
L-D IM-184-18
Package Outlines - Raw Card C (128 MByte, 1 Rank Module)
30
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
L -D IM - 1 8 4- 3 0
Figure 8
Data Sheet
Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, ECC)
31
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
1)
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 9
Data Sheet
L -D IM - 1 8 4- 3 1
Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, ECC)
32
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
31.75 ±0.13
4 ±0.1
A
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
93
184
17.8
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
L-D IM-184-32
Figure 10
Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, Non ECC)
Data Sheet
33
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
31.75 ±0.13
4 ±0.1
A
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
93
184
17.8
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
L-D IM-184-33
Figure 11
Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, Non ECC)
Data Sheet
34
V1.0, 2003-07
www.infineon.com
Published by Infineon Technologies AG