AD ADG5209BCPZ-RL7 High voltage, latch-up proof Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
5.5 pF off source capacitance
52 pF off drain capacitance
0.4 pC charge injection
Low on resistance: 160 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
Human body model (HBM) ESD rating
4 kV I/O port to supplies
1 kV I/O port to I/O port
4 kV all other pins
ADG5209
ADG5208
S1A
S1
DA
S4A
D
S1B
DB
S4B
S8
1-OF-4
DECODER
1-OF-8
DECODER
A0 A1 A2 EN
A0
A1
EN
09917-001
Data Sheet
High Voltage, Latch-Up Proof,
4-/8-Channel Multiplexers
ADG5208/ADG5209
Figure 1.
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
The ADG5208/ADG5209 are monolithic CMOS analog multiplexers comprising eight single channels and four differential
channels, respectively. The ADG5208 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2. The ADG5209 switches one of
four differential inputs to a common differential output, as
determined by the 2-bit binary address lines, A0 and A1.
An EN input on both devices enables or disables the device.
When EN is disabled, all channels switch off. The ultralow
capacitance and charge injection of these switches make them
ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make
these devices suitable for video signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
The ADG5208/ADG5209 do not have VL pins; instead, the logic
power supply is generated internally by an on-chip voltage
generator.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors
to prevent latch-up even under severe overvoltage conditions.
0.4 pC Charge Injection.
Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5208/ADG5209 can be operated from dual supplies
of up to ±22 V.
Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5208/ADG5209 can be operated from a single rail
power supply of up to 40 V.
3 V Logic-Compatible Digital Inputs.
VINH = 2.0 V, VINL = 0.8 V.
No VL Logic Power Supply Required.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADG5208/ADG5209
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................9
Applications ....................................................................................... 1
ESD Caution...................................................................................9
Functional Block Diagrams ............................................................. 1
Pin Configurations and Function Descriptions ......................... 10
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 12
Product Highlights ........................................................................... 1
Test Circuits..................................................................................... 16
Revision History ............................................................................... 2
Terminology .................................................................................... 19
Specifications..................................................................................... 3
Trench Isolation .............................................................................. 20
±15 V Dual Supply ....................................................................... 3
Applications Information .............................................................. 21
±20 V Dual Supply ....................................................................... 4
Outline Dimensions ....................................................................... 22
12 V Single Supply ........................................................................ 5
Ordering Guide .......................................................................... 22
36 V Single Supply ........................................................................ 6
Continuous Current per Channel, Sx or Dx ............................. 8
REVISION HISTORY
3/12—Rev. 0 to Rev. A
Added 16-Lead LFCSP....................................................... Universal
Changes to Ordering Guide ...........................................................22
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADG5208/ADG5209
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
25°C
160
200
3.5
8
40
50
±0.005
±0.1
±0.005
±0.1
±0.01
±0.2
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; see Figure 28
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
250
280
9
10
65
70
±0.2
±0.4
±0.4
±1.4
±0.5
±1.4
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ±10 V, IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD =  10 V; see Figure 30
VS = ±10 V, VD =  10 V; see Figure 30
VS = VD = ±10 V; see Figure 27
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
3
VIN = VGND or VDD
Charge Injection, QINJ
0.4
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−90
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
−3 dB Bandwidth
ADG5208
ADG5209
Insertion Loss
54
133
−6.4
MHz typ
MHz typ
dB typ
5.5
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 32
VS = 0 V, f = 1 MHz
52
26
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
170
205
145
185
120
145
65
V min
V max
µA typ
µA max
pF typ
245
275
220
245
165
180
30
CS (Off )
CD (Off )
ADG5208
ADG5209
Rev. A | Page 3 of 24
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 34
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 32
ADG5208/ADG5209
Parameter
CD (On), CS (On)
ADG5208
ADG5209
POWER REQUIREMENTS
IDD
ISS
Data Sheet
25°C
−40°C to +85°C
58
31
45
55
0.001
Unit
Test Conditions/Comments
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
µA typ
µA max
µA typ
µA max
V min/V max
Digital inputs = 0 V or VDD
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±15 V, IS = −1 mA; see Figure 28
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −1 mA
70
1
±9/±22
VDD/VSS
1
−40°C to +125°C
GND = 0 V
Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
140
160
3.5
8
34
45
±0.005
±0.1
±0.005
±0.1
±0.01
±0.2
−40°C to +85°C
200
230
9
10
55
60
±0.2
±0.4
±0.4
±1.4
±0.5
±1.4
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
3
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
Charge Injection, QINJ
0.3
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−90
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
160
195
145
170
120
140
55
Ω max
Ω typ
Ω max
225
255
200
225
155
170
30
Rev. A | Page 4 of 24
VS = ±15 V, IS = −1 mA
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD =  15 V; see Figure 30
VS = ±15 V, VD =  15 V; see Figure 30
VS = VD = ±15 V; see Figure 27
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 34
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
Data Sheet
ADG5208/ADG5209
Parameter
−3 dB Bandwidth
ADG5208
ADG5209
Insertion Loss
25°C
60
130
−5.6
MHz typ
MHz typ
dB typ
CS (Off )
CD (Off )
ADG5208
ADG5209
CD (On), CS (On)
ADG5208
ADG5209
POWER REQUIREMENTS
IDD
5.5
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
VS = 0 V, f = 1 MHz
51
26
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
57
31
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
ISS
−40°C to +85°C
50
70
0.001
Unit
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF; see Figure 32
Digital inputs = 0 V or VDD
1
±9/±22
µA typ
µA max
µA typ
µA max
V min/V max
−40°C to +125°C
Unit
Test Conditions/Comments
0 V to VDD
V
Ω typ
110
VDD/VSS
1
−40°C to +125°C
GND = 0 V
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
350
500
5
610
700
Ω max
Ω typ
20
160
280
22
24
VS = 0 V to 10 V, IS = −1 mA
335
370
Ω max
Ω typ
Ω max
nA typ
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 30
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.005
±0.1
±0.005
±0.2
Drain Off Leakage, ID (Off )
±0.1
±0.01
±0.2
±0.4
±1.4
±0.5
±1.4
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±0.4
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
VS = 0 V to 10 V, IS = −1 mA; see
Figure 28
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
3
Rev. A | Page 5 of 24
nA max
nA typ
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 30
nA max
nA typ
nA max
VS = VD = 1 V/10 V; see Figure 27
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
ADG5208/ADG5209
Parameter
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
Data Sheet
25°C
−40°C to +85°C
−40°C to +125°C
330
380
345
400
160
175
Test Conditions/Comments
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 34
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 32
Break-Before-Make Time Delay, tD
210
270
215
275
115
140
135
Charge Injection, QINJ
0.3
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−90
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
−3 dB Bandwidth
ADG5208
ADG5209
Insertion Loss
60
120
−8.8
MHz typ
MHz typ
dB typ
6
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
VS = 6 V, f = 1 MHz
56
28
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
63
35
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
tON (EN)
tOFF (EN)
70
CS (Off )
CD (Off )
ADG5208
ADG5209
CD (On), CS (On)
ADG5208
ADG5209
POWER REQUIREMENTS
IDD
40
50
VDD
1
Unit
65
9/40
µA typ
µA max
V min/V max
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
GND = 0 V, VSS = 0 V
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
25°C
−40°C to +85°C
150
Test Conditions/Comments
VS = 0 V to 30 V, IS = −1 mA; see
Figure 28
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −1 mA
170
3.5
215
245
Ω max
Ω typ
8
35
55
9
10
VS = 0 V to 30 V, IS = −1 mA
65
70
Ω max
Ω typ
Ω max
nA typ
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 30
±0.005
±0.1
±0.2
±0.4
Rev. A | Page 6 of 24
nA max
Data Sheet
Parameter
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
ADG5208/ADG5209
25°C
±0.005
−40°C to +85°C
−40°C to +125°C
Unit
nA typ
±0.1
±0.01
±0.2
±0.4
±1.4
VS = VD = 1 V/30 V; see Figure 27
±0.5
±1.4
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
3
Break-Before-Make Time Delay, tD
185
230
170
210
125
180
70
Charge Injection, QINJ
0.4
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−90
dB typ
Channel-to-Channel Crosstalk
−90
dB typ
−3 dB Bandwidth
ADG5208
ADG5209
Insertion Loss
65
130
−6
MHz typ
MHz typ
dB typ
5.5
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
VS = 18 V, f = 1 MHz
51
25
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
57
32
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
tON (EN)
tOFF (EN)
245
259
230
255
180
180
35
CS (Off )
CD (Off )
ADG5208
ADG5209
CD (On), CS (On)
ADG5208
ADG5209
POWER REQUIREMENTS
IDD
80
100
VDD
1
Test Conditions/Comments
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 30
130
9/40
Guaranteed by design; not subject to production test.
Rev. A | Page 7 of 24
µA typ
µA max
V min/V max
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 34
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 32
GND = 0 V, VSS = 0 V
ADG5208/ADG5209
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx
Table 5. ADG5208
Parameter
CONTINUOUS CURRENT, Sx OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
25°C
85°C
125°C
Unit
40
69
24
37
14.5
18
mA maximum
mA maximum
42
75
26.5
40
14.5
18
mA maximum
mA maximum
28
40
19
25
12
14.5
mA maximum
mA maximum
40
72
26
39
14.5
18
mA maximum
mA maximum
25°C
85°C
125°C
Unit
29
51
19
30
12
16
mA maximum
mA maximum
30
55
20
32
12.5
17
mA maximum
mA maximum
20
29
14
20
10
12.5
mA maximum
mA maximum
30
54
20
31
12.5
17
mA maximum
mA maximum
Table 6. ADG5209
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
Rev. A | Page 8 of 24
Data Sheet
ADG5208/ADG5209
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx, D, or Dx Pins
ADG5208
ADG5209
Continuous Current, Sx, D, or
Dx Pins2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer
Board)
16-Lead LFCSP (4-Layer
Board)
Reflow Soldering Peak
Temperature, Pb Free
HBM ESD
I/O Port to Supplies
I/O Port to I/O Port
All Other Pins
1
2
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
126 mA (pulsed at 1 ms, 10%
duty cycle maximum)
92 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
260(+0/−5)°C
4 kV
1 kV
4 kV
Overvoltages at the Ax, EN, Sx, D, and Dx pins are clamped by internal
diodes. Limit current to the maximum ratings given.
See Table 5 and Table 6.
Rev. A | Page 9 of 24
ADG5208/ADG5209
Data Sheet
D 8
9
S8
11 VDD
S2 3
TOP VIEW
(Not to Scale)
10 S5
9
S3 4
S6
S7 8
10 S7
ADG5208
S8 7
S4 7
12 GND
S1 2
S4 5
11 S6
09917-002
S3 6
13 A2
VSS 1
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
Figure 2. ADG5208 Pin Configuration (TSSOP)
09917-003
14 GND
TOP VIEW 13 VDD
S2 5 (Not to Scale) 12 S5
S1 4
14 A1
15 A2
ADG5208
D 6
VSS 3
16 EN
16 A1
A0 1
EN 2
15 A0
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. ADG5208 Pin Configuration (LFCSP)
Table 8. ADG5208 Pin Function Descriptions
TSSOP
1
2
Pin No.
LFCSP
15
16
Mnemonic
A0
EN
3
1
VSS
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Exposed Pad
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high, the
Ax logic inputs determine the on switches.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG5208 Truth Table
A2
X1
0
0
0
0
1
1
1
1
1
A1
X1
0
0
1
1
0
0
1
1
A0
X1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
X is don’t care.
Rev. A | Page 10 of 24
On Switch
None
1
2
3
4
5
6
7
8
GND
VSS 3
14
VDD
ADG5209
VSS 1
12 VDD
S1A 2
ADG5209
11 S1B
S3A 6
11
S3B
S2A 3
TOP VIEW
(Not to Scale)
10 S2B
S4A 7
10
S4B
DA 8
9
DB
09917-004
TOP VIEW 13 S1B
S2A 5 (Not to Scale) 12 S2B
9
DB 7
S3B
S4B 8
DA 6
S3A 4
S4A 5
S1A 4
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
Figure 4. ADG5209 Pin Configuration (TSSOP)
09917-005
A1
15
13 GND
16
14 A1
A0 1
EN 2
16 EN
ADG5208/ADG5209
15 A0
Data Sheet
Figure 5. ADG5209 Pin Configuration (LFCSP)
Table 10. ADG5209 Pin Function Descriptions
Pin No.
TSSOP LFCSP
1
15
2
16
Mnemonic
A0
EN
3
1
VSS
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
S1A
S2A
S3A
S4A
DA
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
Exposed Pad
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine the on switches.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Drain Terminal A. This pin can be an input or an output.
Drain Terminal B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 11. ADG5209 Truth Table
A1
X1
0
0
1
1
1
A0
X1
0
1
0
1
EN
0
1
1
1
1
On Switch Pair
None
1
2
3
4
X is don’t care.
Rev. A | Page 11 of 24
ADG5208/ADG5209
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
160
TA = 25°C
TA = 25°C
140
VDD = +18V
VSS = –18V
120
ON RESISTANCE (Ω)
120
100
VDD = +20V
VSS = –20V
80
VDD = +22V
VSS = –22V
60
100
60
40
20
20
0
–25
–20
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
VDD = 39.6V
VSS = 0V
VDD = 36V
VSS = 0V
80
40
0
09917-006
ON RESISTANCE (Ω)
VDD = 32.4V
VSS = 0V
140
0
5
10
15
20
25
30
35
40
VS, VD (V)
09917-009
160
Figure 9. RON as a Function of VS, VD (36 V Single Supply)
Figure 6. RON as a Function of VS, VD (±20 V Dual Supply)
250
250
TA = 25°C
VDD = +15V
VSS = –15V
VDD = +9V
VSS = –9V
200
200
ON RESISTANCE (Ω)
150
VDD = +13.2V
VSS = –13.2V
100
VDD = +16.5V
VSS = –16.5V
VDD = +15V
VSS = –15V
TA = +25°C
100
TA = –40°C
–15
–10
–5
0
5
10
15
20
VS, VD (V)
0
–15
09917-007
0
–20
–10
–5
0
5
10
15
VS, VD (V)
09917-010
50
50
Figure 10. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
Figure 7. RON as a Function of VS, VD (±15 V Dual Supply)
200
500
TA = 25°C
VDD = 9V
VSS = 0V
450
180
VDD = 10.8V
VSS = 0V
400
160
350
300
ON RESISTANCE (Ω)
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
250
200
150
140
TA = +25°C
80
TA = –40°C
60
50
20
0
2
4
6
8
10
12
VS, VD (V)
14
TA = +85°C
100
40
0
TA = +125°C
120
100
09917-008
ON RESISTANCE (Ω)
TA = +85°C
150
VDD = +20V
VSS = –20V
0
–20
–15
–10
–5
0
5
10
15
20
VS, VD (V)
Figure 11. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
Figure 8. RON as a Function of VS, VD (12 V Single Supply)
Rev. A | Page 12 of 24
09917-011
ON RESISTANCE (Ω)
TA = +125°C
Data Sheet
ADG5208/ADG5209
100
500
IS (OFF) + –
400
TA = +125°C
350
TA = +85°C
50
LEAKAGE CURRENT (pA)
300
TA = +25°C
250
200
TA = –40°C
150
ID (OFF) + –
ID (OFF) – +
0
IS (OFF) – +
–50
–100
ID, IS (ON) + +
ID, IS (ON) – –
100
–150
50
VDD = 12V
VSS = 0V
0
2
4
6
8
10
12
VS, VD (V)
–200
09917-012
0
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
0
25
50
75
100
125
TEMPERATURE (°C)
09917-015
ON RESISTANCE (Ω)
450
Figure 15. Leakage Currents vs. Temperature, ±20 V Dual Supply
Figure 12. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
100
250
IS (OFF) – +
ID (OFF) – +
VDD = 36V
VSS = 0V
0
TA = +125°C
150
TA = +85°C
TA = +25°C
100
TA = –40°C
ID, IS (ON) + +
–100
IS (OFF) + –
–200
–300
–400
–500
50
0
5
10
15
20
25
30
35
VS, VD (V)
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 13. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply
50
200
IS (OFF) – +
IS (OFF) + –
ID, IS (ON) + +
0
IS (OFF) + –
ID, IS (ON) + +
–50
ID (OFF) + –
ID (OFF) – +
–100
ID, IS (ON) – –
–150
–200
–250
25
50
75
100
125
TEMPERATURE (°C)
Figure 14. Leakage Currents vs. Temperature, ±15 V Dual Supply
ID (OFF) – +
–400
–600
ID (OFF) + –
–800
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
0
IS (OFF) – +
–200
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
ID, IS (ON) – –
–1000
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. A | Page 13 of 24
09917-017
LEAKAGE CURRENT (pA)
0
09917-014
LEAKAGE CURRENT (pA)
ID, IS (ON) – –
–700
09917-013
0
ID (OFF) + –
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
–600
09917-016
LEAKAGE CURRENT (pA)
ON RESISTANCE (Ω)
200
ADG5208/ADG5209
Data Sheet
0
0
–20
–40
–60
–80
NO DECOUPLING
CAPACITORS
–60
–80
–100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
–120
1k
09917-018
–140
10k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
–6
0
TA = 25°C
VDD = +15V
–20 VSS = –15V
TA = 25°C
VDD = +15V
VSS = –15V
–7
ATTENUATION (dB)
–40
BETWEEN S1 AND S2
–60
09917-021
DECOUPLING
CAPACITORS
–100
–120
CROSSTALK (dB)
TA = 25°C
VDD = +15V
VSS = –15V
–40
ACPSRR (dB)
OFF ISOLATION (dB)
TA = 25°C
VDD = +15V
–20 VSS = –15V
–80
–8
ADG5208
ADG5209
–9
–10
–100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
–12
100k
09917-019
–140
10k
1M
1G
6
16
TA = 25°C
DEMUX (DRAIN TO SOURCE)
5
VDD = +15V
VSS = –15V
8
VDD = +36V
VSS = 0V
6
4
VDD = +12V
VSS = 0V
2
0
–20
–10
0
10
20
TA = 25°C
MUX (SOURCE TO DRAIN)
4
VDD = +20V
VSS = –20V
VDD = +15V
VSS = –15V
3
VDD = +36V
VSS = 0V
2
VDD = +12V
VSS = 0V
1
0
–1
30
40
VS (V)
–2
–20
–10
0
10
20
30
40
VS (V)
Figure 23. Charge Injection vs. Source Voltage, Source to Drain
Figure 20. Charge Injection vs. Source Voltage, Drain to Source
Rev. A | Page 14 of 24
09917-039
10
CHARGE INJECTION (pC)
VDD = +20V
VSS = –20V
12
09917-020
CHARGE INJECTION (pC)
100M
Figure 22. Bandwidth
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
14
10M
FREQUENCY (Hz)
09917-023
–11
BETWEEN S1 AND S8
–120
Data Sheet
ADG5208/ADG5209
350
80
300
70
VDD = +12V
VSS = 0V
200
150
VDD = +20V
VSS = –20V
VDD = +15V
VSS = –15V
SOURCE/DRAIN ON
60
VDD = +36V
VSS = 0V
CAPACITANCE (pF)
TIME (ns)
250
TA = 25°C
VDD = +15V
VSS = –15V
100
50
DRAIN OFF
40
30
20
50
10
0
20
40
60
80
100
120
TEMPERATURE (°C)
09917-024
–20
0
–15
Figure 24. tTRANSITION Times vs. Temperature
SOURCE/DRAIN ON
TA = 25°C
VDD = +15V
VSS = –15V
CAPACITANCE (pF)
DRAIN OFF
25
20
15
10
SOURCE OFF
–10
–5
0
VS (V)
5
10
15
09917-025
0
–15
0
5
10
15
Figure 26. ADG5208 Capacitance vs. Source Voltage, ±15 V Dual Supply
30
5
–5
VS (V)
40
35
–10
09917-040
SOURCE OFF
0
–40
Figure 25. ADG5209 Capacitance vs. Source Voltage, ±15 V Dual Supply
Rev. A | Page 15 of 24
ADG5208/ADG5209
Data Sheet
TEST CIRCUITS
ID (ON)
IS (OFF)
A
A
D
VD
NC = NO CONNECT
ID (OFF)
Sx
D
A
09917-031
Sx
VD
VS
09917-027
NC
Figure 30. Off Leakage
Figure 27. On Leakage
VSS
VDD
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
50Ω
Sx
IDS
50Ω
VS
D
V1
RL
50Ω
GND
VS
RON = V1/IDS
OFF ISOLATION = 20 log
Figure 28. On Resistance
VDD
VSS
VDD
0.1µF
VSS
0.1µF
0.1µF
VOUT
VOUT
VS
Figure 31. Off Isolation
0.1µF
NETWORK
ANALYZER
09917-030
D
09917-028
Sx
VOUT
VDD
S1
VSS
VDD
RL
50Ω
D
S2
NETWORK
ANALYZER
VSS
50Ω
Sx
RL
50Ω
VS
D
RL
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
09917-029
GND
INSERTION LOSS = 20 log
Figure 29. Channel-to-Channel Crosstalk
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 32. Bandwidth
Rev. A | Page 16 of 24
VOUT
09917-033
VS
Data Sheet
ADG5208/ADG5209
3V
tr < 20ns
tf < 20ns
ADDRESS
DRIVE (VIN)
50%
50%
VDD
VSS
VDD
VSS
A0
S1
0V
VIN
VS1
A1
50Ω
S2 TO S7
A2
tTRANSITION
tTRANSITION
VS8
S8
90%
ADG5208*
2.0V
OUTPUT
OUTPUT
D
EN
GND
300Ω
35pF
09917-034
90%
*SIMILAR CONNECTION FOR ADG5209.
Figure 33. Address to Output Switching Times, tTRANSITION
VDD
VSS
VDD
VSS
3V
ADDRESS
DRIVE (VIN)
A0
S1
VIN
0V
VS
A1
50Ω
S2 TO S7
A2
S8
80%
ADG5208*
80%
OUTPUT
2.0V
OUTPUT
D
EN
GND
300Ω
35pF
09917-035
tD
*SIMILAR CONNECTION FOR ADG5209.
Figure 34. Break-Before-Make Time Delay, tD
3V
ENABLE
DRIVE (VIN)
50%
VDD
VSS
VDD
VSS
A0
50%
S1
VS
A1
S2 TO S8
0V
A2
ADG5208*
tOFF (EN)
OUTPUT
0.9VOUT
D
EN
OUTPUT
VIN
50Ω
GND
300Ω
35pF
0.1VOUT
*SIMILAR CONNECTION FOR ADG5209.
Figure 35. Enable Delay, tON (EN), tOFF (EN)
Rev. A | Page 17 of 24
09917-036
tON (EN)
ADG5208/ADG5209
Data Sheet
3V
VDD
VSS
VDD
VSS
A0
A1
VIN
A2
ADG5208*
ΔVOUT
S
D
EN
QINJ = CL × ΔVOUT
VS
GND
VOUT
CL
1nF
VIN
*SIMILAR CONNECTION FOR ADG5209.
Figure 36. Charge Injection
Rev. A | Page 18 of 24
09917-037
VOUT
RS
Data Sheet
ADG5208/ADG5209
TERMINOLOGY
IDD
IDD represents the positive supply current.
CIN
CIN represents digital input capacitance.
ISS
ISS represents the negative supply current.
tON (EN)
tON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
tOFF (EN)
tOFF (EN) represents the delay time between the 50% and 90%
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal D and
Terminal S.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
Break-Before-Make Time Delay (tD)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
On Response
On response is the frequency response of the on switch.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of signal on the output to the amplitude of the
modulation is the ACPSRR.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. A | Page 19 of 24
ADG5208/ADG5209
Data Sheet
TRENCH ISOLATION
In the ADG5208/ADG5209, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and the
result is a completely latch-up proof switch.
PMOS
P WELL
N WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 37. Trench Isolation
Rev. A | Page 20 of 24
09917-038
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
NMOS
Data Sheet
ADG5208/ADG5209
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persist until the power supply is
turned off. The ADG5208/ADG5209 high voltage switches
allow single-supply operation from 9 V to 40 V and dual-supply
operation from ±9 V to ±22 V.
Rev. A | Page 21 of 24
ADG5208/ADG5209
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
4
2.70
2.60 SQ
2.50
9
0.80
0.75
0.70
0.45
0.40
0.35
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
0.20 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
08-16-2010-C
TOP VIEW
Figure 39. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG5208BRUZ
ADG5208BRUZ-RL7
ADG5208BCPZ-RL7
ADG5209BCPZ-RL7
ADG5209BRUZ
ADG5209BRUZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
Package Option
RU-16
RU-16
CP-16-17
CP-16-17
RU-16
RU-16
Data Sheet
ADG5208/ADG5209
NOTES
Rev. A | Page 23 of 24
ADG5208/ADG5209
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09917-0-3/12(A)
Rev. A | Page 24 of 24