MAS MAS6180A2TC00 Am receiver ic Datasheet

DA6180.001
27 December, 2006
MAS6180
AM Receiver IC
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Single Band Receiver IC
High Sensitivity
Very Low Power Consumption
Wide Supply Voltage Range
Power Down Control
Control for AGC On
High Selectivity by Crystal Filter
Fast Startup Feature
DESCRIPTION
The MAS6180 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to receive
time signals in the frequency range from 40 kHz to 100
kHz. Only a few external components are required for
time signal receiver. The circuit has preamplifier, wide
range automatic gain control, demodulator and output
comparator built in. The output signal can be
processed directly by an additional digital circuitry to
FEATURES
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extract the data from the received signal. The control
for AGC (automatic gain control) can be used to switch
AGC on or off if necessary.
MAS6180 has options for compensating shunt
capacitances of different crystals (See ordering
information on page 9).
APPLICATIONS
Single Band Receiver IC
Highly Sensitive AM Receiver, 0.4 µVRMS typ.
Wide Supply Voltage Range from 1.1 V to 3.6 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Crystal Compensation Capacitance Options
Differential Input
•
Single Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HGB
(Switzerland) and BPC (China)
BLOCK DIAGRAM
VDD
QOP
VDD
AGC Amplifier
QI
AON
QOM
RFIP
RFIM
Demodulator
&
Comparator
OUT
Power Supply/Biasing
VDD
VSS
PDN
AGC
DEC
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MAS6180 PAD LAYOUT
VSS pad
bonded
first!
VDD
VSS
QOP
RFIM
QOM
RFIP
QI
PDN
AGC
AON
OUT
DEC
1370 µm
1070 µm
MAS6180Ax,
x = 1, 2, 5
DIE size = 1.07 mm x 1.37 mm; PAD size = 80 µm x 80 µm
Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Name
X-coordinate
Y-coordinate
Power Supply Voltage
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for Crystal
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
VDD
QOP
QOM
QI
152 µm
152 µm
152 µm
152 µm
1137 µm
1002 µm
815 µm
629 µm
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
152 µm
152 µm
915 µm
915 µm
915 µm
915 µm
915 µm
915 µm
443 µm
257 µm
265 µm
451 µm
636 µm
824 µm
1010 µm
1158 µm
Note
1
2
3
4
5
5
Notes:
1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left
unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD
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6)
ABSOLUTE MAXIMUM RATINGS
All Voltages with Respect to Ground
Parameter
Supply Voltage
Input Voltage
ESD Rating
Symbol
VDD-VSS
VIN
VESD
Latchup Current Limit
ILUT
Operating Temperature
Storage Temperature
TOP
TST
Conditions
For all pins,
Human Body Model (HBM),
ESD Association Standard
Test Method ESD-STM5.11998, CESD = 100 pF,
Rs = 1500 Ω),
For all pins,
test according to
Micro Analog Systems
specification ESQ0141.
See note below.
Min
Max
Unit
- 0.3
VSS-0.3
±2
5.5
VDD+0.3
V
V
kV
±100
mA
-40
- 55
+85
+150
°C
°C
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will
not be destroyed.
Note: In latchup testing the supply voltages are connected normally to the tested device. Then pulsed test current is fed to each input
separately and device current consumption is observed. If the device current consumption increases suddenly due to test current pulses
and the abnormally high current consumption continues after test current pulses are cut off then the device has gone to latch up. Current
pulse is turned on for 10 ms and off for 20 ms.
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.5V, Temperature = 25°C, unless otherwise specified.
Parameter
Operating Voltage
Current Consumption
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
Input Levels |lIN|<0.5 µA
Output Current
VOL<0.2 VDD;VOH >0.8 VDD
Output Pulse
Symbol
VDD
IDD
IDDoff
fIN
VIN min
VIN max
RRFI
CRFI
VIL
VIH
|IOUT|
T100ms
T200ms
T500ms
T800ms
Startup Time
TStart
Output Delay Time
TDelay
Conditions
VDD=1.5 V, Vin=0 µVrms
VDD=1.5 V, Vin=20 mVrms
VDD=3.6 V, Vin=0 µVrms
VDD=3.6 V, Vin=20 mVrms
See note below.
Min
1.10
40
24
Typ
55
40
58
43
40
0.4
Max
Unit
3.6
80
65
µA
0.1
100
1
20
Differential Input,
f=40 kHz..77.5 kHz
600
0.5
0.35
VDD-0.35
5
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
Fast Start-up, Vin=0.4 µVrms
Fast Start-up, Vin=20 mVrms
V
µA
kHz
µVrms
mVrms
kΩ
pF
V
µA
50
140
ms
150
230
ms
400
500
600
ms
700
800
900
ms
1.3
3.5
50
s
100
ms
Note: Stand-by current consumption may increase if V IH and V IL differ from VDD and 0 respectively.
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TYPICAL APPLICATION
Note 1
Note 4
Optional
Control
for AGC on/hold
MAS6180A1, A2
VDD
QOP
Note 5
QI
VDD
Ferrite
Antenna
AON
QOM
RFIP
Demodulator
&
Comparator
AGC Amplifier
RFIM
OUT
Receiver
Output
Power Supply/Biasing
VDD
VDD
VSS
AGC
PDN
DEC
CAGC
10 µF
1.4 V
CDEC
47 nF
VDD
GND
Note 3
Power Down /
Fast Startup
Control
AGC
VDD
OR
DEC
CAGC +
10 µF
CDEC
47 nF
Note 2
VDD
Note 2
Figure 1. Application circuit of internal compensation capacitance option version MAS6180A1 and A2.
Note 1
Note 4
Optional
Control
for AGC on/hold
CC_EXT=C0
MAS6180A5
VDD
QOP
Note 5
QI
RFIP
VDD
Ferrite
Antenna
AGC Amplifier
RFIM
VDD
AON
QOM
Demodulator
&
Comparator
Receiver
Output
Power Supply/Biasing
VDD
VSS
PDN
AGC
VDD
Note 3
Power Down /
Fast Startup
Control
AGC
DEC
CAGC
10 µF
1.4 V
GND
OUT
CDEC
47 nF
OR
DEC
CAGC +
10 µF
CDEC
47 nF
Note 2
VDD
VDD
Note 2
Figure 2. Application circuit of external compensation capacitance option version MAS6180A5.
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TYPICAL APPLICATION (Continued)
Note 1
Note 4
Optional
Control
for AGC on/hold
MAS6180A5
VDD
QOP
Note 5
QI
Ferrite
Antenna
VDD
AGC Amplifier
RFIM
Antenna
Frequency
Selection
VDD
AON
QOM
RFIP
Demodulator
&
Comparator
VDD
VDD
GND
Receiver
Output
Power Supply/Biasing
VSS
PDN
AGC
Note 3
Power Down /
Fast Startup
Control
AGC
DEC
CAGC
10 µF
1.4 V
OUT
CDEC
47 nF
OR
CAGC
10 µF
DEC
+
CDEC
47 nF
Note 2
VDD
VDD
Note 2
Figure 3. Dual band application circuit of external compensation capacitance option version MAS6180A5. PMOS
switch transistor is used since RFIM input is biased close to VDD voltage.
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TYPICAL APPLICATION (Continued)
Note 1: Crystals
The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The
crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance
compensation capacitor CC of MAS6180. MAS6180A5 is option for external crystal compensation capacitor. The
external compensation capacitor should be matched similarly as well as possible with crystal’s shunt
capacitance. See Compensation Capacitance Options on table 2.
Table 1. Time-Signal System Frequencies
Time-Signal System
Location
Antenna Frequency
Recommended Crystal Frequency
DCF77
HGB
MSF
WWVB
JJY
BPC
77.5 kHz
75 kHz
60 kHz
60 kHz
40 kHz and 60 kHz
68.5 kHz
77.503 kHz
75.003 kHz
60.003 kHz
60.003 kHz
40.003 kHz and 60.003 kHz
68.505 kHz
Germany
Switzerland
United Kingdom
USA
Japan
China
Table 2 . Compensation Capacitance Options
Crystal Description
Device
CC
MAS6180A1
MAS6180A2
MAS6180A5
0.75 pF
1.3 pF
CC_EXT
For low C0 crystals
For high C0 crystals
For any crystals, external compensation capacitor
It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of
floating crystal shunt capacitance. For example crystal with 1 pF floating package shunt capacitance can have
0.85 pF grounded package shunt capacitance. PCB traces of crystal and external compensation capacitance
should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance
mismatching.
In dual band receiver configuration the crystals can be connected in parallel thus external compensation
capacitor value CC_EXT must be sum of two crystals’ shunt capacitances. Instead of parallel crystal connection it is
also possible to connect other crystal from QOP pin and the other crystal from QOM pin to common QI pin (figure
3). In this circuit configuration no external compensation capacitor is required since the crystals compensate
each other. The sensitivity of dual band receiver configuration will be lower than that of single band receiver
configuration since the noise band width of crystal filter with two parallel crystals is double.
Table 3 below presents some crystal manufacturers having suitable crystals for timesignal receiver application.
Table 3. Crystal Manufacturers and Crystal Types in Alphaphetical Order for Timesignal Receiver Application
Manufacturer
Crystal Type
Dimensions
Web Link
Citizen
Epson Toyocom
KDS Daishinku
Microcrystal
Seiko
Instruments
CFV-206
C-2-Type
C-4-Type
DT-261
MX1V-L2N
MX1V-T1K
VTC-120
ø 2.0 x 6.0
ø 1.5 x 5.0
ø 2.0 x 6.0
ø 2.0 x 6.0
ø 2.0 x 6.0
ø 2.0 x 8.1
ø 1.2 x 4.7
http://www.citizen.co.jp/tokuhan/quartz/
http://www.epsontoyocom.co.jp/english/
http://www.kds.info/index_en.htm
http://www.microcrystal.com/
http://www.sii-crystal.com
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TYPICAL APPLICATION (Continued)
Note 2: AGC Capacitor
The AGC and DEC capacitors must have low leakage currents due to very small signal currents through the
capacitors. The insulation resistance of these capacitors should be at minimum 100 MΩ. Also probes with at
least few 100 MΩ impedance should be used for voltage probing of the AGC and DEC pins. Electrolytic AGC
capacitor should have voltage rating at least 25 V for low enough leakage. DEC capacitor can be low leakage
chip capacitor.
Both the AGC and DEC capacitors can be connected either to VDD or to VSS. To minimize leakage currents
during power down the AGC and DEC capacitors are best to be connected to VDD since in power down the AGC
and DEC pins go to VDD voltage potential. In this case the positive polarity pin of electrolyte capacitor should be
connected to VDD. If the capacitors are connected to VSS then the negative polarity pin of electrolyte capacitor
should be connected to VSS.
Note 3: Power Down / Fast Startup Control
Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if
PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered automatically by the falling edge
of PDN signal, i.e., controlling device from power down to power up. The VDD must be high before falling edge of
PDN to guarantee proper operation of fast startup circuitry. Before power up the device should have been kept in
power down state at least 50ms. This guarantees that the AGC capacitor voltage has been completely pulled to
VDD during power down. The startup time without proper fast startup control can be several minutes but with fast
startup it is shortened typically to few seconds.
Note 4: Optional Control for AGC On/Hold
AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected.
Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive of analog clock or
watch can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal level. This can
be avoided by controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC
(AON=VDD) when motors are not driven. The AGC should be in hold only during disturbances and kept on other
time released since due to leakage the AGC can change slowly when in hold.
Note 5: Ferrite Antenna
The ferrite antenna converts the transmitted radio wave into a voltage signal. It has an important role in
determining receiver performance. Recommended antenna impedance at resonance is around 150 kΩ.
Low antenna impedance corresponds to low noise but often also to small signal amplitude. On the other hand
high antenna impedance corresponds to high noise but also large signal. The optimum performance where
signal-to-noise ratio is at maximum is achieved in between.
The antenna should have also some selectivity for rejecting near signal band disturbances. This is determined by
the antenna quality factor which should be approximately 100. Much higher quality factor antennas suffer from
extensive tuning accuracy requirements and possible tuning drifts by the temperature.
Antenna impedance can be calculated using equation 1 where f0, L, Qant and C are resonance frequency, coil
inductance, antenna quality factor and antenna tuning capacitor respectively. Antenna quality factor Qant is
defined by ratio of resonance frequency f0 and antenna bandwidth B (equation 2).
Rantenna = 2π ⋅ f 0 ⋅ L ⋅ Qantenna =
Qantenna =
Qantenna
1
=
2π ⋅ f 0 ⋅ C 2π ⋅ B ⋅ C
f0
B
Equation 1.
Equation 2.
Table 4 below presents some antenna manufacturers for time signal application.
Table 4. Antenna Manufacturers and Antenna Types in Alphaphetical Order for Time Signal Application
Manufacturer
Antenna Type
Dimensions
Web Link
HR Electronic GmbH
Sumida
60716 (60kHz)
60708 (77.5kHz)
ACL80A/B (40kHz, 60kHz)
ACL27 (40kHz, 60kHz)
ø 10 x 60 mm
http://www.hrelectronic.com/
ø 14 x 83 mm
6 x 7.3 x 28 mm
www.sumida.co.jp/jeita/XJA021.pdf
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MAS6180 SAMPLES IN SBDIL 20 PACKAGE
1
20 VSS
19
18 RFIM
VDD 2
3
6
QI 7
AGC 8
MAS6180ZZ
YYWW
XXXXX.X
QOP 4
QOM 5
9
17 RFIP
16
15
14 PDN
13 AON
12 DEC
11
OUT 10
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
ZZ =Sample Version
PIN DESCRIPTION
Pin Name
Pin
Type
QOP
QOM
1
2
3
4
5
NC
P
NC
AO
NC
QI
6
7
NC
AI
8
9
10
11
12
13
14
15
16
17
18
19
20
AO
NC
DO
NC
AO
DI
DI
NC
NC
AI
AI
NC
G
VDD
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
Function
Note
Positive Power Supply
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for External
Compensation Capacitor or Second Crystal
1
2
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
3
Demodulator Capacitor
AGC On Control
Power Down Input
4
5
Positive Receiver Input
Negative Receiver Input
6
6
Power Supply Ground
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left
unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor.
2) Pin 6 between QOM and QI must be connected to VSS to eliminate DIL package lead frame parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) type pins are also
recommended to be connected to VSS to minimize noise coupling.
3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
5) PDN = VSS means receiver on; PDN = VDD means receiver off
- Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
6) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD
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ORDERING INFORMATION
Product Code
Product
Description
Capacitance Option
MAS6180A1TC00
Single Band AM-Receiver IC
with Differential Input
CC = 0.75 pF
MAS6180A2TC00
Single Band AM-Receiver IC
with Differential Input
MAS6180A5TC00
Single Band AM-Receiver IC
with Differential Input
EWS-tested wafer,
diameter 150 mm,
thickness 400 µm.
EWS-tested wafer,
diameter 150 mm,
thickness 400 µm.
EWS-tested wafer,
diameter 150 mm,
thickness 400 µm.
CC = 1.3 pF
External compensation
capacitor
Contact Micro Analog Systems Oy for other wafer thickness options.
◆ The formation of product code
An example for MAS6180A1TC00:
MAS6180 A
1
Product
Design
Capacitance option:
name
version
CC = 0.75 pF
TC
Package type:
TC = 400 µm thick EWS tested wafer
00
Delivery format:
00 = bare wafer
05 = dies on tray
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy
Kamreerintie 2, P.O. Box 51
FIN-02771 Espoo, FINLAND
Tel. +358 9 80 521
Fax +358 9 805 3213
http://www.mas-oy.com
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits
shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no
claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and
Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or
modification.
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