TECHNICAL DATA IN74HC4051A Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS The IN74HC4051A utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input.When the Enable pin is high, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. • Fast Switching and Propagation Speeds • Low Crosstalk Between Switches • Diode Protection on All Inputs/Outputs • Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V • Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V • Low Noise ORDERING INFORMATION IN74HC4051AN Plastic IN74HC4051ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Single-Pole, 8-Position Plus Common Off FUNCTION TABLE Control Inputs Enable PIN 16 =VCC PIN 7 = VEE PIN 8 = GND ON Select Channels C B A L L L L X0 L L L H X1 L L H L X2 L L H H X3 L H L L X4 L H L H X5 L H H L X6 L H H H X7 H X X = don’t care X X None Rev. 00 IN74HC4051A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) -0.5 to +7.0 -0.5 to +14.0 V VEE Negative DC Supply Voltage (Referenced to GND) -7.0 to +0.5 V VIS Analog Input Voltage VEE - 0.5 to VCC+0.5 V VIN Digital Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Input Current Into or Out of Any Pin ±25 mA Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C I PD Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit VCC Positive Supply Voltage (Referenced to GND) (Referenced to VEE) 2.0 2.0 6.0 12.0 V VEE Negative DC Supply Voltage (Referenced to GND) - 6.0 GND V VIS Analog Input Voltage VEE VCC V VIN Digital Input Voltage (Referenced to GND) GND VCC V - 1.2 V -55 +125 °C 0 0 0 1000 500 400 ns VIO * Parameter * Static or Dynamic Voltage Across Switch TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Channel Select or Enable Inputs) VCC =2.0 V VCC =4.5 V VCC =6.0 V For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i. e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range indicated in the Recommended Operating Conditions.. Unused digital input pins must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. Rev. 00 IN74HC4051A DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE=GND, Except Where Noted VCC Symbol Parameter Test Conditions Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum High-Level Input Voltage, Channel-Select or Enable Inputs RON = Per Spec 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage, Channel-Select or Enable Inputs RON = Per Spec 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V IIN Maximum Input Leakage Current, Channel-Select or Enable Inputs VIN=VCC or GND, VEE=-6.0 V 6.0 ±0.1 ±1.0 ±1.0 μA ICC Maximum Quiescent Supply Current (per Package) Channel Select = VCC or GND Enable = VCC or GND VIS = VCC or GND VEE = GND VIO= 0 V VEE = - 6.0 μA 6.0 6.0 2 8 20 80 40 160 DC ELECTRICAL CHARACTERISTICS Analog Section Symbol Parameter RON Maximum “ON” Resistance VCC VEE V V 25 °C to -55°C VIN=VIL or VIH VIS = VCC or VEE IS ≤ 2.0 mA(Figure 1) 4.5 4.5 6.0 0.0 -4.5 -6.0 190 120 100 240 150 125 280 170 140 VIN=VIL or VIH VIS = VCC or VEE (Endpoints) IS ≤ 2.0 mA(Figure 1) 4.5 4.5 0.0 -4.5 150 100 190 125 230 140 6.0 -6.0 80 100 115 Test Conditions Guaranteed Limit ≤85 ≤125 Unit °C °C Ω ΔRON Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package VIN=VIL or VIH VIS = 1/2 (VCC- VEE) IS ≤ 2.0 mA 4.5 4.5 6.0 0.0 -4.5 -6.0 30 12 10 35 15 12 40 18 14 Ω IOFF Maximum Off- Channel Leakage Current, Any One Channel VIN=VIL or VIH VIO= VCC- VEE Switch Off (Figure 2) 6.0 -6.0 0.1 0.5 1.0 μA Maximum Off- Channel Leakage Current, Common Channel VIN=VIL or VIH VIO = VCC- VEE Switch Off (Figure 3) 6.0 -6.0 0.2 2.0 4.0 Maximum On- Channel Leakage Current, Channel to Channel VIN=VIL or VIH Switch to Switch = VCC- VEE (Figure 4) 6.0 -6.0 0.2 2.0 4.0 ION μA Rev. 00 IN74HC4051A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Channel-Select to Analog Output (Figures 8 and 9) 2.0 4.5 6.0 370 74 63 465 93 79 550 110 94 ns tPLH, tPHL Maximum Propagation Delay , Analog Input to Analog Output (Figures 10 and 11) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tPLZ, tPHZ Maximum Propagation Delay , Enable to Analog Output (Figures 12 and 13) 2.0 4.5 6.0 290 58 49 364 73 62 430 86 73 ns tPZL, tPZH Maximum Propagation Delay , Enable to Analog Output (Figures 12 and 13) 2.0 4.5 6.0 345 69 59 435 87 74 515 103 87 ns CIN Maximum Input Capacitance, Channel-Select or Enable Inputs - 10 10 10 pF CI/O Maximum Capacitance Analog I/O - 35 35 35 pF Common O/I - 130 130 130 Feedthrough - 1.0 1.0 1.0 CPD All Switches Off Power Dissipation Capacitance (Per Package) (Figure 14) Typical @25°C,VCC=5.0 V, VEE=0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 45 pF Rev. 00 IN74HC4051A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) Symbol BW - Parameter Test Conditions Maximum OnChannel Bandwidth or Minimum Frequency Response (Figure 5) fin=1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequence Until dB Meter Reads -3 dB RL =50 Ω, CL=10 pF Off-Channel Feedthrough Isolation (Figure 6) fin= Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL =600 Ω, CL=50 pF fin = 1.0 MHz, RL =50 Ω, CL=10 pF - Feedthrough Noise, Channel Select Input to Common O/I (Figure 7) VIN≤ 1 Mhz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS= 0 A Enable = GND RL =600 Ω, CL=50 pF RL =10 Ω, CL=10 pF THD Total Harmonic Distortion (Figure 15) fin= 1 kHz, RL =10 kΩ, CL=50 pF THD = THDMeasured - THDSource VIS =4.0 VPP sine wave VIS =8.0 VPP sine wave VIS =11.0 VPP sine wave VCC VEE Limit* V V 25 °C Unit MHz 2.25 4.50 6.00 -2.25 -4.50 -6.00 80 80 80 dB 2.25 4.50 6.00 -2.25 -4.50 -6.00 -50 -50 -50 2.25 4.50 6.00 -2.25 -4.50 -6.00 -40 -40 -40 mVPP 2.25 4.50 6.00 -2.25 -4.50 -6.00 25 105 135 2.25 4.50 6.00 -2.25 -4.50 -6.00 35 145 190 % 2.25 4.50 6.00 -2.25 -4.50 -6.00 0.10 0.08 0.05 * Limits not tested. Determined by design and verified by qualification. Figure 1. On Resistance Test Set-Up Rev. 00 IN74HC4051A Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-UP Figure 3. Maximum Off Channel Leakage Current, Common Channel, Test Set-UP * Includes all probe and jig capacitance. Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set-UP Figure 5. Maximum On Channel Bandwidth, Test Set-UP * Includes all probe and jig capacitance. * Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set-UP Figure 7.Feedthrough Noise, Channel Select to Common Out, Test Set-UP Rev. 00 IN74HC4051A * Includes all probe and jig capacitance. Figure 8. Switching Weveforms Figure 9. Test Set-UP, Channel Select to Analog Out Figure 10. Switching Weveforms Figure 11. Test Set-UP, Analog In to Analog Out Figure 12. Switching Weveforms Figure 13. Test Set-UP, Enable to Analog Out * Includes all probe and jig capacitance. Rev. 00 IN74HC4051A Figure 14. Power Dissipation Capacitance, Test Set-Up * Includes all probe and jig capacitance Figure 15. Total Harmonic Distortion, Test Set-UP EXPANDED LOGIC DIAGRAM Rev. 00 IN74HC4051A N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 9 16 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 B 1 8 5.33 C F L C D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 -T- SEATING PLANE N G K M H D J 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 H B 1 G P 8 R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. F M Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.72 J 0° 8° K 0.1 0.25 M 0.19 0.25 P 5.8 6.2 R 0.25 0.5 Rev. 00