LINER LTC2241-12 Dual 14-bit 250msp Datasheet

LTC2157-14/
LTC2156-14/LTC2155-14
Dual 14-Bit 250Msps/
210Msps/170Msps ADCs
FEATURES
DESCRIPTION
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The LTC®2157-14/LTC2156-14/LTC2155-14 are 2-channel
simultaneous sampling 250Msps/210Msps/170Msps
14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 70dB SNR and 90dB spurious
free dynamic range (SFDR). The 1.25GHz input bandwidth
allows the ADC to undersample high frequencies with
good performance. The latency is only five clock cycles.
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70dB SNR
90dB SFDR
Low Power: 650mW/616mW/567mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.5VP-P Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin-Compatible 12-Bit Versions
64-Pin (9mm × 9mm) QFN Package
DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.82LSBRMS.
APPLICATIONS
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The digital outputs are double data rate (DDR) LVDS.
The ENC+ and ENC– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
LTC2157-14 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
VDD
OVDD
CHANNEL A
CLOCK
S/H
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
OVDD
CHANNEL B
–20
DDR
LVDS
AMPLITUDE (dBFS)
ANALOG
INPUT
0
DA12_13
t
t
t
DA0_1
–40
–60
–80
–100
ANALOG
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
DB12_13
t
t
t
DB0_1
DDR
LVDS
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21576514 TA01b
GND
21576514 TA01
OGND
21576514fa
1
LTC2157-14/
LTC2156-14/LTC2155-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PAR/SER
CS
SCK
SDI
SDO
GND
DA12_13+
DA12_13–
DA10_11+
DA10_11–
DA8_9+
DA8_9–
DA6_7+
DA6_7 –
OVDD
TOP VIEW
VDD 1
VDD 2
GND 3
AINA+ 4
AINA– 5
GND 6
SENSE 7
VREF 8
GND 9
VCM 10
GND 11
AINB– 12
AINB+ 13
GND 14
VDD 15
VDD 16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
65
GND
OGND
DA4_5+
DA4_5–
DA2_3+
DA2_3–
DA0_1+
DA0_1–
CLKOUT+
CLKOUT–
DB12_13+
DB12_13–
DB10_11+
DB10_11–
DB8_9+
DB8_9–
OGND
VDD
GND
ENC+
ENC–
GND
OF –
OF +
DB0_1–
DB0_1+
DB2_3–
DB2_3+
DB4_5–
DB4_5+
DB6_7 –
DB6_7+
OVDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Supply Voltage
VDD, OVDD................................................ –0.3V to 2V
Analog Input Voltage
AINA/B+, AINA/B –, PAR/SER,
SENSE (Note 3)........................ –0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC– (Note 3) ................ –0.3V to (VDD + 0.3V)
CS, SDI, SCK (Note 4)........................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2157C, LTC2156C, LTC2155C ............ 0°C to 70°C
LTC2157I, LTC2156I, LTC2155I ............–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
UP PACKAGE
64-LEAD (9mm w 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2157CUP-14#PBF
LTC2157CUP-14#TRPBF
LTC2157UP-14
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2157IUP-14#PBF
LTC2157IUP-14#TRPBF
LTC2157UP-14
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LTC2156CUP-14#PBF
LTC2156CUP-14#TRPBF
LTC2156UP-14
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2156IUP-14#PBF
LTC2156IUP-14#TRPBF
LTC2156UP-14
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LTC2155CUP-14#PBF
LTC2155CUP-14#TRPBF
LTC2155UP-14
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2155IUP-14#PBF
LTC2155IUP-14#TRPBF
LTC2155UP-14
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
21576514fa
2
LTC2157-14/
LTC2156-14/LTC2155-14
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
l
Resolution (No Missing Codes)
LTC2157-14
TYP MAX
MIN
14
LTC2156-14
TYP MAX
LTC2155-14
MIN
TYP MAX
14
UNITS
14
Bits
Integral Linearity Error
Differential Analog Input (Note 6) l
–5.5
±0.85
5.5
–5.3
±0.85
5.3
–5.1
±0.85
5.1
LSB
Differential Linearity Error
Differential Analog Input
l
–0.9
±0.25
0.9
–0.9
±0.25
0.9
–0.9
±0.25
0.9
LSB
Offset Error
(Note 7)
l
–13
±5
13
–13
±5
13
–13
±5
13
mV
Gain Error
Internal Reference
External Reference
–4.0
±1.5
±1
–4.0
±1.5
±1
–4.0
±1.5
±1
2.2
%FS
%FS
l
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
Transition Noise
2.2
2.2
±20
±20
±20
μV/°C
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
1.82
1.82
1.82
LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
l
VCM – 20mV
VCM
VCM + 20mV
V
1.250
1.300
V
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
MAX
UNITS
1.5
l
1.200
l
VP-P
IIN1
Analog Input Leakage Current
0 < AIN+, AIN– < VDD, No Encode
–1
1
μA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–1
1
μA
IIN3
SENSE Input Leakage Current
1.2V < SENSE < 1.3V
l
–1
1
μA
tAP
Sample-and-Hold Acquisition Delay Time
1
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.15
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
ns
psRMS
75
dB
1250
MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
15MHz Input
70MHz Input
140MHz Input
SFDR
Spurious Free Dynamic Range 15MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 15MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
Crosstalk Crosstalk Between Channels
15MHz Input
70MHz Input
140MHz Input
Up to 315MHz Input
MIN
l
l
l
l
LTC2157-14
TYP MAX
67.1
70
69.7
69
71
90
85
80
81
98
95
85
66.3
69.9
69.4
68.8
–95
MIN
LTC2156-14
TYP MAX
67.6
70
69.7
69
74
90
85
80
82
95
95
85
67.2
69.9
69.4
68.8
–95
LTC2155-14
MIN
TYP MAX
UNITS
67.7
70
69.8
69.1
dBFS
dBFS
dBFS
76
90
85
80
dBFS
dBFS
dBFS
83
95
95
85
dBFS
dBFS
dBFS
67.3
69.9
69.4
68.5
dBFS
dBFS
dBFS
–95
dB
21576514fa
3
LTC2157-14/
LTC2156-14/LTC2155-14
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.435 •
VDD – 18mV
0.435 •
VDD
0.435 •
VDD + 18mV
VCM Output Temperature Drift
UNITS
V
±37
VCM Output Resistance
–1mA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
ppm/°C
4
1.225
Ω
1.250
VREF Output Temperature Drift
1.275
V
±30
VREF Output Resistance
–400μA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
ppm/°C
7
Ω
0.6
mV/V
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
VDD
Analog Supply Voltage
(Note 9)
l
1.7
OVDD
Output Supply Voltage
(Note 9)
l
1.7
IVDD
Analog Supply Current
IOVDD
Digital Supply Current
PDISS
LTC2157-14
TYP MAX
1.8
MIN
1.9
1.7
1.7
LTC2156-14
TYP MAX
1.8
LTC2155-14
MIN
TYP MAX
1.9
1.7
1.7
1.8
UNITS
1.9
V
1.8
1.9
1.8
1.9
1.8
1.9
V
l
316
350
299
330
274
305
mA
1.75mA LVDS Mode
3.5mA LVDS Mode
l
l
45
76
50
85
43
73
49
84
41
71
48
83
mA
mA
Power Dissipation
1.75mA LVDS Mode
3.5mA LVDS Mode
l
l
650
706
720
783
616
670
682
745
567
621
635
698
mW
mW
PSLEEP
Sleep Mode Power
Clock Disabled
Clocked at fS(MAX)
<5
<5
<5
<5
<5
<5
mW
mW
PNAP
Nap Mode Power
Clocked at fS(MAX)
213
198
184
mW
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
V
1.2
1.5
V
V
RIN
Input Resistance
(See Figure 2)
10
kΩ
CIN
Input Capacitance
(Note 8)
2
pF
DIGITAL INPUTS (CS, SDI, SCK)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
μA
3
pF
200
Ω
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
l
–10
10
4
μA
pF
21576514fa
4
LTC2157-14/
LTC2156-14/LTC2155-14
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
DIGITAL DATA OUTPUTS
CONDITIONS
VOD
Differential Output Voltage
VOS
Common Mode Output Voltage
RTERM
On-Chip Termination Resistance
l
l
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OVDD = 1.8V
l
l
MIN
TYP
MAX
UNITS
247
125
1.125
1.125
350
175
1.250
1.250
100
454
250
1.375
1.375
mV
mV
V
V
Ω
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
fS
tL
PARAMETER
Sampling Frequency
ENC Low Time (Note 8)
tH
ENC High Time (Note 8)
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
l
l
l
MIN
10
1.9
1.5
1.9
1.5
LTC2157-14
TYP MAX
250
2
50
2
50
2
50
2
50
MIN
10
2.26
1.5
2.26
1.5
LTC2156-14
TYP MAX
210
2.38
50
2.38
50
2.38
50
2.38
50
LTC2155-14
MIN
TYP MAX
10
170
2.79 2.94
50
1.5
2.94
50
2.79 2.94
50
1.5
2.94
50
UNITS
MHz
ns
ns
ns
ns
DIGITAL DATA OUTPUTS
LTC215X-14
MIN
SYMBOL
tD
PARAMETER
ENC to Data Delay
CONDITIONS
CL = 5pF (Note 8)
l
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
Pipeline Latency
TYP
MAX
1.7
2
2.3
ns
1.3
1.6
2
ns
0.3
0.4
0.55
ns
5
5
UNITS
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
CS to SCK Set-Up Time
tH
Write Mode
Readback Mode CSDO= 20pF, RPULLUP = 2k
l
l
l
40
250
5
ns
ns
ns
SCK to CS Hold Time
l
5
ns
tDS
SDI Set-Up Time
l
5
ns
tDH
SDI Hold Time
l
5
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
l
ns
125
ns
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 250MHz (LTC2157),
210MHz (LTC2156), or 170MHz (LTC2155), differential ENC+/ENC– = 2VP-P
sine wave, input range = 1.5VP-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111
in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
21576514fa
5
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2157-14: Integral Nonlinearity
(INL)
LTC2157-14: Differential Nonlinearity
(DNL)
LTC2157-14: 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
0.5
2.0
0
1.5
–20
DNL ERROR (LSB)
INL ERROR (LSB)
0.5
0
–0.5
AMPLITUDE (dBFS)
0.25
1.0
0
–60
–80
–0.25
–1.0
–100
–1.5
–2.0
–40
–0.5
0
4096
8192
12288
OUTPUT CODE
0
16383
4096
8192
12288
OUTPUT CODE
16383
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21576514 G02
21576514 G01
21576514 G03
LTC2157-14: 32K Point FFT,
fIN = 122MHz, –1dBFS, 250Msps
0
–20
–20
–20
–40
–60
–80
–120
AMPLITUDE (dBFS)
0
–40
–60
–80
–100
–100
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
–40
–60
–80
–100
0
20
40
60
80
100
FREQUENCY (MHz)
120
–120
LTC2157-14: 32K Point FFT,
fIN = 381MHz, –1dBFS, 250Msps
LTC2157-14: 32K Point FFT,
fIN = 907MHz, –1dBFS, 250Msps
–20
–20
–80
–100
–120
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
–40
–60
–80
–100
0
20
40
60
80
100
FREQUENCY (MHz)
120
21576514 G07
–120
40
60
80
100
FREQUENCY (MHz)
120
21576514 G06
0
–60
20
LTC2157-14: 32K Point 2-Tone FFT,
fIN = 70.5MHz and 69.5MHz,
250Msps
0
–40
0
21576514 G05
21576514 G04
AMPLITUDE (dBFS)
LTC2157-14: 32K Point FFT,
fIN = 171MHz, –1dBFS, 250Msps
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2157-14: 32K Point FFT,
fIN = 70MHz, –1dBFS, 250Msps
–40
–60
–80
–100
0
20
40
60
80
100
FREQUENCY (MHz)
120
–120
0
20
40
60
80
100 120
INPUT FREQUENCY (MHz) 21576514 G08a
21576514 G08
21576514fa
6
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2157-14: SNR vs Input Frequency,
–1dBFS, 250Msps
LTC2157-14: Shorted Input
Histogram
4000
75
3500
70
3000
80
70
2000
1500
SFDR (dBFS)
SNR (dBFS)
60
55
60
50
40
30
50
1000
20
45
500
0
8198 8200 8202 8204 8206 8208 8210 8212 8214
OUTPUT CODE
21576514 G09
10
0
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21576514 G11
21576514 G10
LTC2157-14: SNR vs Input Level,
fIN = 70MHz, 250Msps
LTC2157-14: IVDD vs Sample
Rate, 15MHz Sine Wave Input,
–1dBFS
LTC2157-14: SFDR vs Input Level,
fIN = 70MHz, 250Msps
300
70
120
dBFS
60
dBFS
100
280
50
30
80
60
IVDD (mA)
SFDR (dBFS)
dBc
40
dBc
260
240
40
20
220
20
10
–60
–50
–40 –30 –20
AMPLITUDE (dBFS)
–10
0
21576514 G12
0
–80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE (dBFS)
0
200
0
50
21576514 G13
LTC2157-14: IOVDD vs Sample
Rate, 15MHz Sine Wave Input,
–1dBFS
100
150
200
SAMPLE RATE (Msps)
250
21576514 G14
LTC2157-14: Frequency Response
80
–0.5
LVDS CURRENT
3.5mA
–1.0
–1.5
70
IOVDD (mA)
0
AMPLITUDE (dBFS)
COUNT
90
65
2500
SNR (dBc AND dBFS)
LTC2157-14: SFDR vs Input
Frequency, –1dBFS, 250Msps
60
50
LVDS CURRENT
1.75mA
40
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
30
–6.0
0
50
100
150
200
SAMPLE RATE (Msps)
250
21576514 G15
100
1000
INPUT FREQUENCY (MHz)
21576514 G16
21576514fa
7
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2156-14: Integral Nonlinearity
(INL)
LTC2156-14: 32K Point FFT,
fIN = 15MHz, –1dBFS, 210Msps
LTC2156-14: Differential
Nonlinearity (DNL)
0
0.5
2.0
1.5
–20
0.5
0
–0.5
0.25
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
0
–0.25
–1.0
–80
–120
–0.5
0
4096
8192
12288
OUTPUT CODE
16383
0
4096
8192
12288
OUTPUT CODE
21576514 G17
16383
LTC2156-14: 32K Point FFT,
fIN = 101MHz, –1dBFS, 210Msps
–20
–20
–100
–120
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
–80
–40
–60
–80
20
40
60
80
FREQUENCY (MHz)
100
–120
0
20
40
60
80
FREQUENCY (MHz)
100
21576514 G20
–60
–80
–120
0
20
40
60
80
FREQUENCY (MHz)
0
0
–20
–20
–40
–60
–80
–100
100
21576514 G22
LTC2156-14: 32K Point FFT,
fIN = 379MHz, –1dBFS, 210Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40
21576514 G21
LTC2156-14: 32K Point FFT,
fIN = 227MHz, –1dBFS, 210Msps
–120
100
–100
–100
0
40
60
80
FREQUENCY (MHz)
LTC2156-14: 32K Point FFT,
fIN = 171MHz, –1dBFS, 210Msps
0
–60
20
21576514 G19
0
–40
0
21576514 G18
LTC2156-14: 32K Point FFT,
fIN = 71MHz, –1dBFS, 210Msps
AMPLITUDE (dBFS)
–60
–100
–1.5
–2.0
–40
–40
–60
–80
–100
0
20
40
60
80
FREQUENCY (MHz)
100
21576514 G23
–120
0
20
40
60
80
FREQUENCY (MHz)
100
21576514 G24
21576514fa
8
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–20
–20
–20
–40
–60
–80
–120
AMPLITUDE (dBFS)
0
–40
–60
–80
0
20
40
60
80
FREQUENCY (MHz)
–120
100
–40
–60
–80
–100
–100
–100
–120
0
20
40
60
80
FREQUENCY (MHz)
100
4000
75
3500
70
3000
90
80
70
SFDR (dBFS)
SNR (dBFS)
1500
60
55
60
50
40
30
50
1000
100
40
60
80
INPUT FREQUENCY (MHz)
LTC2156-14: SFDR vs Input
Frequency, –1dBFS, 210Msps
65
2000
20
21576514 G26a
LTC2156-14: SNR vs Input Frequency,
–1dBFS, 210Msps
LTC2156-14: Shorted
Input Histogram
2500
0
21576514 G26
21576514 G25
20
45
500
0
8196 8198 8200 8202 8204 8206 8208 8210 8212
OUTPUT CODE
21576514 G27
10
0
40
70
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21576514 G29
21576514 G28
LTC2156-14: SNR vs Input Level,
fIN = 70MHz, 210Msps
LTC2156-14: SFDR vs Input Level,
fIN = 71MHz, 210Msps
120
dBFS
60
100
50
dBc
SFDR (dBFS)
SNR (dBc AND dBFS)
COUNT
LTC2156-14: 32K Point 2-Tone FFT,
fIN = 70.5MHz and 69.5MHz,
210Msps
LTC2156-14: 32K Point FFT,
fIN = 907MHz, –1dBFS, 210Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2156-14: 32K Point FFT,
fIN = 571MHz, –1dBFS, 210Msps
40
30
dBFS
80
60
dBc
40
20
20
10
0
–60
–50
–40 –30 –20
AMPLITUDE (dBFS)
–10
0
21576514 G30
0
–80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE (dBFS)
0
21576514 G31
21576514fa
9
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2156-14: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2156-14: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2156-14: Frequency Response
80
–0.5
280
LVDS CURRENT
3.5mA
–1.0
–1.5
70
240
AMPLITUDE (dBFS)
IOVDD (mA)
IVDD (mA)
260
60
50
LVDS CURRENT
1.75mA
220
40
0
50
100
150
200
SAMPLE RATE (Msps)
250
–4.0
–4.5
–6.0
0
50
100
150
200
SAMPLE RATE (Msps)
250
100
1000
INPUT FREQUENCY (MHz)
21576514 G33
21576514 G32
0.5
2.0
21576514 G34
LTC2155-14: 32K Point FFT,
fIN = 15MHz, –1dBFS, 170Msps
LTC2155-14: Differential
Nonlinearity (DNL)
LTC2155-14: Integral Nonlinearity
(INL)
0
1.5
–20
0.5
0
–0.5
0.25
AMPLITUDE (dBFS)
DNL ERROR (LSB)
1.0
INL ERROR (LSB)
–3.0
–3.5
–5.5
30
0
–0.25
–1.0
–40
–60
–80
–100
–1.5
–0.5
0
4096
8192
12288
OUTPUT CODE
16383
0
4096
8192
12288
OUTPUT CODE
16383
–120
0
LTC2155-14: 32K Point FFT,
fIN = 70MHz, –1dBFS, 170Msps
–20
–20
–20
–100
AMPLITUDE (dBFS)
0
AMPLITUDE (dBFS)
0
–80
–40
–60
–80
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
21576514 G38
70
80
–40
–60
–80
–100
–100
–120
30 40 50 60
FREQUENCY (MHz)
LTC2155-14: 32K Point FFT,
fIN = 169MHz, –1dBFS, 170Msps
0
–60
20
21576514 G37
LTC2155-14: 32K Point FFT,
fIN = 121MHz, –1dBFS, 170Msps
–40
10
21576514 G36
21576514 G35
AMPLITUDE (dBFS)
–2.5
–5.0
200
–2.0
–2.0
–120
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
21576514 G39
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
21576514 G40
21576514fa
10
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2155-14: 32K Point FFT,
fIN = 380MHz, –1dBFS, 170Msps
LTC2155-14: 32K Point FFT,
fIN = 571MHz, –1dBFS, 170Msps
0
0
–20
–20
–20
–40
–60
–80
AMPLITUDE (dBFS)
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2155-14: 32K Point FFT,
fIN = 225MHz, –1dBFS, 170Msps
–40
–60
–80
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
0
80
–80
–120
–120
–120
–60
–100
–100
–100
–40
10
20
30 40 50 60
FREQUENCY (MHz)
70
0
80
10
20
30 40 50 60
FREQUENCY (MHz)
0
0
–20
–20
80
LTC2155-14: Shorted
Input Histogram
LTC2155-14: 32K Point 2-Tone FFT,
fIN = 70.5MHz and 69.5MHz, 170Msps
LTC2155-14: 32K Point FFT,
fIN = 907MHz, –1dBFS, 170Msps
70
21576514 G43
21576514 G42
21576514 G41
4000
3500
–60
–80
–40
2500
COUNT
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
3000
–40
–60
2000
1500
–80
1000
–100
–100
–120
500
–120
20
30 40 50 60
FREQUENCY (MHz)
70
80
21576514 G44
0
10
20 30 40 50 60 70
INPUT FREQUENCY (MHz)
80
21576514 G44a
LTC2155-14: SNR vs Input Frequency,
–1dBFS, 170Msps
0
8198 8200 8202 8204 8206 8208 8210 8212 8214
OUTPUT CODE
21576514 G45
LTC2155-14: SFDR vs Input
Frequency, –1dBFS, 170Msps
75
90
70
80
70
65
SFDR (dBFS)
10
SNR (dBFS)
0
60
55
60
50
40
30
50
20
45
10
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21576514 G46
0
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21576514 G47
21576514fa
11
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2155-14: SNR vs Input Level,
fIN = 70MHz, 170Msps
70
250
120
dBFS
240
dBFS
60
100
50
dBc
40
30
20
230
80
IVDD (mA)
SFDR (dBc AND dBFS)
SNR (dBc AND dBFS)
LTC2155-14: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2155-14: SFDR vs Input Level,
fIN = 70MHz, 170Msps
dBc
60
0
–60
–50
–40 –30 –20
AMPLITUDE (dBFS)
–10
0
21576514 G48
210
200
40
190
20
10
220
180
0
–80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE (dBFS)
170
0
21576514 G49
LTC2155-14: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
0
20
40
60 80 100 120 140 160 180
SAMPLE RATE (Msps)
21576514 G50
LTC2155-14: Frequency Response
–0.5
80
–1.0
LVDS CURRENT
3.5mA
–1.5
AMPLITUDE (dBFS)
IOVDD (mA)
70
60
50
LVDS CURRENT
1.75mA
40
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
30
–6.0
0
20
40
60 80 100 120 140 160 180
SAMPLE RATE (Msps)
21576514 G51
1000
100
INPUT FREQUENCY (MHz)
21576514 G52
21576514fa
12
LTC2157-14/
LTC2156-14/LTC2155-14
PIN FUNCTIONS
VDD (Pins 1, 2, 15, 16, 17, 64): 1.8V Analog Power Supply.
Bypass to ground with 0.1μF ceramic capacitors. Pins 1,
2, 64 can share a bypass capacitor. Pins 15, 16, 17 can
share a bypass capacitor.
GND (Pins 3, 6, 9, 11, 14, 18, 21, 58, Exposed Pad
Pin 65): ADC Power Ground. The exposed pad must be
soldered to the PCB ground.
AINA+ (Pin 4): Positive Differential Analog Input for
Channel A.
AINA– (Pin 5): Negative Differential Analog Input for
Channel A.
SENSE (Pin 7): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±0.75V
input range. An external reference between 1.2V and 1.3V
applied to SENSE selects an input range of ±0.6 × VSENSE.
VREF (Pin 8): Reference Voltage Output. Bypass to ground
with a 2.2μF ceramic capacitor. Nominally 1.25V.
VCM (Pin 10): Common Mode Bias Output; nominally equal
to 0.435 • VDD. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
AINB– (Pin 12): Negative Differential Analog Input for
Channel B.
AINB+ (Pin 13): Positive Differential Analog Input for
Channel B.
ENC+ (Pin 19): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 20): Encode Complement Input. Conversion
starts on the falling edge.
OGND (Pins 33, 48): Output Driver Ground.
OVDD (Pins 32, 49): 1.8V Output Driver Supply. Bypass
each pin to ground with separate 0.1μF ceramic capacitors.
SDO (Pin 59): Serial Interface Data Output. In serial programming mode, (PAR/SER = 0V), SDO is the optional serial
interface data output. Data on SDO is read back from the
mode control registers and can be latched on the falling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2k pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
SDI (Pin 60): Serial Interface Data Input. In serial programming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI selects 3.5mA or
1.75mA LVDS output current (see Table 2). SDI can be
driven with 1.8V to 3.3V logic.
SCK (Pin 61): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interface clock input. In the parallel programming mode
(PAR/SER = VDD), SCK can be used to place the part in the
low power sleep mode (see Table 2). SCK can be driven
with 1.8V to 3.3V logic.
CS (Pin 62): Serial Interface Chip Select Input. In serial
programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
In the parallel programming mode (PAR/SER = VDD), CS
controls the clock duty cycle stabilizer (see Table 2). CS
can be driven with 1.8V to 3.3V logic.
PAR/SER (Pin 63): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode
where CS, SCK, SDI, SDO become a serial interface that
control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
21576514fa
13
LTC2157-14/
LTC2156-14/LTC2155-14
PIN FUNCTIONS
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OF–/OF+ (Pins 22/23): Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
The overflows for channel A and channel B are multiplexed
together.
DB0_1–/DB0_1+ to DB12_13–/DB12_13+ (Pins 24/25, 26/27,
28/29, 30/31, 34/35, 36/37, 38/39): Channel B Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DB0,
DB2, DB4, DB6, DB8, DB10, DB12) appear when CLKOUT+
is low. The odd data bits (DB1, DB3, DB5, DB7, DB9, DB11,
DB13) appear when CLKOUT+ is high.
CLKOUT –/CLKOUT+ (Pins 40/41): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
DA0_1–/DA0_1+ to DA12_13–/DA12_13+ (Pins 42/43, 44/45,
46/47, 50/51, 52/53, 54/55, 56/57): Channel A Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DA0,
DA2, DA4, DA6, DA8, DA10, DA12) appear when CLKOUT+
is low. The odd data bits (DA1, DA3, DA5, DA7, DA9, DA11,
DA13) appear when CLKOUT+ is high.
21576514fa
14
LTC2157-14/
LTC2156-14/LTC2155-14
FUNCTIONAL BLOCK DIAGRAM
VDD
OVDD
CHANNEL A
ANALOG
INPUT
14-BIT
PIPELINED
ADC CORE
S/H
VCM
0.1μF
CORRECTION
LOGIC
DA12_13
t
t
t
DA0_1
OUTPUT
DRIVERS
VCM
BUFFER
DDR
LVDS
OGND
BUFFER
GND
CLOCK
CLOCK/DUTY
CYCLE CONTROL
CS
SCK
SDI
PAR/SER
SPI
VREF
2.2μF
1.25V
REFERENCE
GND
RANGE
SELECT
SENSE
ANALOG
INPUT
BUFFER
S/H
OVDD
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
DB12_13
t
t
t
DB0_1
OUTPUT
DRIVERS
DDR
LVDS
CHANNEL B
21576514 F01
OGND
GND
Figure 1. Functional Block Diagram
21576514fa
15
LTC2157-14/
LTC2156-14/LTC2155-14
TIMING DIAGRAMS
Double Data Rate Output Timing, All Outputs Are Differential LVDS
N
tAP
N+3
N+2
N+1
tL
tH
ENC–
ENC+
CLKOUT+
CLKOUT –
tC
DA0_1–
DA0_1+
DA0N-5
DA1N-5
DA0N-4
DA1N-4
DA0N-3
DA1N-3
tD
DA12_13–
DA12_13+
DA12N-5 DA13N-5 DA12N-4 DA13N-4 DA12N-3 DA13N-3
DB0_1–
DB0_1+
DB0N-5
DB1N-5
DB0N-4
DB1N-4
DB0N-3
DB1N-3
DB12_13–
DB12_13+
DB12N-5 DB13N-5 DB12N-4 DB13N-4 DB12N-3 DB13N-3
OF–
OF+
OF_A N-5 OF_B N-5 OF_A N-4 OF_B N-4 OF_A N-3 OF_B N-3
tSKEW
21576514 TD01
21576514fa
16
LTC2157-14/
LTC2156-14/LTC2155-14
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
SDO
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
R/W
SDO
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
21576514 TD02
21576514fa
17
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
INPUT DRIVE CIRCUITS
The LTC2157-14/LTC2156-14/LTC2155-14 are twochannel, 14-bit 250Msps/210Msps/170Msps A/D converters that are powered by a single 1.8V supply. The
analog inputs must be driven differentially. The encode inputs should be driven differentially for optimal
performance. The digital outputs are double data rate
LVDS. Additional features can be chosen by programming
the mode control registers through a serial SPI port.
ANALOG INPUT
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wide band noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component values should be chosen based on the application’s
specific input frequency.
Transformer-Coupled Circuits
The analog inputs are differential CMOS sample-andhold circuits (Figure 2). The inputs must be driven differentially around a common mode voltage set by the VCM
output pin, which is nominally 0.435 • VDD. For the 1.5V
input range, the inputs should swing from VCM – 0.375V
to VCM + 0.375V. There should be 180° phase difference
between the inputs.
Figure 3 shows the analog input being driven by an RF
transformer with the common mode supplied through a
pair of resistors via the VCM pin.
At higher input frequencies a transmission line balun
transformer (Figures 4 and 5) has better balance, resulting
in lower A/D distortion.
The two channels are simultaneously sampled by a
shared encode circuit.
10Ω
VCM
0.1μF
LTC2157-14
0.1μF
LTC2157-14
VDD
4.7Ω
AIN+
IN
RON
20Ω
25Ω
2pF
10pF
AIN+
0.1μF
4.7Ω
25Ω
2pF
VDD
RON
20Ω
AIN–
T1: MACOM ETC1-1T
21576514 F03
2pF
AIN–
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
2pF
VDD
10Ω
VCM
1.2V
0.1μF
LTC2157-14
0.1μF
4.7Ω
AIN+
IN
10k
ENC+
45Ω
ENC–
0.1μF
0.1μF
21576514 F02
Figure 2. Equivalent Input Circuit. Only One
of Two Analog Channels Is Shown
100Ω
45Ω
4.7Ω
AIN–
T1: MABA
T2: WBC1-1L
007159-000000
21576514 F04
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 15MHz to 150MHz
21576514fa
18
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
Amplifier Circuits
VCM
10Ω
AIN+
Figure 6 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
AIN–
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
3 and 5) should convert the signal to differential before
driving the A/D. The A/D cannot be driven single-ended.
0.1μF
LTC2157-14
0.1μF
4.7Ω
IN
45Ω
100Ω
0.1μF
45Ω
0.1μF
4.7Ω
T1: MABA
007159-000000
21576514 F05
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 150MHz to 900MHz
Reference
The LTC2157-14/LTC2156-14/LTC2155-14 has an internal
1.25V voltage reference. For a 1.5V input range with internal reference, connect SENSE to VDD. For a 1.5V input
range with an external reference, apply a 1.25V reference
voltage to SENSE (Figure 7).
VCM
50Ω
0.1μF
50Ω
Encode Input
LTC2157-14
3pF
0.1μF
4.7Ω
AIN+
INPUT
0.1μF
3pF
4.7Ω
AIN–
3pF
21576514 F06
Figure 6. Front-End Circuit Using a High
Speed Differential Amplifier
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
the encode inputs directly. Otherwise a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD +0.1V or go below –0.1V.
LTC2157-14
VDD
LTC2157-14
VREF
5Ω
1.25V
1.2V
2.2μF
SCALER/
BUFFER
ADC
REFERENCE
ENC+
10k
SENSE
SENSE
DETECTOR
ENC–
21576514 F07
Figure 7. Reference Circuit
21576514 F08
Figure 8. Equivalent Encode Input Circuit
21576514fa
19
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
output pair. There are seven LVDS output pairs for channel A (DA0_1+/DA0_1– through DA12_13–/DA12_13+)
and seven pairs for channel B (DB0_1+/DB0_1– through
DB12_13–/DB12_13+). Overflow (OF+/OF –) and the data
output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that overflow for both channels is multiplexed onto the OF+/OF – output pair.
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 3) or
by CS in parallel programming mode.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage.
An external 100Ω differential termination resistor is required
for each LVDS output pair. The termination resistors should
be located as close as possible to the LVDS receiver.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this cases care should be taken to make the clock a 50%
(± 5%) duty cycle.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
DIGITAL OUTPUTS
The digital outputs are double data rate LVDS signals. Two
data bits are multiplexed and output on each differential
LTC2157-14
VDD
1.2V
0.1μF
10k
50Ω
100Ω
0.1μF
50Ω
T1: MACOM
ETC1-1-13
21576514 F09
Figure 9. Sinusoidal Encode Drive
LTC2157-14
VDD
1.2V
0.1μF
PECL OR
LVDS INPUT
ENC+
10k
100Ω
0.1μF
ENC–
21576514 F10
Figure 10. PECL or LVDS Encode Drive
21576514fa
20
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 3). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
The OF output is double data rate; when CLKOUT+ is low,
channel A’s overflow is available; when CLKOUT+ is high,
channel B’s overflow is available.
Phase Shifting the Output Clock
To allow adequate set-up and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combination of these two features enables phase shifts of 45° up
to 315° (Figure 11).
ENC+
D0-D13, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1
CLKPHASE0
0°
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
CLKOUT+
21576514 F11
Figure 11. Phase Shifting CLKOUT
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21
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
DATA FORMAT
CLKOUT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
OF
OF
D13
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
CLKOUT
D13/D0
D12
(1.5V Range)
OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>0.75 V
1
11 1111 1111 1111
01 1111 1111 1111
+0.75V
0
11 1111 1111 1111
01 1111 1111 1111
+0.749908V
0
11 1111 1111 1110
01 1111 1111 1110
+0.0000915V
0
10 0000 0000 0001
00 0000 0000 0001
+0.000000V
0
10 0000 0000 0000
00 0000 0000 0000
–0.0000915V
0
01 1111 1111 1111
11 1111 1111 1111
–0.0001831V
0
01 1111 1111 1110
11 1111 1111 1110
–0.7499084V
0
00 0000 0000 0001
10 0000 0000 0001
–0.75V
0
00 0000 0000 0000
10 0000 0000 0000
< –0.75V
1
00 0000 0000 0000
10 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled
by serially programming mode control register A4.
D12/D0
•
•
•
RANDOMIZER
ON
D1
D1/D0
D0
D0
21576514 F12
Figure 12. Functional Equivalent of Digital Output Randomizer
PC BOARD
CLKOUT FPGA
OF
D13/D0
LTC2157-14
D13
D12/D0
D12
D1/D0
t
t
t
D1
D0
D0
21576514 F13
Figure 13. Decoding a Randomized Digital
Output Signal
21576514fa
22
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
Alternate Bit Polarity
Sleep Mode
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11, D13) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The A/D may be placed in sleep mode to conserve power.
In sleep mode the entire A/D converter is powered down,
resulting in < 5mW power consumption. If the encode
input signal is not disabled the power consumption will be
higher (up to 5mW at 250Msps). Sleep mode is enabled
by mode control register A1 (serial programming mode),
or by SCK (parallel programming mode).
In the serial programming mode it is also possible to disable channel B while leaving channel A in normal operation.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output randomizer—either both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitor on VREF . For
the suggested value in Figure 1, the A/D will stabilize after
0.1ms + 2500 • tp where tp is the period of the sampling
clock.
Digital Output Test Patterns
Nap Mode
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13 to D0) to known values:
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wakeup. Recovering from nap mode requires at least 100
clock cycles. Nap mode is enabled by setting register A1
in the serial programming mode.
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Wake-up time from nap mode is guaranteed only if the
clock is kept running, otherwise sleep mode Wake-up
conditions apply.
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples.
DEVICE PROGRAMMING MODES
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
The operating modes of the LTC215X-14 can be programmed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
21576514fa
23
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
Software Reset
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is necessary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is write-only.
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 3 shows a map of the mode control registers.
GROUNDING AND BYPASSING
The LTC215X-14 requires a printed circuit board with a
clean unbroken ground plane in the first layer beneath the
ADC. A multilayer board with an internal ground plane is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF pins. Bypass capacitors must be
located as close to the pins as possible. Size 0402 ceramic
capacitors are recommended. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC215X-14 is transferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
21576514fa
24
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). X Indicates Unused Bit
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
Bit 7
RESET
Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused Bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
SLEEP
NAP
PDB
0
Bits 7-4
Unused, this bit read back as 0
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
Bit 1
PDB
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0
Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, This Bit Read Back as 0
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
21576514fa
25
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
X
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
Bits 7-5
Unused, This Bit Read Back as 0
Bits 4-2
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
Bit 0
OUTOFF
Digital Output Mode Control Bits
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled (High Impedance)
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
OUTTEST2
Bits 7-5
D6
D5
D4
D3
D2
D1
D0
OUTTEST1
OUTTEST0
ABP
0
DTESTON
RAND
TWOSCOMP
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111
100 = Checkerboard Output Pattern. OF, D13-D0 alternate between 101 0101 0101 0101 and 010 1010 1010 1010
Note 1: Other bit combinations are not used.
Note 2: Patterns from channel A and channel B may not be synchronous.
Bit 4
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3
Must Be Set to 0
Bit 2
DTESTON
Enable the digital output test patterns (set by Bits 7-5)
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Bit 1
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
21576514fa
26
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
21576514fa
27
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL APPLICATIONS
Inner Layer 2 GND
Inner Layer 3
21576514fa
28
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5
21576514fa
29
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL APPLICATIONS
Bottom Side
21576514fa
30
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL APPLICATIONS
LTC2157-14 Schematic
SPI BUS
C13, 0.1μF
PAR/SER
C7
0.1μF
AINA+
AINA–
R33
R8
SENSE
C29, 0.1μF
C4
2.2μF
AINB+
R7
R6
R12
VDD
VDD
GND
AINA+
AINA–
GND
SENSE
VREF
GND
VCM
GND
AINB–
AINB+
GND
VDD
VDD
LTC2157-14
OGND
DA4_5+
DA4_5–
DA2_3+
DA2_3–
DA0_1+
DA0_1–
CLKOUT+
CLKOUT–
DB12_13+
DB12_13–
DB10_11+
DB10_11–
DB8_9+
DB8_9–
OGND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DIGITAL
OUTPUTS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AINB–
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
GND
ENC+
ENC–
GND
OF –
OF +
DB0_1–
DB0_1+
DB2_3–
DB2_3+
DB4_5–
DB4_5+
DB6_7 –
DB6_7+
OVDD
VDD
R34
VDD
PAR/SER
CS
SCK
SDI
SDO
GND
DA12_13+
DA12_13–
DA10_11+
DA10_11–
DA8_9+
DA8_9–
DA6_7+
DA6_7 –
OVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
OVDD
VDD
OVDD
C14
0.1μF
C12
0.1μF
C78
0.1μF
C79
0.1μF
R56
ENCODE CLOCK
21576514 TA09
21576514fa
31
LTC2157-14/
LTC2156-14/LTC2155-14
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 ±0.05
7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
7.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9 .00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
63 64
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 ±0.10
7.50 REF
(4-SIDES)
7.15 ±0.10
(UP64) QFN 0406 REV C
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
21576514fa
32
LTC2157-14/
LTC2156-14/LTC2155-14
REVISION HISTORY
REV
DATE
DESCRIPTION
A
03/12
Corrected common mode voltage range to 0.435 • VDD
PAGE NUMBER
18
Inserted 4.7Ω resistor in Figure 5.
19
Corrected Nap Mode paragraph description
23
LTC2157 Schematic. Replaced C8, C12 with R8, R12.
31
21576514fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL APPLICATION
LTC2157-14: 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
VDD
OVDD
CHANNEL A
CLOCK
S/H
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
–20
DDR
LVDS
AMPLITUDE (dBFS)
ANALOG
INPUT
0
DA12_13
t
t
t
DA0_1
OVDD
–40
–60
–80
CHANNEL B
–100
ANALOG
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
DB12_13
t
t
t
DB0_1
OUTPUT
DRIVERS
DDR
LVDS
–120
0
20
100
40
60
80
FREQUENCY (MHz)
120
21576514 TA10b
GND
21576514 TA10a
OGND
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
1250mW, 77.7dB SNR, 100dB SFDR, 48-Pin QFN
ADCs
LTC2208
LTC2157-12/ LTC2156-12/ 12-Bit, 250Msps/210Msps/170Msps,
LTC2155-12
1.8V Dual ADC, LVDS DDR Outputs
588mW/543mW/495mW, 68.5dB SNR, 90dB SFDR
LTC2242-10/LTC2241-10/
LTC2241-10
10-Bit, 250Msps/210Msps/170Msps,
2.5V ADC, LVDS Outputs
740mW/585mW/445mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN
LTC2242-12/LTC2241-12/
LTC2240-12
12-Bit, 250Msps/210Msps/170Msps,
2.5V ADC, LVDS Outputs
740mW/585mW/445mW, 65.5dB SNR, 80dB SFDR, 64-Pin QFN
LTC2262-14
14-Bit, 150Msps 1.8V ADC, Ultralow Power
149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm 36-Pin QFN
RF Mixers/Demodulators
LT5517
40MHz to 900MHz Direct Conversion Quadrature High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
Demodulator
LT5527
400MHz to 3.7GHz High Linearity
Downconverting Mixer
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
LT5575
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator,
Integrated RF and LO Transformer
LTC6409
10GHz GBW, 1.1nV/√Hz Differential Amplifier/
ADC Driver
88dB SFDR at 100MHz, Input Range Includes Ground 52mA Supply Current
3mm × 2mm QFN Package
LTC6412
800MHz, 31dB Range, Analog-Controlled
Variable Gain Amplifier
Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise
Figure, 4mm × 4mm QFN-24
LTC6420-20
1.8GHz Dual Low Noise, Low Distortion
Differential ADC Drivers for 300MHz IF
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per
Amplifier, 3mm × 4mm QFN-20
LTM9002
14-Bit Dual Channel IF/Baseband Receiver
Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
LTM9003
12-Bit Digital Pre-Distortion Receiver
Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to 3.8GHz Input
Frequency Range
Amplifiers/Filters
Receiver Subsystems
21576514fa
34 Linear Technology Corporation
LT 0312 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2011