May 1997 ML2258* µP Compatible 8-Bit A/D Converter with 8-Channel Multiplexer GENERAL DESCRIPTION FEATURES The ML2258 combines an 8-bit A/D converter, 8-channel analog multiplexer, and a microprocessor compatible 8bit parallel interface and control logic in a single monolithic device. ■ Easy interface to microprocessors is provided by the latched and decoded multiplexer address inputs and latched three-state outputs. ■ The device is suitable for a wide range of applications from process and machine control to consumer, automotive, and telecommunication applications. ■ The ML2258 is an enhanced, pin-compatible, second source for the industry standard ADC0808/ADC0809. The ML2258 enhancements are faster conversion time, true sample and hold function, superior power supply rejection, wider reference range, and a double buffered data bus as well as faster digital timing. All parameters are guaranteed over temperature with a power supply voltage of 5V ±10%. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Conversion time 6.6µs Total unadjusted error ±1/2LSB or ±1LSB No missing codes Sample and hold 390ns acquisition Capable of digitizing a 5V, 50kHz sine wave 8-input multiplexer 0V to 5V analog input range with single 5V power supply Operates ratiometrically or with up to 5V voltage reference No zero-or full-scale adjust required Analog input protection 25mA per input min Low power dissipation 3mA max TTL and CMOS compatible digital inputs and outputs Standard 28-pin DIP or surface mount PCC Superior pin compatible replacement for ADC0808 and ADC0809 * Some Packages Are End Of Life As Of August 1, 2000 BLOCK DIAGRAM START IN0 A/D WITH SAMPLE HOLD IN1 CLOCK END OF CONVERSION (INTERRUPT) CONTROL & TIMING IN2 IN3 IN4 8-CHANNEL MULTIPLEXER S.A.R. IN5 COMPARATOR THREE STATE OUTPUT LATCH BUFFER IN6 IN7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 SWITCH TREE ADDR0 ADDR1 ADDR2 ADDRESS LATCH AND DECODER CAPACITOR/ RESISTOR ARRAY ADDRESS LATCH ENABLE VCC GND +VREF –VREF OUTPUT ENABLE 1 ML2258 PIN CONFIGURATION IN7 5 24 ADDR1 START 6 23 ADDR2 EOC 7 22 ALE DB3 8 21 DB7 OE 9 20 DB6 CLK 10 19 DB5 VCC 11 18 DB4 +VREF 12 17 DB0 GND 13 16 –VREF DB1 14 15 DB2 IN0 ADDR0 3 2 1 28 27 26 25 5 ADDR0 START 6 24 ADDR1 EOC 7 23 ADDR2 DB3 8 22 ALE OE 9 21 DB7 CLK 10 20 DB6 VCC 11 12 14 15 16 17 19 18 DB5 13 DB4 25 IN1 4 4 IN7 DB0 IN6 IN2 IN0 –VREF 26 IN3 3 DB2 IN1 IN5 IN4 IN2 27 DB1 28 2 GND 1 IN4 +VREF IN3 IN5 ML2258 28-Pin PCC (Q28) IN6 ML2258 28-Pin DIP (P28) TOP VIEW TOP VIEW PIN DESCRIPTION PIN# NAME FUNCTION 1 IN3 Analog input 3. 2 IN4 Analog input 4. 3 IN5 Analog input 5. 4 IN6 Analog input 6. 5 IN7 Analog input 7. 6 START Start of conversion. Active high digital input pulse initiates conversion. 7 EOC End of conversion. This output goes low after a START pulse occurs, stays low for the entire A/D conversion, and goes high after conversion is completed. Data on DB0–DB7 is valid on rising edge of EOC and stays valid until next EOC rising edge. 8 DB3 Data output 3. 9 OE Output enable input. When OE = 0, DB0–DB7 are in high impedance state; OE = 1, DB0–DB7 are active outputs. PIN# NAME FUNCTION 13 GND Ground. 0V, all analog and digital inputs or outputs are reference to this point. 14 DB1 Data output 1. 15 DB2 Data output 2. 16 –VREF Negative reference voltage. 17 DB0 Data output 0. 18 DB4 Data output 4. 19 DB5 Data output 5. 20 DB6 Data output 6. 21 DB7 Data output 7. 22 ALE Address latch enable. Input to latch in the digital address (ADDR2–0) on the rising edge of the multiplexer. 23 ADDR0 Address input 0 to multiplexer. Digital input for selecting analog input. 24 ADDR1 Address input 1 to multiplexer. Digital input for selecting analog input. 10 CLK Clock. Clock input provides timing for A/D converter, S/H, and digital interface. 25 ADDR2 Address input 2 to multiplexer. Digital input for selecting analog input. 11 VCC Positive supply. 5V ± 10%. 26 IN0 Analog input 0. 12 +VREF Positive reference voltage. 27 IN1 Analog input 1. 28 IN2 Analog input 2. 2 ML2258 ABSOLUTE MAXIMUM RATINGS (Note 1) Molded Chip Carrier Package Vapor Phase (60 sec.) ..................................... 215°C Infrared (15 sec.) ............................................ 220°C Supply Voltage, VCC .............................................................. 6.5V Voltage Logic Inputs .................................. –0.3V to VCC +0.3V Analog Inputs ............................... –0.3V to VCC +0.3V Input Current per Pin (Note 2) .............................. ±25mA Storage Temperature .............................. –65°C to +150°C Package Dissipation at TA = 25°C (Board Mount) ............................. 875mW Lead Temperature (Soldering 10 sec.) Dual-In-Line Package (Plastic) ............................ 260°C OPERATING CONDITIONS Supply Voltage, VCC .................................... 4.5VDC to 6.3VDC Temperature Range (Note 3) ................. TMIN - TA - TMAX ML2258BIP, ML2258BIQ, ML2258CIP, ML2258CIQ ........................................ –40°C to +85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = TMIN to TMAX, VCC = +VREF = 5V ±10%, –VREF = GND and fCLK = 10.24MHz ML2258B PARAMETER NOTES CONDITIONS 5, 7 VREF = VCC MIN TYP (NOTE 4) ML2258C MAX MIN TYP (NOTE 4) MAX UNITS ±1 LSB Converter and Multiplexer Total Unadjusted Error ±1/2 +VREF Voltage Range 6 –VREF VCC + 0.1 –VREF VCC + 0.1 V –VREF Voltage Range 6 GND – 0.1 +VREF GND – 0.1 +VREF V Reference Input Resistance 5 14 28 14 28 ký 5, 8 GND – 0.1 VCC + 0.1 V ±1/4 LSB Analog Input Range Power Supply Sensitivity IOFF, Off Channel Leakage Current (Note 9) 6 5, 9 20 VCC + 0.1 GND – 0.1 DC, VCC = 5V ± 10% ±1/32 100mVp-p, 100kHz sine on VCC, VIN = 0 ±1/16 On Channel = VCC Off Channel = 0V 5, 9 On Channel = 0V Off Channel = VCC ±1/4 ±1/32 ±1/16 –1 LSB –1 On Channel = 0V Off Channel = VCC ION, On Channel Leakage Current (Note 9) 20 µA 1 –1 1 –1 On Channel = VCC Off Channel = 0V µA µA 1 1 µA Digital and DC VIN(1), Logical “1” Input Voltage 5 VIN(0), Logical “0” Input Voltage 5 IIN(1), Logical “1” Input Current 5 VIN = VCC IIN(0), Logical “0” Input Current 5 VIN = 0V –1 –1 µA VOUT(1), Logical “1” Output Voltage 5 IOUT = –2mA 4.0 4.0 V VOUT(0), Logical “0” Output Voltage 5 IOUT = 2mA IOUT, Three-State Output 5 VOUT = 0V Current ICC, Supply Current 2.0 2.0 0.8 0.8 V 1 1 µA 0.4 –1 0.4 –1 VOUT = VCC 5 V µA 1 1.5 3 V 1.5 1 µA 3 mA 3 ML2258 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Continued) NOTES CONDITIONS TYP MIN (NOTE 4) MAX UNITS AC and Dynamic Performance Characteristics (Note 10) tACQ Sample and Hold Acquisition 4 fCLK Clock Frequency 5 tC Conversion Time 5 SNR Signal to Noise Ratio VIN = 51kHz, 5V sine. fCLK = 10.24MHz (fSAMPLING > 150kHz). Noise is sum of all nonfundamental components up to 1/2 of fSAMPLING 47 dB THD Total Harmonic Distortion VIN = 51kHz, 5V sine. fCLK = 10.24MHz (fSAMPLING > 150kHz). THD is sum of 2, 3, 4, 5 harmonics relative to fundamental –60 dB IMD Intermodulation Distortion VIN = fA + fB. fA = 49kHz, 2.5V sine. fB = 47.8kHz, 2.5V sine, fCLK = 10.24MHz (fSAMPLING > 150kHz). IMD is (fA + fB), (fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB), (fA – 2fB) relative to fundamental –60 dB FR Frequency Response VIN = 0 to 50kHz. 5V sine relative to 1kHz 0.1 dB tDC Clock Duty Cycle tEOC End of Conversion Delay tWS Start Pulse Width tSS Start Pulse Setup Time tWALE Address Latch Enable Pulse Width tS 100 10240 67 6, 11 40 5 8 kHz 67 + 250ns 1/fCLK 60 % 8 + 250ns 1/fCLK 50 ns 40 ns 5 50 ns Address Setup 5 0 ns tH Address Hold 5 50 ns tH1, H0 Output Enable for DB0–DB7 6 Figure 1, CL = 50pF 100 ns 6 Figure 1, CL = 10pF 50 ns 6 Figure 1, CL = 50pF 200 ns 6 Figure 1, CL = 10pF 100 ns t1H, 0H Output Disable for DB0–DB7 CIN Capacitance of Logic Input COUT Capacitance of Logic Outputs Note 1: Note 2: Note 3: Note Note Note Note Note 4: 5: 6: 7: 8: Note 9: Note 10: Note 11: Note 12: 4 5 1/fCLK 6, 12 Synchronous only 5 pF 10 pF Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V– or VIN > V+) the absolute value of current at that pin should be limited to 25mA or less. –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worstcase test conditions. Typicals are parametric norm at 25°C. Parameter guaranteed and 100% production tested. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation. Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors. For –VREF • VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading. Leakage current is measured with the clock not switching. CL = 50pF, timing measured at 50% point. A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs. The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met, start conversion will have an uncertainty of one clock pulse. ML2258 t1H,tH1 t1H,CL = 10pF tH1,CL = 50pF tr tf OUTPUT ENABLE DATA OUTPUT VCC GND 90% 50% 10% 10K CL 90% t1H VOH 50% 10% t0H 90% 50% OUTPUT GND t0H,CL = 10pF t0H,tH0 VCC tH0,CL = 50pF tf OUTPUT ENABLE 10K DATA OUTPUT VCC GND tr 90% 90% 50% 10% t0H 50% 10% tH0 VCC CL OUTPUT 50% 10% VOL Figure 1. High Impedance Test Circuits and Waveforms TYPICAL PERFORMANCE CURVES 1.0 VCC = 5V VREF = 5V LINEARITY ERROR (LSB) 0.75 0.5 125 C –55 C 0.25 25 C 0 0.01 0.1 1.0 CLOCK FREQUENCY (MHz) 10 Figure 2. Linearity Error vs fCLK 5 ML2258 TYPICAL PERFORMANCE CURVES (Continued) 1 VCC = 5V fCLK = 10.4MHz LINEARITY ERROR (LSB) 0.75 0.5 125 C –55 C 25 C 0.25 0 0 1 2 3 4 5 VREF (VDC) Figure 3. Linearity Error vs VREF Voltage 2 VCC = 5V VREF = 5V VIN = 0V VOS = 3MV fCLK = 10.4MHz TA = 25 C OFFSET ERROR (LSB) 1.5 1 0.5 0 0 1 2 3 4 VREF (VDC) Figure 4. Unadjusted Offset Error vs VREF Voltage 6 5 ML2258 1.0 FUNCTIONAL DESCRIPTION 1.1 MULTIPLEXER ADDRESSING The ML2258 contains an 8-channel single ended analog multiplexer. A particular input channel is selected by using the address decoder. The relationship between the address inputs, ADDR0–ADDR2, and the analog input selected is shown in Table 1. The address inputs are latched into the decoder on the rising edge of the address latch signal ALE. SELECTED ANALOG CHANNEL ADDRESS INPUT ADDR2 ADDR1 ADDR0 IN0 0 0 0 IN1 0 0 1 IN2 0 1 0 IN3 0 1 1 IN4 1 0 0 IN5 1 0 1 IN6 1 1 0 IN7 1 1 1 The capacitor/resistor array offers fast conversion, superior linearity and accuracy since matching is only required between 24 = 16 elements (as opposed to 28 = 256 elements in conventional designs). And since the levels are based on the ratio of capacitors to capacitors and resistors to resistors, the accuracy and long term stability of the converter is improved. This also guarantees monotonicity and no missing codes, as well as eliminating any linearity temperature or power supply dependence. The successive approximation register is a digital block used to store the bit decisions from the conversion. The comparator design is unique in that it is fully differential and auto-zeroed. The fully differential architecture provides excellent noise immunity, excellent power supply rejection, and wide common mode range. The comparator is auto zeroed at the start of each conversion in order to remove any DC offset and full scale gain error, thus improving accuracy and linearity. Another advantage of the capacitor array approach used in the ML2258 over conventional designs is the inherent sample and hold function. This true S/H allows an accurate conversion to be done on the input even if the analog signal is not stable. Linearity and accuracy are maintained for analog signals up to 1/2 the sampling frequency. As a result, input signals up to 75kHz can be converted without degradation in linearity or accuracy. Table 1. Multiplexer Address Decoding 1.2 A/D CONVERTER The A/D converter uses successive approximation to perform the conversion. The converter is composed of the successive approximation register, the DAC and the comparator. The DAC generates the precise levels that determine the linearity and accuracy of the conversion. The DAC is composed of a capacitor upper array and a resistor lower array. The capacitor upper array generates the 4 MSB decision levels while the series resistor lower array generates the 4 LSB decision levels. A switch decoder tree is used to decode the proper level from both arrays. The sequence of events during a conversion is shown in figure 5. The rising edge of a START pulse resets the internal registers and the falling edge initiates a conversion on the next rising edge of CLK. Four CLK pulses later, sampling of the analog input begins. The input is then sampled for the next four CLK periods until EOC goes low. EOC goes low on the rising edge of the 8th CLK pulse indicating that the conversion is now beginning. The actual conversion now takes place for the next 56 CLK pulses, one bit for each 7 CLK pulses. After the conversion is done, the data is updated on DB0–DB7 and EOC goes high on the rising edge of the 67th CLK pulse, indicating that the conversion has been completed and data is valid on DB0–DB7. The data will stay 1/fCLK CLK 1 2 3 4 5 6 7 8 66 67 68 69 70 tSS START tWS ALE tWALE ADDR0–ADDR2 tS tH tEOC EOC tC DB0–DB7 PREVIOUS DATA DATA tDIS tEN tH OE Figure 5. Timing Diagram 7 ML2258 valid on DB0–DB7 until the next conversion updates the data word on the next rising edge of EOC. A conversion can be interrupted and restarted at any time by a new START pulse. 1.3 ANALOG INPUTS AND SAMPLE/HOLD The ML2258 has a true sample and hold circuit which samples both the selected input and ground simultaneously. This simultaneous sampling with a true S/H will give common mode rejection and AC linearity performance that is superior to devices where the two input terminals are not sampled at the same instant and where true sample and hold capability does not exist. Thus, the ML2258 can reject AC common mode signals from DC–50kHz as well as maintain linearity for signals from DC–50kHz. source. If more charging or settling time is needed to reduce these analog input errors, a longer CLK period can be used. The ML2258 has improved latchup immunity. Each analog input has dual diodes to the supply rails, and a minimum of ±25mA (±100mA typically) can be injected into each analog input without causing latchup. 1.4 REFERENCE The plot below (figure 6) shows a 2048 point FFT of the ML2258 converting a 50kHz, 0 to 5V, low distortion sine wave input. The ML2258 samples and digitizes, at its specified accuracy, dynamic input signals with frequency components up to the Nyquist frequency (one-half the sampling rate). The output spectra yields precise measurements of input signal level, harmonic components, and signal to noise ratio up to the 8-bit level. The near-ideal signal to noise ratio is maintained independent of increasing analog input frequencies to 50kHz. The signal at the analog input is sampled during the interval when the sampling switch is open prior to conversion start. The sampling window (S/H acquisition time) is 4 CLK periods long and occurs 4 CLK periods after START goes low. When the sampling switch closes at the start of the S/H acquisition time, 8pF of capacitance is thrown onto the analog input. 4 CLK periods later, the sampling switch opens, the signal present at analog input is stored and conversion starts. Since any error on the analog input at the end of the S/H acquisition time will cause additional conversion error, care should be taken to insure adequate settling and charging time from the The voltage applied to the +VREF and –VREF inputs defines the voltage span of the analog input (the difference between VINMAX and VINMIN) over which the 256 possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable of driving the reference input resistance, typically 20ký. In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the +VREF pin can be tied to VCC and –VREF tied to GND. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy, where the analog input varies between specific voltage limits, the reference pins can be biased with a time and temperature stable voltage source. In contrast to the ADC0808 and ADC0809, the ML2258 –VREF and +VREF reference values do not have to be symmetric around one half of the supply. +VREF and –VREF can be at any voltage between VCC and GND. In addition, the difference between +VREF and –VREF can be set to small values for conversions over smaller voltage ranges. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter. 0 –10 –20 MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 –110 37.5 FREQUENCY (kHz) Figure 6. Output Spectrum 8 75 ML2258 1.5 POWER SUPPLY AND REFERENCE DECOUPLING Intermodulation Distortion A 10µF electrolytic capacitor is recommended to bypass VCC to GND, using as short a lead length as possible. In addition, with clock frequencies above 1MHz, a 0.1µF ceramic disc capacitor should be used to bypass VCC to GND. With inputs consisting of sine waves at two frequencies, fA and fB, any active device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfA + nfB, where m, n = 0, 1, 2, 3,... . Intermodulation terms are those for which m or n is not equal to zero. The ML2258 (IMD) intermodulation distortion specification includes the second order terms (fA + fB) and (fA – fB) and the third order terms (2fA + fB), (2fA – fB), (fA + 2fB) and (fA – 2fB) only. If REF+ and REF– inputs are driven by long lines, they should be bypassed by 0.1µF Ceramic disc capacitors at the reference pins (pins 12, 16). 1.6 DYNAMIC PERFORMANCE Signal-to-Noise Ratio 1.7 DIGITAL INTERFACE Signal-to-noise ratio (SNR) is the measured signal to noise at the output of the converter. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency. SNR is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical SNR for a sine wave is given by A conversion is initiated by the rising edge of a START pulse. As long as this pulse is high, the internal logic is reset. SNR = (6.02N + 1.76)dB where N is the number of bits. Thus for ideal 8-bit converter, SNR = 49.92dB. Harmonic Distortion Harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. Total harmonic distortion (THD) of the ML2258 is defined as V 2 + V 2 + V 2 + V 2 3 4 5 2 THD = 20 log V1 1/ 2 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 are the rms amplitudes of the individual harmonics. The analog inputs are selected by the digital addresses, ADDR0–ADDR2, and latched on the rising edge of ALE. This is described in the Multiplexer Addressing section. The sampling interval starts with the 4th CLK rising edge after a START falling edge and ends on the 8th rising edge of CLK, 4 CLK periods later. On the rising edge of the 8th CLK pulse, the conversion starts and EOC goes low. Each bit conversion in the successive approximation process takes 7 CLK periods. On the rising edge of the 64th CLK pulse, the digital output of the conversion is updated on the outputs DB0–DB7. On the rising edge of the 65th CLK pulse, EOC goes high indicating the conversion is done and data on DB0–DB7 is valid. One feature of the ML2258 over conventional devices is that the data is double-buffered. This means that the outputs DB0–DB7 will stay valid until updated at the end of the next conversion and will not become invalid when the next conversion starts. This facilitates interfacing with external logic of µP. The signal OE drives the data bus, DB0–DB7, into a high impedance state when held low. This allows the ML2258 to be tied directly to a µP system bus without any latches or buffers. 9 ML2258 2.0 TYPICAL APPLICATIONS VCC 15VDC + – –15VDC VCC 600Ω ANALOG IN 20kΩ XDR VXDR VCC 1kΩ ZERO ADJ + ML2258 10µF IN 0.15VCC 3kΩ VCC + –VREF 10µF ML2258 4kΩ – +VREF GND 0.85VCC + 1kΩ FS ADJ 24kΩ Figure 7. Protecting the Input from Overvoltage Figure 8. Operating with Ratiometric Transducers 15% of VCC - VXDR - 85% of VCC ML2258 START EOC 1/2 74HC221 A Q B R VCC R C C Figure 9. Continuous Conversion Mode 10 ML2258 PHYSICAL DIMENSIONS inches (millimeters) Package: P28N 28-Pin Narrow PDIP 1.355 - 1.365 (34.42 - 34.67) 28 0.280 - 0.296 0.299 - 0.325 (7.11 - 7.52) (7.60 - 8.26) PIN 1 ID 1 0.045 - 0.055 (1.14 - 1.40) 0.100 BSC (2.54 BSC) 0.020 MIN (0.51 MIN) 0.180 MAX (4.57 MAX) 0.015 - 0.021 (0.38 - 0.53) 0.125 - 0.135 (3.18 - 3.43) SEATING PLANE 0.008 - 0.012 (0.20 - 0.31) 0º - 15º Package: Q28 28-Pin PLCC 0.485 - 0.495 (12.32 - 12.57) 0.042 - 0.056 (1.07 - 1.42) 0.450 - 0.456 (11.43 - 11.58) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 0.042 - 0.048 (1.07 - 1.22) PIN 1 ID 8 22 0.300 BSC (7.62 BSC) 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.390 - 0.430 (9.90 - 10.92) 15 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.099 - 0.110 (2.51 - 2.79) SEATING PLANE 11 ML2258 ORDERING INFORMATION ALTERNATE PART NUMBER TOTAL UNADJUSTED ERROR ML2258BIP (EOL) ML2258BIQ ADC0808CCN ADC0808CCV ±1/2LSB –40°C to 85°C –40°C to 85°C Molded DIP (P28N) Molded PCC (Q28) ML2258CIP (EOL) ML2258CIQ ADC0809CCN ADC0809CCV ±1LSB –40°C to 85°C –40°C to 85°C Molded DIP (P28N) Molded PCC (Q28) PART NUMBER TEMPERATURE RANGE PACKAGE © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS2258-01