ICST ICS83940AY Low skew, 1-to-18 lvcmos fanout buffer Datasheet

PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83940 is a low skew, 1-to-18 Fanout
Buffer and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be increased from 18 to 36 by utilizing the ability of the outputs to
drive two series terminated lines. The differential clock
input is designed to accept any differential input levels
including LVPECL.
• 18 LVCMOS outputs, 23Ω typical output impedance
The ICS83940 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the
ICS83940 ideal for those clock distribution applications demanding well defined performance and repeatability.
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
,&6
• Output frequency up to 200MHz
• 150ps output skew
• Part to part skew: 850ps
• Selectable LVCMOS or differential clock input
• LVTTL / LVCMOS clock select input
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• Industrial temperature information available upon request
GND
Q5
Q4
Q3
VDDO
32 31 30 29 28 27 26 25
0
Q0
LVCMOS_CLK
Q2
CLK0
nCLK0
Q1
Q0
CLK_SEL
1
Q1 - Q16
Q17
GND
1
24
Q6
GND
2
23
Q7
LVCMOS_CLK
3
22
Q8
CLK_SEL
4
21
VDDI
CLK
5
20
Q9
nCLK
6
19
Q10
VDDI
7
18
Q11
VDDO
8
17
GND
ICS83940
9 10 11 12 13 14 15 16
VDDO
Q12
Q13
Q14
GND
Q15
Q16
Q17
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940AY
www.icst.com/products/hiperclocks.html
1
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 12, 17, 25
Name
GND
Type
Description
Output power supply ground. Connect to ground.
Power
3
LVCMOS_CLK
Input
4
CLK_SEL
Input
5
CLK
Input
6
nCLK
Input
7, 21
VDDI
Power
8, 16, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
VDDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Power
Output power supply. Connect to 3.3V or 2.5V.
Output
Clock outputs. 23Ω typical output impedance.
LVCMOS interface levels
Pulldown Clock input. LVCMOS interface levels.
Clock select input. Select LVCMOS clock input
Pulldown when HIGH. Selects LVPECL clock inputs when
LOW.
Non-inver ting differential clock input. Any differential
Pulldown
inteface levels.
Inver ting differential clock input. Any differential
Pullup
inteface levels.
Input power supply. Connect to 3.3V or 2.5V.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
Parameter
Input
Capacitance
Maximum
Units
CLK0, nCLK0,
LVCMOS_CLK
Test Conditions
4
pF
CLK_SEL
4
pF
Power Dissipation Capacitance
(per output)
RPULLUP
Input Pullup Resistor
RPULLDOWN
ROUT
83940AY
Minimum Typical
VDDI, VDDO = 3.465V
pF
VDDI = 3.465V,
VDDO = 2.625V
pF
VDDI, VDDO = 2.625V
pF
51
KΩ
Input Pulldown Resistor
51
KΩ
Output Impedance
23
Ω
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2
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK0, nCLK0
LVCMOS_CLK
0
Selected
De-selected
1
De-selected
Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK-SEL
LVCMOS_CLK
CLK0
nCLK0
0
—
0
1
Outputs
Q0 thru
Q17
LOW
0
—
1
0
0
—
0
Biased; NOTE 1
0
—
1
Biased; NOTE 1
0
—
Biased; NOTE 1
0
0
—
Biased; NOTE 1
1
1
0
—
—
Input to Output Mode
Polarity
Differential to Single Ended
Non Inver ting
HIGH
Differential to Single Ended
Non Inver ting
LOW
Single Ended to Single Ended
Non Inver ting
HIGH
Single Ended to Single Ended
Non Inver ting
HIGH
Single Ended to Single Ended
Inver ting
LOW
Single Ended to Single Ended
Inver ting
LOW
Single Ended to Single Ended
Non Inver ting
1
1
—
—
HIGH
Single Ended to Single Ended Non Inver ting
NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets
the switch point for the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to
VDDI, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is
VDDI/2.
83940AY
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3
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, Tstg
4.6V
-0.5V to VDD+0.5 V
-0.5V to VDD+0.5V
46°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4A. DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0° TO 70°
Symbol Parameter
VDDI
Test Conditions
Input Power Supply Voltage
VDDO
Output Power Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
3.135
3.3
3.465
V
70
mA
Maximum
Units
VDDI = VDDO = 3.465V
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0° TO 70°
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
Test Conditions
Minimum
VDDI = 3.465V
2
3.8
V
REF_CLK
VDDI = 3.135V
-0.3
1.3
V
CLK_SEL
REF_CLK,
CLK_SEL
REF_CLK,
CLK_SEL
VDDI = 3.135V
-0.3
0.8
V
150
µA
REF_CLK
CLK_SEL
Typical
VDDI = VIN = 3.465V
VDDI = 3.465V, VIN = 0V
VDDO = 3.135V,
IOH = -20mA
VDDO = 3.135V,
IOL = 20mA
-5
µA
2.4
V
0.6
V
Maximum
Units
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0° TO 70°
Symbol Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
CLK0
VDDI = VIN = 3.465V
150
µA
nCLK0
VDDI = VIN = 3.465V
5
µA
CLK0
VDDI = 3.465V, VIN = 0V
-5
µA
nCLK0
VDDI = 3.465V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Input Voltage
0.15
Input Common Mode Voltage;
VCMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
83940AY
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4
1.3
V
VDD - 0.85
V
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0° TO 70°
Symbol
fMAX
Parameter
Maximum Input Frequency
tpLH
tpHL
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR
tF
Output Rise Time
Output Fall Time
Test Conditions
CLK, nCLK
CLK, nCLK
0 < f ≤ 200MHz
0 < f ≤ 200MHz
Measured on rising edge
@VDDO/2
Measured on rising edge
@VDDO/2
20% to 80% @ 50MHz
20% to 80% @ 50MHz
Minimum Typical
2.3
odc
Output Duty Cycle
45
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions, and using the same type of inputs.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY
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5
Maximum
200
Units
MHz
4
ns
ns
150
ps
850
ps
ns
ns
55
%
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDDI = 3.3V±5%; VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol Parameter
VDDI
Test Conditions
Input Power Supply Voltage
VDDO
Output Power Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
2.375
2.5
2.625
VDDI = 3.465V, VDDO = 2.625V
V
mA
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDDI = 3.3V±5%; VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
REF_CLK
CLK_SEL
REF_CLK
CLK_SEL
REF_CLK,
CLK_SEL
REF_CLK,
CLK_SEL
Test Conditions
Minimum
VDDI = 3.465V
VDDI = 3.135V
Typical
Maximum
Units
2
3.8
V
-0.3
1.3
V
150
µA
VDDI = VIN = 3.465V
VDDI = 3.465V, VIN = 0V
VDDO = 2.375V,
IOH = -12mA
VDDO = 2.375V,
IOL = 12mA
-5
µA
1.8
V
0.5
V
Maximum
Units
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDDI = 3.3V±5%; VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
CLK0
VDDI = VIN = 3.465V
150
µA
nCLK0
VDDI = VIN = 3.465V
5
µA
CLK0
VDDI = 3.465V, VIN = 0V
-5
µA
nCLK0
VDDI = 3.465V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Input Voltage
0.15
Input Common Mode Voltage;
VCMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
83940AY
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6
1.3
V
VDD - 0.85
V
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 5B. AC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol
fMAX
Parameter
Maximum Input Frequency
tpLH
tpHL
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR
tF
Output Rise Time
Output Fall Time
Test Conditions
CLK, nCLK
CLK, nCLK
Minimum Typical
0 < f ≤ 200MHz
0 < f ≤ 200MHz
Measured on rising edge
@VDDO/2
Measured on rising edge
@VDDO/2
20% to 80% @ 50MHz
20% to 80% @ 50MHz
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions, and using the same type of inputs.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY
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7
Maximum
Units
MHz
ns
ns
ps
ps
ns
ns
%
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol Parameter
VDDI
Test Conditions
Input Power Supply Voltage
VDDO
Output Power Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
2.375
2.5
2.625
VDDI = VDDO = 2.625V
V
mA
TABLE 4H. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
REF_CLK
CLK_SEL
REF_CLK
CLK_SEL
REF_CLK,
CLK_SEL
REF_CLK,
CLK_SEL
Test Conditions
Minimum
VDDI = 2.625V
2
Maximum
Units
2.96
V
VDDI = 2.375V
0.8
V
VDDI = VIN = 2.625V
150
µA
VDDI = 2.625V, VIN = 0V
VDDO = 2.375V,
IOH = -12mA
VDDO = 2.375V,
IOL = 12mA
Typical
-5
µA
1.8
V
0.5
V
Maximum
Units
TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 25V±5%, TA = 0° TO 70°
Symbol Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
CLK0
VDDI = VIN = 2.625V
150
µA
nCLK0
VDDI = VIN = 2.375V
5
µA
CLK0
VDDI = 2.625V, VIN = 0V
-5
µA
nCLK0
VDDI = 2.625V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Input Voltage
0.15
Input Common Mode Voltage;
VCMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
83940AY
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8
1.3
V
VDD - 0.85
V
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 5C. AC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol
fMAX
Parameter
Maximum Input Frequency
tpLH
tpHL
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR
tF
Output Rise Time
Output Fall Time
Test Conditions
CLK, nCLK
CLK, nCLK
Minimum Typical
0 < f ≤ 200MHz
0 < f ≤ 200MHz
Measured on rising edge
@VDDO/2
Measured on rising edge
@VDDO/2
20% to 80% @ 50MHz
20% to 80% @ 50MHz
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions, and using the same type of inputs.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY
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9
Maximum
Units
MHz
ns
ns
ps
ps
ns
ns
%
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
q
0°
--
7°
ccc
--
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026
83940AY
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10
REV. B JULY 31, 2001
PRELIMINARY
ICS83940
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-18
LVCMOS FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS83940AY
ICS83940AY
32 Lead LQFP
250 per tray
0°C to 70°C
ICS83940AYT
ICS83940AY
32 Lead LQFP on Tape and Reel
1000
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
83940AY
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11
REV. B JULY 31, 2001
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