To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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HAT1036R Silicon P Channel Power MOS FET Power Switching REJ03G1149-0700 (Previous: ADE-208-662E) Rev.7.00 Sep 07, 2005 Features • Low on-resistance RDS (on) = 11 mΩ typ • Capable of –4 V gate drive • Low drive current • High density mounting Outline RENESAS Package code: PRSP0008DD-D (Package name: SOP-8 <FP-8DAV> ) 5 6 7 8 D D D D 65 87 1, 2, 3 4 5, 6, 7, 8 4 G 3 12 4 S S S 1 2 3 Rev.7.00 Sep 07, 2005 page 1 of 6 Source Gate Drain HAT1036R Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Symbol VDSS Value –30 Unit V VGSS ID ±20 –12 V A –96 –12 A A 2.5 150 W °C ID (pulse) IDR Note 1 Note 2 Channel dissipation Channel temperature Pch Tch °C Storage temperature Tstg –55 to +150 Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol V (BR) DSS Min –30 Typ — Max — Unit V IGSS IDSS — — — — ±0.1 –1 µA µA VGS = ±20 V, VDS = 0 VDS = –30 V, VGS = 0 Gate to source cutoff voltage Static drain to source on state resistance VGS (off) RDS (on) –1.0 — — 11 –2.5 14 V mΩ VDS = –10 V, ID = –1 mA Note 3 ID = –6 A, VGS = –10 V Forward transfer admittance RDS (on) |yfs| — 12 21 20 34 — mΩ S ID = –6 A, VGS = –4 V Note 3 ID = –6 A, VDS = –10 V Input capacitance Output capacitance Ciss Coss — — 4200 870 — — pF pF Reverse transfer capacitance Total gate charge Crss Qg — — 360 70 — — pF nC VDS = –10 V VGS = 0 f = 1 MHz Gate to source charge Gate to drain charge Qgs Qgd — — 12 14 — — nC nC VDD = –10 V VGS = –10 V ID = –12 A Turn-on delay time Rise time td (on) tr — — 120 350 — — ns ns VGS = –4 V, ID = –6 A, VDD ≅ –10 V Turn-off delay time Fall time td (off) tf — — 100 120 — — ns ns Body-drain diode forward voltage Body-drain diode reverse recovery time VDF trr — — –0.85 55 –1.11 — V ns Gate to source leak current Zero gate voltage drain current Note: 3. Pulse test Rev.7.00 Sep 07, 2005 page 2 of 6 Test Conditions ID = –10 mA, VGS = 0 Note 3 IF = –12 A, VGS = 0 IF = –12 A, VGS = 0 diF/dt = 20 A/µs Note 3 HAT1036R Main Characteristics Power vs. Temperature Derating 3.0 –500 10 µs ID (A) Test Condition: When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s Drain Current Channel Dissipation Pch (W) 4.0 Maximum Safe Operation Area 2.0 1.0 0 0 50 100 150 Ambient Temperature 200 100 µs –100 1m PW s =1 DC 0m Op era s tion ( PW No –1 Operation in ≤ 1 te 4 this area is 0s ) limited by RDS (on) –0.1 Ta = 25°C 1 shot pulse –0.01 –0.1 –0.3 –1 –3 –10 –30 –10 –100 Drain to Source Voltage VDS (V) Ta (°C) Note 4: When using the glass epoxy board (FR4 40 × 40 × 1.6 mm) Typical Transfer Characteristics Typical Output Characteristics –50 –10 V –40 Pulse Test –40 –30 –3.5 V –20 –10 ID (A) –5 V –30 Drain Current VDS = –10 V Pulse Test –4 V Drain Current ID (A) –50 VGS = –3 V –20 –10 25°C Tc = 75°C 0 0 –2 –4 –6 –8 Drain to Source Voltage 0 0 –10 VDS (V) –0.4 –0.3 –0.2 ID = –10 A –0.1 –5 A –2 A 0 0 –4 –8 –12 Gate to Source Voltage Rev.7.00 Sep 07, 2005 page 3 of 6 –16 –20 VGS (V) –3 –4 –5 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (mΩ) Drain to Source Saturation Voltage VDS (on) (V) Pulse Test –2 Gate to Source Voltage Drain to Source Saturation Voltage vs. Gate to Source Voltage –0.5 –1 –25°C 100 Pulse Test 50 VGS = –4 V 20 10 –10 V 5 2 1 –0.1 –0.2 –0.5 –1 –2 –5 –10 –20 –50 –100 Drain Current ID (A) Static Drain to Source on State Resistance vs. Temperature Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) (mΩ) HAT1036R 50 Pulse Test 40 ID = –2 A, –5 A, –10 A 30 VGS = –4 V 20 10 –2 A, –5 A, –10 A –10 V 0 –40 0 40 80 Case Temperature 120 160 100 Tc = –25°C 30 10 75°C 3 25°C 1 0.3 VDS = –10 V Pulse Test 0.1 –0.1 –0.3 Tc (°C) –30 –100 10000 Ciss Capacitance C (pF) Reverse Recovery Time trr (ns) –10 Typical Capacitance vs. Drain to Source Voltage 100 50 20 3000 1000 Coss 300 Crss 100 30 di / dt = 20 A / µs VGS = 0, Ta = 25°C 10 –0.1 –0.2 –0.5 –1 VGS = 0 f = 1 MHz 10 –2 0 –5 –10 –20 Reverse Drain Current –4 VGS –20 VDS –30 –8 VDD = –25 V –10 V –5 V –12 –16 –40 ID = –12 A –50 0 40 80 Gate Charge Rev.7.00 Sep 07, 2005 page 4 of 6 120 160 Qg (nc) –30 –40 –50 –20 200 1000 Switching Time t (ns) –10 VGS (V) 0 VDD = –5 V –10 V –25 V –20 Switching Characteristics Gate to Source Voltage 0 –10 Drain to Source Voltage VDS (V) IDR (A) Dynamic Input Characteristics VDS (V) –3 Drain Current ID (A) Body-Drain Diode Reverse Recovery Time Drain to Source Voltage –1 tr 500 200 100 tf td(on) td(off) 50 20 V = –4 V, V = –10 V GS DS Rg = 50 Ω, duty ≤ 1 % 10 –0.1 –0.2 –0.5 –1 –2 –5 –10 –20 Drain Current ID (A) HAT1036R Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) 50 –10 V 40 VGS = 0 30 –5 V 20 10 Pulse Test 0 –0.4 0 –0.8 –1.2 Source to Drain Voltage –1.6 VSD –2.0 (V) Normalized Transient Thermal Impedance γ s (t) Normalized Transient Thermal Impedance vs. Pulse Width 10 1 D=1 0.5 0.2 0.1 0.1 θch – f (t) = γ s (t) • θch – f θch – f = 83.3°C/W, Ta = 25°C When using the glass epoxy board (FR4 40 × 40 × 1.6 mm) 0.05 0.01 0.02 0.01 D= PDM 0.001 o 1sh 0.0001 10 µ tp uls e PW T PW T 100 µ 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (S) Switching Time Test Circuit Switching Time Waveform Vin Vout Monitor Vin Monitor 10% D.U.T. 90% RL 90% 90% Vin –4 V 50 Ω VDD = –10 V Vout td(on) Rev.7.00 Sep 07, 2005 page 5 of 6 10% tr 10% td(off) tf HAT1036R Package Dimensions JEITA Package Code RENESAS Code P-SOP8-3.95 × 4.9-1.27 PRSP0008DD-D Package Name FP-8DAV 0.085g F *1 D MASS[Typ.] bp 1 c *2 E Index mark HE 5 8 4 Z Terminal cross section (Ni/Pd/Au plating) *3 bp x M NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. e Reference Symbol L1 Dimension in Millimeters Min Nom Max D 4.90 5.3 E 3.95 A2 A1 0.10 0.14 0.25 0.34 0.40 0.46 0.15 0.20 0.25 1.75 A A bp A1 b1 c L c1 0° y HE Detail F 5.80 e 8° 6.10 6.20 1.27 x 0.25 y 0.1 Z 0.75 L L1 0.40 0.60 1.27 1.08 Ordering Information Part Name Quantity Shipping Container HAT1036R-EL-E 2500 pcs Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.7.00 Sep 07, 2005 page 6 of 6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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