ON CAT9554HV4I-GT2 8-bit iâ²c and smbus i/o port with interrupt Datasheet

CAT9554, CAT9554A
8-bit I²C and SMBus I/O Port with Interrupt
FEATURES
DESCRIPTION
„ 400kHz I²C bus compatible
(1)
The CAT9554 and CAT9554A are CMOS devices that
provide 8-bit parallel input/output port expansion for
I²C and SMBus compatible applications. These I/O
expanders provide a simple solution in applications
where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
„ 2.3V to 5.5V operation
„ Low stand-by current
„ 5V tolerant I/Os
„ 8 I/O pins that default to inputs at power-up
„ High drive capability
The CAT9554/9554A consist of an input port register,
an output port register, a configuration register, a
polarity inversion register and an I²C/SMBuscompatible serial interface.
„ Individual I/O configuration
„ Polarity inversion register
„ Active low interrupt output
Any of the eight I/Os can be configured as an input or
output by writing to the configuration register. The
system master can invert the CAT9554/9554A input
data by writing to the active-high polarity inversion
register.
„ Internal power-on reset
„ No glitch on power-up
„ Noise filter on SDA/SCL inputs
„ Cascadable up to 8 devices
„ Industrial temperature range
The CAT9554/9554A features an active low interrupt
output which indicates to the system master that an
input state has changed.
„ RoHS-compliant 16-lead SOIC and TSSOP, and
16-pad TQFN (4 x 4mm) packages
The device’s extended addressing capability allows up
to 8 devices to share the same bus. The CAT9554A is
identical to the CAT9554 except the fixed part of the
I²C slave address is different. This allows up to 16 of
devices (eight CAT9554 and eight CAT9554A) to be
connected on the same bus.
APPLICATIONS
„ White goods (dishwashers, washing machines)
„ Handheld devices (cell phones, PDAs, digital
cameras)
„ Data Communications (routers, hubs and
servers)
BLOCK DIAGRAM
For Ordering Information details, see page 15.
(1)
A0
I/O0
A1
I/O1
A2
SCL
SDA
I/O2
8-BIT
INPUT
FILTER
I2C/SMBUS
CONTROL
WRITE pulse
INPUT/
OUTPUT
PORTS
I/O4
I/O5
READ pulse
VCC
I/O3
I/O6
VCC
I/O7
POWER-ON
RESET
VSS
LP FILTER
INT
Notes:
(1) All I/Os are set to inputs at RESET.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
1
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
PIN CONFIGURATION
TQFN 4 x 4mm (HV4)
(Top View)
SOIC (W), TSSOP (Y)
A0 1
16 VCC
A1 2
15 SDA
A2 3
14 SCL
A1
A0
VCC SDA
16
15
14
13
A2
1
12 SCL
I/O0 4
13 INT
I/O0
2
11 INT
I/O1 5
12 I/O7
I/O1
3
10 I/O7
I/O2 6
11
I/O2
4
9
I/O3 7
10 I/O5
VSS 8
9
I/O6
5
I/O4
6
7
I/O6
8
I/O3 VSS I/O4 I/O5
PIN DESCRIPTION
SOIC / TSSOP
1
2
3
4-7
8
9-12
13
14
15
16
TQFN
15
16
1
2-5
6
7-10
11
12
13
14
Pin Name
A0
A1
A2
I/O0-3
VSS
I/O4-7
¯¯¯
INT
SCL
SDA
VCC
Function
Address Input 0
Address Input 1
Address Input 2
Input/Output Port 0 to Input/Output Port 3
Ground
Input/Output Port 4 to Input/Output Port 7
Interrupt Output (open drain)
Serial Clock
Serial Data
Power Supply
ABSOLUTE MAXIMUM RATINGS (1)
Parameters
VCC with Respect to Ground
Voltage on Any Pin with Respect to Ground
DC Current on I/O0 to I/O7
DC Input Current
VCC Supply Current
VSS Supply Current
Package Power Dissipation Capability (TA = 25°C)
Junction Temperature
Storage Temperature
Ratings
-0.5 to +6.5
-0.5 to +5.5
±50
±20
85
100
1.0
+150
-65 to +150
Units
V
V
mA
mA
mA
mA
W
ºC
ºC
RELIABILITY CHARACTERISTICS
Symbol
VZAP(2)
ILTH (2)(3)
Parameter
ESD Susceptibility
Latch-up
Reference Test Method
JEDEC Standard JESD 22
JEDEC Standard 17
Min
2000
100
Units
Volts
mA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC +1V.
Doc. No. MD-9002 Rev. F
2
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT9554, CAT9554A
D.C. OPERATING CHARACTERISTICS
VCC = 2.3 to 5.5V; TA = -40°C to +85°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
—
5.5
V
—
104
175
µA
—
550
700
µA
—
0.25
1
µA
—
1.5
1.65
V
-0.5
—
0.3 x VCC
V
0.7 x VCC
—
5.5
V
VOL = 0.4V
3
—
—
mA
VI = VCC or VSS
VI = VSS
VO = VSS
-1
—
—
—
—
—
+1
6
8
µA
pF
pF
-0.5
2.0
-1
—
—
—
0.8
5.5
1
V
V
µA
-0.5
2.0
8
10
8
10
8
10
1.8
1.7
2.6
2.5
4.1
4.0
—
—
—
—
—
—
10
13
17
24
14
19
—
—
—
—
—
—
—
—
—
—
0.8
5.5
—
—
—
—
—
—
—
—
—
—
—
—
1
-100
5
8
V
V
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
µA
µA
pF
pF
Supplies
VCC
Supply voltage
ICC
Supply current
Istbl
Standby current
Istbh
Standby current
VPOR
Power-on reset voltage
Operating mode; VCC = 5.5V;
no load; fSCL = 100kHz
Standby mode; VCC = 5.5V; no load;
VI = VSS; fSCL = 0kHz; I/O = inputs
Standby mode; VCC = 5.5V; no load;
VI = VCC; fSCL = 0kHz; I/O = inputs
No load; VI = VCC or VSS
SCL, SDA, ¯¯¯
INT
VIL (1)
VIH
Low level input voltage
(1)
High level input voltage
Low level output
IOL
current
IL
Leakage current
(2)
CI
Input capacitance
CO (2)
Output capacitance
A0, A1, A2
VIL (1)
Low level input voltage
(1)
VIH
High level input voltage
ILI
Input leakage current
I/Os
VIL
Low level input voltage
VIH
High level input voltage
IOL
Low level output
current
VOH
High level output
voltage
IIH
IIL
CI (2)
CO (2)
Input leakage current
Input leakage current
Input capacitance
Output capacitance
VOL = 0.5V; VCC = 2.3V (3)
VOL = 0.7 V; VCC = 2.3 V (3)
VOL = 0.5 V; VCC = 4.5 V (3)
VOL = 0.7 V; VCC = 4.5 V (3)
VOL = 0.5 V; VCC = 3.0 V (3)
VOL = 0.7 V; VCC = 3.0 V (3)
IOH = -8 mA; VCC = 2.3 V (4)
IOH = -10 mA; VCC = 2.3 V (4)
IOH = - 8 mA; VCC = 3.0 V (4)
IOH = -10 mA; VCC = 3.0 V (4)
IOH = -8 mA; VCC = 4.75 V (4)
IOH = -10 mA; VCC = 4.75 V (4)
VCC = 3.6V; VI = VCC
VCC = 5.5V; VI = VSS
Notes:
(1) VIL min and VIH max are reference values only and are not tested.
(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(3) The total current sunk by all I/Os must be limited to 100mA and each I/O limited to 25mA maximum.
(4) The total current sourced by all I/Os must be limited to 85mA.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
3
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
A.C. CHARACTERISTICS
VCC = 2.3V to 5.5V; TA = -40°C to +85°C, unless otherwise specified. (1)
Symbol
Standard I2C
Parameter
Min
FSCL
Clock Frequency
tHD:STA
Max
Fast I2C
Min
100
START Condition Hold Time
Units
Max
400
kHz
4
0.6
µs
tLOW
Low Period of SCL Clock
4.7
1.3
µs
tHIGH
High Period of SCL Clock
4
0.6
µs
4.7
0.6
µs
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
µs
tSU:DAT
Data In Setup Time
250
100
ns
(2)
SDA and SCL Rise Time
1000
300
ns
(2)
SDA and SCL Fall Time
300
300
ns
tR
tF
tSU:STO
tBUF
STOP Condition Setup Time
(2)
Bus Free Time Between STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
(2)
Ti
Symbol
4
0.6
µs
4.7
1.3
µs
3.5
100
Noise Pulse Filtered at SCL and SDA Inputs
Parameter
0.9
50
100
Min
µs
ns
100
ns
Max
Units
200
ns
Port Timing
tPV
Output Data Valid
tPS
Input Data Setup Time
100
ns
tPH
Input Data Hold Time
1
µs
Interrupt Timing
tIV
Interrupt Valid
4
µs
tIR
Interrupt Reset
4
µs
Notes:
(1) Test conditions according to "AC Test Conditions" table.
(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. MD-9002 Rev. F
4
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT9554, CAT9554A
A.C. TEST CONDITIONS
Input Rise and Fall time
≤ 10ns
CMOS Input Voltages
0.2VCC to 0.8VCC
CMOS Input Reference Voltages
0.3VCC to 0.7VCC
TTL Input Voltages
0.4V to 2.4V
TTL Input Reference Voltages
0.8V, 2.0V
Output Reference Voltages
0.5VCC
Output Load: SDA, ¯¯¯
INT
Current Souce IOL = 3mA; CL = 100pF
Output Load: I/Os
Current Source: IOL/IOH = 10mA; CL = 50pF
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 1. I²C Serial Interface Timing
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
5
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
PIN DESCRIPTION
SCL: Serial Clock
The serial clock input clocks all data transferred into
or out of the device. The SCL line requires a pull-up
resistor if it is driven by an open drain output.
A0, A1, A2: Device Address Inputs
These inputs are used for extended addressing
capability. The A0, A1, A2 pins should be hardwired to
VCC or VSS. When hardwired, up to eight
CAT9554/9554As may be addressed on a single bus
system. The levels on these inputs are compared with
corresponding bits, A2, A1, A0, from the slave
address byte.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs. A pullup resistor must be connected from SDA line to VCC.
The value of the pull-up resistor, RP, can be calculated
based on minimum and maximum values from Figure
2 and Figure 3 (see Note).
I/O0 to I/O7: Input / Output Ports
Any of these pins may be configured as input or
output. The simplified schematic of I/O0 to I/O7 is
shown in Figure 4. When an I/O is configured as an
input, the Q1 and Q2 output transistors are off
creating a high impedance input with a weak pull-up
resistor (typical 100kΩ). If the I/O pin is configured as
an output, the push-pull output stage is enabled. Care
should be taken if an external voltage is applied to an
I/O pin configured as an output due to the low
impedance paths that exist between the pin and either
VCC or VSS.
IOL = 3mA @ VOLmax
Fast Mode I²C Bus / tr max - 300ns
8.00
RPmax (KΩ)
RPmin (KΩ)
2.5
2
1.5
1
0.5
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0
2
2.4 2.8 3.2 3.6
4
0.00
4.4 4.8 5.2 5.6
50
VCC (V)
100
150
200
250
300
350
400
CBUS (pF)
Figure 2. Minimum RP Value versus
Supply Voltage
Figure 3. Maximum RP Value versus
Bus Capacitance
Note: According to the Fast Mode I²C bus specification, for bus capacitance up to 200pF, the pull up device can
be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA)
or a switched resistor circuit.
Doc. No. MD-9002 Rev. F
6
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT9554, CAT9554A
¯¯¯
INT: Interrupt Output
The open-drain interrupt output is activated when one
of the port pins configured as an input changes state
(differs from the corresponding input port register bit
state). The interrupt is deactivated when the input
Data from
Shift Register
Data from
Shift Register
returns to its previous state or the input port register is
read. Changing an I/O from an output to an input may
cause a false interrupt if the state of the pin does not
match the contents of the input port register.
Output Port
Register Data
Configuration
Register
D
Q
VCC
FF
Write
Configuration Pulse
Q1
100kΩ
CK
Q
D
Q
FF
Write Pulse
I/O 0 to I/O 7
CK
Q
Output Port
Register
Q2
Input Port
Register
D
VSS
Q
Input Port
Register Data
CK
Q
To INT
D
Q
Polarity
Register Data
LATCH
Read Pulse
Data from
Shift Register
FF
Write
Polarity
Register
CK
Q
Polarity
Inversion Register
Figure 4. Simplified Schematic of I/O0 to I/O7
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
7
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
FUNCTIONAL DESCRIPTION
The CAT9554 and CAT9554A general purpose input/
output (GPIO) peripherals provide up to eight I/O
ports, controlled through an I²C compatible serial
interface
SDA when SCL is HIGH. The CAT9554/9554A
monitors the SDA and SCL lines and will not respond
until this condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
The CAT9554/54A support the I²C Bus data
transmission protocol. This I²C Bus protocol defines
any device that sends data to the bus to be a
transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master
device which generates the serial clock and all
START and STOP conditions for bus access. The
CAT9554/9554A operate as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls
which mode is activated.
DEVICE ADDRESSING
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9554/9554A
for a read or write operation. The four most significant
bits of the slave address are fixed as binary 0100 for
the CAT9554 (Figure 6) and as 0111 for the CAT9554A
(Figure 7). The CAT9554/9554A uses the next three
bits as address bits.
I²C BUS PROTOCOL
The address bits A2, A1 and A0 are used to select
which device is accessed from maximum eight
devices on the same bus. These bits must compare to
their hardwired input pins. The 8th bit following the 7bit slave address is the R/W̄¯ bit that specifies whether
a read or write operation is to be performed. When
this bit is set to “1”, a read operation is initiated, and
when set to “0”, a write operation is selected.
The features of the I²C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition (Figure 5).
Following the START condition and the slave address
byte, the CAT9554/9554A monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT9554/9554A then performs a read or a write
operation depending on the state of the R/W̄¯ bit.
START AND STOP CONDITIONS
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 5. START/STOP Condition
SLAVE ADDRESS
0
1
0
FIXED
0
A2
SLAVE ADDRESS
A1
A0
R/W
0
PROGRAMMABLE
HARDWARE
SELECTABLE
1
FIXED
Figure 6. CAT9554 Slave Address
Doc. No. MD-9002 Rev. F
1
1
A2
A1
A0
R/W
PROGRAMMABLE
HARDWARE
SELECTABLE
Figure 7. CAT9554A Slave Address
8
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT9554, CAT9554A
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine
which register will be written or read.
ACKNOWLEDGE
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data. The SDA line remains stable LOW during
the HIGH period of the acknowledge related clock
pulse (Figure 5).
The input port register is a read only port. It reflects
the incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output by
the configuration register. Writes to the input port
register are ignored.
The CAT9554/9554A respond with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with a
write operation, it responds with an acknowledge after
receiving each 8-bit byte.
Table 2. Register 0 – Input Port Register
When the CAT9554/9554A begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT9554/9554A will continue
to transmit data. If no acknowledge is sent by the
Master, the device terminates data transmission and
waits for a STOP condition. The master must then
issue a STOP condition to return the CAT9554/9554A
to the standby power mode and place the device in a
known state.
bit
I7
I6
I5
I4
I3
I2
I1
I0
default
1
1
1
1
1
1
1
1
Table 3. Register 1 – Output Port Register
bit
O7
O6
O5
O4
O3
O2
O1
O0
default
1
1
1
1
1
1
1
1
Table 4. Register 2 – Polarity Inversion Register
REGISTERS AND BUS TRANSACTIONS
bit
N7
N6
N5
N4
N3
N2
N1
N0
default
0
0
0
0
0
0
0
0
Table 5. Register 3 – Configuration Register
The CAT9554/9554A consist of an input port register,
an output port register, a polarity inversion register
and a configuration register. Table 1 shows the
register address table. Tables 2 to 5 list Register 0
through Register 3 information.
bit
C7
C6
C5
C4
C3
C2
C1
C0
default
1
1
1
1
1
1
1
1
Table 1. Register Command Byte
Command
(hex)
0x00
Protocol
Function
Read byte
Input port register
0x01
Read/write byte
Output port register
0x02
Read/write byte
Polarity inversion register
0x03
Read/write byte
Configuration register
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP
ACK DELAY
Figure 8. Acknowledge Timing
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
9
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
The output port register sets the outgoing logic levels
of the I/O ports, defined as outputs by the
configuration register. Bit values in this register have
no effect on I/O pins defined as inputs. Reads from
the output port register reflect the value that is in the
flip-flop controlling the output, not the actual I/O
pin value.
the corresponding port pin as an input with a high
impedance output driver. If a bit in this register is
cleared, the corresponding port pin is enabled as an
output. At power-up, the I/Os are configured as inputs
with a weak pull-up resistor to VCC.
Data is transmitted to the CAT9554/9554A registers
using the write mode shown in Figure 9 and Figure 10.
The polarity inversion register allows the user to invert
the polarity of the input port register data. If a bit in
this register is set (“1”) the corresponding input port
data is inverted. If a bit in the polarity inversion
register is cleared (“0”), the original input port polarity
is retained.
The CAT9554/9554A registers are read according to
the timing diagrams shown in Figure 11 and Figure
12. Once a command byte has been sent, the register
which was addressed will continue to be accessed by
reads until a new command byte will be sent.
The configuration register sets the directions of the
ports. Set the bit in the configuration register to enable
1
SCL
2
3
4
5
6
7
slave address
SDA
S
0
1
0
0
8
9
command byte
R/W
A2 A1 A0
0
A
0
0
0
0
0
0
1
A
DATA 1
acknowledge from slave
acknowledge
from slave
start condition
0
data to port
A
acknowledge from slave
P
stop
condition
WRITE TO
PORT
DATA OUT
FROM PO RT
DATA 1 VALID
tpv
Figure 9. Write to Output Port Register
1
SCL
2
3
4
5
6
7
slave address
SDA
S
0
1
start condition
0
0
A2 A1 A0
8
9
command byte
R/W
0
acknowledge
from slave
A
0
0
0
0
0
0
data to register
1 1/0
acknowledge from slave
A
DATA 1
acknowledge from slave
A
P
stop
condition
WRITE TO
REGISTER
Figure 10. Write to Configuration or Polarity Inversion Register
Doc. No. MD-9002 Rev. F
10
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT9554, CAT9554A
POWER-ON RESET OPERATION
When the power supply is applied to VCC pin, an
internal
power-on
reset
pulse
holds
the
CAT9554/9554A in a reset state until VCC reaches
VPOR level. At this point, the reset condition is released
slave address
S
0
1
0
and the internal state machine and the
CAT9554/9554A registers are initialized to their
default state.
slave address
R/W
0 A2 A1 A0
0
A
A
COMMAND BYTE
S
0
1
acknowledge from slave
acknowledge from slave
0
0
R/W
acknowledge
from master
data from register
DATA
A2 A1 A0 1 A
acknowledge from slave
A
first byte
At this moment master-transmitter becomes
master-receiver and slave-receiver
becomes slave-transmitter
no acknowledge
from master
data from register
DATA
NA
P
last byte
Figure 11. Read from Register
1
SCL
2
3
4
5
6
7
8
slave address
SDA
S
0
1
0
0
9
A2 A1 A0
1
A
DATA 1
A
acknowledge
from slave
start condition
data from port
data from port
R/W
acknowledge
from master
DATA 4
NA
no acknowledge
from master
P
stop
condition
READ FROM
PORT
DATA INTO
PORT
DATA 3
DATA 2
DATA 1
tPH
DATA 4
tPS
INT
tIV
tIR
Figure 12. Read Input Port Register
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
11
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
PACKAGE OUTLINE DRAWINGS
SOIC 16-Lead 150mils (W)
(1) (2)
E1
SYMBOL
MIN
E
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
D
9.80
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
PIN#1 IDENTIFICATION
NOM
0.25
9.90
10.00
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
θ
A
e
b
A1
SIDE VIEW
c
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-012
Doc. No. MD-9002 Rev. F
12
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT9554, CAT9554A
TSSOP 16-Lead 4.4mm (Y)
(1) (2)
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
c
0.13
0.20
D
4.90
5.10
E
6.30
6.50
E1
4.30
4.50
e
0.65 BSC
L
1.00 REF
L1
0.45
0.75
θ1
0°
8°
e
PIN#1
IDENTIFICATION
TOP VIEW
D
A2
A
c
θ1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-153.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
13
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
TQFN 16-Pad 4 x 4mm (HV4)
(1) (2)
A
D
DETAIL A
E2
E
PIN#1 ID
PIN#1 INDEX AREA
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
BOTTOM VIEW
e
b
0.20 REF
b
0.25
0.30
0.35
D
3.90
4.00
4.10
D2
2.00
–
2.25
E
3.90
4.00
4.10
E2
2.00
–
2.25
e
L
D2
A1
L
DETAIL A
A
0.65 BSC
0.45
–
0.65
A3
A1
FRONT VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-220.
Doc. No. MD-9002 Rev. F
14
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT9554, CAT9554A
EXAMPLE OF ORDERING INFORMATION (1)
Prefix
Device #
Suffix
CAT
9554
W
Optional
Company ID
Product
Number
Package
W: SOIC
Y: TSSOP
HV4: TQFN
9554
9554A
I
-G
T2
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Tape & Reel
T: Tape & Reel
2: 2,000/Reel
Temperature Range
I = Industrial (-40ºC to 85ºC)
ORDERING PART NUMBER
Part Number
Package
Lead Finish
CAT9554WI-G
SOIC
NiPdAu
CAT9554WI-GT2
SOIC
CAT9554YI-G
Part Number
Package
Lead Finish
CAT9554AWI-G
SOIC
NiPdAu
NiPdAu
CAT9554AWI-GT2
SOIC
NiPdAu
TSSOP
NiPdAu
CAT9554AYI-G
TSSOP
NiPdAu
CAT9554YI-GT2
TSSOP
NiPdAu
CAT9554AYI-GT2
TSSOP
NiPdAu
CAT9554HV4I-G
TQFN
NiPdAu
CAT9554AHV4I-G
TQFN
NiPdAu
CAT9554HV4I-GT2
TQFN
NiPdAu
CAT9554AHV4I-GT2
TQFN
NiPdAu
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT9554WI-GT2 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel).
(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
15
Doc. No. MD-9002, Rev. F
CAT9554, CAT9554A
REVISION HISTORY
Date
08-Jul-05
28-Jun-06
Revision
A
B
Description
Initial Issue
Update Features
Add Applications
Update Descriptions
Update Pin Description
Table Update Absolute Maximum Ratings
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update A.C. Test Conditions
Update Pin Description
Update Figure 2, Figure 4, Figure 5, Figure 8 and Figure 12
Update Functional Description
Update Package Drawings
Update Ordering Information
Update Package Outline Drawings
Update Example of Ordering Information
Update Ordering Part Number Change Document number from 25088
Delete TQFN package in Matte-Tin.
Update Package Outline Drawing - TQFN 16-Pad 4 x 4mm
21-Jan-08
C
24-Apr-08
D
02-June-08
E
Update Package Outline Drawing - TQFN 16-Pad 4 x 4mm
01-Dec-08
F
Update A.C. Characteristics table to include Standard I2C and Fast I2C.
Change logo and fine print to ON Semiconductor
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operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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Doc. No. MD-9002, Rev. F
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16
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© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
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