PD - 97475A
IRFI4410ZPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
VDSS
RDS(on) typ.
max.
ID
100V
7.9m:
9.3m:
43A
D
D
G
G
S
D
S
TO-220AB Full-Pak
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
A
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
43
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
30
IDM
Pulsed Drain Current c
170
PD @TC = 25°C
Maximum Power Dissipation
47
W
Linear Derating Factor
0.3
±30
W/°C
V
EAS (Thermally limited)
Gate-to-Source Voltage
Single Pulse Avalanche Energy d
310
mJ
TJ
Operating Junction and
-55 to + 175
°C
TSTG
Storage Temperature Range
VGS
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
RθJC
Junction-to-Case f
–––
3.2
°C/W
RθJA
Junction-to-Ambient f
–––
65
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1
4/19/11
IRFI4410ZPbF
Static @ T J = 25°C (unless otherwise specified)
Symbol
Param eter
Min. Typ. Max. Units
Conditions
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
100
–––
–––
2.0
–––
–––
–––
–––
–––
95
7.9
–––
–––
–––
–––
–––
–––
V VGS = 0V, ID = 250μA
––– mV/°C Reference to 25°C, ID = 5mA
9.3
m
VGS = 10V, ID = 26A
4.0
V VDS = VGS, I D = 150μA
20
μA VDS = 100V, V GS = 0V
VDS = 100V, V GS = 0V, TJ = 125°C
250
100
nA VGS = 20V
-100
VGS = -20V
Internal Gate Resistance
–––
0.9
–––
V( BR)DSS
V(BR)DSS/ T J
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
RG(int)
e
e
Dynamic @ T J = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Param eter
Min. Typ. Max. Units
80
–––
–––
–––
–––
81
18
23
–––
110
–––
–––
S
nC
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related) –––
–––
Coss eff. (TR) Effective Output Capacitance (Time Related)
15
27
43
30
4910
330
150
420
–––
–––
–––
–––
–––
–––
–––
–––
ns
680
–––
td( on)
tr
td( off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
pF
Conditions
VDS = 50V, ID = 26A
ID = 26A
VDS = 50V
VGS = 10V
VDD = 65V
ID = 26A
RG = 2.7
VGS = 10V
VGS = 0V
VDS = 50V
e
e
ƒ = 1.0MHz
VGS = 0V, V DS = 0V to 80V
VGS = 0V, V DS = 0V to 80V
h, See Fig.11
g
Diode Characteristics
Symbol
IS
Parameter
VSD
trr
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
c
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.91mH
RG = 25Ω, IAS = 26A, VGS =10V. Part not recommended for use
above this value.
2
Min. Typ. Max. Units
–––
–––
Conditions
MOSFET symbol
showing the
–––
––– 170
A integral reverse
G
p-n junction diode.
–––
–––
1.3
V TJ = 25°C, IS = 26A, V GS = 0V
–––
47
71
ns TJ = 25°C
V R = 85V,
–––
54
81
TJ = 125°C
IF = 26A
di/dt = 100A/μs
–––
110 160
nC TJ = 25°C
–––
140 210
TJ = 125°C
–––
2.5
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
43
A
e
D
S
e
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Rθ is measured at TJ approximately 90°C
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
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IRFI4410ZPbF
ID, Drain-to-Source Current (A)
TOP
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
1000
≤60μs PULSE WIDTH
Tj = 25°C
100
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
ID, Drain-to-Source Current (A)
1000
BOTTOM
100
4.5V
4.5V
≤60μs PULSE WIDTH
Tj = 175°C
10
10
0.1
1
10
100
0.1
100
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
VDS, Drain-to-Source Voltage (V)
1000
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 50V
≤60μs PULSE WIDTH
0.1
ID = 26A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
2
3
4
5
6
-60 -40 -20 0 20 40 60 80 100120140160180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
8000
16
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
6000
C, Capacitance (pF)
1
VDS, Drain-to-Source Voltage (V)
Ciss
4000
2000
Coss
Crss
0
1
VDS = 80V
VDS = 50V
12
VDS = 20V
8
4
0
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 26A
0
20
40
60
80
100
120
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFI4410ZPbF
1000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
TJ = 175°C
10
TJ = 25°C
1
VGS = 0V
0.5
1.0
100
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
20
10
0
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
ID , Drain Current (A)
30
125
1000
Id = 5mA
125
120
115
110
105
100
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
1400
EAS, Single Pulse Avalanche Energy (mJ)
2.0
1.5
Energy (μJ)
100
130
TC , CaseTemperature (°C)
1.0
0.5
0.0
ID
8.6A
14A
BOTTOM 26A
1200
TOP
1000
800
600
400
200
0
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
10
Fig 8. Maximum Safe Operating Area
40
100
1
VDS , Drain-toSource Voltage (V)
50
75
DC
1.5
Fig 7. Typical Source-Drain Diode
Forward Voltage
50
1msec
10
VSD , Source-to-Drain Voltage (V)
25
100μsec
0.1
0.1
0.0
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFI4410ZPbF
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
R1
R1
τJ
0.02
0.01
τJ
τ1
R2
R2
R3
R3
R4
R4
τC
τ2
τ1
τ3
τ2
τ4
τ3
τ4
Ci= τi/Ri
Ci i/Ri
0.01
τ
Ri (°C/W) τι (sec)
0.117574 0.000176
1.337531 0.7389
1.260992 0.103059
0.508931 0.008379
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Avalanche Current (A)
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
320
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 26A
240
160
80
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFI4410ZPbF
16
ID = 1.0A
4.0
ID = 1.0mA
14
3.5
ID = 150μA
12
ID = 250μA
10
3.0
IRR (A)
VGS(th) Gate threshold Voltage (V)
4.5
2.5
8
6
2.0
IF = 17A
VR = 85V
TJ = 25°C
4
1.5
2
1.0
-75
-50 -25
0
25
50
75
TJ = 125°C
0
100 125 150 175
100
200
300
TJ , Temperature ( °C )
400
500
600
700
diF /dt (A/μs)
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
16
350
14
300
12
250
QRR (A)
IRR (A)
10
8
6
IF = 26A
VR = 85V
TJ = 25°C
4
2
200
150
IF = 17A
VR = 85V
100
TJ = 25°C
TJ = 125°C
50
TJ = 125°C
0
0
100
200
300
400
500
600
700
100
200
diF /dt (A/μs)
300
400
500
600
700
diF /dt (A/μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
350
300
QRR (A)
250
200
150
IF = 26A
VR = 85V
100
TJ = 25°C
TJ = 125°C
50
0
100
200
300
400
500
600
700
diF /dt (A/μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFI4410ZPbF
D.U.T
Driver Gate Drive
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
tp
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD
Fig 22b. Unclamped Inductive Waveforms
VDS
VDS
+
90%
VDD -
10%
D.U.T
VGS
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
Fig 23a. Switching Time Test Circuit
tr
td(off)
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
1K
VCC
Vgs(th)
Qgs1 Qgs2
Fig 24a. Gate Charge Test Circuit
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Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFI4410ZPbF
TO-220AB Full-Pak Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Full-Pak Part Marking Information
EXAMPLE: T HIS IS AN IRFI840G
WIT H AS S EMBLY
LOT CODE 3432
AS S EMBLED ON WW 24, 2001
IN T HE AS S EMBLY LINE "K"
Note: "P" in as s embly line pos ition
indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
IRFI840G
124K
34
32
DAT E CODE
YEAR 1 = 2001
WEEK 24
LINE K
TO-220AB Full-Pak packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/11
8
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