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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), MSP430FR682x(1)
Mixed‑‑Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16-MHz Clock
– Wide Supply Voltage Range (1.8 V to 3.6 V) (1)
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 100 µA/MHz
– Standby (LPM3 With VLO): 0.4 µA (Typical)
– Real-Time Clock (RTC) (LPM3.5):
0.35 µA (Typical) (2)
– Shutdown (LPM4.5): 0.04 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM)
– Up to 64KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns per Word (64KB in 4 ms)
– Unified Memory = Program + Data + Storage in
One Single Space
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– Three-Channel Internal Direct Memory Access
(DMA)
– RTC With Calendar and Alarm Functions
– Five 16-Bit Timers With up to Seven
Capture/Compare Registers
– 16-Bit and 32-Bit Cyclic Redundancy Checker
(CRC16, CRC32)
• High-Performance Analog
– Up to 8-Channel Analog Comparator
– 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference and Sample-and-Hold and
up to 8 External Input Channels
– Integrated 116-Segment LCD Driver With
Contrast Control
• Code Security and Encryption
– 128-Bit or 256-Bit AES Security Encryption and
Decryption Coprocessor (MSP430FR69xx(1)
Only)
(1)
(2)
Minimum supply voltage is restricted by SVS levels.
The RTC is clocked by a 3.7-pF crystal.
•
•
•
•
•
•
– True Random Number Seed for Random
Number Generation Algorithm
– Lockable Memory Segments for IP
Encapsulation and Secure Storage
Multifunction Input/Output Ports
– All I/O Pins Support Capacitive Touch Capability
Without Need for External Components
– Accessible Bit-, Byte- and Word-Wise (in Pairs)
– Edge-Selectable Wakeup From LPM on Ports
P1, P2, P3, and P4
– Programmable Pullup and Pulldown on All Ports
Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support:
• UART With Automatic Baud-Rate Detection
• IrDA Encode and Decode
• SPI at Rates up to 10 Mbps
– eUSCI_B0 and eUSCI_B1 Support:
• I2C With Multiple-Slave Addressing
• SPI at Rates up to 10 Mbps
Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
Development Tools and Software
– Free Professional Development Environments
With EnergyTrace++™ Technology for Power
Profiling and Debugging
– Microcontroller Development Boards Available
Family Members
– Section 3 Summarizes the Available Variants
and Packages
For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, and MSP430FR69xx Family
User's Guide (SLAU367)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
1.2
•
•
•
www.ti.com
Applications
Heat Cost Allocators
Utility Meters – Electricity, Water, and Gas
Thermostats
1.3
•
•
•
Portable Medical Equipment
Sensor Management
Weigh Scales
Description
This ultra-low-power MSP430FRxx FRAM microcontroller family consists of several devices featuring
embedded nonvolatile FRAM, a 16-bit CPU, and different sets of peripherals targeted for various
applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are
optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new
nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash, all at lower total power consumption.
Device Information (1)
PACKAGE
BODY SIZE (2)
MSP430FR6972IPMR
LQFP (64)
10 mm × 10 mm
MSP430FR6972IRGC
VQFN (64)
9 mm × 9 mm
MSP430FR6922IG56
TSSOP (56)
6.1 mm × 14 mm
PART NUMBER
(1)
(2)
2
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
1.4
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
LFXIN/
HFXIN
P1.x,P2.x P3.x,P4.x P5.x,P6.x
up to
up to
up to
2x8
2x8
2x8
LFXOUT/
HFXOUT
P7.x
up to
1x8
P9.x
up to
1x8
PJ.x
up to
1x8
Capacitive Touch IO 0, Capacitive Touch IO 1
MCLK
Clock
System
Comp_E
ADC12_B
(up to 16
inputs)
(up to 16
std. inputs,
up to 8
diff. inputs)
SMCLK
DMA
Controller
3 Channel
Bus
Control
Logic
MAB
I/O Port
P5, P6
2x8 I/Os
I/O Port
P7
1x8 I/Os
I/O Port
P9
1x8 I/Os
PC
PB
PA
1x16 I/Os 1x16 I/Os 1x16 I/Os
PD
1x8 I/Os
PE
1x8 I/Os
I/O Ports
P1, P2
2x8 I/Os
REF_A
ACLK
Voltage
Reference
I/O Ports
P3, P4
2x8 I/Os
I/O Port
PJ
1x8 I/Os
MAB
MDB
CPUXV2
incl. 16
Registers
MPU
IP Encap
MDB
FRAM
64KB
32KB
EEM
(S: 3+1)
CRC16
Power
Mgmt
RAM
2KB
Tiny RAM
26B
LDO
SVS
Brownout
TA2
TA 3
Timer_A
Timer_A
2 CC
Registers
(int. only)
5 CC
Registers
AES256
CRC-16CCITT
CRC32
MPY32
Watchdog
Security
En-/Decryption
(128/256)
CRC-32ISO-3309
MDB
JTAG
Interface
MAB
Spy-BiWire
TB0
TA0
TA1
RTC_C
Calendar
RTC
_A
and
Counter
Mode
Timer_B
Timer_A
Timer_A
7 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
(UART,
IrDA,
SPI)
(I2C,
SPI)
LCD_C
(up to
RTC
_A
116 seg;
static,
2 to 4 mux)
LPM3.5 Domain
NOTE: AES256 is not implemented in the MSP430FR682x, MSP430FR687x, MSP430FR682x1, and MSP430FR687x1
devices.
NOTE: HFXIN and HFOUT are not implemented in the MSP430FR692x, MSP430FR682x, MSP430FR692x1, and
MSP430FR682x1 devices.
Figure 1-1. Functional Block Diagram
Device Overview
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
3
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
Device Overview ......................................... 1
1.2
Applications ........................................... 2
6.1
Overview
1.3
Description ............................................ 2
6.2
CPU
1.4
Functional Block Diagram ............................ 3
6.3
Revision History ......................................... 5
Device Comparison ..................................... 6
Terminal Configuration and Functions .............. 8
6.4
4.1
Pin Diagrams ......................................... 8
6.7
4.2
Pin Attributes ........................................ 11
6.8
4.3
Signal Descriptions .................................. 17
6.9
6.10
71
Memory Protection Unit (MPU) Including IP
Encapsulation ....................................... 71
26
6.11
Peripherals
26
6.12
Device Descriptors (TLV) .......................... 109
26
6.13
Memory
26
6.14
Identification........................................ 128
.....................................
4.5
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings .........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
Pin Multiplexing
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
4
Timing and Switching Characteristics ............... 35
Features .............................................. 1
4.4
5
5.13
1.1
Active Mode Supply Current Into VCC Excluding
External Current ....................................
Typical Characteristics - Active Mode Supply
Currents .............................................
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................
Low-Power Mode LPM2, LPM3, LPM4 Supply
Currents (Into VCC) Excluding External Current ....
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current ....................
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
Typical Characteristics, Current Consumption per
Module ..............................................
Thermal Characteristics
Table of Contents
............................
6
Detailed Description ................................... 64
6.5
6.6
25
25
7
27
28
8
29
31
32
33
34
34
9
..........................................
............................................
64
64
65
67
70
70
71
71
72
112
Applications, Implementation, and Layout ...... 129
7.1
7.2
28
............................................
.................................................
Operating Modes ....................................
Interrupt Vector Table and Signatures ..............
Bootstrap Loader (BSL) .............................
JTAG Operation .....................................
FRAM................................................
RAM .................................................
Tiny RAM ............................................
Device Connection and Layout Fundamentals .... 129
Peripheral- and Interface-Specific Design
Information ......................................... 133
Device and Documentation Support .............. 136
8.1
Device Support..................................... 136
8.2
Documentation Support ............................ 139
8.3
Related Links
8.4
Community Resources............................. 140
8.5
Trademarks ........................................ 141
8.6
Electrostatic Discharge Caution
8.7
Export Control Notice .............................. 141
8.8
Glossary............................................ 141
......................................
...................
139
141
Mechanical, Packaging, and Orderable
Information ............................................. 141
9.1
Packaging Information ............................. 141
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from April 28, 2015 to May 1, 2015
•
Page
Removed 48KB FRAM option from Figure 1-1, Functional Block Diagram ................................................... 3
Revision History
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
5
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
3 Device Comparison
Table 3-1 and Table 3-2 summarize the available family members.
Table 3-1. Device Comparison – Family Members With UART BSL
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
Timer_A (1)
Timer_B (2)
MSP430FR6972
64
2
DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6) (7)
MSP430FR6872
64
2
DCO
HFXT
LFXT
MSP430FR6970
32
2
MSP430FR6870
32
MSP430FR6922
eUSCI
AES
ADC12_B
LCD_C
I/O
PACKAGE
TYPE
2
yes
8 ext
112 seg
51
64 PM
64 RGC
2
2
no
8 ext
112 seg
51
64 PM
64 RGC
7
2
2
yes
8 ext
112 seg
51
64 PM
64 RGC
3, 3 (5)
2, 5 (6) (7)
7
2
2
no
8 ext
112 seg
51
64 PM
64 RGC
DCO
LFXT
3, 3 (5)
2, 5 (6) (7)
7
2
2
yes
8 ext
116 seg
100 seg
(DGG)
52
46 (DGG)
64 PM
64 RGC
56 DGG
2
DCO
LFXT
3, 3 (5)
2, 5 (6) (7)
7
2
2
no
8 ext
116 seg
100 seg
(DGG)
52
46 (DGG)
64 PM
64 RGC
56 DGG
32
2
DCO
LFXT
3, 3 (5)
2, 5 (6) (7)
7
2
2
yes
8 ext
116 seg
100 seg
(DGG)
52
46 (DGG)
64 PM
64 RGC
56 DGG
32
2
DCO
LFXT
3, 3 (5)
2, 5 (6) (7)
7
2
2
no
8 ext
116 seg
100 seg
(DGG)
52
46 (DGG)
64 PM
64 RGC
56 DGG
A (3)
B (4)
7
2
3, 3 (5)
2, 5 (6) (7)
7
DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6) (7)
2
DCO
HFXT
LFXT
64
2
MSP430FR6822
64
MSP430FR6920
MSP430FR6820
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).
Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR692x(1) and FR682x(1) with RGC and PM packages. For FR692x(1) and
FR682x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).
Device Comparison
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 3-2. Device Comparison – Family Members With I2C BSL
(1)
(2)
(3)
(4)
(5)
(6)
(7)
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
Timer_A (1)
Timer_B (2)
MSP430FR69721
64
2
DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6) (7)
MSP430FR68721
64
2
DCO
HFXT
LFXT
MSP430FR69221
64
2
MSP430FR68221
64
2
eUSCI
AES
ADC12_B
LCD_C
I/O
PACKAGE
TYPE
2
yes
8 ext
112 seg
51
64 PM
64 RGC
2
2
no
8 ext
112 seg
51
64 PM
64 RGC
7
2
2
yes
8 ext
116 seg
100 seg
(DGG)
52
46 (DGG)
64 PM
64 RGC
56 DGG
7
2
2
no
8 ext
116 seg
100 seg
(DGG)
52
46 (DGG)
64 PM
64 RGC
56 DGG
A (3)
B (4)
7
2
3, 3 (5)
2, 5 (6) (7)
7
DCO
LFXT
3, 3 (5)
2, 5 (6) (7)
DCO
LFXT
3, 3 (5)
2, 5 (6) (7)
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).
Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR692x(1) and FR682x(1) with RGC and PM packages. For FR692x(1) and
FR682x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Device Comparison
7
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
AVCC1
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS2
P5.4/UCA1SIMO/UCA1TXD/S11
P5.5/UCA1SOMI/UCA1RXD/S10
P5.6/UCA1CLK/S9
P5.7/UCA1STE/TB0CLK/S8
P4.4/UCB1STE/TA1CLK/S7
P4.5/UCB1CLK/TA1.0/S6
P4.6/UCB1SIMO/UCB1SDA/TA1.1/S5
P4.7/UCB1SOMI/UCB1SCL/TA1.2/S4
DVSS3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
DVCC3
Figure 4-1 show the pin assignments for the 64-pin PM and RGC packages of the MSP430FR692x(1) and
MSP430FR682x(1).
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
1
48
P9.7/A15/C15
P1.4/UCB0CLK/UCA0STE/TA1.0/S3
2
47
P9.6/A14/C14
P1.5/UCB0STE/UCA0CLK/TA0.0/S2
3
46
P9.5/A13/C13
P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1
4
45
P9.4/A12/C12
P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0
5
44
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
R33/LCDCAP
6
43
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P6.0/R23
7
42
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P6.1/R13/LCDREF
8
41
P1.3/TA1.2/A3/C3
P6.2/COUT/R03
9
40
DVCC2
P6.3/COM0
10
39
DVSS2
P6.4/TB0.0/COM1/S31
11
38
P7.4/SMCLK/S12
P6.5/TB0.1/COM2/S30
12
37
P7.3/TA0.2/S13
P6.6/TB0.2/COM3/S29
13
36
P7.2/TA0.1/S14
P3.0/UCB1CLK/S28
14
35
P7.1/TA0.0/S15
P3.1/UCB1SIMO/UCB1SDA/S27
15
34
P7.0/TA0CLK/S16
P3.2/UCB1SOMI/UCB1SCL/S26
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S17
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S18
P2.2/UCA0CLK/TB0.4/RTCCLK/S19
P2.3/UCA0STE/TB0OUTH/S20
P3.7/UCA1STE/TB0.3/S21
P3.6/UCA1CLK/TB0.2/S22
P3.5/UCA1SOMI/UCA1RXD/TB0.1/S23
P3.4/UCA1SIMO/UCA1TXD/TB0.0/S24
P3.3/TA1.1/TB0CLK/S25
PJ.3/TCK/COUT/SRCPUOFF
PJ.2/TMS/ACLK/SROSCOFF
PJ.1/TDI/TCLK/MCLK/SRSCG0
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
TEST/SBWTCK
RST/NMI/SBWTDIO
DVSS1
DVCC1
MSP430FR692xPM/RGC
MSP430FR682xPM/RGC
On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
Figure 4-1. 64-Pin PM and RGC Packages (Top View), MSP430FR692x(1) MSP430FR682x(1)
8
Terminal Configuration and Functions
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
AVCC1
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
PJ.7/HFXOUT
AVSS2
AVSS3
PJ.6/HFXIN
P5.7/UCA1STE/TB0CLK/S10
P4.4/UCB1STE/TA1CLK/S9
P4.5/UCB1CLK/TA1.0/S8
P4.6/UCB1SIMO/UCB1SDA/TA1.1/S7
P4.7/UCB1SOMI/UCB1SCL/TA1.2/S6
DVSS3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK/S5
DVCC3
Figure 4-2 shows the pin assignments for the 64-pin PM and RGC packages of the MSP430FR697x(1)
and MSP430FR687x(1).
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P4.3/UCA0SOMI/UCA0RXD/UCB1STE/S4
1
48
P9.7/A15/C15
P1.4/UCB0CLK/UCA0STE/TA1.0/S3
2
47
P9.6/A14/C14
P1.5/UCB0STE/UCA0CLK/TA0.0/S2
3
46
P9.5/A13/C13
P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1
4
45
P9.4/A12/C12
P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0
5
44
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
R33/LCDCAP
6
43
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P6.0/R23
7
42
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P6.1/R13/LCDREF
8
41
P1.3/TA1.2/A3/C3
P6.2/COUT/R03
9
40
DVCC2
P6.3/COM0
10
39
DVSS2
P6.4/TB0.0/COM1/S30
11
38
P7.4/SMCLK/S11
P6.5/TB0.1/COM2/S29
12
37
P7.3/TA0.2/S12
P6.6/TB0.2/COM3/S28
13
36
P7.2/TA0.1/S13
P3.0/UCB1CLK/TA3.2/S27
14
35
P7.1/TA0.0/S14
P3.1/UCB1SIMO/UCB1SDA/TA3.3/S26
15
34
P7.0/TA0CLK/S15
P3.2/UCB1SOMI/UCB1SCL/TA3.4/S25
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S16
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S17
P2.2/UCA0CLK/TB0.4/RTCCLK/S18
P3.7/UCA1STE/TB0.3/S20
P2.3/UCA0STE/TB0OUTH/S19
P3.6/UCA1CLK/TB0.2/S21
P3.5/UCA1SOMI/UCA1RXD/TB0.1/S22
P3.4/UCA1SIMO/UCA1TXD/TB0.0/S23
P3.3/TA1.1/TB0CLK/S24
PJ.3/TCK/COUT/SRCPUOFF
PJ.2/TMS/ACLK/SROSCOFF
PJ.1/TDI/TCLK/MCLK/SRSCG0
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
TEST/SBWTCK
RST/NMI/SBWTDIO
DVSS1
DVCC1
MSP430FR697xPM/RGC
MSP430FR687xPM/RGC
On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
Figure 4-2. 64-Pin PM and RGC Packages (Top View) – MSP430FR697x(1), MSP430FR687x(1)
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
9
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Figure 4-3 shows the pin assignments for the 56-pin DGG package of the MSP430FR692x(1) and
MSP430FR682x(1) devices.
P4.4/UCB1STE/TA1CLK/S7
P4.5/UCB1CLK/TA1.0/S6
P4.6/UCB1SIMO/UCB1SDA/TA1.1/S5
P4.7/UCB1SOMI/UCB1SCL/TA1.2/S4
DVSS3
DVCC3
P1.4/UCB0CLK/UCA0STE/TA1.0/S3
P1.5/UCB0STE/UCA0CLK/TA0.0/S2
P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1
P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0
R33/LCDCAP
P6.0/R23
P6.1/R13/LCDREF
P6.2/COUT/R03
P6.3/COM0
P6.4/TB0.0/COM1/S27
P6.5/TB0.1/COM2/S26
P6.6/TB0.2/COM3/S25
P3.0/UCB1CLK/TA3.2/S24
P3.1/UCB1SIMO/UCB1SDA/TA3.3/S23
P3.2/UCB1SOMI/UCB1SCL/TA3.4/S22
TEST/SBWTCK
RST /NMI/SBWTDIO
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
PJ.1/TDI/TCLK/MCLK/SRSCG0
PJ.2/TMS/ACLK/SROSCOFF
PJ.3/TCK/COUT/SRCPUOFF
P3.3/TA1.1/TB0CLK/S21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MSP430FR692xG56
MSP430FR682xG56
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
AVSS2
PJ.5/LFXOUT
PJ.4/LFXIN
AVSS1
AVCC1
P9.7/A15/C15
P9.6/A14/C14
P9.5/A13/C13
P9.4/A12/C12
P1.0/TA0.1/RTCCLK/DMAE0/A0/C0/VREF-/VeREFP1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/A3/C3
DVCC2
DVSS2
P7.4/SMCLK/S8
P7.3/TA0.2/S9
P7.2/TA0.1/S10
P7.1/TA0.0/S11
P7.0/TA0CLK/S12
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S13
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S14
P2.2/UCA0CLK/TB0.4/RTCCLK/S15
P2.3/UCA0STE/TB0OUTH/S16
P3.7/UCA1STE/TB0.3/S17
P3.6/UCA1CLK/TB0.2/S18
P3.5/UCA1SOMI/UCA1RXD/TB0.1/S19
P3.4/UCA1SIMO/UCA1TXD/TB0.0/S20
On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
Figure 4-3. 56-Pin DGG Package (Top View) – MSP430FR692x(1), MSP430FR682x(1)
10
Terminal Configuration and Functions
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
4.2
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Pin Attributes
Table 4-1 lists the attributes of each pin.
Table 4-1. Pin Attributes
FR697x(1),
FR687x(1)
FR692x(1), FR682x(1)
PM, RGC
PIN
NO.
DGG
LCD
SEG
PIN
NO.
PM, RGC
LCD
SEG
1
2
3
4
5
6
7
(1)
(2)
(3)
(4)
(5)
(6)
PIN
NO.
1
S3
S2
S1
S0
7
8
9
10
11
12
S3
S2
S1
S0
2
3
4
5
6
7
SIGNAL
TYPE (4)
BUFFER
TYPE (5)
POWER
SOURCE
RESET
STATE
AFTER
BOR (6)
P4.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SOMI
I/O
LVCMOS
DVCC
-
UCA0RXD
I
LVCMOS
DVCC
-
UCB1STE
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
-
UCA0STE
I/O
LVCMOS
DVCC
-
TA1.0
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
-
UCA0CLK
I/O
LVCMOS
DVCC
-
TA0.0
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
-
UCB0SDA
I/O
LVCMOS
DVCC
-
SIGNAL NAME (1)
(2) (3)
LCD
SEG
S4
S3
S2
S1
S0
BSL_DAT
I
LVCMOS
DVCC
-
TA0.1
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
-
UCB0SCL
I/O
LVCMOS
DVCC
-
BSL_CLK
I
LVCMOS
DVCC
-
TA0.2
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
R33
I/O
Analog
DVCC
-
LCDCAP
I/O
Analog
DVCC
-
P6.0 (RD)
I/O
LVCMOS
DVCC
OFF
R23
I/O
Analog
DVCC
-
Signals names with (RD) denote the reset default pin name.
To determine the pin mux encodings for each pin, refer to the Port I/O Schematics section.
Sz = The LCD segment that is assigned to each pin can vary by package – see the "LCD SEG" columns for the assignment on this pin.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
11
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 4-1. Pin Attributes (continued)
FR697x(1),
FR687x(1)
FR692x(1), FR682x(1)
PM, RGC
PIN
NO.
DGG
LCD
SEG
8
13
14
15
16
S30
S29
S28
S27
S26
16
17
18
19
20
21
10
S27
S26
S25
S24
S23
S22
11
12
13
14
15
16
BUFFER
TYPE (5)
POWER
SOURCE
RESET
STATE
AFTER
BOR (6)
P6.1 (RD)
I/O
LVCMOS
DVCC
OFF
R13
I/O
Analog
DVCC
-
LCDREF
I
Analog
-
-
P6.2 (RD)
I/O
LVCMOS
DVCC
OFF
COUT
O
LVCMOS
DVCC
-
R03
I/O
Analog
DVCC
-
P6.3 (RD)
I/O
LVCMOS
DVCC
OFF
(2) (3)
LCD
SEG
9
15
S31
PIN
NO.
8
14
10
12
PM, RGC
LCD
SEG
13
9
11
PIN
NO.
SIGNAL
TYPE (4)
SIGNAL NAME (1)
S30
S29
S28
S27
S26
S25
COM0
O
Analog
DVCC
-
P6.4 (RD)
I/O
LVCMOS
DVCC
OFF
TB0.0
I/O
LVCMOS
DVCC
-
COM1
O
Analog
DVCC
-
Sz
O
Analog
DVCC
-
P6.5 (RD)
I/O
LVCMOS
DVCC
OFF
TB0.1
I/O
LVCMOS
DVCC
-
COM2
O
Analog
DVCC
-
Sz
O
Analog
DVCC
-
P6.6 (RD)
I/O
LVCMOS
DVCC
OFF
TB0.2
I/O
LVCMOS
DVCC
-
COM3
O
Analog
DVCC
-
Sz
O
Analog
DVCC
-
P3.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
-
TA3.2
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P3.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
-
UCB1SDA
I/O
LVCMOS
DVCC
-
TA3.3
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P3.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
-
UCB1SCL
I/O
LVCMOS
DVCC
-
TA3.4
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
N/A
17
17
DVSS1
P
Power
-
18
18
DVCC1
P
Power
-
N/A
TEST
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
-
RST
I
LVCMOS
DVCC
OFF
NMI
I
LVCMOS
DVCC
-
I/O
LVCMOS
DVCC
-
19
20
22
23
19
20
SBWTDIO
12
Terminal Configuration and Functions
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 4-1. Pin Attributes (continued)
FR697x(1),
FR687x(1)
FR692x(1), FR682x(1)
PM, RGC
PIN
NO.
DGG
LCD
SEG
21
PIN
NO.
PM, RGC
LCD
SEG
24
PIN
NO.
SIGNAL
TYPE (4)
BUFFER
TYPE (5)
POWER
SOURCE
RESET
STATE
AFTER
BOR (6)
PJ.0 (RD)
I/O
LVCMOS
DVCC
OFF
TDO
O
LVCMOS
DVCC
-
TB0OUTH
I
LVCMOS
DVCC
-
SMCLK
O
LVCMOS
DVCC
-
SRSCG1
O
LVCMOS
DVCC
-
PJ.1 (RD)
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
-
TCLK
I
LVCMOS
DVCC
-
MCLK
O
LVCMOS
DVCC
-
SRSCG0
O
LVCMOS
DVCC
-
PJ.2 (RD)
SIGNAL NAME (1)
(2) (3)
LCD
SEG
21
TDI
22
25
23
26
24
25
26
27
28
29
30
22
23
27
S25
S24
S23
S22
S21
S20
28
29
30
31
32
33
24
S21
S20
S19
S18
S17
S16
25
26
27
28
29
30
S24
S23
S22
S21
S20
S19
I/O
LVCMOS
DVCC
OFF
TMS
I
LVCMOS
DVCC
-
ACLK
O
LVCMOS
DVCC
-
SROSCOFF
O
LVCMOS
DVCC
-
PJ.3 (RD)
I/O
LVCMOS
DVCC
OFF
TCK
I
LVCMOS
DVCC
-
COUT
O
LVCMOS
DVCC
-
SRCPUOFF
O
LVCMOS
DVCC
-
P3.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
-
TB0CLK
I
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P3.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SIMO
I/O
LVCMOS
DVCC
-
UCA1TXD
O
LVCMOS
DVCC
-
TB0.0
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P3.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SOMI
I/O
LVCMOS
DVCC
-
UCA1RXD
I
LVCMOS
DVCC
-
TB0.1
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P3.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1CLK
I/O
LVCMOS
DVCC
-
TB0.2
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P3.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1STE
I/O
LVCMOS
DVCC
-
TB0.3
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
-
TB0OUTH
I
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
13
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 4-1. Pin Attributes (continued)
FR697x(1),
FR687x(1)
FR692x(1), FR682x(1)
PM, RGC
PIN
NO.
31
32
DGG
LCD
SEG
S19
S18
PIN
NO.
34
35
PM, RGC
LCD
SEG
S15
S14
PIN
NO.
31
32
SIGNAL
TYPE (4)
BUFFER
TYPE (5)
POWER
SOURCE
RESET
STATE
AFTER
BOR (6)
P2.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
-
TB0.4
I/O
LVCMOS
DVCC
-
RTCCLK
O
LVCMOS
DVCC
-
SIGNAL NAME (1)
(2) (3)
LCD
SEG
S18
S17
Sz
O
Analog
DVCC
-
P2.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SOMI
I/O
LVCMOS
DVCC
-
UCA0RXD
I
LVCMOS
DVCC
-
BSL_RX
I
LVCMOS
DVCC
-
I/O
LVCMOS
DVCC
-
DMAE0
I
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SIMO
I/O
LVCMOS
DVCC
-
UCA0TXD
O
LVCMOS
DVCC
-
BSL_TX
O
LVCMOS
DVCC
-
TB0.6
I/O
LVCMOS
DVCC
-
TB0CLK
I
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P7.0 (RD)
I/O
LVCMOS
DVCC
OFF
TA0CLK
I
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P7.1 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.0
I/O
LVCMOS
DVCC
-
TB0.5
33
34
35
36
37
38
S16
S15
S14
S13
S12
36
37
38
39
40
41
S13
S12
S11
S10
S9
S8
33
34
35
36
37
38
S16
S15
S14
S13
S12
S11
Sz
O
Analog
DVCC
-
P7.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P7.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P7.4 (RD)
I/O
LVCMOS
DVCC
OFF
SMCLK
O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
N/A
39
42
39
DVSS2
P
Power
-
40
43
40
DVCC2
P
Power
-
N/A
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.2
41
14
S17
44
41
Terminal Configuration and Functions
I/O
LVCMOS
DVCC
-
A3
I
Analog
AVCC
-
C3
I
Analog
AVCC
-
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 4-1. Pin Attributes (continued)
FR697x(1),
FR687x(1)
FR692x(1), FR682x(1)
PM, RGC
PIN
NO.
42
43
44
DGG
LCD
SEG
PIN
NO.
45
46
47
LCD
SEG
PM, RGC
PIN
NO.
42
43
44
SIGNAL
TYPE (4)
BUFFER
TYPE (5)
POWER
SOURCE
RESET
STATE
AFTER
BOR (6)
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
-
TA0CLK
I
LVCMOS
DVCC
-
COUT
O
LVCMOS
DVCC
-
A2
I
Analog
AVCC
-
C2
I
Analog
AVCC
-
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.2
SIGNAL NAME (1)
(2) (3)
LCD
SEG
I/O
LVCMOS
DVCC
-
TA1CLK
I
LVCMOS
DVCC
-
COUT
O
LVCMOS
DVCC
-
A1
I
Analog
AVCC
-
C1
I
Analog
AVCC
-
VREF+
O
Analog
AVCC
-
VeREF+
I
Analog
-
-
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
-
DMAE0
I
LVCMOS
DVCC
-
RTCCLK
O
LVCMOS
DVCC
-
A0
I
Analog
AVCC
-
C0
I
Analog
AVCC
-
VREF-
O
Analog
AVCC
-
VeREF-
I
Analog
-
-
I/O
LVCMOS
DVCC
OFF
I
Analog
AVCC
-
P9.4 (RD)
45
48
45
A12
C12
P9.5 (RD)
46
49
46
A13
C13
P9.6 (RD)
47
50
47
A14
C14
51
48
Analog
AVCC
-
LVCMOS
DVCC
OFF
I
Analog
AVCC
-
I
Analog
AVCC
-
I/O
LVCMOS
DVCC
OFF
I
Analog
AVCC
-
I
Analog
AVCC
-
I/O
LVCMOS
DVCC
OFF
A15
I
Analog
AVCC
-
C15
I
Analog
AVCC
N/A
P9.7 (RD)
48
I
I/O
49
52
49
AVCC1
P
Power
-
50
53
50
AVSS1
P
Power
-
N/A
I/O
LVCMOS
DVCC
OFF
51
54
51
52
55
52
53
56
53
54
PJ.4 (RD)
LFXIN
I
Analog
AVCC
-
PJ.5 (RD)
I/O
LVCMOS
DVCC
OFF
LFXOUT
O
Analog
AVCC
-
AVSS2
P
Power
-
N/A
PJ.7 (RD)
I/O
LVCMOS
DVCC
OFF
HFXOUT
O
Analog
AVCC
-
Terminal Configuration and Functions
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
15
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 4-1. Pin Attributes (continued)
FR697x(1),
FR687x(1)
FR692x(1), FR682x(1)
PM, RGC
PIN
NO.
DGG
LCD
SEG
PIN
NO.
PM, RGC
LCD
SEG
PIN
NO.
PJ.6 (RD)
56
55
56
57
58
59
60
61
S10
S9
S7
S6
S5
S4
57
1
2
3
4
S7
S6
S5
S4
58
59
60
61
RESET
STATE
AFTER
BOR (6)
OFF
S10
S9
S8
S7
S6
LVCMOS
DVCC
I
Analog
AVCC
-
AVSS3
P
Power
-
N/A
P5.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SIMO
I/O
LVCMOS
DVCC
-
UCA1TXD
O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P5.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SOMI
I/O
LVCMOS
DVCC
-
UCA1RXD
I
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P5.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1CLK
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P5.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1STE
I/O
LVCMOS
DVCC
-
I
LVCMOS
DVCC
-
TB0CLK
Sz
O
Analog
DVCC
-
P4.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
-
TA1CLK
I
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P4.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
-
TA1.0
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P4.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
-
UCB1SDA
I/O
LVCMOS
DVCC
-
TA1.1
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P4.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
-
UCB1SCL
I/O
LVCMOS
DVCC
-
TA1.2
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
P
Power
-
N/A
62
DVSS3
63
6
63
DVCC3
Terminal Configuration and Functions
POWER
SOURCE
I/O
5
64
BUFFER
TYPE (5)
HFXIN
62
64
16
S11
S8
(2) (3)
SIGNAL
TYPE (4)
LCD
SEG
55
54
SIGNAL NAME (1)
S5
P
Power
-
N/A
P4.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SIMO
I/O
LVCMOS
DVCC
-
UCA0TXD
O
LVCMOS
DVCC
-
UCB1CLK
I/O
LVCMOS
DVCC
-
Sz
O
Analog
DVCC
-
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
4.3
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Signal Descriptions
Table 4-2 describes the signals.
Table 4-2. Signal Descriptions
FR692x(1), FR682x(1)
SIGNAL
NAME
FUNCTION
PM, RGC
PIN
NO.
ADC
BSL (I2C)
BSL (UART)
Clock
Comparator
LCD
SEG
DGG
PIN
NO.
LCD
SEG
FR697x(1),
FR687x(1)
PM, RGC
PIN
NO.
SIGNAL
TYPE
DESCRIPTION
LCD
SEG
A0
44
47
44
I
Analog input A0
A1
43
46
43
I
Analog input A1
A2
42
45
42
I
Analog input A2
A3
41
44
41
I
Analog input A3
A12
45
48
45
I
Analog input A12
A13
46
49
46
I
Analog input A13
A14
47
50
47
I
Analog input A14
A15
48
51
48
I
Analog input A15
VREF+
43
46
43
O
Output of positive reference voltage
VREF-
44
47
44
O
Output of negative reference voltage
VeREF+
43
46
43
I
Input for an external positive reference
voltage to the ADC
VeREF-
44
47
44
I
Input for an external negative reference
voltage to the ADC
BSL_CLK
5
10
5
I
BSL clock (I2C BSL)
BSL_DAT
4
9
4
I/O
BSL data (I2C BSL)
BSL_RX
32
35
32
I
BSL receive (UART BSL)
BSL_TX
33
36
33
O
BSL transmit (UART BSL)
ACLK
23
26
23
O
ACLK output
HFXIN
55
I
Input terminal of crystal oscillator XT2
HFXOUT
54
O
Output terminal for crystal oscillator XT2
LFXIN
51
54
51
I
Input terminal for crystal oscillator XT1
LFXOUT
52
55
52
O
Output terminal of crystal oscillator XT1
MCLK
22
25
22
O
MCLK output
RTCCLK
31
44
34
47
31
44
O
RTC clock output for calibration
SMCLK
21
38
24
41
21
38
O
SMCLK output
C0
44
47
44
I
Comparator input C0
C1
43
46
43
I
Comparator input C1
C2
42
45
42
I
Comparator input C2
C3
41
44
41
I
Comparator input C3
C12
45
48
45
I
Comparator input C12
C13
46
49
46
I
Comparator input C13
C14
47
50
47
I
Comparator input C14
C15
48
51
48
I
Comparator input C15
COUT
9
24
42
43
14
27
45
46
9
24
42
43
O
Comparator output
Terminal Configuration and Functions
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
17
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 4-2. Signal Descriptions (continued)
FR692x(1), FR682x(1)
FUNCTION
SIGNAL
NAME
PM, RGC
PIN
NO.
Debug
DMA
GPIO
18
LCD
SEG
DGG
PIN
NO.
LCD
SEG
FR697x(1),
FR687x(1)
PM, RGC
PIN
NO.
SIGNAL
TYPE
DESCRIPTION
LCD
SEG
SBWTCK
19
22
19
I
SBWTDIO
20
23
20
I/O
Spy-Bi-Wire data input/output
SRCPUOFF
24
27
24
O
Low-power debug: CPU status register
CPUOFF
SROSCOFF
23
26
23
O
Low-power debug: CPU status register
OSCOFF
SRSCG0
22
25
22
O
Low-power debug: CPU status register
SCG0
SRSCG1
21
24
21
O
Low-power debug: CPU status register
SCG1
TCK
24
27
24
I
Test clock
TCLK
22
25
22
I
Test clock input
TDI
22
25
22
I
Test data input
TDO
21
24
21
O
Test data output port
TEST
19
22
19
I
Test mode pin - select digital I/O on JTAG
pins
TMS
23
26
23
I
Test mode select
DMAE0
32
44
35
47
32
44
I
DMA external trigger input
P1.0
44
47
44
I/O
General-purpose digital I/O
P1.1
43
46
43
I/O
General-purpose digital I/O
P1.2
42
45
42
I/O
General-purpose digital I/O
P1.3
41
44
41
I/O
General-purpose digital I/O
P1.4
2
7
2
I/O
General-purpose digital I/O
P1.5
3
8
3
I/O
General-purpose digital I/O
P1.6
4
9
4
I/O
General-purpose digital I/O
P1.7
5
10
5
I/O
General-purpose digital I/O
P2.0
33
36
33
I/O
General-purpose digital I/O
P2.1
32
35
32
I/O
General-purpose digital I/O
P2.2
31
34
31
I/O
General-purpose digital I/O
P2.3
30
33
30
I/O
General-purpose digital I/O
P3.0
14
19
14
I/O
General-purpose digital I/O
P3.1
15
20
15
I/O
General-purpose digital I/O
P3.2
16
21
16
I/O
General-purpose digital I/O
P3.3
25
28
25
I/O
General-purpose digital I/O
P3.4
26
29
26
I/O
General-purpose digital I/O
P3.5
27
30
27
I/O
General-purpose digital I/O
P3.6
28
31
28
I/O
General-purpose digital I/O
P3.7
29
32
29
I/O
General-purpose digital I/O
Terminal Configuration and Functions
Spy-Bi-Wire input clock
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 4-2. Signal Descriptions (continued)
FR692x(1), FR682x(1)
FUNCTION
SIGNAL
NAME
PM, RGC
PIN
NO.
GPIO
I2C
LCD
SEG
DGG
PIN
NO.
LCD
SEG
FR697x(1),
FR687x(1)
PM, RGC
PIN
NO.
SIGNAL
TYPE
DESCRIPTION
LCD
SEG
P4.2
64
64
I/O
General-purpose digital I/O
P4.3
1
1
I/O
General-purpose digital I/O
P4.4
58
1
58
I/O
General-purpose digital I/O
P4.5
59
2
59
I/O
General-purpose digital I/O
P4.6
60
3
60
I/O
General-purpose digital I/O
P4.7
61
4
61
I/O
General-purpose digital I/O
P5.4
54
I/O
General-purpose digital I/O
P5.5
55
I/O
General-purpose digital I/O
P5.6
56
I/O
General-purpose digital I/O
P5.7
57
57
I/O
General-purpose digital I/O
P6.0
7
12
7
I/O
General-purpose digital I/O
P6.1
8
13
8
I/O
General-purpose digital I/O
P6.2
9
14
9
I/O
General-purpose digital I/O
P6.3
10
15
10
I/O
General-purpose digital I/O
P6.4
11
16
11
I/O
General-purpose digital I/O
P6.5
12
17
12
I/O
General-purpose digital I/O
P6.6
13
18
13
I/O
General-purpose digital I/O
P7.0
34
37
34
I/O
General-purpose digital I/O
P7.1
35
38
35
I/O
General-purpose digital I/O
P7.2
36
39
36
I/O
General-purpose digital I/O
P7.3
37
40
37
I/O
General-purpose digital I/O
P7.4
38
41
38
I/O
General-purpose digital I/O
P9.4
45
48
45
I/O
General-purpose digital I/O
P9.5
46
49
46
I/O
General-purpose digital I/O
P9.6
47
50
47
I/O
General-purpose digital I/O
P9.7
48
51
48
I/O
General-purpose digital I/O
PJ.0
21
24
21
I/O
General-purpose digital I/O
PJ.1
22
25
22
I/O
General-purpose digital I/O
PJ.2
23
26
23
I/O
General-purpose digital I/O
PJ.3
24
27
24
I/O
General-purpose digital I/O
PJ.4
51
54
51
I/O
General-purpose digital I/O
PJ.5
52
55
52
I/O
General-purpose digital I/O
PJ.6
55
I/O
General-purpose digital I/O
PJ.7
54
I/O
General-purpose digital I/O
UCB0SCL
5
10
5
I/O
USCI_B0: I2C clock (I2C mode)
UCB0SDA
4
9
4
I/O
USCI_B0: I2C data (I2C mode)
UCB1SCL
16
61
21
4
16
61
I/O
USCI_B1: I2C clock (I2C mode)
UCB1SDA
15
60
20
3
15
60
I/O
USCI_B1: I2C data (I2C mode)
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
19
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 4-2. Signal Descriptions (continued)
FR692x(1), FR682x(1)
FUNCTION
SIGNAL
NAME
PM, RGC
PIN
NO.
LCD
20
LCD
SEG
DGG
PIN
NO.
LCD
SEG
FR697x(1),
FR687x(1)
PM, RGC
PIN
NO.
SIGNAL
TYPE
DESCRIPTION
LCD
SEG
COM0
10
15
10
O
LCD common output COM0 for LCD
backplane
COM1
11
16
11
O
LCD common output COM1 for LCD
backplane
COM2
12
17
12
O
LCD common output COM2 for LCD
backplane
COM3
13
18
13
O
LCD common output COM3 for LCD
backplane
LCDCAP
6
11
6
I
LCD capacitor connection
LCDREF
8
13
8
I
External reference voltage input for
regulated LCD voltage
R03
9
14
9
I/O
Input/output port of lowest analog LCD
voltage (V5)
R13
8
13
8
I/O
Input/output port of third most positive
analog LCD voltage (V3 or V4)
R23
7
12
7
I/O
Input/output port of second most positive
analog LCD voltage (V2)
R33
6
11
6
I/O
Input/output port of most positive analog
LCD voltage (V1)
Terminal Configuration and Functions
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 4-2. Signal Descriptions (continued)
FR697x(1),
FR687x(1)
FR692x(1), FR682x(1)
SIGNAL
NAME
FUNCTION
PM, RGC
PIN
NO.
LCD
Sz
LCD
SEG
DGG
PIN
NO.
LCD
SEG
PIN
NO.
LCD
SEG
SIGNAL
TYPE
1
S4
O
64
S5
O
5
S0
10
S0
5
S0
O
4
S1
9
S1
4
S1
O
3
S2
8
S2
3
S2
O
2
S3
7
S3
2
S3
O
61
S4
4
S4
61
S6
O
60
S5
3
S5
60
S7
O
59
S6
2
S6
59
S8
O
58
S7
1
S7
58
S9
O
57
S8
57
S10
O
56
S9
O
55
S10
O
54
S11
O
38
S12
41
S8
38
S11
O
37
S13
40
S9
37
S12
O
36
S14
39
S10
36
S13
O
35
S15
38
S11
35
S14
O
34
S16
37
S12
34
S15
O
33
S17
36
S13
33
S16
O
32
S18
35
S14
32
S17
O
31
S19
34
S15
31
S18
O
30
S20
33
S16
30
S19
O
29
S21
32
S17
29
S20
O
28
S22
31
S18
28
S21
O
27
S23
30
S19
27
S22
O
26
S24
29
S20
26
S23
O
25
S25
28
S21
25
S24
O
16
S26
21
S22
16
S25
O
15
S27
20
S23
15
S26
O
14
S28
19
S24
14
S27
O
13
S29
18
S25
13
S28
O
12
S30
17
S26
12
S29
O
11
S31
16
S27
11
S30
O
DESCRIPTION
LCD segment output (package specific)
AVCC1
49
52
49
P
Analog power supply
AVSS1
50
53
50
P
Analog ground supply
AVSS2
53
56
53
P
Analog ground supply
56
P
Analog ground supply
18
P
Digital power supply
AVSS3
Power
PM, RGC
DVCC1
18
DVCC2
40
43
40
P
Digital power supply
DVCC3
63
6
63
P
Digital power supply
DVSS1
17
17
P
Digital ground supply
DVSS2
39
42
39
P
Digital ground supply
DVSS3
62
5
62
P
Digital ground supply
Terminal Configuration and Functions
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
21
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 4-2. Signal Descriptions (continued)
FR692x(1), FR682x(1)
FUNCTION
SIGNAL
NAME
PM, RGC
PIN
NO.
SPI
System
22
LCD
SEG
DGG
PIN
NO.
LCD
SEG
FR697x(1),
FR687x(1)
PM, RGC
PIN
NO.
SIGNAL
TYPE
DESCRIPTION
LCD
SEG
UCA0CLK
3
31
8
34
3
31
I/O
USCI_A0: Clock signal input (SPI slave
mode), Clock signal output (SPI master
mode)
UCA0SIMO
33
64
36
33
64
I/O
USCI_A0: Slave in, master out (SPI mode)
UCA0SOMI
1
32
35
1
32
I/O
USCI_A0: Slave out, master in (SPI mode)
UCA0STE
2
30
7
33
2
30
I/O
USCI_A0: Slave transmit enable (SPI
mode)
UCA1CLK
28
56
31
28
I/O
USCI_A1: Clock signal input (SPI slave
mode), Clock signal output (SPI master
mode)
UCA1SIMO
26
54
29
26
I/O
USCI_A1: Slave in, master out (SPI mode)
UCA1SOMI
27
55
30
27
I/O
USCI_A1: Slave out, master in (SPI mode)
UCA1STE
29
57
32
29
57
I/O
USCI_A1: Slave transmit enable (SPI
mode)
UCB0CLK
2
7
2
I/O
USCI_B0: Clock signal input (SPI slave
mode), Clock signal output (SPI master
mode)
UCB0SIMO
4
9
4
I/O
USCI_B0: Slave in, master out (SPI mode)
UCB0SOMI
5
10
5
I/O
USCI_B0: Slave out, master in (SPI mode)
UCB0STE
3
8
3
I/O
USCI_B0: Slave transmit enable (SPI
mode)
UCB1CLK
14
59
64
19
2
14
59
64
I/O
USCI_B1: Clock signal input (SPI slave
mode), Clock signal output (SPI master
mode)
UCB1SIMO
60
15
3
20
60
15
I/O
USCI_B1: Slave in, master out (SPI mode)
UCB1SOMI
16
61
21
4
16
61
I/O
USCI_B1: Slave out, master in (SPI mode)
UCB1STE
1
58
1
1
58
I/O
USCI_B1: Slave transmit enable (SPI
mode)
NMI
20
23
20
I
Nonmaskable interrupt input
RST
20
23
20
I
Reset input active low
Terminal Configuration and Functions
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 4-2. Signal Descriptions (continued)
FR692x(1), FR682x(1)
FUNCTION
SIGNAL
NAME
PM, RGC
PIN
NO.
Timer_A
LCD
SEG
PIN
NO.
LCD
SEG
PM, RGC
PIN
NO.
SIGNAL
TYPE
DESCRIPTION
LCD
SEG
TA0.0
3
35
8
38
3
35
I/O
Timer_A TA0 CCR0 capture: CCI0A input,
compare: Out0 output
TA0.1
4
36
44
9
39
47
4
36
44
I/O
Timer_A TA0 CCR1 capture: CCI1A input,
compare: Out1 output
TA0.2
5
37
43
10
40
46
5
37
43
I/O
Timer_A TA0 CCR2 capture: CCI2A input,
compare: Out2 output
TA0CLK
34
42
37
45
34
42
I
TA1.0
2
59
7
2
2
59
I/O
Timer_A TA1 CCR0 capture: CCI0A input,
compare: Out0 output
TA1.1
25
42
60
28
45
3
25
42
60
I/O
Timer_A TA1 CCR1 capture: CCI1A input,
compare: Out1 output
TA1.2
41
61
44
4
41
61
I/O
Timer_A TA1 CCR2 capture: CCI2A input,
compare: Out2 output
TA1CLK
43
58
46
1
43
58
I
TA3.2
19
TA3.3
20
TA3.4
Timer_B
DGG
FR697x(1),
FR687x(1)
14
15
Timer_A TA0 clock signal TA0CLK input
Timer_A TA1 clock signal TA1CLK input
I/O
Timer_A TA3 CCR2 capture: CCI2B input,
compare: Out2 output
(Note: Not availble for FR692x and
FR682x 64-pin package. Internally tied to
DVSS when TA3 is selected)
I/O
Timer_A TA3 CCR3 capture: CCI3B input,
compare: Out3 output
(Note: Not availble for FR692x and
FR682x 64-pin package. Internally tied to
DVSS when TA3 is selected)
21
16
I/O
Timer_A TA3 CCR4 capture: CCI4B input,
compare: Out4 output
(Note: Not availble for FR692x and
FR682x 64-pin package. Internally tied to
DVSS when TA3 is selected)
TB0.0
11
26
16
29
11
26
I/O
Timer_B TB0 CCR0 capture: CCI0B input,
compare: Out0 output
TB0.1
12
27
17
30
12
27
I/O
Timer_B TB0 CCR1 capture: CCI1A input,
compare: Out1 output
TB0.2
13
28
18
31
13
28
I/O
Timer_B TB0 CCR2 capture: CCI2A input,
compare: Out2 output
TB0.3
29
32
29
I/O
Timer_B TB0 CCR3 capture: CCI3B input,
compare: Out3 output
TB0.4
31
34
31
I/O
Timer_B TB0 CCR4 capture: CCI4B input,
compare: Out4 output
TB0.5
32
35
32
I/O
Timer_B TB0 CCR5 capture: CCI5B input,
compare: Out5 output
TB0.6
33
36
33
I/O
Timer_B TB0 CCR6 capture: CCI6B input,
compare: Out6 output
TB0CLK
25
33
57
28
36
25
33
57
I
Timer_B TB0 clock signal TB0CLK input
TB0OUTH
21
30
24
33
21
30
I
Switch all PWM outputs high impedance
input - Timer_B TB0
Terminal Configuration and Functions
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
23
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 4-2. Signal Descriptions (continued)
FR692x(1), FR682x(1)
FUNCTION
SIGNAL
NAME
PM, RGC
PIN
NO.
PIN
NO.
LCD
SEG
PM, RGC
PIN
NO.
SIGNAL
TYPE
DESCRIPTION
LCD
SEG
UCA0RXD
1
32
35
1
32
I
USCI_A0: Receive data (UART mode)
UCA0TXD
33
64
36
33
64
O
USCI_A0: Transmit data (UART mode)
UCA1RXD
27
55
30
27
I
USCI_A1: Receive data (UART mode)
UCA1TXD
26
54
29
26
O
USCI_A1: Transmit data (UART mode)
UART
24
LCD
SEG
DGG
FR697x(1),
FR687x(1)
Terminal Configuration and Functions
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
4.4
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.11.23.
Table 4-3. Buffer Type
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
LVCMOS
3.0 V
Y (1)
Programmable
See Table 5-11
See
Section 5.13.5.1
Analog
3.0 V
N
N/A
N/A
N/A
See analog modules in
Section 5 for details
Power (DVCC)
3.0 V
N
N/A
N/A
N/A
SVS enables hysteresis on
DVCC
Power (AVCC)
3.0 V
N
N/A
N/A
N/A
BUFFER TYPE
(STANDARD)
(1)
OTHER
CHARACTERISTICS
Only for Input pins.
4.5
Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins (1)
PIN
POTENTIAL
COMMENT
AVCC
DVCC
AVSS
DVSS
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
R33/LCDCAP
DVSS or DVCC
If not used, the pin can be tied to either supply.
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF (2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, they
should be set to port function and output direction. When used as JTAG pins, these pins should
remain open.
TEST
Open
This pin always has an internal pulldown enabled.
(1)
(2)
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
Terminal Configuration and Functions
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
25
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins
Voltage applied to any pin
MIN
MAX
–0.3
4.1
V
±0.3
V
VCC + 0.3
–0.3
(4.1 Maximum)
V
(2)
(3)
Diode current at any device pin
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(4)
–40
±2
mA
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN
(1) (2) (3)
VCC
Supply voltage applied at all DVCC and AVCC pins
VSS
Supply voltage applied at all DVSS and AVSS pins
TA
Operating free-air temperature
–40
TJ
Operating junction temperature
–40
CDVCC
Recommended capacitor value at DVCC (5)
fSYSTEM
Processor frequency (maximum MCLK
frequency) (6)
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
26
1.8
NOM
(4)
MAX
UNIT
3.6
V
85
°C
0
V
85
1
°C
µF
No FRAM wait states (NWAITSx = 0)
0
8 (7)
With FRAM wait states (NWAITSx = 1) (8)
0
16 (9)
MHz
50
kHz
16 (9)
MHz
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
Modules may have a different supply voltage range specification. Refer to the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels. Refer to the PMM SVS threshold parameters in Table 5-2 for the
exact values.
As decoupling capacitor for each supply pin pair (DVCC/DVSS, AVCC/AVSS, ...), a low-ESR ceramic capacitor of 100 nF (minimum)
should be placed as close as possible (within a few millimeters) to the respective pin pairs.
Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
DCO settings and HF cyrstals with a typical value less or equal the specified MAX value are permitted.
Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted
without wait states.
DCO settings and HF cyrstals with a typical value less or equal the specified MAX value are permitted. If a clock source with a higher
typical value is used, the clock must be divided in the clock system.
Specifications
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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5.4
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
IAM, FRAM_UNI
(Unified memory) (3)
(4) (5)
MAX
4 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
8 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
12 MHz
1 WAIT
STATES
(NWAITSx = 1)
TYP
MAX
16 MHz
1 WAIT
STATES
(NWAITSx = 1)
TYP
UNIT
MAX
FRAM
3.0 V
210
640
1220
1475
1845
µA
FRAM
0% cache hit
ratio
3.0 V
370
1280
2510
2080
2650
µA
IAM,
FRAM(0%)
IAM,
FRAM(50%)
(4) (5)
FRAM
50% cache hit
ratio
3.0 V
240
745
1440
1575
1990
µA
IAM,
FRAM(66%)
(4) (5)
FRAM
66% cache hit
ratio
3.0 V
200
560
1070
1300
1620
µA
IAM,
FRAM(75%)
(4) (5)
FRAM
75% cache hit
ratio
3.0 V
170
480
890
IAM,
FRAM(100%
FRAM
100% cache hit
ratio
3.0 V
110
235
420
640
730
IAM,
RAM
RAM
3.0 V
130
320
585
890
1070
RAM
3.0 V
100
290
555
860
1040
(6) (5)
IAM, RAM only
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(4) (5)
(7) (5)
255
180
1085
1155
1310
1420
1620
µA
µA
µA
1300
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 - cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 - 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 5.4.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Specifications
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
27
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.5
www.ti.com
Typical Characteristics - Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
Active Mode Current [µA]
I(AM,75%)
2000
I(AM,100%)
I(AM,75%)[uA] = 103*f[MHz] + 68
I(AM,RAMonly)
1500
1000
500
0
0
1
2
3
4
5
6
7
8
9
MCLK Frequency [MHz]
C001
I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents, No Wait States
5.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
ILPM1
(1)
(2)
28
2.2 V
75
3.0 V
80
2.2 V
40
3.0 V
40
4 MHz
MAX
120
65
TYP
MAX
8 MHz
TYP
MAX
12 MHz
TYP
MAX
16 MHz
TYP
105
165
250
230
115
175
260
240
65
130
215
195
65
130
215
195
UNIT
MAX
275
220
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency - except for 12 MHz: here fDCO=24MHz and fSMCLK = fDCO/2.
Specifications
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
5.7
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
–40°C
TYP
MAX
25°C
TYP
ILPM2,XT12
Low-power mode 2, 12-pF
crystal (2) (3) (4)
2.2 V
0.8
1.2
3.0 V
0.8
1.2
ILPM2,XT3.7
Low-power mode 2, 3.7-pF
crystal (2) (5) (4)
2.2 V
0.7
3.0 V
0.7
ILPM2,VLO
Low-power mode 2, VLO,
includes SVS (6)
2.2 V
0.5
0.9
3.0 V
0.5
0.9
ILPM3,XT12
Low-power mode 3, 12-pF
crystal, includes SVS (2) (3) (7)
2.2 V
0.7
0.9
3.0 V
0.7
0.9
Low-power mode 3, 3.7-pF
crystal, excludes SVS (2) (5) (8)
(refer also to Figure 5-2)
2.2 V
0.6
ILPM3,XT3.7
3.0 V
ILPM3,VLO
Low-power mode 3,
VLO, excludes SVS (9)
Low-power mode 3,
VLO, excludes SVS, RAM
powered down completely (10)
ILPM3,VLO,
RAMoff
(1)
60°C
MAX
TYP
85°C
MAX
TYP
3.1
8.8
3.1
8.8
1.1
3.0
8.7
1.1
3.0
8.7
2.8
8.5
2.8
8.5
1.2
2.5
1.2
2.5
0.7
1.1
2.4
0.6
0.7
1.1
2.4
2.2 V
0.35
0.4
0.9
1.8
3.0 V
0.35
0.4
0.9
1.8
2.2 V
0.35
0.4
0.8
1.7
3.0 V
0.35
0.4
0.8
1.7
2.2
2.0
1.2
0.8
0.7
MAX
17
UNIT
μA
μA
16.7
6.4
μA
μA
μA
6.1
5.2
μA
μA
(1)
(2)
(3)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. Refer to the idle currents specified for the respective peripheral groups.
(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. Refer to the idle currents specified for the respective peripheral groups.
(9) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. Refer to the idle currents specified for the respective peripheral groups.
(10) Low-power mode 3, VLO, excludes SVS, RAM powered down completely test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. Refer to the idle currents specified for the respective peripheral groups.
Specifications
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
29
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
–40°C
TYP
MAX
25°C
TYP
ILPM4,SVS
Low-power mode 4, includes
SVS (11)
2.2 V
0.45
0.55
3.0 V
0.45
0.55
ILPM4
Low-power mode 4, excludes
SVS (12)
2.2 V
0.25
0.4
3.0 V
0.25
0.4
Low-power mode 4, excludes
SVS, RAM powered down
completely (13)
2.2 V
0.25
0.4
ILPM4,RAMoff
3.0 V
0.25
0.4
IIDLE,GroupA
Additional idle current if one or
more modules from Group A
(refer to ) are activated in
LPM3 or LPM4
3.0V
IIDLE,GroupB
Additional idle current if one or
more modules from Group B
(refer to ) are activated in
LPM3 or LPM4
IIDLE,GroupC
Additional idle current if one or
more modules from Group C
(refer to ) are activated in
LPM3 or LPM4
(1)
60°C
MAX
TYP
85°C
MAX
TYP
MAX
UNIT
0.9
1.8
0.9
1.8
0.7
1.6
0.7
1.6
0.7
1.4
0.7
1.4
4.6
0.02
0.4
1.0
μA
3.0V
0.02
0.4
1.0
μA
3.0V
0.02
0.3
0.8
μA
0.8
0.65
0.65
6.2
4.6
μA
μA
μA
(11) Low-power mode 4, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. Refer to the idle currents specified for the respective peripheral groups.
(12) Low-power mode 4, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. Refer to the idle currents specified for the respective peripheral groups.
(13) Low-power mode 4, excludes SVS, RAM powered down completely test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. Refer to the idle currents specified for the respective peripheral groups.
30
Specifications
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
5.8
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEMPERATURE (TA)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM3,XT12
LCD,
ext. bias
Low-power mode 3 (LPM3)
current,12-pF crystal, LCD 4mux mode, external biasing,
excludes SVS (1) (2)
3.0 V
0.8
1.0
ILPM3,XT12
LCD,
int. bias
Low-power mode 3 (LPM3)
current, 12-pF crystal, LCD 4mux mode, internal biasing,
charge pump disabled,
excludes SVS (1) (3)
3.0 V
2.5
2.7
Low-power mode 3 (LPM3)
current,12-pF crystal, LCD 4mux mode, internal biasing,
charge pump enabled, 1/3 bias,
excludes SVS (1) (4)
2.2 V
6.2
ILPM3,XT12
LCD,CP
3.0 V
5.8
(1)
(2)
(3)
(4)
60°C
MAX
TYP
85°C
MAX
TYP
UNIT
MAX
1.5
3.1
2.8
4.4
6.4
7.0
8.0
µA
6.0
6.8
7.5
µA
3.4
µA
9.3
µA
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current (idle current of Group containing LCD module already included). Refer to the idle currents specified for the respective
peripheral groups.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD= 3 V typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. CLCDCAP = 10 µF
Specifications
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
31
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.9
www.ti.com
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
–40°C
TYP
MAX
25°C
TYP
ILPM3.5,XT12
Low-power mode 3.5, 12-pF
crystal including SVS (2) (3) (4)
2.2 V
0.45
0.5
3.0 V
0.45
0.5
ILPM3.5,XT3.7
Low-power mode 3.5, 3.7-pF
crystal excluding SVS (2) (5) (6)
2.2 V
0.3
3.0 V
0.3
ILPM4.5,SVS
Low-power mode 4.5, including
SVS (7)
2.2 V
0.2
0.3
3.0 V
0.2
0.3
ILPM4.5
Low-power mode 4.5,
excluding SVS (8)
2.2 V
0.03
3.0 V
0.03
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
32
60°C
MAX
TYP
85°C
MAX
TYP
0.6
0.75
0.6
0.75
0.35
0.4
0.65
0.35
0.4
0.65
0.35
0.4
0.35
0.4
0.04
0.06
0.14
0.04
0.06
0.14
0.75
0.5
MAX
1.4
UNIT
μA
μA
0.7
0.5
μA
μA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Specifications
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.10 Typical Characteristics, Low-Power Mode Supply Currents
3
3
@ 3.0V, SVS off
@ 3.0V, SVS off
@ 2.2V, SVS off
@ 2.2V, SVS off
@ 3.0V, SVS on
2.5
@ 3.0V, SVS on
2.5
@ 2.2V, SVS on
LPM4 Supply Current [A]
LPM3 Supply Current [A]
@ 2.2V, SVS on
2
1.5
1
0.5
2
1.5
1
0.5
0
0
-50
-25
0
25
50
75
100
-50
-25
0
25
Temperature [C]
50
75
C003
Figure 5-2. LPM3 Supply Current vs Temperature (LPM3,XT3.7)
C001
Figure 5-3. LPM4 Supply Current vs Temperature (LPM4,SVS)
7.00E-01
0.7
@ 3.0V, SVS off
@ 3.0V, SVS off
@ 2.2V, SVS off
@ 2.2V, SVS off
6.00E-01
@ 3.0V, SVS on
LPM.54 Supply Current [A]
LPM3.5 Supply Current [A]
0.6
0.5
0.4
0.3
0.2
-50.00
100
Temperature [C]
@ 2.2V, SVS on
5.00E-01
4.00E-01
3.00E-01
2.00E-01
1.00E-01
0.00E+00
-25.00
0.00
25.00
50.00
75.00
100.00
Temperature [C]
-50
-25
0
25
50
75
100
Temperature [C]
C004
C003
Figure 5-4. LPM3.5 Supply Current vs Temperature
(LPM3.5,XT3.7)
Figure 5-5. LPM4.5 Supply Current vs Temperature (LPM4.5)
Specifications
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
33
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
5.11 Typical Characteristics, Current Consumption per Module (1)
MODULE
TEST CONDITIONS
REFERENCE CLOCK
Timer_A
MIN
Module input clock
TYP
MAX
UNIT
3
μA/MHz
Module input clock
5
μA/MHz
eUSCI_A
UART mode
Module input clock
5.5
μA/MHz
eUSCI_A
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
3.5
μA/MHz
32 kHz
100
nA
Timer_B
RTC_C
MPY
Only from start to end of operation
MCLK
25
μA/MHz
AES
Only from start to end of operation
MCLK
21
μA/MHz
CRC16
Only from start to end of operation
MCLK
2.5
μA/MHz
CRC32
Only from start to end of operation
MCLK
2.5
μA/MHz
(1)
LCD_C: Refer to Section 5.8. For other module currents not listed here, refer to the module specific parameter sections.
5.12 Thermal Characteristics (1)
PARAMETER
PACKAGE
θJA
Junction-to-ambient thermal resistance, still air
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
(2)
(4)
θJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
TSSOP-56 (DGG)
(5)
VALUE (1)
UNIT
57.7
°C/W
15.1
°C/W
26.5
°C/W
26.2
°C/W
0.5
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (2)
59.3
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
19.5
°C/W
θJB
Junction-to-board thermal resistance (4)
30.8
°C/W
ΨJB
Junction-to-board thermal characterization parameter
30.5
°C/W
ΨJT
Junction-to-top thermal characterization parameter
1.0
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (5)
N/A
°C/W
QFP-64 (PN)
(2)
θJA
Junction-to-ambient thermal resistance, still air
29.6
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
15.8
°C/W
θJB
Junction-to-board thermal resistance (4)
8.5
°C/W
ΨJB
Junction-to-board thermal characterization parameter
8.5
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (5)
1.2
°C/W
(1)
(2)
(3)
(4)
(5)
34
QFN-64 (RGC)
N/A = not applicable
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Specifications
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13 Timing and Switching Characteristics
5.13.1 Power Supply Sequencing
It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits
specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device
including erroneous writes to RAM and FRAM.
Table 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VVCC_BOR–
VVCC_BOR+
(1)
(2)
TEST CONDITIONS
Brownout power-down level (1)
Brownout power-up level
(1)
MIN
MAX
UNIT
| dDVCC/dt | < 3 V/s (2)
0.73
1.66
V
(2)
0.79
1.68
V
| dDVCC/dt | < 3 V/s
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply.
Table 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISVSH,LPM
SVSH current consumption, low power modes
170
300
nA
VSVSH-
SVSH power-down level
1.75
1.80
1.85
V
VSVSH+
SVSH power-up level
1.77
1.88
1.99
V
VSVSH_hys
SVSH hysteresis
120
mV
tPD,SVSH, AM
SVSH propagation delay, active mode
10
µs
40
dVVcc/dt = -10 mV/µs
5.13.2 Reset Timing
Table 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(RST)
(1)
External reset pulse duration on RST
(1)
VCC
2.2 V, 3.0 V
MIN
MAX
UNIT
2
µs
Not applicable if the RST/NMI pin is configured as NMI.
Specifications
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
35
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
5.13.3 Clock Specifications
Table 5-4. Low-Frequency Crystal Oscillator, LFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IVCC.LFXT
Current consumption
TEST CONDITIONS
VCC
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
3.0 V
180
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
3.0 V
185
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
3.0 V
225
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈
40 kΩ
3.0 V
330
fLFXT
LFXT oscillator crystal
frequency
LFXTBYPASS = 0
DCLFXT
LFXT oscillator duty cycle
Measured at ACLK,
fLFXT = 32768 Hz
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (2)
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
OALFXT
Oscillation allowance for
LF crystals (4)
MIN
TYP
MAX
nA
32768
30%
(3)
UNIT
10.5
Hz
70%
32.768
30%
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
210
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
300
kΩ
CLFXIN
Integrated load capacitance at
LFXIN terminal (5) (6)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (5) (6)
2
pF
(1)
(2)
(3)
(4)
(5)
(6)
36
To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 3.7
pF, 6 pF, 9pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds additional capacitance, so it must also be considered
in the overall capacitance. It is recommended to verify that the recommended effective load capacitance of the selected crystal is met.
Specifications
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,LFXT
fFault,LFXT
(7)
(8)
(9)
Start-up time
TEST CONDITIONS
(7)
Oscillator fault frequency (8)
VCC
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
3.0 V
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
MIN
TYP
MAX
UNIT
800
ms
(9)
1000
0
3500
Hz
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition will set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5. High-Frequency Crystal Oscillator, HFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1 (2),
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
IDVCC.HFXT
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1
TA = 25°C,
HFXT oscillator crystal current HF CL,eff = 18 pF, typical ESR, Cshunt
mode at typical ESR
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
(2)
HFXT oscillator crystal frequency,
crystal mode
HFXTBYPASS = 0, HFFREQ = 2
HFXTBYPASS = 0, HFFREQ = 3
DCHFXT
(1)
(2)
(3)
HFXT oscillator duty cycle.
Measured at SMCLK,
fHFXT = 16 MHz
UNIT
120
μA
3.0 V
190
250
4
8
(3)
8.01
16
(3)
16.01
24
(3)
fHFXT
MAX
75
fOSC = 24 MHz
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
HFXTBYPASS = 0, HFFREQ = 1
TYP
40%
50%
MHz
60%
To improve EMI on the HFXT oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and praxis to avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
HFFREQ = {0} is not supported for HFXT crystal mode of operation.
Maximum frequency of operation of the entire device cannot be exceeded.
Specifications
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
37
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
HFXTBYPASS = 1, HFFREQ = 0 (4)
(3)
fHFXT,SW
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
HFXTBYPASS = 1, HFFREQ = 1 (4)
(3)
HFXTBYPASS = 1, HFFREQ = 2
HFXT oscillator logic-level
square-wave input duty cycle
tSTART,HFXT Start-up time (5)
MAX
0.9
4
4.01
8
8.01
16
16.01
24
40%
60%
UNIT
MHz
(3)
(3)
SW
TYP
(4)
HFXTBYPASS = 1, HFFREQ = 3 (4)
DCHFXT,
MIN
HFXTBYPASS = 1
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
3.0 V
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
3.0 V
1.6
ms
0.6
CHFXIN
Integrated load capacitance at
HFXIN terminaI (6) (7)
2
pF
CHFXOUT
Integrated load capacitance at
HFXOUT terminaI (6) (7)
2
pF
fFault,HFXT
(4)
(5)
(6)
(7)
(8)
(9)
38
Oscillator fault frequency
(8) (9)
0
800
kHz
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
Includes start-up counter of 1024 clock cycles.
This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14
pF, 16pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds additional capacitance, so it must also be considered in the
overall capacitance. It is recommended to verify that the recommended effective load capacitance of the selected crystal is met.
Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX might set the flag. A static
condition or stuck at fault condition will set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1
±3.5%
MHz
fDCO1
DCO frequency range 1 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0
DCORSEL = 1, DCOFSEL = 0
fDCO2.7
DCO frequency range 2.7 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667
±3.5%
MHz
fDCO3.5
DCO frequency range 3.5 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5
±3.5%
MHz
fDCO4
DCO frequency range 4 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
4
±3.5%
MHz
fDCO5.3
DCO frequency range 5.3 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4
DCORSEL = 1, DCOFSEL = 1
5.333
±3.5%
MHz
fDCO7
DCO frequency range 7 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5
DCORSEL = 1, DCOFSEL = 2
7
±3.5%
MHz
fDCO8
DCO frequency range 8 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6
DCORSEL = 1, DCOFSEL = 3
8
±3.5%
MHz
fDCO16
DCO frequency range 16 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16
±3.5% (1)
MHz
fDCO21
DCO frequency range 21 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21
±3.5% (1)
MHz
fDCO24
DCO frequency range 24 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24
±3.5% (1)
MHz
Duty cycle
Measured at SMCLK, divide by 1,
No external divide, all DCORSEL and
DCOFSEL settings except DCORSEL
= 1, DCOFSEL = 5 and DCORSEL =
1, DCOFSEL = 6
50%
52%
DCO jitter
Based on fsignal = 10 kHz and DCO
used for 12-bit SAR ADC sampling
source. This achieves > 74-dB SNR
due to jitter; that is, it is limited by
ADC performance.
2
3
fDCO,DC
tDCO,
JITTER
dfDCO/dT
(1)
(2)
DCO temperature drift (2)
48%
3.0 V
0.01
ns
%/ºC
After a wakeup from LPM1, LPM2, LPM3 or LPM4 the DCO frequency fDCO might exceed the specified frequency range for a few clocks
cycles by up to 5% before settling into the specified steady state frequency range.
Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IVLO
Current consumption
fVLO
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at ACLK (2)
fVLO,DC
Duty cycle
Measured at ACLK
(1)
(2)
VCC
MIN
TYP
MAX
100
6
9.4
nA
14
0.2
50%
kHz
%/°C
0.7
40%
UNIT
%/V
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
39
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift (1)
fMODOSC/dVCC
MODOSC frequency supply voltage
drift (2)
DCMODOSC
Duty cycle
(1)
(2)
40
TEST CONDITIONS
MIN
Enabled
MAX
40%
UNIT
μA
25
4.0
Measured at SMCLK, divide by 1
TYP
4.8
5.4
MHz
0.08
%/℃
1.4
%/V
50%
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.4 Wake-up Characteristics
Table 5-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
tWAKE-UP FRAM
MIN
Additional wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected
MCLKREQEN = 1
(1)
tWAKE-UP LPM0
VCC
Wake-up time from LPM0 to active mode
MCLKREQEN = 0
(1) (2)
TYP
MAX
6
10
2.2 V, 3.0 V
400 ns +
1.5/fDCO
2.2 V, 3.0 V
400 ns +
2.5/fDCO
UNIT
μs
tWAKE-UP LPM1
Wake-up time from LPM1 to active mode (1)
2.2 V, 3.0 V
6
μs
tWAKE-UP LPM2
Wake-up time from LPM2 to active mode (1)
2.2 V, 3.0 V
6
μs
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode
(1)
2.2 V, 3.0 V
7
10
μs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode (1)
2.2 V, 3.0 V
7
10
μs
2.2 V, 3.0 V
250
350
μs
SVSHE = 1
2.2 V, 3.0 V
250
350
μs
SVSHE = 0
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode (3)
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (3)
2.2 V, 3.0 V
0.4
0.8
ms
tWAKE-UP-RST
Wake-up time from a RST pin triggered reset to
active mode (3)
2.2 V, 3.0 V
250
350
μs
tWAKE-UP-BOR
Wake-up time from power-up to active mode
(3)
2.2 V, 3.0 V
0.5
1.0
ms
(1)
(2)
(3)
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wakeup.
With MCLKREQEN =0, the MCLK is gated one additoinal one clock cycle (wake up from LPM0, LPM1, LPM2, LPM3, and LPM4). The
devcie wake-up time is not affected by the status of the MCLKREQEN bit.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 5-10. Typical Wake-up Charge (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QWAKE-UP FRAM
Charge used for activating the FRAM in AM or during wakeup
from LPM0 if previously disabled by the FRAM controller.
15.1
nAs
QWAKE-UP LPM0
Charge used to wake up from LPM0 to active mode (with FRAM
active)
4.4
nAs
QWAKE-UP LPM1
Charge used to wake up from LPM1 to active mode (with FRAM
active)
15.1
nAs
QWAKE-UP LPM2
Charge used to wake up from LPM2 to active mode (with FRAM
active)
15.3
nAs
QWAKE-UP LPM3
Charge used to wake up from LPM3 to active mode (with FRAM
active)
16.5
nAs
QWAKE-UP LPM4
Charge used to wake up from LPM4 to active mode (with FRAM
active)
16.5
nAs
QWAKE-UP LPM3.5
Charge used to wake up from LPM3.5 to active mode (2)
76
nAs
QWAKE-UP LPM4.5
Charge used to wake up from LPM4.5 to active mode (2)
QWAKE-UP-RESET
Charge used for reset from RST or BOR event to active mode (2)
(1)
(2)
SVSHE = 1
77
SVSHE = 0
77.5
75
nAs
nAs
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
Specifications
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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5.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
LPM2,XT12
Average Wake-up Current [A]
1000.00
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-Up Frequency [Hz]
C001
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-6. Average LPM Currents vs Wake-up Frequency at 25°C
10000.00
LPM0
LPM1
LPM2,XT12
Average Wake-up Current [A]
1000.00
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-Up Frequency [Hz]
C001
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-7. Average LPM Currents vs Wake-up Frequency at 85°C
42
Specifications
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.5 Digital I/Os
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
2.2 V
1.2
1.65
3.0 V
1.65
2.25
2.2 V
0.55
1.00
3.0 V
0.75
1.35
2.2 V
0.44
0.98
3.0 V
0.60
1.30
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions (1)
5
pF
Ilkg(Px.y)
High-impedance input leakage current
Refer to notes
t(int)
External interrupt timing (external trigger pulse
duration to set interrupt flag) (4)
Ports with interrupt capability
(see block diagram and
terminal function
descriptions).
t(RST)
External reset pulse duration on RST (5)
(1)
(2)
(3)
(4)
(5)
(2)
and
(3)
20
35
50
V
V
V
kΩ
2.2 V,
3.0 V
-20
2.2 V,
3.0 V
20
ns
2.2 V,
3.0 V
2
µs
+20
nA
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and
PJ.5/LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Not applicable if the RST/NMI pin is configured as NMI.
Specifications
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MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP
I(OHmax) = –3 mA (2)
VCC –
0.60
VCC
I(OHmax) = –2 mA (1)
VCC –
0.25
VCC
VCC –
0.60
VCC
VSS
VSS +
0.25
I(OLmax) = 3 mA (2)
VSS
VSS +
0.60
I(OLmax) = 2 mA (1)
VSS
VSS +
0.25
VSS
VSS +
0.60
2.2 V
High-level output voltage
3.0 V
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (1)
Low-level output voltage
3.0 V
I(OLmax) = 6 mA (2)
fPx.y
Port output frequency (with load) (3)
CL = 20 pF, RL
fPort_CLK
Clock output frequency (3)
ACLK, MCLK, or SMCLK at
configured output port
CL = 20 pF (5)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
trise,ana
Port output rise time, port pins with shared
analog functions
CL = 20 pF
tfall,ana
Port output fall time, port pins with shared
analog functions
CL = 20 pF
(1)
(2)
(3)
(4)
(5)
44
(4) (5)
2.2 V
16
3.0 V
16
2.2 V
16
3.0 V
16
UNIT
V
2.2 V
VOL
MAX
VCC
I(OHmax) = –1 mA (1)
VOH
MIN
VCC –
0.25
V
MHz
MHz
2.2 V
4
15
3.0 V
3
15
2.2 V
4
15
3.0 V
3
15
2.2 V
6
15
3.0 V
4
15
2.2 V
6
15
3.0 V
4
15
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit. It might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.5.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
30
@ 25°C
@ 85°C
Low-Level Output Current [mA]
Low-Level Output Current [mA]
15
10
5
@ 25°C
@ 85°C
20
10
P1.1
P1.1
0
0
0
0.5
1
1.5
2
0
0.5
Low-Level Output Voltage [V]
1
1.5
2
2.5
3
Low-Level Output Voltage [V]
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
@ 25°C
@ 85°C
High-Level Output Current [mA]
High-Level Output Current [mA]
0
Figure 5-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
-5
-10
@ 25°C
@ 85°C
-10
-20
P1.1
P1.1
-15
-30
0
0.5
1
1.5
2
0
0.5
High-Level Output Voltage [V]
1
1.5
2
2.5
C001
VCC = 2.2 V
Figure 5-10. Typical High-Level Output Current vs High-Level
Output Voltage
C001
VCC = 3.0 V
Figure 5-11. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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MSP430FR6820
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3
High-Level Output Voltage [V]
45
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
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Table 5-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foPx.y
(1)
TEST CONDITIONS
Pin-oscillator frequency
VCC
MIN
TYP
MAX
UNIT
Px.y, CL = 10 pF (1)
3.0 V
1200
kHz
(1)
3.0 V
650
kHz
Px.y, CL = 20 pF
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
1000
fitted
fitted
25°C
25°C
85°C
Pin Oscillator Frequency [kHz]
Pin Oscillator Frequency [kHz]
5.13.5.2 Typical Characteristics, Pin-Oscillator Frequency
100
1000
85°C
100
10
100
10
External Load Capacitance (incl. board etc.) [pF]
100
External Load Capacitance (incl. board etc.) [pF]
C002
VCC = 2.2 V
One output active at a time.
Figure 5-12. Typical Oscillation Frequency vs Load Capacitance
46
Specifications
C002
VCC = 3.0 V
One output active at a time.
Figure 5-13. Typical Oscillation Frequency vs Load Capacitance
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.6 Timer_A and Timer_B
Table 5-14. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
2.2 V,
3.0 V
tTA,cap
Timer_A capture timing
All capture inputs, Minimum pulse
duration required for capture
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
Table 5-15. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ± 10%
tTB,cap
Timer_B capture timing
All capture inputs, Minimum pulse
duration required for capture
VCC
2.2 V,
3.0 V
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
Specifications
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ns
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
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5.13.7 eUSCI
Table 5-16. eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
VCC
MIN
MAX
UNIT
16
MHz
4
MHz
MAX
UNIT
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
Table 5-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
UCGLITx = 0
UCGLITx = 1
UART receive deglitch time (1)
tt
2.2 V,
3.0 V
UCGLITx = 2
UCGLITx = 3
(1)
TYP
5
30
20
90
35
160
50
220
ns
Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. Thus the selected
deglitch time can limit the maximum usable baud rate. To make sure that pulses are correctly recognized, their duration should exceed
the maximum specification of the deglitch time.
Table 5-18. eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
feUSCI
CONDITIONS
VCC
MIN
MAX
UNIT
16
MHz
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
eUSCI input clock frequency
Table 5-19. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,LAG
STE lag time, Last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,ACC
STE access time, STE active to
SIMO data out
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
60
ns
tSTE,DIS
STE disable time, STE inactive to
SOMI high impedance
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
80
ns
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
48
2.2 V
40
3.0 V
40
2.2 V
0
3.0 V
0
UCxCLK
cycles
ns
ns
2.2 V
10
3.0 V
10
2.2 V
0
3.0 V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-14 and Figure 5-15.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-14 and Figure 5-15.
Specifications
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-14. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 5-15. SPI Master Mode, CKPH = 1
Specifications
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MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 5-20. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
50
VCC
MIN
2.2 V
50
3.0 V
40
2.2 V
2
3.0 V
3
TYP
MAX
ns
ns
2.2 V
50
3.0 V
40
2.2 V
50
3.0 V
45
2.2 V
4
3.0 V
4
2.2 V
7
3.0 V
7
35
35
3.0 V
0
ns
ns
3.0 V
0
ns
ns
2.2 V
2.2 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-16 and Figure 5-17.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams
inFigure 5-16 and Figure 5-17.
Specifications
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 1
Specifications
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51
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Table 5-21. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V, 3.0 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3.0 V
100
ns
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
tSU,STO
Setup time for STOP
tBUF
Bus free time between a STOP and
START condition
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
0
MAX
2.2 V, 3.0 V
2.2 V, 3.0 V
4.7
4.0
4.7
1.3
UCGLITx = 0
50
2.2 V, 3.0 V
UCGLITx = 3
µs
0.6
fSCL > 100 kHz
UCGLITx = 2
µs
0.6
fSCL = 100 kHz
UCGLITx = 1
µs
0.6
us
250
25
125
12.5
62.5
6.3
31.5
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2.2 V, 3.0 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-18. I2C Mode Timing
52
Specifications
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.8 Segment LCD Controller
Table 5-22. LCD_C Recommended Operating Conditions
PARAMETER
CONDITIONS
MIN
VCC,LCD_C,CP en,3.6
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1111b
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_C,CP en,3.3
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1100b
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_C,int.
bias
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,ext.
bias
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,VLCDEXT
Supply voltage range, external
LCD voltage, internal or external LCDCPEN = 0, VLCDEXT = 1
biasing, charge pump disabled
2.0
3.6
V
VLCDCAP
External LCD voltage at
LCDCAP, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor value on LCDCAP
when charge pump enabled
LCDCPEN = 1, VLCDx > 0000b (charge
pump enabled)
fACLK,in
ACLK input frequency range
fLCD
LCD frequency range
fFRAME = (1 / (2 × mux)) × fLCD with mux
= 1 (static) to 8
fFRAME,4mux
LCD frame frequency range
fFRAME,4mux(MAX) = (1 / (2 × 4)) ×
fLCD(MAX)
= (1 / (2 × 4)) × 1024 Hz
CPanel
Panel capacitance
fLCD = 1024 Hz,
all common lines equally loaded
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
NOM
MAX
4.7–20%
4.7
10+20%
µF
30
32.768
40
kHz
1024
Hz
128
Hz
10000
pF
0
2.4
VCC + 0.2
V
VR13
VR03 +
2/3 ×
(VR33 –
VR03)
VR33
V
VR03
VR03 +
1/3 ×
(VR33 –
VR03)
VR23
V
VR03
VR03 +
1/2 ×
(VR33 –
VR03)
VR33
V
VR23,1/3bias
Analog input voltage at R23
VR13,1/3bias
Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,
1/3 biasing
LCD2B = 0
VR13,1/2bias
Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,
1/2 biasing
LCD2B = 1
VR03
Analog input voltage at R03
R0EXT = 1
VSS
VLCD-VR03
Voltage difference between
VLCD and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF
External LCD reference voltage
applied at LCDREF
VLCDREFx = 01
0.8
V
1.0
VCC + 0.2
V
1.2
V
Specifications
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UNIT
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 5-23. LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VLCDx = 0000, VLCDEXT = 0
VLCD,1
LCDCPEN = 1, VLCDx = 0001b
2 V to 3.6 V
VLCD,2
LCDCPEN = 1, VLCDx = 0010b
2 V to 3.6 V
2.66
VLCD,3
LCDCPEN = 1, VLCDx = 0011b
2 V to 3.6 V
2.72
VLCD,4
LCDCPEN = 1, VLCDx = 0100b
2 V to 3.6 V
2.78
VLCD,5
LCDCPEN = 1, VLCDx = 0101b
2 V to 3.6 V
2.84
VLCD,6
LCDCPEN = 1, VLCDx = 0110b
2 V to 3.6 V
2.90
VLCD,7
LCDCPEN = 1, VLCDx = 0111b
2 V to 3.6 V
2.96
LCDCPEN = 1, VLCDx = 1000b
2 V to 3.6 V
3.02
VLCD,9
LCDCPEN = 1, VLCDx = 1001b
2 V to 3.6 V
3.08
VLCD,10
LCDCPEN = 1, VLCDx = 1010b
2 V to 3.6 V
3.14
VLCD,11
LCDCPEN = 1, VLCDx = 1011b
2 V to 3.6 V
3.20
VLCD,12
LCDCPEN = 1, VLCDx = 1100b
2 V to 3.6 V
3.26
VLCD,13
LCDCPEN = 1, VLCDx = 1101b
2.2 V to 3.6 V
3.32
VLCD,14
LCDCPEN = 1, VLCDx = 1110b
2.2 V to 3.6 V
3.38
LCDCPEN = 1, VLCDx = 1111b
2.2 V to 3.6 V
LCD voltage
VLCD,8
VLCD,15
2.4 V to 3.6 V
TYP
VLCD,0
MAX
UNIT
VCC
2.49
3.32
2.60
3.44
2.72
V
3.6
VLCD,7,0.8
LCD voltage with external
reference of 0.8 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b, VLCDREF = 0.8 V
2 V to 3.6 V
2.96 ×
0.8 V
V
VLCD,7,1.0
LCD voltage with external
reference of 1.0 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b, VLCDREF = 1.0 V
2 V to 3.6 V
2.96 ×
1.0 V
V
VLCD,7,1.2
LCD voltage with external
reference of 1.2 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b, VLCDREF = 1.2 V
2.2 V to 3.6 V
2.96 ×
1.2 V
V
ΔVLCD
Voltage difference between
consecutive VLCDx settings
ΔVLCD = VLCD,x - VLCD,x–1
with x = 0010b to 1111b
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111b
external, with decoupling capacitor on
DVCC supply ≥1 µF
2.2 V
ICC,Peak,CP
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111b
2.2 V
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111b
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 0, ILOAD = ±10 µA
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 0, ILOAD = ±10 µA
54
Specifications
40
60
80
600
2.2 V
100
µA
500
50
2.2 V
2.2 V
mV
ms
µA
10
kΩ
10
kΩ
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.9 ADC12
Table 5-24. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(Ax)
Analog input voltage
TEST CONDITIONS
(1)
MIN
All ADC12 analog input pins Ax
I(ADC12_B)
Operating supply current into
singleAVCC plus DVCC terminal (2)
ended mode
I(ADC12_B)
Operating supply current into
differential
AVCC and DVCC terminals (2)
mode
(3)
(3)
NOM
0
MAX
UNIT
AVCC
V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
145
199
2.2 V
140
190
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
175
245
2.2 V
170
230
2.2 V
10
15
>2V
0.5
4
<2V
1
10
CI
Input capacitance
Only one terminal Ax can be selected
at one time
RI
Input MUX ON resistance
0 V ≤ V(Ax) ≤ AVCC
(1)
(2)
(3)
VCC
µA
µA
pF
kΩ
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
The internal reference supply current is not included in current consumption parameter I(ADC12_B).
Typically about 60% of the total current into the AVCC and DVCC terminal is from AVCC.
Table 5-25. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fADC12CLK
Specified
performance
For specified performance of ADC12 linearity parameters
with ADC12PWRMD = 0.
If ADC12PWRMD = 1, the maximum is 1/4 of the value
shown here.
fADC12CLK
Reduced
performance
Linearity parameters have reduced performance
fADC12OSC
Internal
oscillator (1)
ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK
tCONVERT
Conversion time
REFON = 0, Internal oscillator
fADC12CLK = fADC12OSC from MODCLK, ADC12WINC = 0
Turn on settling
time of the ADC
See
tADC12OFF
Time ADC must
be off before
can be turned
on again
tADC12OFF must be met to make sure tADC12ON time holds
tSample
Sampling time
RS = 400 Ω, RI = 4 kΩ, CI = 15 pF, Cpext= 8 pF (4)
(4)
MIN
TYP
0.45
MAX
UNIT
5.4
MHz
32.768
4
4.8
2.6
kHz
5.4
MHz
3.5
µs
External fADC12CLK from ACLK, MCLK, or SMCLK,
ADC12SSEL ≠ 0
tADC12ON
(1)
(2)
(3)
VCC
(2)
(3)
100
100
ns
ns
1
µs
The ADC12OSC is sourced directly from MODOSC inside the UCS.
14 × ADC12DIV × 1/fADC12CLK. If ADC12WINC = 1, then 15 × ADC12DIV × 1/fADC12CLK
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signals are already
settled.
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS + RI) × (CI + Cpext), where n = ADC
resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.
Specifications
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
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Table 5-26. 12-Bit ADC, Linearity Parameters With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Number of no missing code
Resolution
output-code bits
TYP
MAX
UNIT
12
bits
EI
Integral linearity error (INL)
for differential input
1.2V ≤ VR+ - VR-≤ AVCC
±1.8
LSB
EI
Integral linearity error (INL)
for single ended inputs
1.2V ≤ VR+ - VR-≤ AVCC
±2.2
LSB
ED
Differential linearity error
(DNL)
+1.0
LSB
EO
Offset error (2)
mV
EG,ext
(3)
Gain error
–0.99
ADC12VRSEL = 0x2 or 0x4 without TLV calibration,
TLV calibration data can be used to improve the parameter (4)
±0.5
±1.5
With external voltage reference without internal buffer
(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,
TLV calibration data can be used to improve the parameter (4),
VR+ = 2.5 V, VR- = AVSS
±0.8
±2.5
LSB
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR- = AVSS
ET,ext
(1)
(2)
(3)
(4)
Total unadjusted error
±1
±20
With external voltage reference without internal buffer
(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,
TLV calibration data can be used to improve the parameter (4),
VR+ = 2.5 V, VR- = AVSS
±1.4
±3.5
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR- = AVSS
±1.4
LSB
±21.0
See Table 5-28 and Table 5-34 electrical sections for more information on internal reference performance and refer to the application
report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your
application with the choice of internal versus external reference.
Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
Offset increases as IR drop increases when VR- is AVSS.
For details, see the device descriptor table section in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx
Family User's Guide (SLAU367).
Table 5-27. 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SNR
ENOB
(1)
(2)
TEST CONDITIONS
Signal-to-noise ratio
Effective number of bits
(2)
MIN
TYP
VR+ = 2.5 V, VR- = AVSS
68
71
MAX
UNIT
dB
VR+ = 2.5 V, VR- = AVSS
10.7
11.2
bits
See Table 5-28 and Table 5-34 electrical sections for more information on internal reference performance and refer to the application
report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your
application with the choice of internal versus external reference.
ENOB = (SINAD – 1.76) / 6.02
Table 5-28. 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ENOB
(1)
(2)
56
Effective number of bits
TEST CONDITIONS
(2)
VR+ = 2.5V, VR- = AVSS
MIN
TYP
10.3
10.7
MAX
UNIT
Bits
See Table 5-34 electrical section for more information on internal reference performance and refer to the application report Designing
With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the
choice of internal versus external reference.
ENOB = (SINAD – 1.76) / 6.02
Specifications
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 5-29. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SNR
ENOB
(1)
(2)
TEST CONDITIONS
Signal-to-noise ratio
Effective number of bits
(2)
MIN
TYP
VR+ = 2.5 V, VR- = AVSS
64
68
MAX
UNIT
dB
VR+ = 2.5 V, VR- = AVSS
10.2
10.7
bits
See Table 5-30 and Table 5-34 electrical sections for more information on internal reference performance and refer to the application
report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your
application with the choice of internal versus external reference.
ENOB = (SINAD – 1.76) / 6.02
Table 5-30. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ENOB
(1)
(2)
TEST CONDITIONS
Effective number of bits
(2)
MIN
TYP
9.4
10.4
VR+ = 2.5 V, VR- = AVSS
MAX
UNIT
bits
See Table 5-34 electrical section for more information on internal reference performance and refer to the application report Designing
With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the
choice of internal versus external reference.
ENOB = (SINAD – 1.76) / 6.02
Table 5-31. 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ENOB
Effective number of bits (1)
MIN
TYP
MAX
10
UNIT
bits
ENOB = (SINAD – 1.76) / 6.02
Typical Temperature Sensor Voltage – mV
(1)
TEST CONDITIONS
Reduced performance with fADC12CLK from ACLK LFXT
32.768 KHz,
VR+ = 2.5 V, VR- = AVSS
950
900
850
800
750
700
650
600
550
500
-40
-20
0
20
40
60
80
Ambient Temperature – °C
Figure 5-19. Typical Temperature Sensor Voltage
Specifications
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MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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Table 5-32. 12-Bit ADC, Temperature Sensor and Built-In V1/2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSENSOR
See
(1) (2)
ADC12ON = 1, ADC12TCMAP = 1,
TA = 0°C
TCSENSOR
See
(2)
ADC12ON = 1, ADC12TCMAP = 1
tSENSOR(sample)
Sample time required if
ADCTCMAP = 1 and channel
(MAX - 1) is selected (3)
ADC12ON = 1, ADC12TCMAP = 1,
Error of conversion result ≤ 1 LSB
V1/2
AVCC voltage divider for
ADC12BATMAP = 1 on MAX input
channel
ADC12ON = 1, ADC12BATMAP = 1
IV
current for battery monitor during
sample time
ADC12ON = 1, ADC12BATMAP = 1
Sample time required if
ADC12BATMAP = 1 and channel
MAX is selected (4)
ADC12ON = 1, ADC12BATMAP = 1
1/2
tV 1/2 (sample)
(1)
(2)
(3)
(4)
VCC
MIN
TYP
MAX
UNIT
700
mV
2.5
mV/°C
30
µs
47.5%
50% 52.5%
38
72
1.7
µA
µs
The temperature sensor offset can be as much as ±30°C. A single-point calibration is recommended to minimize the offset error of the
built-in temperature sensor.
The device descriptor structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tV1/2(on) is included in the sampling time tV1/2(sample); no additional on time is needed.
Table 5-33. 12-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VR+
Positive external reference voltage input VeREF+
or VeREF- based on ADC12VRSEL bit
VR+ > VR-
1.2
AVCC
V
VR-
Negative external reference voltage input
VeREF+ or VeREF- based on ADC12VRSEL bit
VR+ > VR-
0
1.2
V
(VR+ - VR-)
Differential external reference voltage input
VR+ > VR-
1.2
AVCC
V
IVeREF+
IVeREF-
Static input current singled ended input mode
IVeREF+
IVeREF-
Static input current differential input mode
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
±10
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
±2.5
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, , ADC12PWRMD = 0
±20
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, , ADC12PWRMD = 1
±5
1.5
mA
3
mA
IVeREF+
Peak input current with single ended input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0
IVeREF+
Peak input current with differential input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1
CVeREF+/-
Capacitance at VeREF+ or VeREF- terminal
See
(1)
(2)
58
(2)
µA
uA
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
Two decoupling capacitors, 10 µF and 470 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_B. See also the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx
Family User's Guide (SLAU367).
Specifications
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.10 REF Module
Table 5-34. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF+
Positive built-in reference
voltage output
TEST CONDITIONS
2.5 ±1.5%
2.2 V
2.0 ±1.5%
REFVSEL = {0} for 1.2 V, REFON = 1
1.8 V
1.2 ±1.8%
VREF ADC BUF_INT buffer TA = 25°C , ADC ON, REFVSEL = {0},
offset (2)
REFON = 1, REFOUT = 0
VOS_BUF_EXT
VREF ADC BUF_EXT
buffer offset (3)
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal (4)
From 0.1 Hz to 10 Hz, REFVSEL = {0}
110
V
µV
–12
+12
mV
TA = 25°C, REFVSEL = {0} , REFOUT = 1,
REFON = 1 or ADC ON
–12
+12
mV
REFVSEL = {0} for 1.2 V
1.8
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
V
REFON = 1
3V
8
15
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0,
3V
225
355
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0
3V
1030
1660
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
3V
120
185
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
3V
545
895
ADC OFF, REFON=1, REFOUT=1,
REFVSEL = {0, 1, 2}
3V
1085
1780
VREF maximum load
current, VREF+ terminal
REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for
each reference level,
REFON = REFOUT = 1
ΔVout/ΔIo
(VREF+)
Load-current regulation,
VREF+ terminal
REFVSEL = {0, 1, 2},
IO(VREF+) = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
CVREF+/-
Capacitance at VREF+ and
VREF- terminals
REFON = REFOUT = 1
TCREF+
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1,
TA = –40°C to 85°C (5)
18
PSRR_DC
Power supply rejection ratio
(dc)
AVCC = AVCC (min) - AVCC(max), TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
120
PSRR_AC
Power supply rejection ratio
(ac)
dAVCC= 0.1 V at 1 kHz
3.0
tSETTLE
Settling time of reference
voltage (6)
AVCC = AVCC (min) - AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
75
(2)
(3)
(4)
(5)
(6)
UNIT
600
IO(VREF+)
(1)
MAX
2.7 V
VOS_BUF_INT
IREF+_ADC_BUF
TYP
REFVSEL = {1} for 2.0 V, REFON = 1
RMS noise at VREF (1)
Operating supply current
into AVCC terminal (4)
MIN
REFVSEL = {2} for 2.5 V, REFON = 1
Noise
IREF+
VCC
–1000
+10
µA
µA
µA
2500 µV/mA
0
100
pF
50 ppm/K
400
µV/V
mV/V
80
µs
Internal reference noise affects ADC performance when ADC uses internal reference. Refer to the application report Designing With the
MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the choice of
internal versus external reference.
Buffer offset affects ADC gain error and thus total unadjusted error.
Buffer offset affects ADC gain error and thus total unadjusted error.
The internal reference current is supplied through terminal AVCC.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
Specifications
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MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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5.13.11 Comparator
Table 5-35. Comparator_E
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
CEPWRMD = 00, CEON = 1, CERSx = 00
(fast)
IAVCC_COMP
Comparator operating
supply current into AVCC,
excludes reference
resistor ladder
CEPWRMD = 01, CEON = 1, CERSx = 00
(medium)
CEPWRMD = 10, CEON = 1, CERSx = 00
(slow), TA = 30°C
2.2 V,
3.0 V
TYP
MAX
11
20
9
17
µA
0.5
CEPWRMD = 10, CEON = 1, CERSx = 00
(slow), TA = 85°C
IAVCC_REF
VREF
Quiescent current of
resistor ladder into AVCC,
including REF module
current
Reference voltage level
VIC
Common mode input
range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
Series input resistance
tPD
Propagation delay,
response time
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 0
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 1
1.3
2.2 V,
3.0 V
12
15
5
7
µA
CERSx = 11, CEREFLx = 01, CEREFACC = 0
1.8 V
1.17
1.2
1.23
CERSx = 11, CEREFLx = 10, CEREFACC = 0
2.2 V
1.92
2.0
2.08
CERSx = 11, CEREFLx = 11, CEREFACC = 0
2.7 V
2.40
2.5
2.60
CERSx = 11, CEREFLx = 01, CEREFACC = 1
1.8 V
1.10
1.2
1.245
CERSx = 11, CEREFLx = 10, CEREFACC = 1
2.2 V
1.90
2.0
2.08
CERSx = 11, CEREFLx = 11, CEREFACC = 1
2.7 V
2.35
2.5
2.60
0
VCC-1
CEPWRMD = 00
–32
32
CEPWRMD = 01
–32
32
CEPWRMD = 10
–30
9
CEPWRMD = 10
9
ON - switch closed
tPD,filter
tEN_CMP
60
Comparator enable time
Specifications
V
mV
1
pF
3
50
kΩ
MΩ
CEPWRMD = 00, CEF = 0, Overdrive ≥ 20 mV
260
330
CEPWRMD = 01, CEF = 0, Overdrive ≥ 20 mV
350
460
CEPWRMD = 10, CEF = 0, Overdrive ≥ 20 mV
Propagation delay with
filter active
V
30
CEPWRMD = 00 or CEPWRMD = 01
OFF - switch open
UNIT
ns
15
µs
700
1000
ns
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
1.0
1.8
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 10
2.0
3.5
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
4.0
7.0
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 00
0.9
1.5
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 01
0.9
1.5
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 10
15
100
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
µs
µs
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Comparator_E (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tEN_CMP_VREF
tEN_CMP_RL
VCE_REF
TYP
MAX
CEON = 0 → 1, CEREFLX = 10, CERSx = 11,
REFON = 0, Overdrive ≥ 20 mV,
CEPWRMD = 00
TEST CONDITIONS
VCC
MIN
1
2
CEON = 0 → 1, CEREFLX = 10, CERSx = 11,
REFON = 0, Overdrive ≥ 20 mV,
CEPWRMD = 01
1
2
10
50
CEON = 0 → 1, CEREFLX = 10, CERSx = 11,
REFON = 0, Overdrive ≥ 20 mV,
Comparator and reference CEPWRMD = 10
ladder and reference
CEON = 0 → 1, CEREFLX = 10, CERSx = 10,
voltage enable time
REFON = 0, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV, CEPWRMD = 00
µs
2
5
CEON = 0 → 1, CEREFLX = 10, CERSx = 10,
REFON = 0, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV, CEPWRMD = 01
2
5
CEON = 0 → 1, CEREFLX = 10, CERSx = 10,
REFON = 0, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV, CEPWRMD = 10
10
50
CEON = 0 → 1, CEREFLX = 10, CERSx = 10,
REFON = 1, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV, CEPWRMD = 00
1
2
CEON = 0 → 1, CEREFLX = 10, CERSx = 10,
Comparator and reference
REFON = 1, CEREF0 = CEREF1 = 0x0F,
ladder enable time
Overdrive ≥ 20 mV, CEPWRMD = 01
1
2
CEON = 0 → 1, CEREFLX = 10, CERSx = 10,
REFON = 1, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV, CEPWRMD = 10
10
50
VIN ×
(n+1)
/32
VIN ×
(n+1.1)
/32
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
VIN ×
(n+0.9)
/32
Specifications
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
UNIT
µs
V
61
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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5.13.12 FRAM Controller
Table 5-36. FRAM Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
Data retention duration
IWRITE
Current to write into FRAM
IERASE
Erase current
tWRITE
tREAD
(1)
(2)
(3)
(4)
62
Write time
TYP
MAX
1015
Read and write endurance
tRetention
MIN
TJ = 25°C
100
TJ = 70°C
40
TJ = 85°C
10
UNIT
cycles
years
IREAD (1)
nA
N/A (2)
nA
(3)
ns
tREAD
Read time, NWAITSx=0
1/fSYSTEM (4)
ns
Read time, NWAITSx=1
2/fSYSTEM (4)
ns
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption numbers IAM,FRAM.
N/A = not applicable. FRAM does not require a special erase sequence.
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
Specifications
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
5.13.13 Emulation and Debug
Table 5-37. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
40
UNIT
IJTAG
Supply current adder when JTAG active (but not clocked)
2.2 V, 3.0 V
100
μA
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3.0 V
0
10
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3.0 V
0.04
15
μs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V, 3.0 V
110
μs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
15
100
μs
fTCK
TCK input frequency - 4-wire JTAG (2)
2.2 V
0
16
MHz
3.0 V
0
16
MHz
Rinternal
Internal pulldown resistance on TEST
2.2 V, 3.0 V
20
50
kΩ
fTCLK
TCLK/MCLK frequency during JTAG access, no FRAM access
(limited by fSYSTEM)
16
MHz
tTCLK,Low/High
TCLK low or high clock pulse duration, no FRAM access
25
ns
fTCLK,FRAM
TCLK/MCLK frequency during JTAG access, including FRAM access
(limited by fSYSTEM with no FRAM wait states)
4
MHz
tTCLK,FRAM,Low/High
TCLK low or high clock pulse duration, including FRAM accesses
(1)
(2)
35
100
ns
Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
63
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
6 Detailed Description
6.1
Overview
The
Texas
Instruments
MSP430FR697x(1),
MSP430FR687x(1),
MSP430FR692x(1),
and
MSP430FR682x(1) family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals. The architecture, combined with seven low-power modes is optimized to
achieve extended battery life for example in portable measurement applications. The devices features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The devices are microcontroller configurations with up to five 16-bit timers, Comparator,
universal serial communication interfaces (eUSCI) that supports UART, SPI, and I2C, a hardware
multiplier, an AES accelerator, DMA, a real-time clock module with alarm capabilities, up to 52 I/O pins,
and a high-performance 12-bit analog-to-digital converter (ADC). The MSP430FR6xxx(1) devices also
include an LCD module with contrast control for displays with up to 116 segments.
6.2
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. CPUxV2 can also operate on address-word data (20-bit).
64
Detailed Description
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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6.3
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Operating Modes
The device has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from
low-power modes LPM0 through LPM4, service the request, and restore back to the low-power mode on return from the interrupt program. Lowpower modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
Table 6-1. Operating Modes
Mode
AM
Active
Maximum System Clock
Typical Current Consumption,
25°C
LPM0
Active,
FRAM Off
(1)
16 MHz
103
µA/MHz
Typical Wake-up time
65 µA/MHz
N/A
LPM1
LPM2
LPM3
LPM4
LPM3.5
CPU Off
Standby
Standby
Off
RTC-only
16 MHz
16 MHz
50 kHz
50 kHz
0
75 µA at
1 MHz
40 µA at
1 MHz
0.9 µA
0.4 µA
0.3 µA
0.35 µA
0.2 µA
0.02 µA
instant.
6 µs
6 µs
7 µs
7 µs
250 µs
250 µs
1000 µs
LF
RTC
I/O
Comp
_
I/O
Comp
RTC
I/O
_
I/O
CPU Off
(2)
(3)
LPM4.5
Shutdown
without
SVS
Shutdown
with SVS
50 kHz
0
(3)
Wake-up events
N/A
all
all
LF
RTC
I/O
Comp
CPU
on
off
off
off
off
off
reset
reset
standby (or off
(1)
)
off
off
off
off
off
off
available
available
off
off
off
reset
reset
FRAM
High-frequency peripherals
off (1)
on
available
Low-frequency peripherals
available
available
available
available
available
(4)
Unclocked peripherals (5)
available
available
available
available
available
(4)
on
off
off
off
off
off
off
MCLK
SMCLK
opt.
(6)
opt.
(6)
opt.
(6)
ACLK
on
on
on
on
Full retention
yes
yes
yes
yes
SVS
always
always
always
opt.
Brownout
always
always
always
always
(8)
on
off
RTC
reset
reset
reset
off
off
off
off
off
off
off
off
available
off
yes
(7)
yes
(7)
opt.
(8)
opt.
(8)
always
(4)
always
no
opt.
no
(8)
always
on
(9)
off
(10)
always
(1)
(2)
FRAM disabled in FRAM controller
Disabling the FRAM via the FRAM controller decreases the LPM current consumption, but the wake-up time can increase. If the wake-up is for FRAM access (for example, to fetch an
interrupt vector), wake-up time is increased. If the wake-up is for a non-FRAM operation (for example, DMA transfer to RAM), wake-up time is not increased.
(3) All clocks disabled
(4) See Section 6.3.1, which describes the use of peripherals in LPM3 and LPM4.
(5) "Unclocked peripherals" are peripherals that do not require a clock source to operate; for example, the comparator and REF, or the eUSCI when operated as an SPI slave.
(6) Controlled by SMCLKOFF
(7) Using the RAM Controller, the RAM can be completely powered down to save leakage; however, all data is lost.
(8) Activated SVS (SVSHE = 1) results in higher current consumption. SVS not included in typical current consumption.
(9) SVSHE = 1
(10) SVSHE = 0
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6.3.1
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Peripherals in LPM3 and LPM4
Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are even
operational in LPM4 because they do not require a clock to operate (for example, the comparator).
Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply
current contribution but also due to an additional idle current. To limit the idle current adder, certain
peripherals are group together. To achieve optimal current consumption try to use modules within one
group and to limit the number of groups with active modules. The grouping is shown in Table 6-2. Modules
not listed there are either already included in the standard LPM3 current consumption specifications or
cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C); refer to the IIDLE current parameters in the electrical characteristics section for details.
Table 6-2. Peripheral Groups
66
Detailed Description
Group A
Group B
Group C
Timer TA0
Timer TA2
Timer TA3
Timer TA1
Timer B0
eUSCI_A1
Comparator
eUSCI_A0
LCD_C
ADC12_B
eUSCI_B0
REF_A
eUSCI_B1
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6.4
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address, and signatures are located in the address range
0FFFFh to 0FF80h. Table 6-3 summarizes the content of this address range.
The power-up start address or reset vector is located at 0FFFFh to 0FFFEh. It contains the 16-bit address
pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh extending to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature)
The signatures are located at 0FF80h extending to higher addresses. Signatures are evaluated during
device start-up. Starting from address 0FF88h extending to higher addresses a JTAG password can
programmed. The password can extend into the interrupt vector locations using the interrupt vector
addresses as additional bits for the password.
Refer to the chapter "System Resets, Interrupts, and Operating Modes, System Control Module (SYS)" in
the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide
(SLAU367) for details.
Table 6-3. Interrupt Sources, Flags, Vectors, and Signatures
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up, Brownout, Supply
Supervisor
External Reset RST
Watchdog Time-out (Watchdog
mode)
WDT, FRCTL MPU, CS, PMM
Password Violation
FRAM uncorrectable bit error
detection
FRAM access time error
MPU segment violation
Software POR, BOR
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
ACCTEIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
Reset
0FFFEh
highest
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM bit error detection
MPU segment violation
VMAIFG
JMBNIFG, JMBOUTIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
Comparator_E
Comparator_E interrupt flags
(CEIV) (1)
Maskable
0FFF8h
Timer_B TB0
TB0CCR0.CCIFG
Maskable
0FFF6h
Timer_B TB0
TB0CCR1.CCIFG ... TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) (1)
Maskable
0FFF4h
Watchdog Timer (Interval Timer
Mode)
WDTIFG
Maskable
0FFF2h
Reserved
Reserved
Maskable
0FFF0h
(1)
(2)
(3)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
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Table 6-3. Interrupt Sources, Flags, Vectors, and Signatures (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
eUSCI_A0 Receive or Transmit
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA0IV) (1)
Maskable
0FFEEh
eUSCI_B0 Receive or Transmit
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV) (1)
Maskable
0FFECh
ADC12_B
ADC12IFG0 ... ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG
(ADC12IV) (1) (4)
Maskable
0FFEAh
Timer_A TA0
TA0CCR0.CCIFG
Maskable
0FFE8h
Timer_A TA0
TA0CCR1.CCIFG ... TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV) (1)
Maskable
0FFE6h
eUSCI_A1 Receive or Transmit
UCA1IFG:UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA1IV) (1)
Maskable
0FFE4h
eUSCI_B1 Receive or Transmit
(Reserved on MSP430FR692x)
UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB1IV) (1)
Maskable
0FFE2h
DMA
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
(DMAIV) (1)
Maskable
0FFE0h
Timer_A TA1
TA1CCR0.CCIFG
Maskable
0FFDEh
Timer_A TA1
TA1CCR1.CCIFG ... TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV) (1)
Maskable
0FFDCh
I/O Port P1
P1IFG.0 to P1IFG.7
(P1IV) (1)
Maskable
0FFDAh
Timer_A TA2
TA2CCR0.CCIFG
Maskable
0FFD8h
Timer_A TA2
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV) (1)
Maskable
0FFD6h
I/O Port P2
P2IFG.0 to P2IFG.7
(P2IV) (1)
Maskable
0FFD4h
Timer_A TA3
TA3CCR0.CCIFG
Maskable
0FFD2h
Timer_A TA3
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV) (1)
Maskable
0FFD0h
I/O Port P3
P3IFG.0 to P3IFG.7
(P3IV) (1)
Maskable
0FFCEh
I/O Port P4
P4IFG.0 to P4IFG.7
(P4IV) (1)
Maskable
0FFCCh
Maskable
0FFCAh
LCD_C
(4)
68
LCD_C Interrupt Flags (LCDCIV)
(1)
RTC_C
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) (1)
Maskable
0FFC8h
AES
AESRDYIFG
Maskable
0FFC6h
PRIORITY
lowest
Only on devices with ADC, otherwise reserved.
Detailed Description
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-3. Interrupt Sources, Flags, Vectors, and Signatures (continued)
INTERRUPT SOURCE
SYSTEM
INTERRUPT
INTERRUPT FLAG
WORD
ADDRESS
PRIORITY
0FFC4h
Reserved
Reserved
(5)
⋮
0FF8Ch
(5)
0FF8Ah
(5) (7)
0FF88h
IP Encapsulation Signature2
IP Encapsulation Signature1
Signatures
(5)
(6)
(7)
(6)
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
May contain a JTAG password required to enable JTAG access to the device.
Signatures are evaluated during device start-up. See the "System Resets, Interrupts, and Operating Modes, System Control Module
(SYS)" chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide (SLAU367) for
details.
Must not contain 0AAAAh if used as JTAG password.
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6.5
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Bootstrap Loader (BSL)
The BSL enables programming of the FRAM or RAM using a UART serial interface (FRxxxx devices) or
an I2C interface (FRxxxx1 devices). Access to the device memory via the BSL is protected by an userdefined password. Use of the BSL requires four pins as shown in Table 6-4. BSL entry requires a specific
entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the
features of the BSL and its implementation, see the MSP430 Memory Programming User's Guide
(SLAU265).
Table 6-4. BSL Pin Requirements and Functions
6.6
6.6.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
BSL_TX
Devices with UART BSL (FRxxxx):
Data transmit
BSL_RX
Devices with UART BSL (FRxxxx):
Data receive
BSL_DAT
Devices with I2C BSL (FRxxxx1):
Data
BSL_CLK
Devices with I2C BSL (FRxxxx1):
Clock
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 65. For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface
and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).
Table 6-5. JTAG Pin Requirements and Functions
6.6.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
The Spy-Bi-Wire interface pin requirements are shown in Table 6-6. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278).
70
Detailed Description
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MSP430FR6820
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Table 6-6. Spy-Bi-Wire Pin Requirements and Functions
6.7
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
FRAM
The FRAM can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:
• Ultra-low-power ultra-fast-write nonvolatile memory
• Byte and word access capability
• Programmable and automated wait-state generation
• Error correction coding (ECC)
NOTE
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow
described in the "Wait State Control" section of the "FRAM Controller (FRCTRL)"
chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and
MSP430FR69xx Family User's Guide (SLAU367).
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
the application report MSP430™ FRAM Technology – How To and Best Practices (SLAA628).
6.8
RAM
The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to
save leakage; however, all data is lost during shutdown.
6.9
Tiny RAM
Twenty-six bytes of Tiny RAM are provided in addition to the complete RAM (see Table 6-35). This
memory is always available even in LPM3 and LPM4, while the complete RAM can be powered down in
LPM3 and LPM4. Tiny RAM can be used to hold data or a very small stack when the complete RAM
memory is powered down in LPM3 and LPM4. Note that Tiny RAM is not available in LPMx.5.
6.10 Memory Protection Unit (MPU) Including IP Encapsulation
The FRAM can be protected by the MPU from inadvertent CPU execution and read or write access.
Features of the MPU include:
• IP encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP
software) in steps of 1KB.
• Main memory partionioning that can be configured in up to three segments in steps of 1KB.
• The access rights for each main and information memory segment can be indivually selected.
• Access violation flags with interrupt capability for easy servicing of access violations.
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6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide (SLAU367).
6.11.1 Digital I/O
There are up to nine 8-bit I/O ports implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wakeup input capability is available for all pins of
ports P1, P2, P3, and P4.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive touch functionality is supported on all pins of ports P1, P2, P3, P4, P5, P6, P7, P9, and PJ.
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross-currents during start-up of the device all port pins are highimpedance with Schmitt triggers and their module functions disabled. To enable the
I/O functionality after a BOR reset the ports must be configured first and then the
LOCKLPM5 bit must be cleared. For details refer to the "Digital I/O" chapter,
section "Configuration After Reset" in the MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, and MSP430FR69xx Family User's Guide (SLAU367).
6.11.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-lowpower low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
The clock system module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency
oscillator (VLO), or a digital external low frequency (<50kHz) clock source.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal digitally-controlled oscillator DCO, a 32-kHz watch crystal (LFXT1), the
internal low-frequency oscillator (VLO), or a digital external clock source.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
6.11.3 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device . The PMM
also includes the supply voltage supervisor (SVS) and brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS circuitry detects if the supply voltage drops below a safe level. SVS circuitry is available on the
primary and core supplies.
72
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MSP430FR6820
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6.11.4 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and
unsigned multiplication as well as signed and unsigned multiply and accumulate operations.
6.11.5 Real-Time Clock (RTC_C)
The RTC_C module contains an integrated real-time clock (RTC) with the following features implemented:
• Calendar mode with leap year correction
• General-purpose counter mode
The internal calendar compensates for months with fewer than 31 days and includes leap year correction.
The RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is
available in LPM3.5 modes to minimize power consumption.
6.11.6 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
Table 6-7. WDT_A Clocks
WDTSSELx
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
LFMODOSC
6.11.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
and power-up clear handling, NMI source selection and management, reset interrupt vector generators,
bootstrap loader entry mechanisms, and configuration management (device descriptors). Also included is
a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the application.
Table 6-8. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
SYSRSTIV , System Reset
019Eh
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
PRIORITY
Highest
Detailed Description
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MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
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Table 6-8. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTER
SYSSNIV , System NMI
SYSUNIV, User NMI
74
Detailed Description
ADDRESS
019Ch
019Ah
INTERRUPT EVENT
VALUE
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
MPUPW MPU password violation (PUC)
22h
CSPW CS password violation (PUC)
24h
MPUSEGPIFG encapsulated IP memory segment
violation (PUC)
26h
MPUSEGIIFG information memory segment violation
(PUC)
28h
MPUSEG1IFG segment 1 memory violation (PUC)
2Ah
MPUSEG2IFG segment 2 memory violation (PUC)
2Ch
MPUSEG3IFG sgement 3 memory violation (PUC)
2Eh
ACCTEIFG access time error (PUC)
30h
Reserved
32h to 3Eh
No interrupt pending
00h
Reserved
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
MPUSEGPIFG encapsulated IP memory segment
violation
08h
MPUSEGIIFG information memory segment violation
0Ah
MPUSEG1IFG segment 1 memory violation
0Ch
MPUSEG2IFG segment 2 memory violation
0Eh
MPUSEG3IFG segment 3 memory violation
10h
VMAIFG Vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIFG NMI pin
02h
OFIFG oscillator fault
04h
Reserved
06h
Reserved
08h
Reserved
0Ah to 1Eh
PRIORITY
Lowest
Highest
Lowest
Highest
Lowest
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
Table 6-9. DMA Trigger Assignments
TRIGGER
CHANNEL 0
CHANNEL 1
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TA2 CCR0 CCIFG
TA2 CCR0 CCIFG
TA2 CCR0 CCIFG
6
TA3 CCR0 CCIFG
TA3 CCR0 CCIFG
TA3 CCR0 CCIFG
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
CHANNEL 2
Reserved
9
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
AES Trigger 0 (2)
AES Trigger 0 (2)
AES Trigger 0 (2)
12
AES Trigger 1 (2)
AES Trigger 1 (2)
AES Trigger 1 (2)
13
AES Trigger 2
(2)
(2)
AES Trigger 2 (2)
14
UCA0RXIFG
AES Trigger 2
UCA0RXIFG
UCA0RXIFG
15
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
16
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
17
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
18
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
19
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
20
UCB0RXIFG1 (I2C)
UCB0RXIFG1 (I2C)
UCB0RXIFG1 (I2C)
21
(1)
(2)
(3)
(1)
2
UCB0TXIFG1 (I C)
2
2
UCB0TXIFG1 (I2C)
2
UCB0TXIFG1 (I C)
22
UCB0RXIFG2 (I C)
UCB0RXIFG2 (I C)
UCB0RXIFG2 (I2C)
23
UCB0TXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB0TXIFG2 (I2C)
24
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
25
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
26
ADC12 end of conversion (3)
ADC12 end of conversion (3)
ADC12 end of
conversion (3)
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
If a reserved trigger source is selected, no trigger is generated.
Only on devices with AES. Reserved on devices without AES.
Only on devices with ADC. Reserved on devices without ADC.
Detailed Description
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
75
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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6.11.9 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3-pin or 4-pin) and I2C.
Two eUSCI_A modules and two eUSCI_B module are implemented.
6.11.10 Timer_A TA0, Timer_A TA1
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. Each
can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-10. Timer_A TA0 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P1.2 or P7.0
TA0CLK
TACLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
OUTPUT PORT PIN
SIGNAL
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P1.2 or P7.0
TA0CLK
INCLK
P1.5
TA0.0
CCI0A
P7.1
TA0.0
CCI0B
DVSS
GND
DVCC
VCC
TA0.1
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
ADC12(internal) (1)
ADC12SHSx = {1}
TA0.2
CCI2A
P1.1
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
P1.0 or P1.6 or
P7.2
P1.1 or P1.7 or
P7.3
(1)
Only on devices with ADC.
76
Detailed Description
N/A
P1.5
CCR0
TA0
P7.1
TA0.0
P1.0
P1.6
CCR1
CCR2
TA1
TA2
TA0.1
P7.2
TA0.2
P1.7
P7.3
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-11. Timer_A TA1 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P1.1 or P4.4
TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P1.1 or P4.4
TA1CLK
INCLK
P1.4 or P4.5
TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
TA1.1
CCI1A
COUT (internal)
CCI1B
DVSS
GND
P1.2 or P3.3 or
P4.6
MODULE
OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
OUTPUT PORT PIN
SIGNAL
N/A
P1.4
CCR0
TA0
TA1.0
P4.5
P1.2
P4.6
CCR1
TA1
TA1.1
P3.3
DVCC
VCC
ADC12(internal) (1)
ADC12SHSx = {4}
TA1.2
CCI2A
P1.3
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
P1.3 or P4.7
(1)
MODULE
BLOCK
CCR2
TA2
TA1.2
P4.7
Only on devices with ADC.
6.11.11 Timer_A TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers each and with internal
connections only. It can support multiple capture/compares, PWM outputs, and interval timing. It has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and
from each of the capture/compare registers.
Table 6-12. Timer_A TA2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
COUT (internal)
TACLK
(1)
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
from Capacitive Touch
I/O 0 (internal)
INCLK
TA3 CCR0 output
(internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
DVCC
VCC
from Capacitive Touch
I/O 0 (internal)
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT SIGNAL
TA3 CCI0A input
CCR0
TA0
ADC12(internal) (1)
ADC12SHSx = {5}
CCR1
TA1
Only on devices with ADC.
Detailed Description
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
77
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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6.11.12 Timer_A TA3
TA3 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers each and with internal
connections only. It can support multiple capture/compares, PWM outputs, and interval timing. It has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and
from each of the capture/compare registers.
Table 6-13. Timer_A TA3 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
COUT (internal)
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
from Capacitive Touch
I/O 1 (internal)
INCLK
TA2 CCR0 output
(internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
DVCC
VCC
From Capacitive Touch
I/O 1 (internal)
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
DVSS
CCI2A
P3.0
DVSS (FR692x(1) and
FR682x(1) 64‑pin
package)
CCI2B
DVSS
GND
DVCC
VCC
DVSS
CCI3A
P3.1
DVSS (FR692x(1) and
FR682x(1) 64‑pin
package)
CCI3B
DVSS
GND
DVCC
VCC
DVSS
CCI4A
P3.2
DVSS (FR692x(1) and
FR682x(1) 64‑pin
package)
CCI4B
DVSS
GND
DVCC
VCC
(1)
Only on devices with ADC.
78
Detailed Description
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT SIGNAL
TA2 CCI0A input
CCR0
TA0
ADC12 (internal) (1)
ADC12SHSx = {6}
CCR1
CCR2
CCR3
CCR4
TA1
TA2
P3.0 (Note: Not available for
FR692x(1) and FR682x(1)
64-pin package devices)
TA3
P3.1 (Note: Not available for
FR692x(1) and FR682x(1)
64-pin package devices)
TA4
P3.2 (Note: Not available for
FR692x(1) and FR682x(1)
64-pin package devices)
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.13 Timer_B TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers each. It can support
multiple capture/compares, PWM outputs, and interval timing. It has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-14. Timer_B TB0 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P2.0 or P3.3 or
P5.7
TB0CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P2.0 or P3.3 or
P5.7
TB0CLK
INCLK
P3.4
TB0.0
CCI0A
P6.4
TB0.0
CCI0B
P3.5 or P6.5
DVSS
GND
DVCC
VCC
TB0.1
CCI1A
COUT (internal)
CCI1B
DVSS
P3.6 or P6.6
P3.7
P2.2
P2.1
P2.0
(1)
GND
DVCC
VCC
TB0.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
DVSS
CCI3A
TB0.3
CCI3B
DVSS
GND
DVCC
VCC
DVSS
CCI4A
TB0.4
CCI4B
DVSS
GND
DVCC
VCC
DVSS
CCI5A
TB0.5
CCI5B
DVSS
GND
DVCC
VCC
DVSS
CCI6A
TB0.6
CCI6B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
OUTPUT PORT PIN
SIGNAL
N/A
P3.4
P6.4
CCR0
TB0
TB0.0
ADC12 (internal) (1)
ADC12SHSx = {2}
P3.5
P6.5
CCR1
TB1
TB0.1
ADC12 (internal) (1)
ADC12SHSx = {3}
P3.6
CCR2
TB2
TB0.2
CCR3
TB3
TB0.3
CCR4
TB4
TB0.4
CCR5
TB5
TB0.5
CCR6
TB6
TB0.6
P6.6
P3.7
P2.2
P2.1
P2.0
Only on devices with ADC.
Detailed Description
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MSP430FR6820
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79
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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6.11.14 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 12-bit SAR core, sample select control, reference generator and a
conversion result buffer. A window comparator with a lower and upper limit allows CPU independent result
monitoring with three window comparator interrupt flags.
Table 6-15 summarizes the available external trigger sources.
Table 6-16 lists the available multiplexing between internal and external analog inputs.
Table 6-15. ADC12_B Trigger Signal Connections
ADC12SHSx
CONNECTED TRIGGER
SOURCE
BINARY
DECIMAL
000
0
Software (ADC12SC)
001
1
Timer_A TA0 CCR1 output
010
2
Timer_B TB0 CCR0 output
011
3
Timer_B TB0 CCR1 output
100
4
Timer_A TA1 CCR1 output
101
5
Timer_A TA2 CCR1 output
110
6
Timer_A TA3 CCR1 output
111
7
Reserved (DVSS)
Table 6-16. ADC12_B External and Internal Signal Mapping
(1)
CONTROL BIT
EXTERNAL
(CONTROL BIT = 0)
INTERNAL
(CONTROL BIT = 1)
ADC12BATMAP
A31
Battery monitor
ADC12TCMAP
A30
Temperature sensor
ADC12CH0MAP
A29
N/A (1)
ADC12CH1MAP
A28
N/A (1)
ADC12CH2MAP
A27
N/A (1)
ADC12CH3MAP
A26
N/A (1)
N/A: No internal signal available on this device.
6.11.15 Comparator_E
The primary function of the Comparator_E module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.11.16 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 signature is based on the CRC-CCITT standard.
6.11.17 CRC32
The CRC32 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC32 signature is based on the ISO 3309 standard.
6.11.18 AES256 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit, 192-bit, or
256-bit keys according to the advanced encryption standard (AES) (FIPS PUB 197) in hardware.
80
Detailed Description
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.19 True Random Seed
The Device Descriptor Info (TLV) (see Section 6.12) contains a 128-bit true random seed that can be used
to implement a deterministic random-number generator.
6.11.20 Shared Reference (REF_A)
The REF_A module is responsible for generation of all critical reference voltages that can be used by the
various analog peripherals in the device.
6.11.21 LCD_C
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static, and 2-mux up to 4-mux LCDs are
supported. The module can provide an LCD voltage independent of the supply voltage with its integrated
charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The
module also provides an automatic blinking capability for individual segments in static, 2-mux, 3-mux, and
4-mux modes.
6.11.22 Embedded Emulation
6.11.22.1 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
6.11.22.2 EnergyTrace++™ Technology
The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology
allows you to observe information about the internal states of the microcontroller. These states include the
CPU Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of
the clock source), and the low-power mode currently in use. These states can always be read by a debug
tool, even when the microcontroller sleeps in LPMx.5 modes.
The activity of the following modules can be observed:
• MPY is calculating.
• WDT is counting.
• RTC is counting.
• ADC: a sequence, sample, or conversion is active.
• REF: REFBG or REFGEN active and BG in static mode.
• COMP is on.
• AES is encrypting or decrypting.
• eUSCI_A0 is transferring (receiving or transmitting) data.
• eUSCI_A1 is transferring (receiving or transmitting) data.
• eUSCI_B0 is transferring (receiving or transmitting) data.
• eUSCI_B1 is transferring (receiving or transmitting) data.
• TB0 is counting.
• TA0 is counting.
• TA1 is counting.
Detailed Description
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
•
•
•
82
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TA2 is counting.
TA3 is counting.
LCD: timing generator is active.
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23 Input/Output Schematics
6.11.23.1 Digital I/O Functionality Port P1, P2, P3, P4, P5, P6, P7, and P9
The port pins provide the following features:
• Interrupt and wake-up from LPMx.5 capability for ports P1, P2, P3, and P4
• Capacitive touch functionality (see Section 6.11.23.2)
• Up to three digital module input and/or output functions
• LCD segment functionality (not all pins, package dependent)
The features and the corresponding control logic (besides the Capacitive Touch logic) is shown in
Figure 6-1. It is applicable for all port pins P1.0 through P9.7, unless a dedicated schematic is available in
the following sections. The module functions provided per pin and whether the direction is controlled by
the module or by the port direction register for the selected secondary function are described in the
following pin function tables.
Pad Logic
Sz
LCDSz
PxREN.y
PxDIR.y
(B)
From module 1
00
01
(B)
10
(B)
11
From module 2
From module 3
PxOUT.y
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
From module 3
11
Px.y/Mod1/Mod2/Mod3/Sz
PxSEL1.y
PxSEL0.y
PxIN.y
(A)
To module 1
(A)
To module 2
(A)
To module 3
A.
B.
The direction is either controlled by connected module or by the corresponding PxDIR.y bit. Refer to pin function
tables.
The inputs from several pins towards a module are ORed together.
Functional representation only.
Figure 6-1. General Port Pin Schematic
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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6.11.23.2 Capacitive Touch Functionality Port P1, P2, P3, P4, P5, P6, P7, P9, and PJ
All port pins provide the capacitive touch functionality as shown in Figure 6-2. The capacitive touch
functionality is controlled using the capacitive touch I/O control registers CAPTIO0CTL and CAPTIO1CTL
as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide (SLAU367). The capacitive touch functionality is not shown in the other pin schematics.
Analog Enable
PxREN.y
Capacitive Touch Enable 0
Capacitive Touch Enable 1
DVSS
0
DVCC
1
1
Direction Control
PxOUT.y
0
1
Output Signal
Px.y
Input Signal
Q
D
EN
Capacitive Touch Signal 0
Capacitive Touch Signal 1
Functional representation only.
Figure 6-2. Capacitive Touch I/O Functionality
84
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.3 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
Pad Logic
P1REN.x
P1DIR.x
00
01
10
11
P1OUT.x
00
DVSS
01
DVSS
10
DVSS
11
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
P1.0/TA0.1/DMAE0/RTCCLK/
A0/C0/VREF-/VeREFP1.1/TA0.2/TA1CLK/COUT/
A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/A3/C3
P1SEL1.x
P1SEL0.x
P1IN.x
Bus
Keeper
Detailed Description
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MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-17. Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/
VREF-/VeREF-
x
0
FUNCTION
P1.0 (I/O)
1
2
3
(3)
(4)
(5)
86
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
DMAE0
0
RTCCLK (2)
1
P1.1 (I/O)
TA0.CCI2A
0
TA0.2
1
TA1CLK
0
COUT (5)
1
P1.2 (I/O)
(3) (4)
TA1.CCI1A
0
TA1.1
1
TA0CLK
0
COUT (5)
1
(3) (4)
P1.3 (I/O)
TA1.CCI2A
0
TA1.2
1
N/A
0
Internally tied to DVSS
1
A3, C3
(1)
(2)
P1SEL0.x
0
1
A2, C2
P1.3/TA1.2/A3/C3
P1SEL1.x
TA0.1
A1, C1, VREF+, VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1DIR.x
0
(3) (4)
(3) (4)
(1)
I: 0; O: 1
TA0.CCI1A
A0, C0, VREF-, VeREFP1.1/TA0.2/TA1CLK/COUT/A1/C1/
VREF+/VeREF+
CONTROL BITS OR SIGNALS
X
X = Don't care
NOTE: Do not use this pin as RTCCLK output if the DMAE0 functionality is used on any other pin. Select an alternative RTCCLK output
pin.
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
NOTE: Do not use this pin as COUT output if the TA1CLK functionality is used on any other pin. Select an alternative COUT output pin.
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.4 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
Pin Schematic: see Figure 6-1.
Table 6-18. Port P1 (P1.4 to P1.7) Pin Functions
PIN NAME (P1.x)
x
P1.4/UCB0CLK/UCA0STE/TA1.0/Sz
4
FUNCTION
P1.4 (I/O)
UCB0CLK
UCA0STE
5
0
X
(2)
0
1
0
X
(3)
1
0
0
1
1
0
X
X
X
1
P1.5 (I/O)
I: 0; O: 1
0
0
0
X
(2)
0
1
0
X
(3)
1
0
0
1
1
0
TA0.CCI0A
0
TA0.0
1
(4)
X
X
X
1
P1.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
N/A
0
Internally tied to DVSS
1
TA0.CCI1A
0
TA0.1
1
(4)
X
X
X
1
P1.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
UCB0SOMI/UCB0SCL
X
(2)
N/A
0
Internally tied to DVSS
1
TA0.CCI2A
0
TA0.2
1
(4)
X
Sz
(1)
(2)
(3)
(4)
LCDSz
0
(4)
UCB0SIMO/UCB0SDA
7
P1SEL0.x
0
1
Sz
P1.7/UCB0SOMI/UCB0SCL/TA0.2/
Sz
P1SEL1.x
TA1.0
UCA0CLK
6
P1DIR.x
0
UCB0STE
P1.6/UCB0SIMO/UCB0SDA/TA0.1/
Sz
(1)
I: 0; O: 1
TA1.CCI0A
Sz
P1.5/UCB0STE/UCA0CLK/TA0.0/Sz
CONTROL BITS OR SIGNALS
X = Don't care
Direction controlled by eUSCI_B0 module.
Direction controlled by eUSCI_A0 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
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MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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6.11.23.5 Port P2, P2.0 to P2.3, Input/Output With Schmitt Trigger
Pin Schematic: see Figure 6-1.
Table 6-19. Port P2 (P2.0 to P2.3) Pin Functions
PIN NAME (P2.x)
P2.0/UCA0SIMO/UCA0TXD/TB0.6/
TB0CLK/Sz
x
0
FUNCTION
P2.0 (I/O)
UCA0SIMO/UCA0TXD
1
1
0
1
0
0
1
1
0
(2)
Internally tied to DVSS
1
(3)
X
X
X
1
P2.1 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
TB0.CCI5B
0
TB0.5
1
DMA0E
0
Internally tied to DVSS
1
(3)
X
X
X
1
P2.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
TB0.CCI4B
0
TB0.4
1
N/A
0
RTCCLK
1
(3)
X
X
X
1
P2.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
X
(2)
TB0OUTH
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
Sz
88
0
0
X
0
UCA0STE
(1)
(2)
(3)
LCDSz
0
TB0CLK
Sz
3
P2SEL0.x
0
1
UCA0CLK
P2.3/UCA0STE/TB0OUTH/Sz
P2SEL1.x
0
UCA0SOMI/UCA0RXD
2
P2DIR.x
TB0.6
Sz
P2.2/UCA0CLK/TB0.4/RTCCLK/Sz
(1)
I: 0; O: 1
TB0.CCI6B
Sz
P2.1/UCA0SOMI/UCA0RXD/TB0.5/
DMAE0/Sz
CONTROL BITS OR SIGNALS
(3)
X
X = Don't care
Direction controlled by eUSCI_A0 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.6 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Pin Schematic: see Figure 6-1.
Table 6-20. Port P3 (P3.0 to P3.3) Pin Functions
PIN NAME (P3.x)
P3.0/UCB1CLK/Sz
x
0
FUNCTION
P3.0 (I/O)
UCB1CLK
1
P3SEL1.x
P3SEL0.x
LCDSz
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
TA3.2
Internally tied to DVSS (for FR692x(1)
and FR682x(1) 64-pin package devices)
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.1 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
TA3.CCI3B (Note: not available for
FR692x(1) and FR682x(1) 64-pin
package devices)
0
TA3.3
Internally tied to DVSS (for FR692x(1)
and FR682x(1) 64-pin package devices)
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
Sz
2
P3DIR.x
0
UCB1SIMO/UCB1SDA
P3.2/UCB1SOMI/UCB1SCL/Sz
UCB1SOMI/UCB1SCL
X
(2)
TA3.CCI4B (Note: not available for
FR692x(1) and FR682x(1) 64-pin
package devices)
0
TA3.4
Internally tied to DVSS (for FR692x(1)
and FR682x(1) 64-pin package devices)
1
0
1
(3)
X
X
X
1
P3.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
P3.3/TA1.1/TB0CLK/Sz
3
N/A
0
Internally tied to DVSS
1
TA1.CCI1A
0
TA1.1
1
TB0CLK
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
(1)
I: 0; O: 1
TA3.CCI2B (Note: not available for
FR692x(1) and FR682x(1) 64-pin
package devices)
Sz
P3.1/UCB1SIMO/UCB1SDA/Sz
CONTROL BITS OR SIGNALS
(3)
X
X = Don't care
Direction controlled by eUSCI_B1 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-21. Port P3 (P3.4 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.4/UCA1SIMO/UCA1TXD/TB0.0/
Sz
x
4
FUNCTION
P3.4 (I/O)
UCA1SIMO/UCA1TXD
5
1
0
1
0
0
1
1
0
(2)
Internally tied to DVSS
1
(3)
X
X
X
1
P3.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
TB0CCI1A
0
TB0.1
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
TB0CCI2A
0
TB0.2
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P3.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
X
(2)
TB0CCI3B
0
TB0.3
1
N/A
0
Internally tied to DVSS
1
Sz
90
0
0
X
0
UCA1STE
(1)
(2)
(3)
LCDSz
0
N/A
Sz
7
P3SEL0.x
0
1
UCA1CLK
P3.7/UCA1STE/TB0.3/Sz
P3SEL1.x
0
UCA1SOMI/UCA1RXD
6
P3DIR.x
TB0.0
Sz
P3.6/UCA1CLK/TB0.2/Sz
(1)
I: 0; O: 1
TB0CCI0A
Sz
P3.5/UCA1SOMI/UCA1RXD/TB0.1/
Sz
CONTROL BITS OR SIGNALS
(3)
X
X = Don't care
Direction controlled by eUSCI_A1 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.7 Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger
Pin Schematic: see Figure 6-1.
Table 6-22. Port P4 (P4.2 to P4.3) Pin Functions
PIN NAME (P4.x)
P4.2/UCA0SIMO/UCA0TXD/
UCB1CLK/Sz
x
2
FUNCTION
P4.2 (I/O)
UCA0SIMO/UCA0TXD
UCB1CLK
3
P4DIR.x
P4SEL1.x
P4SEL0.x
LCDSz
0
0
0
X
(2)
0
1
0
X
(3)
1
0
0
1
1
0
0
Internally tied to DVSS
1
(4)
X
X
X
1
P4.3 (I/O)
I: 0; O: 1
0
0
0
UCA0SOMI/UCA0RXD
UCB1STE
X
(2)
0
1
0
X
(3)
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
(4)
(1)
I: 0; O: 1
N/A
Sz
P4.3/UCA0SOMI/UCA0RXD/
UCB1STE/Sz
CONTROL BITS OR SIGNALS
(4)
X
X = Don't care
Direction controlled by eUSCI_A0 module.
Direction controlled by eUSCI_B1 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
91
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-23. Port P4 (P4.4 to P4.7) Pin Functions
PIN NAME (P4.x)
x
P4.4/UCB1STE/TA1CLK/Sz
4
FUNCTION
P4.4 (I/O)
1
0
1
0
0
1
1
0
X
(2)
1
(3)
X
X
X
1
P4.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
X
(2)
TA1CCI0A
0
TA1.0
1
(3)
X
X
X
1
P4.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
X
(2)
TA1CCI1A
0
TA1.1
1
(3)
X
X
X
1
P4.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
X
(2)
TA1CCI2A
0
TA1.2
1
(3)
X
Sz
92
0
Internally tied to DVSS
UCB1SOMI/UCB1SCL
(1)
(2)
(3)
0
0
Sz
7
LCDSz
0
TA1CLK
UCB1SIMO/UCB1SDA
P4.7/UCB1SOMI/UCB1SCL/TA1.2/
Sz
P4SEL0.x
0
1
Sz
6
P4SEL1.x
Internally tied to DVSS
UCB1CLK
P4.6/UCB1SIMO/UCB1SDA/TA1.1/
Sz
P4DIR.x
0
Sz
5
(1)
I: 0; O: 1
N/A
UCB1STE
P4.5/UCB1CLK/TA1.0/Sz
CONTROL BITS OR SIGNALS
X = Don't care
Direction controlled by eUSCI_B1 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.8 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
Pin Schematic: see Figure 6-1.
Table 6-24. Port P5 (P5.4 to P5.7) Pin Functions
PIN NAME (P5.x)
P5.4/UCA1SIMO/UCA1TXD/Sz
x
4
FUNCTION
P5.4 (I/O)
UCA1SIMO/UCA1TXD
5
0
0
1
0
1
0
0
1
1
0
X
(2)
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
(2)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
UCA1STE
X
(2)
N/A
0
Internally tied to DVSS
1
TB0CLK
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
LCDSz
0
N/A
Sz
7
P5SEL0.x
0
1
UCA1CLK
P5.7/UCA1STE/TB0CLK/Sz
P5SEL1.x
0
Sz
6
P5DIR.x
Internally tied to DVSS
UCA1SOMI/UCA1RXD
P5.6/UCA1CLK/Sz
(1)
I: 0; O: 1
N/A
Sz
P5.5/UCA1SOMI/UCA1RXD/Sz
CONTROL BITS OR SIGNALS
(3)
X
X = Don't care
Direction controlled by eUSCI_A1 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
93
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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6.11.23.9 Port P6, P6.0 to P6.6, Input/Output With Schmitt Trigger
To/From
LCD module
Pad Logic
P6REN.x
P6DIR.x
00
01
10
11
P6OUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
DVSS
11
P6.0/R23
P6.1/R13/LCDREF
P6.2/COUT/R03
P6.3/COM0
P6.4/TB0.0/COM1
P6.5/TB0.1/COM2
P6.6/TB0.2/COM3
P6SEL1.x
P6SEL0.x
P6IN.x
(A)
To module 1
Bus
Keeper
(A)
To module 2
Functional representation only.
94
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-25. Port P6 (P6.0 to P6.2) Pin Functions
PIN NAME (P6.x)
P6.0/R23
x
0
FUNCTION
P6.0 (I/O)
P6.1/R13/LCDREF
1
2
P6SEL0.x
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
P6.1 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
P6.2 (I/O)
N/A
0
COUT
1
N/A
0
Internally tied to DVSS
1
R03
(1)
(2)
P6SEL1.x
0
R13/LCDREF
P6.2/COUT/R03
P6DIR.x
I: 0; O: 1
N/A
R23
(2)
(1)
CONTROL BITS OR SIGNALS
X
X = Don't care
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Detailed Description
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
95
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 6-26. Port P6 (P6.3 to P6.6) Pin Functions
PIN NAME (P6.x)
P6.3/COM0
3
P6.4/TB0.0/COM1
P6.5/TB0.1/COM2
P6.6/TB0.2/COM3
(1)
(2)
96
x
4
5
6
FUNCTION
P6.3 (I/O)
(1)
CONTROL BITS OR SIGNALS
P6DIR.x
P6SEL1.x
P6SEL0.x
I: 0; O: 1
0
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
COM0 (2)
X
1
1
P6.4 (I/O)
I: 0; O: 1
0
0
TB0CCI0B
0
TB0.0
1
0
1
N/A
0
Internally tied to DVSS
1
1
0
COM1 (2)
X
1
1
P6.5 (I/O)
I: 0; O: 1
0
0
TB0CCI1A
0
TB0.1
1
0
1
N/A
0
Internally tied to DVSS
1
1
0
COM2 (2)
X
1
1
P6.6 (I/O)
I: 0; O: 1
0
0
TB0CCI2A
0
TB0.2
1
0
1
N/A
0
Internally tied to DVSS
1
1
0
COM3 (2)
X
1
1
X = Don't care
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.10 Port P7, P7.0 to P7.4, Input/Output With Schmitt Trigger
Pin Schematic: see Figure 6-1.
Table 6-27. Port P7 (P7.0 to P7.3) Pin Functions
PIN NAME (P7.x)
P7.0/TA0CLK/Sz
x
0
FUNCTION
1
P7DIR.x
P7SEL1.x
P7SEL0.x
LCDSz
I: 0; O: 1
0
0
0
TA0CLK
0
Internally tied to DVSS
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
(2)
X
X
X
1
P7.1 (I/O)
I: 0; O: 1
0
0
0
TA0CCI0B
0
TA0.0
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
ACLK
1
1
1
0
(2)
X
X
X
1
P7.2 (I/O)
I: 0; O: 1
0
0
0
TA0CCI1A
0
TA0.1
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
N/A
1
1
1
0
Sz
P7.2/TA0.1/Sz
2
(2)
X
X
X
1
P7.3 (I/O)
I: 0; O: 1
0
0
0
TA0CCI2A
0
TA0.2
1
0
1
0
N/A
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
X
X
1
Sz
P7.3/TA0.2/Sz
3
Sz
(1)
(2)
(1)
P7.0 (I/O)
Sz
P7.1/TA0.0/Sz
CONTROL BITS OR SIGNALS
(2)
X
X = Don't care
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
97
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 6-28. Port P7 (P7.4) Pin Functions
PIN NAME (P7.x)
P7.4/SMCLK/Sz
x
4
FUNCTION
P7.4 (I/O)
98
P7DIR.x
P7SEL1.x
P7SEL0.x
LCDSz
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
N/A
0
SMCLK
1
(2)
(1)
I: 0; O: 1
N/A
Sz
(1)
(2)
CONTROL BITS OR SIGNALS
X
X = Don't care
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.11 Port P9, P9.4 to P9.7, Input/Output With Schmitt Trigger
To ADC
From ADC
To Comparator
From Comparator
CEPD.x
Pad Logic
P9REN.x
P9DIR.x
00
01
10
11
P9OUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P9.4/A12/C12
P9.5/A13/C13
P9.6/A14/C14
P9.7/A15/C15
P9SEL1.x
P9SEL0.x
P9IN.x
Bus
Keeper
Functional representation only.
Detailed Description
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
99
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 6-29. Port P9 (P9.4 to P9.7) Pin Functions
PIN NAME (P9.x)
P9.4/A12/C12
x
4
FUNCTION
P9.4 (I/O)
5
6
7
(3)
100
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
N/A
0
Internally tied to DVSS
1
P9.5 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2) (3)
P9.6 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2) (3)
P9.7 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
A15/C15
(1)
(2)
P9SEL0.x
0
1
A14/C14
P9.7/A15/C15
P9SEL1.x
Internally tied to DVSS
A13/C13
P9.6/A14/C14
P9DIR.x
0
(2) (3)
(2) (3)
(1)
I: 0; O: 1
N/A
A12/C12
P9.5/A13/C13
CONTROL BITS OR SIGNALS
X
X = Don't care
Setting P9SEL1.x and P9SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.12 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
Pad Logic
To LFXT XIN
PJREN.4
PJDIR.4
00
01
10
Direction
0: Input
1: Output
11
PJOUT.4
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
PJ.4/LFXIN
PJSEL1.4
PJSEL0.4
PJIN.4
EN
To modules
Bus
Keeper
D
Functional representation only.
Detailed Description
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
101
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Pad Logic
To LFXT XOUT
PJSEL0.4
PJSEL1.4
LFXTBYPASS
PJREN.5
PJDIR.5
00
01
10
Direction
0: Input
1: Output
11
PJOUT.5
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.5/LFXOUT
PJSEL1.5
PJSEL0.5
PJIN.5
EN
To modules
Bus
Keeper
D
Functional representation only.
102
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-30. Port PJ (PJ.4 and PJ.5) Pin Functions
PIN NAME (PJ.x)
PJ.4/LFXIN
x
4
PJ.4 (I/O)
PJSEL1.5
PJSEL0.5
PJSEL1.4
PJSEL0.4
LFXTBYPASS
X
X
0
0
X
X
X
1
X
X
Internally tied to DVSS
1
(2)
X
X
X
0
1
0
X
X
X
0
1
1
I: 0; O: 1
0
0
(2)
5
PJ.5 (I/O)
N/A
Internally tied to DVSS
LFXOUT crystal mode
(2)
(3)
(4)
PJDIR.x
I: 0; O: 1
0
LFXIN bypass mode
(1)
(2)
(1)
N/A
LFXIN crystal mode
PJ.5/LFXOUT
CONTROL BITS OR SIGNALS
FUNCTION
0
1
X
see (4)
see
X
(4)
see (4)
see
X
(4)
0
0
1
X
X
X
0
1 (3)
0
0
1
X
X
X
0
0
1
X
X
X
1 (3)
0
1
0
0
1 (3)
0
X = Don't care
Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When LFXTBYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
With PJSEL0.5 = 1 or PJSEL1.5 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as
output, the pin is actively pulled to zero.
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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6.11.23.13 Port PJ, PJ.6 and PJ.7 Input/Output With Schmitt Trigger
Pad Logic
To HFXT XIN
PJREN.6
PJDIR.6
00
01
10
Direction
0: Input
1: Output
11
PJOUT.6
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
PJ.6/HFXIN
PJSEL1.6
PJSEL0.6
PJIN.6
EN
To modules
Bus
Keeper
D
Functional representation only.
104
Detailed Description
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Pad Logic
To HFXT XOUT
PJSEL0.6
PJSEL1.6
HFXTBYPASS
PJREN.7
PJDIR.7
00
01
10
Direction
0: Input
1: Output
11
PJOUT.7
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.7/HFXOUT
PJSEL1.7
PJSEL0.7
PJIN.7
EN
To modules
Bus
Keeper
D
Functional representation only.
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-31. Port PJ (PJ.6 and PJ.7) Pin Functions
PIN NAME (PJ.x)
PJ.6/HFXIN
x
6
PJ.7/HFXOUT
FUNCTION
PJ.6 (I/O)
PJSEL1.7
PJSEL0.7
PJSEL1.6
PJSEL0.6
HFXTBYPASS
X
X
0
0
X
X
X
1
X
X
Internally tied to DVSS
1
HFXIN crystal mode (2)
X
X
X
0
1
0
HFXIN bypass mode (2)
X
X
X
0
1
1
I: 0; O: 1
0
0
7
Internally tied to DVSS
HFXOUT crystal mode (2)
106
PJDIR.x
I: 0; O: 1
0
N/A
(3)
(4)
(1)
N/A
PJ.7 (I/O)
(1)
(2)
CONTROL BITS OR SIGNALS
0
1
X
see (4)
see
X
(4)
see (4)
see
X
(4)
0
0
1
X
X
X
0
1 (3)
0
0
1
X
X
X
0
0
1
X
X
X
1 (3)
0
1
0
0
1 (3)
0
X = Don't care
Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are
configured for crystal operation and PJSEL1.6 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass
operation and PJ.7 is configured as general-purpose I/O.
When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.
With PJSEL0.7 = 1 or PJSEL1.7 = 1 the general-purpose I/O functionality is disabled. No input function is available. Configured as
output, the pin is actively pulled to zero.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.11.23.14 Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
Pad Logic
DVSS
JTAG enable
From JTAG
From JTAG
PJREN.x
PJDIR.x
00
1
01
10
Direction
0: Input
1: Output
11
PJOUT.x
DVSS
0
DVCC
1
0
1
00
From module 1
01
1
From Status Register (SR)
10
0
DVSS
11
PJSEL1.x
PJSEL0.x
PJIN.x
EN
To modules
and JTAG
Bus
Keeper
PJ.0/TDO/TB0OUTH/
SMCLK SRSCG1
PJ.1/TDI/TCLK/MCLK/
SRSCG0
PJ.2/TMS/ACLK/
SROSCOFF
PJ.3/TCK/COUT/
SRCPUOFF
D
Functional representation only.
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-32. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
PJ.1/TDI/TCLK/MCLK/
SRSCG0
PJ.2/TMS/ACLK/
SROSCOFF
PJ.3/TCK/COUT/
SRCPUOFF
(1)
(2)
(3)
(4)
(5)
108
x
0
FUNCTION
PJ.0 (I/O)
TDO
1
2
(3)
PJDIR.x
PJSEL1.x
I: 0; O: 1
0
0
X
X
X
0
1
1
0
1
1
0
SMCLK (4)
1
N/A
0
CPU Status Register Bit SCG1
1
N/A
0
Internally tied to DVSS
1
PJ.1 (I/O)
(2)
I: 0; O: 1
0
0
TDI/TCLK
(3) (5)
X
X
X
0
1
1
0
1
1
N/A
0
MCLK
1
N/A
0
CPU Status Register Bit SCG0
1
N/A
0
Internally tied to DVSS
1
(2)
I: 0; O: 1
0
0
X
X
X
0
1
1
0
1
1
PJ.2 (I/O)
(3) (5)
N/A
0
ACLK
1
N/A
0
CPU Status Register Bit OSCOFF
1
N/A
0
Internally tied to DVSS
1
(2)
I: 0; O: 1
0
0
X
X
X
0
1
1
0
1
1
PJ.3 (I/O)
TCK
(3) (5)
N/A
0
COUT
1
N/A
0
CPU Status Register Bit CPUOFF
1
N/A
0
Internally tied to DVSS
1
(1)
PJSEL0.x
TB0OUTH
TMS
3
(2)
CONTROL BITS OR SIGNALS
X = Don't care
Default condition
The pin direction is controlled by the JTAG module. JTAG mode selection is made via the SYS module or by the SpyBiWire four wire
entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPD.x bits have an effect in these cases.
NOTE: Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternative SMCLK output
pin.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.12 Device Descriptors (TLV)
Table 6-34 list the contents of the device descriptor tag-length-value (TLV) structure. Table 6-33
summarizes the Device IDs.
Table 6-33. Device ID
DEVICE
PACKAGE
MSP430FR6970
DEVICE ID
At 01A05h
At 01A04h
PM and RGC
82h
49h
MSP430FR6972(1)
PM and RGC
82h
4Bh
MSP430FR6870
PM and RGC
82h
4Ch
MSP430FR6872(1)
PM and RGC
82h
4Eh
MSP430FR6920
MSP430FR6922(1)
MSP430FR6820
MSP430FR6822(1)
DGG
82h
4Fh
PM and RGC
82h
50h
DGG
82h
53h
PM and RGC
82h
54h
DGG
82h
55h
PM and RGC
82h
56h
DGG
82h
59h
PM and RGC
82h
5Ah
Table 6-34. Device Descriptor Table
DESCRIPTION
Info Block
ADDRESS
VALUE
ADDRESS
VALUE
01A00h
06h
01A00h
06h
CRC length
01A01h
06h
01A01h
06h
01A02h
per unit
01A02h
per unit
01A03h
per unit
01A03h
per unit
Device ID
01A04h
Device ID
01A05h
Hardware revision
01A06h
per unit
01A06h
per unit
Firmware revision
01A07h
per unit
01A07h
per unit
Die Record Tag
01A08h
08h
01A08h
08h
Die Record length
01A09h
0Ah
01A09h
0Ah
01A0Ah
per unit
01A0Ah
per unit
01A0Bh
per unit
01A0Bh
per unit
01A0Ch
per unit
01A0Ch
per unit
01A0Dh
per unit
01A0Dh
per unit
01A0Eh
per unit
01A0Eh
per unit
01A0Fh
per unit
01A0Fh
per unit
01A10h
per unit
01A10h
per unit
01A11h
per unit
01A11h
per unit
01A12h
per unit
01A12h
per unit
01A13h
per unit
01A13h
per unit
ADC12B Calibration Tag
01A14h
11h
01A14h
11h
ADC12B Calibration length
01A15h
10h
01A15h
10h
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC12B
Calibration
(1)
MSP430FRxxxx1 (I2C BSL)
Info length
CRC value
Die Record
MSP430FRxxxx (UART BSL)
(1)
see Table 6-33
01A04h
01A05h
see Table 6-33
NA = Not applicable
per unit = content can differ from device to device
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-34. Device Descriptor Table (1) (continued)
DESCRIPTION
ADC Gain Factor (2)
ADC Offset (3)
REF Calibration
ADDRESS
VALUE
01A16h
per unit
01A16h
per unit
01A17h
per unit
01A17h
per unit
01A18h
per unit
01A18h
per unit
per unit
01A19h
per unit
per unit
01A1Ah
per unit
01A1Bh
per unit
01A1Bh
per unit
ADC 1.2-V Reference
Temp. Sensor 85°C
01A1Ch
per unit
01A1Ch
per unit
01A1Dh
per unit
01A1Dh
per unit
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh
per unit
01A1Eh
per unit
01A1Fh
per unit
01A1Fh
per unit
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h
per unit
01A20h
per unit
01A21h
per unit
01A21h
per unit
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h
per unit
01A22h
per unit
01A23h
per unit
01A23h
per unit
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h
per unit
01A24h
per unit
01A25h
per unit
01A25h
per unit
REF Calibration Tag
01A26h
12h
01A26h
12h
REF Calibration length
01A27h
06h
01A27h
06h
01A28h
per unit
01A28h
per unit
01A29h
per unit
01A29h
per unit
01A2Ah
per unit
01A2Ah
per unit
01A2Bh
per unit
01A2Bh
per unit
01A2Ch
per unit
01A2Ch
per unit
01A2Dh
per unit
01A2Dh
per unit
128-bit Random Number
Tag
01A2Eh
15h
01A2Eh
15h
Random Number Length
01A2Fh
10h
01A2Fh
10h
01A30h
per unit
01A30h
per unit
01A31h
per unit
01A31h
per unit
01A32h
per unit
01A32h
per unit
01A33h
per unit
01A33h
per unit
01A34h
per unit
01A34h
per unit
01A35h
per unit
01A35h
per unit
01A36h
per unit
01A36h
per unit
01A37h
per unit
01A37h
per unit
01A38h
per unit
01A38h
per unit
01A39h
per unit
01A39h
per unit
01A3Ah
per unit
01A3Ah
per unit
01A3Bh
per unit
01A3Bh
per unit
01A3Ch
per unit
01A3Ch
per unit
01A3Dh
per unit
01A3Dh
per unit
01A3Eh
per unit
01A3Eh
per unit
01A3Fh
per unit
01A3Fh
per unit
128-bit Random Number (4)
110
VALUE
01A19h
REF 2.5-V Reference
(3)
(4)
ADDRESS
01A1Ah
REF 2.0-V Reference
(2)
MSP430FRxxxx1 (I2C BSL)
ADC 1.2-V Reference
Temp. Sensor 30°C
REF 1.2-V Reference
Random Number
MSP430FRxxxx (UART BSL)
ADC Gain: The gain correction factor is measured using the internal voltage reference with REFOUT = 0. Other settings (for example,
with REFOUT = 1) can result in different correction factors.
ADC Offset: The offset correction factor is measured using the internal 2.5-V reference.
128-bit Random Number: The random number is generated during production test using the CryptGenRandom() function from
Microsoft®.
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-34. Device Descriptor Table (1) (continued)
DESCRIPTION
BSL Configuration
MSP430FRxxxx (UART BSL)
MSP430FRxxxx1 (I2C BSL)
ADDRESS
VALUE
ADDRESS
VALUE
BSL Tag
01A40h
1Ch
01A40h
1Ch
BSL length
01A41h
02h
01A41h
02h
BSL Interface
01A42h
00h
01A42h
01h
BSL Interface
Configuration
01A43h
00h
01A43h
48h
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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6.13 Memory
Table 6-35 shows the memory map for all devices.
Table 6-35. Memory Organization (1)
Memory (FRAM)
Main: interrupt vectors and
signatures
Main: code memory
RAM
MSP430FR69x2(1)
MSP430FR68x2(1)
MSP430FR69x0
MSP430FR68x0
Total Size
63KB
00FFFFh–00FF80h
013FFFh–004400h
32KB
00FFFFh–00FF80h
00FF7Fh–008000h
Sect 1
2KB
0023FFh–001C00h
2KB
0023FFh–001C00h
256 B
001AFFh–001A00h
256 B
001AFFh–001A00h
Info A
128 B
0019FFh–001980h
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
Size
4KB
000FFFh–000020h
4KB
000FFFh–000020h
Size
26 B
000001Fh–000006h
26 B
000001Fh–000006h
Size
6B
000005h–000000h
6B
000005h–000000h
Device Descriptor Info (TLV)
(FRAM)
Information memory (FRAM)
Bootstrap loader (BSL) memory
(ROM)
Peripherals
Tiny RAM
Reserved
(Read Only) (2)
(1)
(2)
112
All address space not listed is considered vacant memory.
Read as: D032h at 00h (Opcode: BIS.W LPM4, SR), 00F0h at 02h (Opcode: BIS.W LPM4, SR), 3FFFh at 04h (Opcode: JMP$)
Detailed Description
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
6.13.1 Peripheral File Map
Table 6-36. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 6-37)
0100h
000h-01Fh
PMM (see Table 6-38)
0120h
000h-01Fh
FRAM Control (see Table 6-39)
0140h
000h-00Fh
CRC16 (see Table 6-40)
0150h
000h-007h
RAM Controller (see Table 6-41)
0158h
000h-001h
Watchdog (see Table 6-42)
015Ch
000h-001h
CS (see Table 6-43)
0160h
000h-00Fh
SYS (see Table 6-44)
0180h
000h-01Fh
Shared Reference (see Table 6-45)
01B0h
000h-001h
Port P1, P2 (see Table 6-46)
0200h
000h-01Fh
Port P3, P4 (see Table 6-47)
0220h
000h-01Fh
Port P5, P6 (see Table 6-48)
0240h
000h-01Fh
Port P7 (see Table 6-49)
0260h
000h-01Fh
Port P9 (see Table 6-50)
0280h
000h-01Fh
Port PJ (see Table 6-51)
0320h
000h-01Fh
Timer_A TA0 (see Table 6-52)
0340h
000h-02Fh
Timer_A TA1 (see Table 6-53)
0380h
000h-02Fh
Timer_B TB0 (see Table 6-54)
03C0h
000h-02Fh
Timer_A TA2 (see Table 6-55)
0400h
000h-02Fh
Capacitive Touch I/O 0 (see Table 6-56)
0430h
000h-00Fh
Timer_A TA3 (see Table 6-57)
0440h
000h-02Fh
Capacitive Touch I/O 1 (see Table 6-58)
0470h
000h-00Fh
Real-Time Clock (RTC_C) (see Table 6-59)
04A0h
000h-01Fh
32-bit Hardware Multiplier (see Table 6-60)
04C0h
000h-02Fh
DMA General Control (see Table 6-61)
0500h
000h-00Fh
DMA Channel 0 (see Table 6-61)
0510h
000h-00Fh
DMA Channel 1 (see Table 6-61)
0520h
000h-00Fh
DMA Channel 2 (see Table 6-61)
0530h
000h-00Fh
MPU Control (see Table 6-62)
05A0h
000h-00Fh
eUSCI_A0 (see Table 6-63)
05C0h
000h-01Fh
eUSCI_A1 (see Table 6-64)
05E0h
000h-01Fh
eUSCI_B0 (see Table 6-65)
0640h
000h-02Fh
eUSCI_B1 (see Table 6-66)
0680h
000h-02Fh
ADC12_B (see Table 6-67)
0800h
000h-09Fh
Comparator_E (see Table 6-68)
08C0h
000h-00Fh
CRC32 (see Table 6-69)
0980h
000h-02Fh
AES (see Table 6-70)
09C0h
000h-00Fh
LCD_C (see Table 6-71)
0A00h
000h-05Fh
Detailed Description
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Table 6-37. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-38. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM interrupt flags
PMMIFG
0Ah
PM5 Control 0
PM5CTL0
10h
Table 6-39. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
FRAM control 0
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 6-40. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRCDI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 6-41. RAM Controller Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM controller control register 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-42. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 6-43. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CS control 0
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
Table 6-44. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
JTAG mailbox control
SYSJMBC
06h
114
Detailed Description
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-44. SYS Registers (Base Address: 0180h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-45. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 6-46. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 complement selection
P1SELC
16h
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Dh
Port P2 complement selection
P2SELC
17h
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 6-47. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 selection 0
P3SEL0
0Ah
Port P3 selection 1
P3SEL1
0Ch
Port P3 interrupt vector word
P3IV
0Eh
Detailed Description
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Table 6-47. Port P3, P4 Registers (Base Address: 0220h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 complement selection
P3SELC
16h
Port P3 interrupt edge select
P3IES
18h
Port P3 interrupt enable
P3IE
1Ah
Port P3 interrupt flag
P3IFG
1Ch
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 selection 0
P4SEL0
0Bh
Port P4 selection 1
P4SEL1
0Dh
Port P4 complement selection
P4SELC
17h
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
Port P4 interrupt enable
P4IE
1Bh
Port P4 interrupt flag
P4IFG
1Dh
Table 6-48. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 selection 0
P5SEL0
0Ah
Port P5 selection 1
P5SEL1
0Ch
Reserved
0Eh
Port P5 complement selection
P5SELC
16h
Reserved
18h
Reserved
1Ah
Reserved
1Ch
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 selection 0
P6SEL0
0Bh
Port P6 selection 1
P6SEL1
0Dh
Port P6 complement selection
P6SELC
17h
Reserved
1Eh
Reserved
19h
Reserved
1Bh
Reserved
1Dh
Table 6-49. Port P7 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pullup/pulldown enable
P7REN
06h
116
Detailed Description
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-49. Port P7 Registers (Base Address: 0260h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 selection 0
P7SEL0
0Ah
Port P7 selection 1
P7SEL1
0Ch
Reserved
0Eh
Port P7 complement selection
P7SELC
16h
Reserved
18h
Reserved
1Ah
Reserved
1Ch
Table 6-50. Port P9 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 pullup/pulldown enable
P9REN
06h
Port P9 selection 0
P9SEL0
0Ah
Port P9 selection 1
P9SEL1
0Ch
Reserved
0Eh
Port P9 complement selection
P9SELC
16h
Reserved
18h
Reserved
1Ah
Reserved
1Ch
Table 6-51. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ selection 0
PJSEL0
0Ah
Port PJ selection 1
PJSEL1
0Ch
Port PJ complement selection
PJSELC
16h
Table 6-52. Timer_A TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Detailed Description
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MSP430FR6820
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MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-53. Timer_A TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 6-54. Timer_B TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 register
TB0R
10h
Capture/compare register 0
TB0CCR0
12h
Capture/compare register 1
TB0CCR1
14h
Capture/compare register 2
TB0CCR2
16h
Capture/compare register 3
TB0CCR3
18h
Capture/compare register 4
TB0CCR4
1Ah
Capture/compare register 5
TB0CCR5
1Ch
Capture/compare register 6
TB0CCR6
1Eh
TB0 expansion register 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
Table 6-55. Timer_A TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
TA2 register
TA2R
10h
Capture/compare register 0
TA2CCR0
12h
Capture/compare register 1
TA2CCR1
14h
TA2 expansion register 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Table 6-56. Capacitive Touch I/O 0 Registers (Base Address: 0430h)
REGISTER DESCRIPTION
Capacitive Touch I/O 0 control
118
Detailed Description
REGISTER
CAPTIO0CTL
OFFSET
0Eh
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-57. Timer_A TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA3 control
TA3CTL
00h
Capture/compare control 0
TA3CCTL0
02h
Capture/compare control 1
TA3CCTL1
04h
Capture/compare control 2
TA3CCTL2
06h
Capture/compare control 3
TA3CCTL3
08h
Capture/compare control 4
TA3CCTL4
0Ah
TA3 register
TA3R
10h
Capture/compare register 0
TA3CCR0
12h
Capture/compare register 1
TA3CCR1
14h
Capture/compare register 2
TA3CCR2
16h
Capture/compare register 3
TA3CCR3
18h
Capture/compare register 4
TA3CCR4
1Ah
TA3 expansion register 0
TA3EX0
20h
TA3 interrupt vector
TA3IV
2Eh
Table 6-58. Capacitive Touch I/O 1 Registers (Base Address: 0470h)
REGISTER DESCRIPTION
Capacitive Touch I/O 1 control
REGISTER
CAPTIO1CTL
OFFSET
0Eh
Table 6-59. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC password
RTCPWD
01h
RTC control 1
RTCCTL1
02h
RTC control 3
RTCCTL3
03h
RTC offset calibration
RTCOCAL
04h
RTC temperature compensation
RTCTCMP
06h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter register 1
RTCSEC/RTCNT1
10h
RTC minutes/counter register 2
RTCMIN/RTCNT2
11h
RTC hours/counter register 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter register 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year
RTCYEAR
16h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion register
BIN2BCD
1Ch
BCD-to-Binary conversion register
BCD2BIN
1Eh
Detailed Description
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MSP430FR6820
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MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-60. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
Table 6-61. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
120
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-61. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 6-62. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
MPU control 0
MPUCTL0
00h
MPU control 1
MPUCTL1
02h
MPU Segmentation Border 2
MPUSEGB2
04h
MPU Segmentation Border 1
MPUSEGB1
06h
MPU access management
MPUSAM
08h
MPU IP control 0
MPUIPC0
0Ah
MPU IP Encapsulation Segment Border 2
MPUIPSEGB2
0Ch
MPU IP Encapsulation Segment Border 1
MPUIPSEGB1
0Eh
Table 6-63. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI _A control word 1
UCA0CTLW1
02h
eUSCI_A baud rate 0
UCA0BR0
06h
eUSCI_A baud rate 1
UCA0BR1
07h
eUSCI_A modulation control
UCA0MCTLW
08h
eUSCI_A status word
UCA0STATW
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
UCA0IRTCTL
12h
eUSCI_A IrDA receive control
UCA0IRRCTL
13h
eUSCI_A interrupt enable
UCA0IE
1Ah
eUSCI_A interrupt flags
UCA0IFG
1Ch
eUSCI_A interrupt vector word
UCA0IV
1Eh
Table 6-64. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA1CTLW0
00h
eUSCI _A control word 1
UCA1CTLW1
02h
eUSCI_A baud rate 0
UCA1BR0
06h
eUSCI_A baud rate 1
UCA1BR1
07h
eUSCI_A modulation control
UCA1MCTLW
08h
eUSCI_A status word
UCA1STATW
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
UCA1IRTCTL
12h
Detailed Description
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MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-64. eUSCI_A1 Registers (Base Address:05E0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A IrDA receive control
UCA1IRRCTL
13h
eUSCI_A interrupt enable
UCA1IE
1Ah
eUSCI_A interrupt flags
UCA1IFG
1Ch
eUSCI_A interrupt vector word
UCA1IV
1Eh
Table 6-65. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B received address
UCB0ADDRX
1Ch
eUSCI_B address mask
UCB0ADDMASK
1Eh
eUSCI_B I2C slave address
UCB0I2CSA
20h
eUSCI_B interrupt enable
UCB0IE
2Ah
eUSCI_B interrupt flags
UCB0IFG
2Ch
eUSCI_B interrupt vector word
UCB0IV
2Eh
Table 6-66. eUSCI_B1 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB1CTLW0
00h
eUSCI_B control word 1
UCB1CTLW1
02h
eUSCI_B bit rate 0
UCB1BR0
06h
eUSCI_B bit rate 1
UCB1BR1
07h
eUSCI_B status word
UCB1STATW
08h
eUSCI_B byte counter threshold
UCB1TBCNT
0Ah
eUSCI_B receive buffer
UCB1RXBUF
0Ch
eUSCI_B transmit buffer
UCB1TXBUF
0Eh
eUSCI_B I2C own address 0
UCB1I2COA0
14h
eUSCI_B I2C own address 1
UCB1I2COA1
16h
eUSCI_B I2C own address 2
UCB1I2COA2
18h
eUSCI_B I2C own address 3
UCB1I2COA3
1Ah
eUSCI_B received address
UCB1ADDRX
1Ch
eUSCI_B address mask
UCB1ADDMASK
1Eh
eUSCI_B I2C slave address
UCB1I2CSA
20h
eUSCI_B interrupt enable
UCB1IE
2Ah
eUSCI_B interrupt flags
UCB1IFG
2Ch
eUSCI_B interrupt vector word
UCB1IV
2Eh
122
Detailed Description
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Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-67. ADC12_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC12_B Control 0
ADC12CTL0
00h
ADC12_B Control 1
ADC12CTL1
02h
ADC12_B Control 2
ADC12CTL2
04h
ADC12_B Control 3
ADC12CTL3
06h
ADC12_B Window Comparator Low Threshold Register
ADC12LO
08h
ADC12_B Window Comparator High Threshold Register
ADC12HI
0Ah
ADC12_B Interrupt Flag Register 0
ADC12IFGR0
0Ch
ADC12_B Interrupt Flag Register 1
ADC12IFGR1
0Eh
ADC12_B Interrupt Flag Register 2
ADC12IFGR2
10h
ADC12_B Interrupt Enable Register 0
ADC12IER0
12h
ADC12_B Interrupt Enable Register 1
ADC12IER1
14h
ADC12_B Interrupt Enable Register 2
ADC12IER2
16h
ADC12_B Interrupt Vector
ADC12IV
18h
ADC12_B Memory Control 0
ADC12MCTL0
20h
ADC12_B Memory Control 1
ADC12MCTL1
22h
ADC12_B Memory Control 2
ADC12MCTL2
24h
ADC12_B Memory Control 3
ADC12MCTL3
26h
ADC12_B Memory Control 4
ADC12MCTL4
28h
ADC12_B Memory Control 5
ADC12MCTL5
2Ah
ADC12_B Memory Control 6
ADC12MCTL6
2Ch
ADC12_B Memory Control 7
ADC12MCTL7
2Eh
ADC12_B Memory Control 8
ADC12MCTL8
30h
ADC12_B Memory Control 9
ADC12MCTL9
32h
ADC12_B Memory Control 10
ADC12MCTL10
34h
ADC12_B Memory Control 11
ADC12MCTL11
36h
ADC12_B Memory Control 12
ADC12MCTL12
38h
ADC12_B Memory Control 13
ADC12MCTL13
3Ah
ADC12_B Memory Control 14
ADC12MCTL14
3Ch
ADC12_B Memory Control 15
ADC12MCTL15
3Eh
ADC12_B Memory Control 16
ADC12MCTL16
40h
ADC12_B Memory Control 17
ADC12MCTL17
42h
ADC12_B Memory Control 18
ADC12MCTL18
44h
ADC12_B Memory Control 19
ADC12MCTL19
46h
ADC12_B Memory Control 20
ADC12MCTL20
48h
ADC12_B Memory Control 21
ADC12MCTL21
4Ah
ADC12_B Memory Control 22
ADC12MCTL22
4Ch
ADC12_B Memory Control 23
ADC12MCTL23
4Eh
ADC12_B Memory Control 24
ADC12MCTL24
50h
ADC12_B Memory Control 25
ADC12MCTL25
52h
ADC12_B Memory Control 26
ADC12MCTL26
54h
ADC12_B Memory Control 27
ADC12MCTL27
56h
ADC12_B Memory Control 28
ADC12MCTL28
58h
ADC12_B Memory Control 29
ADC12MCTL29
5Ah
ADC12_B Memory Control 30
ADC12MCTL30
5Ch
ADC12_B Memory Control 31
ADC12MCTL31
5Eh
ADC12_B Memory 0
ADC12MEM0
60h
ADC12_B Memory 1
ADC12MEM1
62h
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
123
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
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Table 6-67. ADC12_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC12_B Memory 2
ADC12MEM2
64h
ADC12_B Memory 3
ADC12MEM3
66h
ADC12_B Memory 4
ADC12MEM4
68h
ADC12_B Memory 5
ADC12MEM5
6Ah
ADC12_B Memory 6
ADC12MEM6
6Ch
ADC12_B Memory 7
ADC12MEM7
6Eh
ADC12_B Memory 8
ADC12MEM8
70h
ADC12_B Memory 9
ADC12MEM9
72h
ADC12_B Memory 10
ADC12MEM10
74h
ADC12_B Memory 11
ADC12MEM11
76h
ADC12_B Memory 12
ADC12MEM12
78h
ADC12_B Memory 13
ADC12MEM13
7Ah
ADC12_B Memory 14
ADC12MEM14
7Ch
ADC12_B Memory 15
ADC12MEM15
7Eh
ADC12_B Memory 16
ADC12MEM16
80h
ADC12_B Memory 17
ADC12MEM17
82h
ADC12_B Memory 18
ADC12MEM18
84h
ADC12_B Memory 19
ADC12MEM19
86h
ADC12_B Memory 20
ADC12MEM20
88h
ADC12_B Memory 21
ADC12MEM21
8Ah
ADC12_B Memory 22
ADC12MEM22
8Ch
ADC12_B Memory 23
ADC12MEM23
8Eh
ADC12_B Memory 24
ADC12MEM24
90h
ADC12_B Memory 25
ADC12MEM25
92h
ADC12_B Memory 26
ADC12MEM26
94h
ADC12_B Memory 27
ADC12MEM27
96h
ADC12_B Memory 28
ADC12MEM28
98h
ADC12_B Memory 29
ADC12MEM29
9Ah
ADC12_B Memory 30
ADC12MEM30
9Ch
ADC12_B Memory 31
ADC12MEM31
9Eh
Table 6-68. Comparator_E Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comparator control register 0
CECTL0
00h
Comparator control register 1
CECTL1
02h
Comparator control register 2
CECTL2
04h
Comparator control register 3
CECTL3
06h
Comparator interrupt register
CEINT
0Ch
Comparator interrupt vector word
CEIV
0Eh
Table 6-69. CRC32 Registers (Base Address: 0980h)
REGISTER DESCRIPTION
CRC32 data input
REGISTER
CRC32DIW0
Reserved
OFFSET
00h
02h
Reserved
04h
CRC32 data input reverse
CRC32DIRBW0
06h
CRC32 initialization and result word 0
CRC32INIRESW0
08h
124
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-69. CRC32 Registers (Base Address: 0980h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC32 initialization and result word 1
CRC32INIRESW1
0Ah
CRC32 result reverse word 1
CRC32RESRW1
0Ch
CRC32 result reverse word 0
CRC32RESRW1
0Eh
CRC16 data input
CRC16DIW0
10h
Reserved
12h
Reserved
14h
CRC16 data input reverse
CRC16DIRBW0
16h
CRC16 initialization and result word 0
CRC16INIRESW0
18h
Reserved
1Ah
Reserved
1Ch
CRC16 result reverse word 0
CRC16RESRW1
1Eh
Reserved
20h
Reserved
22h
Reserved
24h
Reserved
26h
Reserved
28h
Reserved
2Ah
Reserved
2Ch
Reserved
2Eh
Table 6-70. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
AES accelerator control register 0
REGISTER
AESACTL0
Reserved
OFFSET
00h
02h
AES accelerator status register
AESASTAT
04h
AES accelerator key register
AESAKEY
06h
AES accelerator data in register
AESADIN
008h
AES accelerator data out register
AESADOUT
00Ah
AES accelerator XORed data in register
AESAXDIN
00Ch
AES accelerator XORed data in register (no trigger)
AESAXIN
00Eh
Table 6-71. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C control register 0
LCDCCTL0
000h
LCD_C control register 1
LCDCCTL1
002h
LCD_C blinking control register
LCDCBLKCTL
004h
LCD_C memory control register
LCDCMEMCTL
006h
LCD_C voltage control register
LCDCVCTL
008h
LCD_C port control 0
LCDCPCTL0
00Ah
LCD_C port control 1
LCDCPCTL1
00Ch
LCD_C port control 2
LCDCPCTL2
00Eh
LCD_C charge pump control register
LCDCCPCTL
012h
LCD_C interrupt vector
LCDCIV
01Eh
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
LCD_C memory 3
LCDM3
022h
Static and 2 to 4 mux modes
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
125
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 6-71. LCD_C Registers (Base Address: 0A00h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C memory 4
LCDM4
023h
LCD_C memory 5
LCDM5
024h
LCD_C memory 6
LCDM6
025h
LCD_C memory 7
LCDM7
026h
LCD_C memory 8
LCDM8
027h
LCD_C memory 9
LCDM9
028h
LCD_C memory 10
LCDM10
029h
LCD_C memory 11
LCDM11
02Ah
LCD_C memory 12
LCDM12
02Bh
LCD_C memory 13
LCDM13
02Ch
LCD_C memory 14
LCDM14
02Dh
LCD_C memory 15
LCDM15
02Eh
LCD_C memory 16
LCDM16
02Fh
LCD_C memory 17
LCDM17
030h
LCD_C memory 18
LCDM18
031h
LCD_C memory 19
LCDM19
032h
LCD_C memory 20
LCDM20
033h
LCD_C memory 21
LCDM21
034h
LCD_C memory 22
LCDM22
035h
Reserved
036h
Reserved
037h
LCD_C blinking memory 1
LCDBM1
040h
LCD_C blinking memory 2
LCDBM2
041h
LCD_C blinking memory 3
LCDBM3
042h
LCD_C blinking memory 4
LCDBM4
043h
LCD_C blinking memory 5
LCDBM5
044h
LCD_C blinking memory 6
LCDBM6
045h
LCD_C blinking memory 7
LCDBM7
046h
LCD_C blinking memory 8
LCDBM8
047h
LCD_C blinking memory 9
LCDBM9
048h
LCD_C blinking memory 10
LCDBM10
049h
LCD_C blinking memory 11
LCDBM11
04Ah
LCD_C blinking memory 12
LCDBM12
04Bh
LCD_C blinking memory 13
LCDBM13
04Ch
LCD_C blinking memory 14
LCDBM14
04Dh
LCD_C blinking memory 15
LCDBM15
04Eh
LCD_C blinking memory 16
LCDBM16
04Fh
LCD_C blinking memory 17
LCDBM17
050h
LCD_C blinking memory 18
LCDBM18
051h
LCD_C blinking memory 19
LCDBM19
052h
LCD_C blinking memory 20
LCDBM20
053h
LCD_C blinking memory 21
LCDBM21
054h
LCD_C blinking memory 22
LCDBM22
055h
Reserved
056h
Reserved
057h
5 to 8 mux modes
LCD_C memory 1
126
Detailed Description
LCDM1
020h
Copyright © 2015, Texas Instruments Incorporated
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Table 6-71. LCD_C Registers (Base Address: 0A00h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C memory 2
LCDM2
021h
LCD_C memory 3
LCDM3
022h
LCD_C memory 4
LCDM4
023h
LCD_C memory 5
LCDM5
024h
LCD_C memory 6
LCDM6
025h
LCD_C memory 7
LCDM7
026h
LCD_C memory 8
LCDM8
027h
LCD_C memory 9
LCDM9
028h
LCD_C memory 10
LCDM10
029h
LCD_C memory 11
LCDM11
02Ah
LCD_C memory 12
LCDM12
02Bh
LCD_C memory 13
LCDM13
02Ch
LCD_C memory 14
LCDM14
02Dh
LCD_C memory 15
LCDM15
02Eh
LCD_C memory 16
LCDM16
02Fh
LCD_C memory 17
LCDM17
030h
LCD_C memory 18
LCDM18
031h
LCD_C memory 19
LCDM19
032h
LCD_C memory 20
LCDM20
033h
LCD_C memory 21
LCDM21
034h
LCD_C memory 22
LCDM22
035h
LCD_C memory 23
LCDM23
036h
LCD_C memory 24
LCDM24
037h
LCD_C memory 25
LCDM25
038h
LCD_C memory 26
LCDM26
039h
LCD_C memory 27
LCDM27
03Ah
LCD_C memory 28
LCDM28
03Bh
LCD_C memory 29
LCDM29
03Ch
LCD_C memory 30
LCDM30
03Dh
LCD_C memory 31
LCDM31
03Eh
LCD_C memory 32
LCDM32
03Fh
LCD_C memory 33
LCDM33
040h
LCD_C memory 34
LCDM34
041h
LCD_C memory 35
LCDM35
042h
LCD_C memory 36
LCDM36
043h
LCD_C memory 37
LCDM37
044h
LCD_C memory 38
LCDM38
045h
LCD_C memory 39
LCDM39
046h
LCD_C memory 40
LCDM40
047h
LCD_C memory 41
LCDM41
048h
LCD_C memory 42
LCDM42
049h
LCD_C memory 43
LCDM43
04Ah
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
127
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
6.14 Identification
6.14.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see Section 8.2.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.12.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 8.2.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.12.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320).
128
Detailed Description
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MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
It is recommended to connect a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail
ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters). Additionally, separated grounds with a single-point connection are recommend
for better noise isolation from digital to analog circuits on the board and are especially recommended to
achieve high analog accuracy.
DVCC
Digital
Power Supply
Decoupling
+
1 µF
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
+
1 µF
100 nF
AVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
Depending on the device variant (see Section 3), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, they must be terminated according to Section 4.5.
Figure 7-2 shows a typical connection diagram.
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LFXIN
or
HFXIN
CL1
LFXOUT
or
HFXOUT
CL2
Figure 7-2. Typical Crystal Connection
See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on
selecting, testing, and designing a crystal oscillator with the MSP430 devices.
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the
target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate
the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide (SLAU278).
130
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TCK
TMS
TCK
GND
RST
TEST/SBWTCK
C1
2.2 nF
(see Note B)
A.
B.
AVSS/DVSS
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kΩ
See Note B
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
2.2 nF
See Note B
A.
B.
AVSS/DVSS
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide
(SLAU367) for more information on the referenced control registers and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see Section 4.5.
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
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7.1.6
SLASE23C – JANUARY 2015 – REVISED MAY 2015
General Layout Recommendations
•
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the
application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
Refer to the Circuit Board Layout Techniques design guide (SLOA089) for a detailed discussion of
PCB layout considerations. This document is written primarily about op amps, but the guidelines are
generally applicable for all mixed-signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See the application report MSP430 System-Level ESD Considerations
(SLAA530) for guidelines.
Do's and Don'ts
It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power
up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed
the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause
malfunction of the device including erroneous writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC12_B Peripheral
7.2.1.1
Partial Schematic
AVSS
Using an
External
Positive
Reference
Using an
External
Negative
Reference
VREF+/VEREF+
+
10 µF
4.7 µF
VEREF+
10 µF
4.7 µF
Figure 7-5. ADC12_B Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. A noise-free design using
separate analog and digital ground planes with a single-point connection is recommend to achieve high
accuracy.
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Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the IO(VREF+) specification of the
Reference module.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A bypass capacitor of 4.7 µF is used to filter out any high frequency noise.
7.2.1.3
Detailed Design Procedure
For additional design information, see the application report Designing With the MSP430FR58xx, FR59xx,
FR68xx, and FR69xx ADC (SLAA624).
7.2.1.4
Layout Guidelines
Component that are shown in the partial schematic (see Figure 7-5) should be placed as close as possible
to the respective device pins. Avoid long traces, because they add additional parasitic capacitance,
inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely
together to minimize the effect of noise on the resulting signal.
7.2.2
LCD_C Peripheral
7.2.2.1
Partial Schematic
Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether
external or internal biasing is used, and whether the on-chip charge pump is employed. Also, there is a
fair amount of flexibility as to how the segment (Sx) and common (COMx) signals are connected to the
MCU which can provide unique benefits. Since LCD connections are application specific, it is difficult to
provide a single one-fits-all schematic. However for examples as well as how-to circuit design guidance
refer to the application report Designing With MSP430™ MCUs and Segment LCDs (SLAA654).
7.2.2.2
Design Requirements
Due to the flexibility of the LCD_C peripheral module to accommodate various segment-based LCDs,
selecting the right display for the application in combination with determining specific design requirements
is often an iterative process. TI strongly recommends reviewing the LCD_C peripheral module chapter in
the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide
(SLAU367) as well as the application report Designing With MSP430™ MCUs and Segment LCDs
(SLAA654) during the initial design requirements and decision process.
7.2.2.3
Detailed Design Procedure
A major component in designing the LCD solution is determining the exact connections between the
LCD_C peripheral module and the display itself. Two basic design processes can be employed for this
step, although in reality often a balanced co-design approach is recommended:
• PCB layout-driven design, optimizing signal routing, or
• Software-driven design, focusing on optimizing computational overhead.
For a detailed discussion of the design procedure as well as for design information regarding the LCD
controller input voltage selection including internal and external options, contrast control, and bias
generation, refer to the application report Designing With MSP430™ MCUs and Segment LCDs
(SLAA654) and the LCD_C controller chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx,
and MSP430FR69xx Family User's Guide (SLAU367).
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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7.2.2.4
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Layout Guidelines
LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is
enabled and should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent
any noise coupling. TI recommends keeping the LCD signal traces on one side of the PCB grouped
together in a bus-like fashion. A ground plane underneath the LCD traces and guard traces employed
alongside the LCD traces can provide shielding.
If the internal charge pump of the LCD module is used, the externally provided capacitor on the LCDCAP
pin should be located as close as possible to the MCU. The capacitor should be connected to the device
using a short and direct trace and also have a solid connection to the ground plane that is supplying the
VSS pins of the MCU.
For an example layouts and a more in-depth discussion of this topic refer to the application report
Designing With MSP430™ MCUs and Segment LCDs (SLAA654).
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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
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8 Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Getting Started
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.1.1.2
Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
8.1.1.2.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
See the application reports Advanced Debugging Using the Enhanced Emulation Module (EEM) With
Code Composer Studio Version 6 (SLAA393) and MSP430™ Advanced Power Optimizations: ULP
Advisor™ and EnergyTrace™ Technology (SLAA603) for further information.
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
EnergyTrace+
+
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
Yes
Yes
EnergyTrace™ technology is supported with Code Composer Studio version 6.0 and newer. It requires
specialized debugger circuitry, which is supported with the second-generation onboard eZ-FET flash
emulation tool and second-generation standalone MSP-FET JTAG emulator. See the application report
MSP430™ Advanced Power Optimizations: ULP Advisor™ and EnergyTrace™ Technology (SLAA603),
the Code Composer Studio for MSP430 User's Guide (SLAU157), and the MSP430 Hardware Tools
User's Guide (SLAU278) for more detailed information.
8.1.1.2.2 Recommended Hardware Options
8.1.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
PACKAGE
TARGET BOARD AND
PROGRAMMER BUNDLE
TARGET BOARD ONLY
64-pin LQFP (PM)
MSP-FET430U64F
MSP-TS430PM64F
8.1.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. The
MSP430FR6989 LaunchPad™ Development Kit (MSP-EXP430FR6989) can be used to experiment with
the devices in this data sheet. See www.ti.com/msp430tools for details.
136
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
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SLASE23C – JANUARY 2015 – REVISED MAY 2015
8.1.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third-party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
PART NUMBER
PC PORT
FEATURES
PROVIDER
MSP-FET
USB
Fast download and debugging. Supports EnergyTrace++ Technology.
Compatible with 4-wire JTAG and 2-wire Spy-Bi-Wire (SBW) JTAG modes.
Small form factor.
Texas Instruments
MSP-FET430UIF
USB
Legacy interface – superseded by MSP-FET. Compatible with 4-wire JTAG
and 2-wire Spy-Bi-Wire (SBW) JTAG modes.
Texas Instruments
8.1.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
PART NUMBER
PC PORT
MSP-GANG
Serial and USB
FEATURES
Program up to eight devices at a time. Works with PC or standalone.
PROVIDER
Texas Instruments
8.1.1.2.3 Recommended Software Options
8.1.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
8.1.1.2.3.2 MSPWare
MSPWare is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSPWare also includes a high-level API called MSP430 Driver Library. This
library makes it easy to program MSP430 hardware. MSPWare is available as a component of CCS or as
a standalone package.
8.1.1.2.3.3 TI-RTOS Kernel
TI-RTOS Kernel is an advanced real-time operating system for the MSP430 microcontrollers. It features
preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time
analysis. TI-RTOS Kernel is available free of charge and is provided with full source code.
8.1.1.2.3.4 Command-Line Programmer
MSP430 Flasher is an open-source shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the
need for an IDE.
8.1.1.3
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430FR59721). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
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XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RGC) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
MSP
430 FR 6 9721
I
RGC
T
Feature Set
Processor Family
430 MCU Platform
Optional: Distribution Format
Device Type
Packaging
Series
Optional: Temperature Range
AES
Oscillators
Optional: BSL
FRAM
Processor
Family
MSP = Mixed Signal Processor
XMS = Experimental Silicon
430 MCU
Platform
TI’s 16-bit Low-Power Microcontroller Platform
Device
Type
Memory Type
FR = FRAM
Series
FRAM 6 Series = Up to 16 MHz with LCD
FRAM 5 Series = Up to 16 MHz without LCD
Feature
Set
AES
9 = AES
8 = No AES
Optional:
Temperature
Range
S = 0°C to 50°C
I = –40°C to 85°C
T = –40°C to 105°C
Oscillators
7 = HFXT + LFXT
2 = LFXT
FRAM (KB)
2 = 64
0 = 32
Packaging
http://www.ti.com/packaging
Optional:
Distribution
Format
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional:
Additional
Features
-Q1 = Automotive Qualified
-EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
Optional - BSL
1 = I2C
No value = UART
Figure 8-1. Device Nomenclature
8.2
Documentation Support
138
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MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
The following documents describe the MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), and
MSP430FR682x(1) microcontrollers. Copies of these documents are available on the Internet at
www.ti.com.
8.3
SLAU367
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
Detailed description of all modules and peripherals available in this device family.
SLAZ627
MSP430FR6972 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ639
MSP430FR69721 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ633
MSP430FR6970 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ629
MSP430FR6922 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ641
MSP430FR69221 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ635
MSP430FR6920 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ628
MSP430FR6872 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ640
MSP430FR68721 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ634
MSP430FR6870 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ630
MSP430FR6822 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ642
MSP430FR68221 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
SLAZ636
MSP430FR6820 Device Erratasheet. Describes the known exceptions to the functional
specifications for each silicon revision of this device.
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FR6972
Click here
Click here
Click here
Click here
Click here
MSP430FR69721
Click here
Click here
Click here
Click here
Click here
MSP430FR6970
Click here
Click here
Click here
Click here
Click here
MSP430FR6872
Click here
Click here
Click here
Click here
Click here
MSP430FR68721
Click here
Click here
Click here
Click here
Click here
MSP430FR6870
Click here
Click here
Click here
Click here
Click here
MSP430FR6922
Click here
Click here
Click here
Click here
Click here
MSP430FR69221
Click here
Click here
Click here
Click here
Click here
MSP430FR6920
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
139
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table 8-1. Related Links (continued)
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FR6822
Click here
Click here
Click here
Click here
Click here
MSP430FR68221
Click here
Click here
Click here
Click here
Click here
MSP430FR6820
Click here
Click here
Click here
Click here
Click here
8.4
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
140
Device and Documentation Support
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
8.5
SLASE23C – JANUARY 2015 – REVISED MAY 2015
Trademarks
EnergyTrace++, MSP430, ULP Advisor, EnergyTrace, LaunchPad, Code Composer Studio, E2E are
trademarks of Texas Instruments.
Microsoft is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
8.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.8
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical, Packaging, and Orderable Information
Submit Documentation Feedback
Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
Copyright © 2015, Texas Instruments Incorporated
141
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR6820IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6820
MSP430FR6820IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6820
MSP430FR6820IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6820
MSP430FR68221IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR68221
MSP430FR68221IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR68221
MSP430FR68221IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR68221
MSP430FR6822IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6822
MSP430FR6822IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6822
MSP430FR6822IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6822
MSP430FR6870IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6870
MSP430FR6870IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6870
MSP430FR68721IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR68721
MSP430FR68721IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR68721
MSP430FR6872IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6872
MSP430FR6872IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6872
MSP430FR6920IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6920
MSP430FR6920IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6920
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-May-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR6920IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6920
MSP430FR69221IG56
ACTIVE
TSSOP
DGG
56
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69221
MSP430FR69221IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69221
MSP430FR69221IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69221
MSP430FR69221IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69221
MSP430FR69221IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69221
MSP430FR69221IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69221
MSP430FR6922IG56
ACTIVE
TSSOP
DGG
56
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6922
MSP430FR6922IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6922
MSP430FR6922IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6922
MSP430FR6922IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6922
MSP430FR6922IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6922
MSP430FR6922IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6922
MSP430FR6970IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6970
MSP430FR6970IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6970
MSP430FR69721IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69721
MSP430FR69721IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69721
MSP430FR69721IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69721
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-May-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR69721IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR69721
MSP430FR6972IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6972
MSP430FR6972IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6972
MSP430FR6972IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6972
MSP430FR6972IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR6972
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430FR6820IG56R
Package Package Pins
Type Drawing
TSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR6820IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6820IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR68221IG56R
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR68221IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR68221IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6822IG56R
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR6822IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6822IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6870IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6870IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR68721IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR68721IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6872IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6872IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6920IG56R
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR6920IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6920IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430FR69221IG56R
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR69221IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR69221IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR69221IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6922IG56R
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR6922IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6922IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6922IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6970IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6970IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR69721IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR69721IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR69721IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6972IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR6972IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430FR6972IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR6820IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR6820IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6820IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR68221IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
MSP430FR68221IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR68221IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR6822IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
MSP430FR6822IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6822IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR6870IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6870IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR68721IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR68721IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR6872IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6872IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR6920IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
MSP430FR6920IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6920IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR69221IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
MSP430FR69221IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR69221IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR69221IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430FR6922IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
MSP430FR6922IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6922IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR6922IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430FR6970IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6970IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR69721IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR69721IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR69721IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430FR6972IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430FR6972IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430FR6972IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
SCALE 1.200
SMALL OUTLINE PACKAGE
C
8.3
TYP
7.9
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
6.2
6.0
29
56X
0.27
0.17
0.08
1.2 MAX
C A
B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
29
28
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
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