Sony CXP82432A Cmos 8-bit single chip microcomputer Datasheet

CXP82432A/82440A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP82432A/82440A is a CMOS 8-bit single
chip microcomputer integrating on a single chip an
A/D converter, serial interface, timer/counter, time
base timer, capture timer counter, fluorescent display
tube controller/driver, remote control reception circuit,
CTL duty detection circuit, 14-bit PWM output and
high-speed output circuit besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O
port.
The CXP82432A/82440A also provides sleep/stop
function that enables lower power consumption.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
—16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
(122µs at 32kHz operation)
• Incorporated ROM capacity
32K bytes (CXP82432A)
40K bytes (CXP82440A)
• Incorporated RAM capacity
1120 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronized type, 1 channel
— Timers
8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display tube controller/driver
Maximum of 384 segments display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (Mask option)
Hardware key scan function
Maximum of 16 x 8 key matrix compatible
— Remote control reception circuit
Incorporated noise elimination circuit
8-bit pulse measuring counter, 6-stage FIFO
— PWM output circuit
14 bits, 1 channel
— CTL duty detection circuit
— High-speed output circuit
Precision of 800ns at 10MHz, 4 outputs
• Interruption
19 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP82400A 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94Z15-PP
RAM
PE7/ADJ
PE7/TO
PB0/CINT
PE1/INT2/EC1
PE0/INT0/EC0
FIFO
FIFO
16 BIT CAPTURE
TIMER/COUNTER 2
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
SERIAL INTERFACE UNIT 1
SERIAL
INTERFACE
UNIT 0
PB1/CS0
PB3/SI0
PB4/SO0
PB2/SCK0
PB6/SI1
PB7/SO1
PB5/SCK1
REMOCON
PE4/RMC
CTL DUTY DET
24
PD0/S0 to PI7/S23
VFDP
FDP
CONTROLLER/
DRIVER
PE5/CTL
PE7/DDO
8
14 BIT PWM GENERATOR
8
T0 to T7
T15/S24 to T8/S31
AVSS
A/D CONVERTER
2
2
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
2 2 2
INTERRUPT CONTROLLER
AVREF
PE6/PWM
8
PA0/AN0 to
PA7/AN7
2
CH0
4
CH1
REALTIME
PULSE
GENERATOR
PRESCALER/
TIME BASE TIMER
ROM
32K/40K BYTES
SPC 700
CPU CORE
TEX
TX
EXTAL
XTAL
VDD
VSS
RST
32kHz
TIMER/COUNTER
RAM
1120 BYTES
CLOCK GEN./
SYSTEM CONTROL
8
PB0 to PB6
7
PF0 to PF7
PG0 to PG7
PH0 to PH7
2
8
8
8
8
PI0 to PI7
PE0 to PE5
PE6 to PE7
6
PD0 to PD7
PC0 to PC7
PB7
PA0 to PA7
8
8
PORT F
PORT G
–2–
PG0/RTO0 to
PG3/RTO3
PORT A
PORT B
PORT C
PORT D
PORT E
PORT H
PORT I
Block Diagram
CXP82432A/82440A
CXP82432A/82440A
T6
T5
T4
T3
T2
T1
T0
VFDP
VDD
NC
Vss
PG0/RTO0
PG1/RTO1
PG2/RTO2
PG3/RTO3
PG4
PG5
PG6
PG7
PE0/EC0/INT0
Pin Assignment (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
T7
2
79
T8/S31
PE3/INT3/NMI
3
78
T9/S30
PE4/RMC
4
77
T10/S29
PE5/CTL
5
76
T11/S28
PE6/PWM
6
75
T12/S27
PE7/TO/DDO/ADJ
7
74
T13/S26
PB0/CINT
8
73
T14/S25
PB1/CS0
9
72
T15/S24
PB2/SCK0
10
71
PI7/S23
PI6/S22
PE1/EC1/INT1
1
PE2/INT2
PB3/SI0
11
70
PB4/SO0
12
69
PI5/S21
PB5/SCK1
13
68
PI4/S20
PB6/SI1
14
67
PI3/S19
PI2/S18
15
66
PC0/KR0
16
65
PI1/S17
PC1/KR1
17
64
PI0/S16
PC2/KR2
18
63
PF7/S15
PC3/KR3
PB7/SO1
19
62
PF6/S14
PC4/KR4
20
61
PF5/S13
PC5/KR5
21
60
PF4/S12
PC6/KR6
22
59
PF3/S11
PC7/KR7
23
58
PF2/S10
PH0
24
57
PF1/S9
PH1
25
56
PF0/S8
PH2
26
55
PD7/S7
PH3
27
54
PD6/S6
PD5/S5
28
53
PH5
29
52
PD4/S4
PH6
30
51
PD3/S3
Note) 1. NC (Pin 90) must be connected to VDD.
2. Vss (Pins 41 and 91) must be connected to GND.
–3–
PD2/S2
PD1/S1
AVss
PD0/S0
AVREF
PA7/AN7
TEX
PA6/AN6
TX
Vss
XTAL
EXTAL
RST
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PA0/AN0
PH4
CXP82432A/82440A
Pin Description
Pin code
I/O
Functions
(Port A)
8-bit I/O port. I/O can
be set in single bit
units.
(8pins)
PA0/AN0
to
PA7/AN7
I/O/
Analog input
PB0/CINT
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
Serial data input (CH1).
PB7/SO1
Output/Output
Serial data output (CH1).
Analog inputs to A/D converter. (8 pins)
Capture input to 16-bit timer/counter.
(Port B)
8-bit I/O port. I/O for
lower 7 bits can be set
in a unit of single bits.
Uppermost bit (PB7) is
for output only.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
PC0/KR0
to
PC7/KR7
I/O/Input
(Port C)
8-bit I/O port. I/O can
Serves as key return inputs when operating
be set in a unit of single
key scan with FDP segment signal.
bits. Capable of driving
12mA sync current.
PD0/S0
to
PD7/S7
Output/Output
(Port D)
8-bit output port.
(8 pins)
PE0/INT0/
EC0
Input/Input/Input
PE1/INT1/
EC1
Input/Input/Input
PE2/INT2
Input/Input
PE3/INT3/
NMI
Input/Input/Input
PE4/RMC
Input/Input
PE5/CTL
Input/Input
Input for CTL duty direction circuit.
PE6/PWM
Output/Output
14-bit PWM output.
PE7/TO/
DDO/ADJ
Output/Output/
Output/Output
Output for the 16-bit timer/counter rectangular
waves, CTU duty detection, and 32kHz
oscillation frequency demultiplication.
PF0/S8
to
PF7/S15
Output/Output
PG0/RTO0
to
PG3/RTO3
I/O/Output
PG4 to PG7
I/O
(Port E)
8-bit port. Lower 6 bits
are for inputs; upper
2 bits are for outputs.
(8 pins)
(Port F)
8-bit output port.
(8pins)
FDP segment signal outputs.
Inputs for
external
interruption
request.
(4 pins)
External event inputs for
timer/counter.
(2 pins)
Non-maskable interruption
request input.
Remote control reception circuit input.
FDP segment signal outputs.
(Port G)
Outputs for real-time pulse generator (RTG).
8-bit I/O port. I/O can
Functions as high-precision, real-time pulse
be set in a unit of single output port.
bits. Data for the lower (4 pins)
4 bits are gated with the
contents of RTO or OR-gate output. (8 pins)
–4–
CXP82432A/82440A
Pin code
I/O
Functions
PH0 to PH7
I/O
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
PI0/S16
to
PI7/S23
Output/Output
(Port I)
8-bit output ports.
(8 pins)
T8/S31
to
T15/S24
Output/Output
Outputs for FDP timing (digit) signals/segment signals.
T0 to T7
Output
FDP timing signal outputs.
VFDP
FDP segment signal outputs.
FDP voltage supply when incorporated resistor is set by mask option.
Crystal connectors system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to
XTAL.
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.
RST
Input
Low-level active, system reset.
NC
AVREF
NC. Under normal operation, connect to VDD.
Input
Reference voltage input for A/D converter.
AVSS
A/D converter GND.
VDD
Vcc supply.
VSS
GND.
–5–
CXP82432A/82440A
I/O Circuit Format for Pins
Pin
When reset
Circuit format
Port A
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
Input multiplexer
IP
“0” when reset
Hi-Z
Data bus
RD (Port A)
Port A input selection
Input protection circuit
“0” when reset
A/D converter
8 pins
Port B
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
Hi-Z
“0” when reset
Schmitt input
Data bus
RD (Port B)
4 pins
CINT
CS0
SI0
SI1
Port B
SCK OUT
Output enable
Port B output selection
“0” when reset
PB2/SCK0
PB5/SCK1
Port B data
IP
Port B direction
“0” when reset
Schmitt input
Data bus
RD (Port B)
SCK in
2 pins
–6–
Hi-Z
CXP82432A/82440A
Pin
When reset
Circuit format
Port B
SO
Ouput enable
Port B output selection
“0” when reset
PB4/SO0
Port B data
Hi-Z
IP
Port B direction
“0” when reset
Data bus
RD (Port B)
1 pin
Port B
Internal reset signal
SO
AAAA
AAAA
AAAA
Output enable
PB7/SO1
∗
Port B output selection
“0” when reset
AA
High level
Port B data
“1” when reset
∗ Pull-up transistor approx.
200kΩ
Data bus
1 pin
RD (Port B)
AAAA
AAAA
AAAA
Port C
Port C data
PC0/KR0
to
PC7/KR7
∗
Port C direction
“0” when reset
AA
AAA
IP
Hi-Z
Data bus
RD (Port C)
8 pins
∗ High current drive of 12mA possible
Key input signal
Port E
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE4/CTL
AA
AA
AAAA
EC0/INT0
EC1/INT1
INT2
INT3/NMI
RMC
CTL
Data bus
Schmitt input
IP
RD (Port E)
6 pins
–7–
Hi-Z
CXP82432A/82440A
Pin
AAAA
AAAA
AAAA
When reset
Circuit format
Port E
AA
AA
PWM
Port E output selection
“0” when reset
PE6/PWM
Port E data
“1” when reset
High level
Data bus
1 pin
RD (Port E)
AA
AA
AA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Port E
Output enable
0
1
MPX
2
3
TO
DDO
ADJ16K∗
ADJ2K∗
PE7/TO/
DDO/ADJ
AA
AA
Port E output selection
Port E output selection
“00” when reset
Port E output selection
“0” when reset
Port E data
“1” when reset
Data bus
1 pin
AAAA
AAAA
AAAA
AAAA
AAAA
High level
∗ ADJ signal is a frequency demultiplication
output for 32kHz oscillation frequency
adjustment.
ADJ2 can be used for buzzer output.
RD (Port E)
Port G
RTO data
“0” when reset
PC0/RTO0
to
PG3/RTO3
Port G data
Port G direction
“0” when reset
Data bus
4 pins
Port H
AAAAA
AAAAA
AAAAA
Port G or Port H data
Port G or Port H direction
“0” when reset
Data bus
12 pins
Hi-Z
IP
RD (Port G)
Port G
PG4 to PG7
PH0 to PH7
AA
AA
AA
AA
RD (Port G or Port H)
–8–
AA
A
IP
Hi-Z
CXP82432A/82440A
Pin
PD0/S0
to
PD7/S7
When reset
Circuit format
Port D
Port F
Port I
PF0/S8
to
PF7/S15
∗ High voltage drive transistor
Segment output data
∗
Output selection control signal
(“0” when reset)
OP
Data for Port D, F, or I
PI0/S16
to
PI7/S23
“0” when reset
Mask option
Pull-down resistor
Hi-Z or
Low level
(when PD
resistance is
added)
VFDP
Data bus
24 pins
RD (Port D, F, or I)
∗ High voltage drive transistor
T15/S24
to
T8/S31
Segment output data
∗
Output selection control signal
(“0” when reset)
T0 to T7
OP
Mask option
Hi-Z or
Low level
(when PD
resistance is
added)
Pull-down resistor
16 pins
EXTAL
XTAL
VFDP
EXTAL
IP
IP
• Diagram shows circuit
composition during
oscillation.
Oscillation
• Feedback resistor is
removed during stop.
XTAL
2 pins
TEX
TX
TEX
• Diagram shows circuit
composition during
oscillation.
IP
IP
Oscillation
• When the operation of the oscillation
circuit is stopped by the software, the
feedback resistor is removed, and TEX
and TX become “Low” level and “High”
level respectively.
TX
2 pins
Pull-up resistor
RST
OP
Low level
Mask option
IP
Schmitt input
1 pin
–9–
CXP82432A/82440A
Absolute Maximum Ratings
Item
Supply voltage
Symbol
VDD
(Vss = 0V reference)
Rating
Unit
–0.3 to +7.0
V
V
Remarks
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
Display output voltage
VOD
VDD–40 to VDD+0.3
V
IOH
–5
mA
As P channel transistor is open drain,
VDD is reference.
All pins excluding outputs∗2 (value per pin)
IODH1
–15
mA
Display outputs S0 to S23 (value per pin)
IODH2
–35
mA
Display outputs T0 to T7, and T8/S31 to
T15/S24 (value per pin)
∑IOH
–40
mA
Total for all pins excluding display outputs
∑IODH
–100
mA
Total for all display outputs
IOL
15
mA
Port 1
IOLC
20
mA
High current Port 1∗3
Low level total output current ∑IOL
100
mA
Total for all output pins
High level output current
High level total output
current
Low level output current
AVss
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
600
mW
Allowable power dissipation PD
∗1) VIN and VOUT must not exceed VDD + 0.3V.
∗2) Specifies output current of general-purpose I/O ports.
∗3) The high current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 10 –
CXP82432A/82440A
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
Min.
Max.
Unit
4.5
5.5
V
High-speed mode
Guaranteed operation range
3.5
5.5
V
Low-speed mode
Guaranteed operation range
2.7
5.5
V
Guaranteed operation range with TEX
clock
2.5
5.5
V
VIH
0.7VDD
VDD
V
VIHS
0.8VDD
VDD
V
VDD
VIHEX
Low level input
voltage
Operating temperature
(Vss = 0V reference)
VDD – 0.4 VDD + 0.3
Remarks
Guaranteed data hold range during STOP
∗1
V
Hysteresis input∗2
EXTAL∗3
∗1
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–20
+75
°C
Hysteresis input∗2
EXTAL∗3
∗1) Value for each pin of normal input port (PA, PB4, PC, PG, PH).
∗2) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, SI0, SI1, EC0/INT0, EC1/INT1, INT2,
INT3/NMI, RMC, CTL.
∗3) Specifies only during external clock input.
– 11 –
CXP82432A/82440A
Electrical Characteristics
DC Characteristics
Item
High level
output current
Low level
output current
(Ta = –20 to +75°C, Vss = 0V reference)
Symbol
VOH
VOL
Pins
PA, PB,
PC, PE6,
PE7, PG,
PH
PC
IIHE
IILE
Input current
IIHT
IILT
IILR
EXTAL
Conditions
IOH
S24/T15 to
S31/T8
T0 to T7
Max.
Unit
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
VDD = 5.5V
VIL = 0.4V
–0.1
–10
µA
–1.5
–400
µA
S0 to S23
Display output
current
Typ.
VDD = 4.5V, IOH = –0.5mA
TEX
RST∗1
Min.
VDD = 4.5V
VOH = VDD – 2.5V
Open drain output
leakage current
ILOL
(P-CH Tr off
state)
S0 to S23
S24/T15 to
S31/T8
T0 to T7
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
Pull-down
resistance∗2
RL
S0 to S23
S24/T15 to
S31/T8
T0 to T7
VDD = 5V
VFDP = VDD – 35V
I/O
leakage current
IIZ
PA to PC
VDD = 5.5V
PE, PG, PH,
VI = 0, 5.5V
RST∗1
– 12 –
–8
mA
–20
mA
60
100
–20
µA
270
kΩ
±10
µA
CXP82432A/82440A
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
20
40
mA
35
100
µA
1.2
8
mA
9
30
µA
10
µA
20
pF
High speed mode operation
(1/2 frequency demultiplier clock)
IDD1
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDD2
Power supply
current∗3
Input
capacity
IDDS1
VDD
SLEEP mode
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
IDDS2
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDDS3
STOP mode
VDD = 5.5V, 10MHz crystal oscillation;
and termination of 32kHz oscillation
CIN
Pins other
than
S0 to S31,
T0 to T7,
PB7, PE6,
AVREF,
AVSS, VFDP,
VDD, VSS
Clock 1MHz
0V for all pins excluding
measured pins
10
∗1) RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected. PB7 does not specify the leakage current because it’s only for output.
∗2) When incorporated pull-down resistance has been selected through mask option.
∗3) When all pins are open.
– 13 –
CXP82432A/82440A
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
System clock frequency
fC
Event count input clock
rise time, fall time
tXL
tXH
tCR
tCF
tEH
tEL
tER
tEF
System clock frequency
fC
Event count input
pulse width
tTL
tTH
tTR
tTF
System clock input pulse width
System clock input rise time,
fall time
Event count input clock
pulse width
Event count input rise time,
fall time
Pin
Conditions
Min.
XTAL
EXTAL
Fig. 1, Fig. 2
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC0,
EC1
Fig. 3
EC0,
EC1
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
application condition)
TEX
Fig. 3
TEX
Fig. 3
Typ.
1
Max.
Unit
10
MHz
ns
37.5
200
tsys + 50∗
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗ tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock registor (address: 00FEH).
tsys (ns)=2000/fc (upper two bits="00"), 4000/fc (upper two bits="01"), 16000/fc (upper two bits="11")
Fig. 1. Clock timing
1/fc
VDD–0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAAAAAA
Fig. 2. Clock application conditions
Crystal oscillation
Ceramic oscillation
EXTAL
C1
32kHz clock application condition
Crystal oscillation
External clock
EXTAL
XTAL
C2
TEX
XTAL
74HC04
TX
C2
C1
Fig. 3. Event count clock timing
0.8VDD
TEX
EC0
EC1
0.2VDD
tEH
tTH
tEF
tTF
– 14 –
tEL
tTL
tER
tTR
CXP82432A/82440A
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0 High level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0 cycle time
tKCY
Input mode
2tsys + 200
ns
SCK0
16000/fc
ns
SCK0
High, Low level width
tKH
tKL
Input mode
tsys + 100
ns
SCK0
Output mode
8000/fc–50
ns
SI0 input set-up time
(for SCK0 ↑)
tSIK
SCK0 input mode
100
ns
SI0
SCK0 output mode
200
ns
SI0 input hold time
(for SCK0 ↑)
tKSI
tsys + 200
ns
SI0
100
ns
SCK0 ↓ → SO0
delay time
tKSO
SO0
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock registor (address: 00FEH).
tsys (ns)=2000/fc (upper two bits="00"), 4000/fc (upper two bits="01"), 16000/fc (upper two bits="11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 15 –
CXP82432A/82440A
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
SI0
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Ouput data
0.2VDD
– 16 –
CXP82432A/82440A
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
tKCY
SCK1
SCK1
High, Low level width
tKH
tKL
SCK1
SI1 input set-up time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
SCK1 cycle time
Min.
Max.
Input mode
1000
ns
Ouput mode
16000/fc
ns
Input mode
400
ns
Ouput mode
8000/fc–50
ns
SCK1 input mode
100
ns
SCK1 ouput mode
200
ns
SCK1 input mode
200
ns
SCK1 ouput mode
100
ns
SCK1 input mode
200
ns
SCK1 ouput mode
100
ns
Note) The load condition for the SCK1output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
Unit
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 17 –
CXP82432A/82440A
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Ta = 25°C
VDD = 5.0V
VSS = AVSS = 0V
Zero transition
voltage
VZT∗1
Full-scale
transition voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Reference input voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN7
Min.
Typ.
–10
10
70
mV
4910
4970
5030
mV
160/fADC∗3
12/fADC∗3
IREF
AVREF current
Condition
Operation mode
SLEEP mode
STOP mode
32kHz operation mode
AVREF
IREFS
µs
µs
VDD – 0.5
VDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
Fig. 6. Definition of A/D converter terms
Digital conversion value
FFH
FEH
∗1) VZT: Value at which the digital transfer value changes
from 00H to 01H and vice versa.
∗2) VFT: Value at which the digital transfer value changes
from FEH to FFH and vice versa.
∗3) fADC indicates the below values due to ADC operation
clock selection (ADCS: Bit 6 of address 00F9H).
During PS2 selection, fADC = fc/2
During PS1 selection, fADC = fc
Linearity error
01H
00H
VFT
VZT
Analog input
– 18 –
CXP82432A/82440A
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
NMI/INT3
Reset input Low level width
tRSL
RST
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 7. Interruption input timing
tIH
tIL
0.8VDD
INT0
INT1
INT2
NMI/INT3
(NMI specifies only for the
falling edge)
0.2VDD
tIL
tIH
Fig. 8. RST input timing
tRSL
RST
0.2VDD
(5) Others
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
CLK input
High, Low level width
tCTH
tCTL
Pin
Condition
tsys = 2000/fc
CTL
Min.
Max.
tsys + 200
ns
Fig. 9. Other timing
tCTH
tCTL
0.8VDD
CTL
0.2VDD
– 19 –
Unit
CXP82432A/82440A
Appendix
Fig. 10. Recommended oscillation circuit
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAA
AAAAA
AAAA AAAAA
(i) Main clock
EXTAL
(ii) Main clock
EXTAL
XTAL
Rd
C1
(iii) Sub clock
EXTAL
TEX
XTAL
XTAL
TX
Rd
C2
Rd
C1
C2
C 1 C2
Manufacturer
MURATA
MFG
CO., LTD.
Model
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CST4.19MGW∗
CST8.00MTW∗
CST10.0MTW∗
RIVER
ELETEC
CO., LTD
fc (MHz)
C2 (pF)
Rd (Ω)
Circuit
example
(i)
30
30
0
4.19
8.00
(ii)
10.00
4.19
HC-49/U03
8.00
12
12
0
10.00
4.19
KINSEKI
LTD.
C1 (pF)
HC-49/U (-S)
P3
8.00
(i)
27
27
0
10.00
20
20
32.768kHz
50
22
(iii)
1M
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Mask option table
Content
Item
Reset pin pull-up resistance
Non-existent
Existent
High voltage drive output port pull-down resistance
Non-existent
Existent
– 20 –
CXP82432A/82440A
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
(16.3)
0.15
0° to 15°
DETAIL A
0.8 ± 0.2
Package Outline
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
– 21 –
Similar pages