TI1 ADS1299IPAGR Low-noise, 8-channel, 24-bit analog front-end for biopotential measurement Datasheet

ADS1299
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SBAS499A – JULY 2012 – REVISED AUGUST 2012
Low-Noise, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements
Check for Samples: ADS1299
FEATURES
1
•
23
•
•
•
•
•
•
•
•
The ADS1299 has a flexible input multiplexer per
channel that can be independently connected to the
internally-generated signals for test, temperature, and
lead-off detection. Additionally, any configuration of
input channels can be selected for derivation of the
patient bias output signal. The ADS1299 operates at
data rates from 250 SPS to 16 kSPS. Lead-off
detection can be implemented internal to the device,
either with an external pull-up or pull-down resistor or
an excitation current sink or source.
Multiple ADS1299 devices can be cascaded in high
channel count systems in a daisy-chain configuration.
The ADS1299 is offered in a TQFP-64 package
specified from –40°C to +85°C.
REF
Test Signals and
Monitors
Reference
ADC1
A2
ADC2
A3
ADC3
A4
ADC4
SPI
APPLICATIONS
•
Medical Instrumentation (EEG and ECG)
Including:
– EEG, Bispectral index (BIS), Evoked audio
potential (EAP), Sleep study monitor
High-Precision, Simultaneous, Multichannel
Signal Acquisition
Oscillator
MUX
Control
A5
ADC5
A6
ADC6
A7
ADC7
GPIO AND CONTROL
•
INPUTS
CLK
A1
SPI
•
•
•
•
•
•
Eight Low-Noise PGAs and Eight HighResolution Simultaneous-Sampling ADCs
Very Low Input-Referred Noise:
1.0 μVPP (70-Hz BW)
Low Power: 5 mW/channel
Input Bias Current: 300 pA
Data Rate: 250 SPS to 16 kSPS
CMRR: –110 dB
Programmable Gain: 1, 2, 4, 6, 8, 12, or 24
Unipolar or Bipolar Supplies:
– Analog: 4.75 V to 5.25 V
– Digital: 1.8 V to 3.6 V
Built-In Bias Drive Amplifier,
Lead-Off Detection, Test Signals
Built-In Oscillator
Internal or External Reference
Flexible Power-Down, Standby Mode
Pin-Compatible with the ADS1298IPAG
SPI™-Compatible Serial Interface
Operating Temperature Range: –40°C to +85°C
With its high levels of integration and exceptional
performance, the ADS1299 enables the creation of
scalable medical instrumentation systems at
significantly reduced size, power, and overall cost.
ADC8
A8
To Channel
¼
DESCRIPTION
The ADS1299 is a low-noise, multichannel,
simultaneous-sampling, 24-bit, delta-sigma (ΔΣ)
analog-to-digital converter (ADC) with a built-in
programmable gain amplifier (PGA), internal
reference, and an onboard oscillator. The ADS1299
incorporates all commonly-required features for
electroencephalogram (EEG) applications.
¼
PATIENT BIAS AND REFERENCE
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
ADS1299
SBAS499A – JULY 2012 – REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FAMILY AND ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE OPTION
NUMBER OF
CHANNELS
ADS1299IPAG
TQFP
8
ADC RESOLUTION
MAXIMUM SAMPLE
RATE (kSPS)
OPERATING
TEMPERATURE
RANGE
24
16
–40°C to +85°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
AVDD to AVSS
–0.3 to +5.5
V
DVDD to DGND
–0.3 to +3.9
V
AVSS to DGND
–3 to +0.2
V
VREF input to AVSS
AVSS – 0.3 to AVDD + 0.3
V
Analog input to AVSS
AVSS – 0.3 to AVDD + 0.3
V
Digital input voltage to DGND
–0.3 to DVDD + 0.3
V
Digital output voltage to DGND
–0.3 to DVDD + 0.3
V
Momentary
100
mA
Continuous
10
mA
Operating range, TA
–40 to +85
°C
Storage range, Tstg
–60 to +150
°C
Maximum junction, TJ
+150
°C
Human body model (HBM)
JEDEC standard 22, test method A114-C.01, all pins
±1000
V
Charged device model (CDM)
JEDEC standard 22, test method C101, all pins
±500
V
Input current
Temperature
Electrostatic
discharge (ESD)
ratings
(1)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Copyright © 2012, Texas Instruments Incorporated
ADS1299
www.ti.com
SBAS499A – JULY 2012 – REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are
at DVDD = 3.3 V, AVDD – AVSS = 5 V, VREF = 4.5 V, external fCLK = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless
otherwise noted.
ADS1299
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale differential input voltage
(AINP – AINN)
±VREF / gain
See the Input Common-Mode Range
subsection of the PGA Settings and Input
Range section
Input common-mode range
Ci
Input capacitance
IIB
Input bias current
20
TA = +25°C, input = 2.5 V
pF
±300
TA = –40°C to +85°C, input = 2.5 V
No lead-off
DC input impedance
V
±300
pA
1000
Current source lead-off detection
(ILEADOFF = 6 nA)
pA
MΩ
500
MΩ
PGA PERFORMANCE
Gain settings
BW
1, 2, 4, 6, 8, 12, 24
Bandwidth
See Table 5
ADC PERFORMANCE
Resolution
DR
Data rate
24
fCLK = 2.048 MHz
Bits
250
16000
SPS
CHANNEL PERFORMANCE (DC Performance)
Input-referred noise (0.01 Hz to 70 Hz)
10 seconds of data, gain = 24 (1)
1.0
250 points, 1 second of data, gain = 24,
TA = +25°C
1.0
1.35
μVPP
250 points, 1 second of data, gain = 24,
TA = –40°C to +85°C
1.0
1.6
μVPP
All other sample rates and gain settings
μVPP
See Noise Measurements section
INL
Integral nonlinearity
EO
Offset error
60
μV
Offset error drift
80
nV/°C
EG
Full-scale with gain = 12, best fit
Gain error
Excluding voltage reference error
Gain drift
Excluding voltage reference drift
8
0.1
Gain match between channels
ppm
±0.5
% of FS
3
ppm/°C
0.2
% of FS
CHANNEL PERFORMANCE (AC Performance)
CMRR
Common-mode rejection ratio
fCM = 50 Hz and 60 Hz (2)
–120
dB
PSRR
Power-supply rejection ratio
fPS = 50 Hz and 60 Hz
96
dB
Crosstalk
fIN = 50 Hz and 60 Hz
–110
dB
SNR
Signal-to-noise ratio
VIN = –2 dBFs, fIN = 10-Hz input, gain = 12
121
dB
THD
Total harmonic distortion
VIN = –0.5 dBFs, fIN = 10 Hz
–99
dB
(1)
(2)
–110
Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with the input shorted
(without electrode resistance) over a 10-second interval.
CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the eight
channels.
Copyright © 2012, Texas Instruments Incorporated
3
ADS1299
SBAS499A – JULY 2012 – REVISED AUGUST 2012
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ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are
at DVDD = 3.3 V, AVDD – AVSS = 5 V, VREF = 4.5 V, external fCLK = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless
otherwise noted.
ADS1299
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PATIENT BIAS AMPLIFIER
μVRMS
Integrated noise
BW = 150 Hz
GBP
Gain bandwidth product
50 kΩ || 10 pF load, gain = 1
100
2
kHz
SR
Slew rate
50 kΩ || 10 pF load, gain = 1
0.07
V/μs
THD
Total harmonic distortion
fIN = 10 Hz, gain = 1
CMIR
Common-mode input range
ISC
Short-circuit current
1.1
mA
Quiescent power consumption
20
μA
–80
dB
AVSS + 0.3
AVDD – 0.3
V
LEAD-OFF DETECT
Continuous
Frequency
One time or periodic
Current
0, fDR / 4
See Register Map section for settings
Hz
7.8, 31.2
Hz
ILEAD_OFF[1:0] = 00
6
ILEAD_OFF[1:0] = 01
24
nA
ILEAD_OFF[1:0] = 10
6
μA
24
μA
ILEAD_OFF[1:0] = 11
nA
Current accuracy
±20
%
Comparator threshold accuracy
±30
mV
4.5
V
AVSS
V
EXTERNAL REFERENCE
VI(ref)
Reference input voltage
VREFN
Negative input
VREFP
Positive input
5-V supply, VREF = (VREFP – VREFN)
AVSS + 4.5
Input impedance
V
5.6
kΩ
INTERNAL REFERENCE
VO
Output voltage
4.5
V
VREF accuracy
±0.2
%
Drift
TA = –40°C to +85°C
35
ppm
150
ms
Analog supply
2
%
Digital supply
2
%
150
ms
Start-up time
SYSTEM MONITORS
Reading error
From power-up to DRDY low
Device wake up
Temperature
sensor reading
Test signal
STANDBY mode
Voltage
µs
145
mV
Coefficient
μV/°C
490
Signal frequency
See Register Map section for settings
Signal voltage
See Register Map section for settings
Accuracy
4
31.25
TA = +25°C
21
20
fCLK / 2 , fCLK / 2
±1, ±2
Hz
mV
±2
%
Copyright © 2012, Texas Instruments Incorporated
ADS1299
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SBAS499A – JULY 2012 – REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are
at DVDD = 3.3 V, AVDD – AVSS = 5 V, VREF = 4.5 V, external fCLK = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless
otherwise noted.
ADS1299
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK
Internal oscillator clock frequency
Nominal frequency
Internal clock accuracy
2.048
MHz
TA = +25°C
±0.5
–40°C ≤ TA ≤ +85°C
±2.5
Internal oscillator start-up time
%
%
μs
20
Internal oscillator power consumption
External clock input frequency
μW
120
CLKSEL pin = 0
1.5
2.048
2.25
MHz
DIGITAL INPUT/OUTPUT (DVDD = 1.8 V to 3.6 V)
VIH
Logic level,
input voltage
High
0.8 DVDD
DVDD + 0.1
V
Low
–0.1
0.2 DVDD
V
IOH = –500 μA
VOL
Logic level,
output voltage
High
Low
IOL = +500 μA
IIN
Input current
VIL
VOH
0.9 DVDD
0 V < VDigitalInput < DVDD
V
0.1 DVDD
V
+10
μA
–10
POWER-SUPPLY REQUIREMENTS
Analog supply (AVDD – AVSS)
DVDD
Digital supply
AVDD – DVDD
4.75
5
5.25
V
1.8
1.8
3.6
V
3.6
V
–2.1
SUPPLY CURRENT (Bias Turned Off)
IAVDD
IDVDD
AVDD – AVSS = 5 V
Normal mode
7.14
mA
DVDD = 3.3 V
1
mA
DVDD = 1.8 V
0.5
mA
POWER DISSIPATION (Analog Supply = 5 V, Bias Amplifiers Turned Off)
Quiescent power dissipation
Quiescent power dissipation,
per channel
Normal mode
39
Power-down
10
42
mW
μW
Standby mode, internal reference
5.1
mW
Normal mode
4.3
mW
TEMPERATURE
Temperature
range
Specified
–40
+85
°C
Operating
–40
+85
°C
Storage
–60
+150
°C
THERMAL INFORMATION
ADS1299
THERMAL METRIC
(1)
PAG
UNITS
64 PINS
θJA
Junction-to-ambient thermal resistance
43.3
θJCtop
Junction-to-case (top) thermal resistance
36.5
θJB
Junction-to-board thermal resistance
60.6
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
19.5
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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PARAMETRIC MEASUREMENT INFORMATION
NOISE MEASUREMENTS
The ADS1299 noise performance can be optimized by adjusting the data rate and PGA setting. When averaging
is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the
input-referred noise, which is particularly useful when measuring low-level biopotential signals. Table 1 to Table 4
summarize the ADS1299 noise performance with a 5-V analog power supply. The data are representative of
typical noise performance at TA = +25°C. The data shown are the result of averaging the readings from multiple
devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used
to calculate the RMS and peak-to-peak noise for each reading. For the lower data rates, the ratio is
approximately 6.6.
Table 1 shows measurements taken with an internal reference. The data are also representative of the ADS1299
noise performance when using a low-noise external reference such as the REF5025.
Table 1. Input-Referred Noise (μVRMS / μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference (1)
PGA
GAIN = 1
PGA
GAIN = 2
DR BITS OF
CONFIG1
REGISTER
OUTPUT
DATA RATE
(SPS)
–3-dB
BANDWIDTH (Hz)
μVRMS
μVPP
SNR (dB)
NOISEFREE
BITS
ENOB
μVRMS
μVPP
SNR (dB)
NOISEFREE
BITS
ENOB
000
16000
4193
21.70
151.89
103.3
15.85
17.16
10.85
75.94
103.3
15.85
17.16
001
8000
2096
6.93
48.53
113.2
17.50
18.81
3.65
25.52
112.8
17.43
18.74
010
4000
1048
4.33
30.34
117.3
18.18
19.49
2.28
15.95
116.9
18.11
19.41
011
2000
524
3.06
21.45
120.3
18.68
19.99
1.61
11.29
119.9
18.60
19.91
100
1000
262
2.17
15.17
123.3
19.18
20.49
1.14
7.98
122.9
19.10
20.41
101
500
131
1.53
10.73
126.3
19.68
20.99
0.81
5.65
125.9
19.60
20.91
110
250
65
1.08
7.59
129.3
20.18
21.48
0.57
3.99
128.9
20.10
21.41
111
n/a
n/a
—
—
—
—
—
—
—
—
—
—
ENOB
(1)
At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.
Table 2. Input-Referred Noise (μVRMS / μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference (1)
PGA
GAIN = 4
DR BITS OF
CONFIG1
REGISTER
OUTPUT
DATA RATE
(SPS)
–3-dB
BANDWIDTH (Hz)
μVRMS
μVPP
000
16000
4193
5.60
39.23
001
8000
2096
1.98
010
4000
1048
011
2000
100
(1)
6
PGA
GAIN = 6
SNR (dB)
NOISEFREE
BITS
ENOB
μVRMS
μVPP
SNR (dB)
NOISEFREE
BITS
103.0
15.81
17.12
3.87
27.10
102.7
15.76
17.06
13.87
112.1
17.31
18.62
1.31
9.19
112.1
17.32
18.62
1.24
8.66
116.1
17.99
19.29
0.93
6.50
115.1
17.82
19.12
524
0.88
6.13
119.2
18.49
19.79
0.66
4.60
118.1
18.32
19.62
1000
262
0.62
4.34
122.2
18.99
20.29
0.46
3.25
121.1
18.81
20.12
101
500
131
0.44
3.07
125.2
19.49
20.79
0.33
2.30
124.1
19.31
20.62
110
250
65
0.31
2.16
128.2
19.99
21.30
0.23
1.62
127.2
19.82
21.13
111
n/a
n/a
—
—
—
—
—
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.
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Table 3. Input-Referred Noise (μVRMS / μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference (1)
PGA
GAIN = 8
PGA
GAIN = 12
DR BITS OF
CONFIG1
REGISTER
OUTPUT
DATA RATE
(SPS)
–3-dB
BANDWIDTH (Hz)
μVRMS
μVPP
SNR (dB)
NOISEFREE
BITS
ENOB
μVRMS
μVPP
SNR (dB)
NOISEFREE
BITS
ENOB
000
16000
4193
3.05
21.32
102.3
15.69
16.99
2.27
15.89
101.3
15.53
16.83
001
8000
2096
1.11
7.80
111.0
17.14
18.45
0.92
6.41
109.2
16.84
18.14
010
4000
1048
0.79
5.52
114.0
17.64
18.95
0.65
4.53
112.2
17.34
18.64
011
2000
524
0.56
3.90
117.1
18.14
19.44
0.46
3.20
115.2
17.84
19.14
100
1000
262
0.39
2.76
120.1
18.64
19.94
0.32
2.26
118.3
18.34
19.65
101
500
131
0.28
1.95
123.1
19.14
20.44
0.23
1.61
121.2
18.83
20.14
110
250
65
0.20
1.38
126.1
19.64
20.95
0.16
1.13
124.3
19.34
20.65
111
n/a
n/a
—
—
—
—
—
—
—
—
—
—
(1)
At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.
Table 4. Input-Referred Noise (μVRMS / μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference (1)
PGA
GAIN = 24
DR BITS OF
CONFIG1
REGISTER
OUTPUT
DATA RATE
(SPS)
–3-dB
BANDWIDTH (Hz)
μVRMS
μVPP
000
16000
4193
1.66
11.64
001
8000
2096
0.80
010
4000
1048
011
2000
100
(1)
SNR (dB)
NOISEFREE
BITS
ENOB
98.0
14.98
16.28
5.57
104.4
16.04
17.35
0.56
3.94
107.4
16.54
17.84
524
0.40
2.79
110.4
17.04
18.35
1000
262
0.28
1.97
113.5
17.54
18.85
101
500
131
0.20
1.39
116.5
18.04
19.35
110
250
65
0.14
0.98
119.5
18.54
19.85
111
n/a
n/a
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.
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TIMING CHARACTERISTICS
tCLK
CLK
tCSSC
tSCLK
SCLK
tCSH
tSDECODE
CS
1
tSPWL
tSPWH
3
2
8
1
3
2
tDIHD
tDIST
tSCCS
8
tDOHD
tDOPD
DIN
tCSDOZ
tCSDOD
Hi-Z
Hi-Z
DOUT
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
tDISCK2ST
MSBD1
DAISY_IN
SCLK
DOUT
1
tDISCK2HT
LSBD1
3
2
216
219
MSBD1
LSB
MSB
218
217
Figure 2. Daisy-Chain Interface Timing
Timing Requirements For Figure 1 and Figure 2 (1)
2.7 V ≤ DVDD ≤ 3.6 V
PARAMETER
DESCRIPTION
tCLK
Master clock period
tCSSC
CS low to first SCLK, setup time
tSCLK
tSPWH,
MIN
444
TYP
1.8 V ≤ DVDD ≤ 2 V
MAX
MIN
666
444
TYP
MAX
UNIT
666
ns
6
17
ns
SCLK period
50
66.6
ns
SCLK pulse width, high and low
15
25
ns
tDIST
DIN valid to SCLK falling edge: setup time
10
10
ns
tDIHD
Valid DIN after SCLK falling edge: hold time
10
11
ns
tDOHD
SCLK falling edge to invalid DOUT: hold time
10
10
ns
tDOPD
SCLK rising edge to DOUT valid: setup time
tCSH
CS high pulse
tCSDOD
CS low to DOUT driven
tSCCS
tSDECODE
tCSDOZ
CS high to DOUT Hi-Z
tDISCK2ST
Valid DAISY_IN to SCLK rising edge: setup time
10
10
ns
tDISCK2HT
Valid DAISY_IN after SCLK rising edge: hold time
10
10
ns
(1)
8
L
17
32
ns
2
2
tCLKs
10
20
ns
Eighth SCLK falling edge to CS high
4
4
tCLKs
Command decode time
4
4
10
tCLKs
20
ns
Specifications apply from –40°C to +85°C. Load on DOUT = 20 pF || 100 kΩ.
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PIN CONFIGURATION
49 DGND
50 DVDD
52 CLKSEL
51 DGND
54 AVDD1
53 AVSS1
55 VCAP3
57 AVSS
56 AVDD
59 AVDD
58 AVSS
60 BIASREF
62 BIASIN
61 BIASINV
64 RESERVED
63 BIASOUT
PAG PACKAGE
TQFP-64
(TOP VIEW)
IN8N
1
48
DVDD
IN8P
2
47
DRDY
IN7N
3
46
GPIO4
IN7P
4
45
GPIO3
IN6N
5
44
GPIO2
IN6P
6
43
DOUT
IN5N
7
42
GPIO1
IN5P
8
41
DAISY_IN
IN4N
9
40
SCLK
IN4P 10
39
CS
IN3N 11
38
START
IN3P 12
37
CLK
IN2N 13
36
RESET
AVSS 32
RESV1 31
VCAP2 30
NC 29
NC 27
VCAP1 28
VCAP4 26
VREFN 25
VREFP 24
AVSS 23
DGND
AVDD 22
33
AVDD 21
IN1P 16
AVSS 20
DIN
AVDD 19
PWDN
34
SRB1 17
35
SRB2 18
IN2P 14
IN1N 15
PIN ASSIGNMENTS
NAME
TERMINAL
FUNCTION
DESCRIPTION
AVDD
19, 21, 22, 56
Supply
Analog supply
AVDD
59
Supply
Charge pump analog supply
AVDD1
54
Supply
Analog supply
AVSS
20, 23, 32, 57
Supply
Analog ground
AVSS
58
Supply
Charge pump analog ground
AVSS1
53
Supply
Analog ground
BIASIN
62
Analog input
Bias drive input to MUX
BIASINV
61
Analog input/output
Bias drive inverting input
BIASOUT
63
Analog output
BIASREF
60
Analog input
Bias drive noninverting input
CS
39
Digital input
SPI chip select; active low
CLK
37
Digital input
Master clock input
CLKSEL
52
Digital input
Master clock select
DAISY_IN
41
Digital input
Daisy-chain input
DGND
33, 49, 51
Supply
DIN
34
Digital input
SPI data in
DOUT
43
Digital output
SPI data out
DRDY
47
Digital output
Data ready; active low
Bias drive output
Digital ground
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PIN ASSIGNMENTS (continued)
(1)
10
NAME
TERMINAL
FUNCTION
DVDD
48, 50
Supply
DESCRIPTION
GPIO1
42
Digital input/output
General-purpose input/output pin
GPIO2
44
Digital input/output
General-purpose input/output pin
GPIO3
45
Digital input/output
GPIO3 in normal mode
GPIO4
46
Digital input/output
GPIO4 in normal mode
IN1N (1)
15
Analog input
Differential analog negative input 1
IN1P
16
Analog input
Differential analog positive input 1
IN2N
13
Analog input
Differential analog negative input 2
IN2P
14
Analog input
Differential analog positive input 2
IN3N
11
Analog input
Differential analog negative input 3
IN3P
12
Analog input
Differential analog positive input 3
IN4N
9
Analog input
Differential analog negative input 4
IN4P
10
Analog input
Differential analog positive input 4
IN5N
7
Analog input
Differential analog negative input 5
IN5P
8
Analog input
Differential analog positive input 5
IN6N
5
Analog input
Differential analog negative input 6
IN6P
6
Analog input
Differential analog positive input 6
IN7N
3
Analog input
Differential analog negative input 7
IN7P
4
Analog input
Differential analog positive input 7
IN8N
1
Analog input
Differential analog negative input 8
IN8P
2
Analog input
Differential analog positive input 8
NC
27, 29
—
Reserved
64
Analog output
RESET
36
Digital input
System reset; active low
RESV1
31
Digital input
Reserved for future use. Must tie to logic low (DGND)
SCLK
40
Digital input
SPI clock
SRB1
17
Analog input/output
Patient stimulus, reference, and bias signal 1
SRB2
18
Analog input/output
Patient stimulus, reference, and bias signal 2
START
38
Digital input
Start conversion
PWDN
35
Digital input
Power-down; active low
VCAP1
28
—
Analog bypass capacitor
VCAP2
30
—
Analog bypass capacitor
VCAP3
55
Analog
Analog bypass capacitor
VCAP4
26
Analog output
Analog bypass capacitor
VREFN
25
Analog input
Negative reference voltage
VREFP
24
Analog input/output
Positive reference voltage
Digital power supply
No connection
Leave as open circuit
Connect unused analog inputs IN1x to IN8x to AVDD.
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TYPICAL CHARACTERISTICS
All plots are at TA = +25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external
clock = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted.
INPUT-REFERRED NOISE
NOISE HISTOGRAM
0.5
800
Gain = 24
Gain = 24
700
0.3
600
0.2
Occurences
0.1
0
−0.1
500
400
300
−0.2
200
−0.3
100
−0.4
G003
0.5
0
10
0.4
9
0.3
8
0.2
7
0.1
5
6
Time (s)
0
4
−0.1
3
−0.2
2
−0.3
1
−0.5
−0.5
−0.4
Input−Referred Noise (µV)
0.4
Input−Referred Noise (µV)
Figure 3.
COMMON-MODE REJECTION RATIO vs FREQUENCY
Data Rate = 4 kSPS
AIN = AVDD − 0.3 V to AVSS + 0.3 V
−110
−115
Gain = 1
Gain = 2
Gain = 4
Gain = 6
Gain = 8
Gain = 12
Gain = 24
−120
−125
−130
10
Data Rate = 250 SPS to 8 kSPS
Data Rate = 16 kSPS
350
Input Leakage Current (pA)
−105
CMRR (dB)
LEAKAGE CURRENT vs INPUT VOLTAGE
400
−100
−135
100
Frequency (Hz)
300
250
200
150
100
50
0
1000
0
0.5
1
G005
Figure 5.
LEAKAGE CURRENT vs TEMPERATURE
4
4.5
5
G006
PSRR vs FREQUENCY
125
100
75
50
Input Voltage = 2.5 V
Data Rate = 250 SPS to 8 kSPS
10 20 30 40 50 60 70 80 90
Temperature (°C)
G007
Power−Supply Rejection Ratio (dB)
150
0
−40 −30 −20 −10 0
2
2.5
3
3.5
Input Voltage (V)
120
175
25
1.5
Figure 6.
200
Leakage Current (pA)
G004
Figure 4.
G=1
G=2
G=4
115
110
G=6
G=8
G = 12
G = 24
105
100
95
90
85
80
10
Figure 7.
100
Frequency (Hz)
1000
G008
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external
clock = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted.
THD vs FREQUENCY
INL vs PGA GAIN
12
Gain = 1
Gain = 2
Gain = 4
Gain = 6
Gain = 8
Gain = 12
Gain = 24
−65
−70
−75
−80
Data Rate = 8 kSPS
AIN = −0.5 dBFS
−85
−90
−95
4
2
0
−2
−4
−6
−8
−10
100
Frequency (Hz)
1000
−0.8 −0.6 −0.4 −0.2 0
0.2 0.4 0.6
Input (Normalized to Full-Scale)
Figure 9.
Figure 10.
INL vs TEMPERATURE
THD FFT PLOT
(60-Hz Signal)
0.8
1
G010
0
PGA Gain = 12
THD = −99 dB
SNR = 120 dB
Data Rate = 500 SPS
−20
−40
Amplitude (dBFS)
4
2
0
−2
−4
−6
−1
−60
−80
−100
−120
−140
+25°C
−40°C
+85°C
−8
−10
−1
G009
Gain = 12
6
Integral Nonlinearity (ppm)
6
−105
8
−160
−0.8 −0.6 −0.4 −0.2 0
0.2 0.4 0.6
Input Range (Normalized to Full−Scale)
0.8
−180
1
0
G011
50
100
150
Frequency (Hz)
200
250
G012
Figure 11.
Figure 12.
FFT PLOT
(60-Hz Signal)
OFFSET vs PGA GAIN
(Absolute Value)
0
600
PGA Gain = 12
THD = −94 dB
SNR = 101 dB
Data Rate = 16 kSPS
−20
−40
500
−60
400
Offset (µV)
Amplitude (dBFS)
8
−100
10
Gain = 1
Gain = 2
Gain = 4
Gain = 6
Gain = 8
Gain = 12
Gain = 24
10
Integral Nonlinearity (ppm)
Total Harmonic Distortion (dB)
−60
−80
−100
−120
300
200
−140
100
−160
−180
0
2000
4000
Frequency (Hz)
6000
8000
0
1
G013
Figure 13.
12
10
PGA Gain
30
G014
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external
clock = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted.
TEST SIGNAL AMPLITUDE ACCURACY
LEAD-OFF COMPARATOR THRESHOLD ACCURACY
80
70
Data From 31 Devices, Two Lots
Data From 31 Devices, Two Lots
70
60
50
Number of Bins
40
30
50
40
30
20
35
30
25
20
15
10
5
0
-20
0.66
0.54
0.42
0.3
0.18
0.06
-0.06
-0.18
-0.29
0
-0.41
0
-0.53
10
-10
20
10
-15
Number of Bins
60
Threshold Error (mV)
Error (%)
G016
G015
Figure 15.
Figure 16.
LEAD-OFF CURRENT SOURCE ACCURACY DISTRIBUTION
350
Current Setting = 24 nA
Number of Bins
300
250
200
150
100
50
2
2.5
1.5
1
0.5
0
−1
−0.5
−1.5
−2
−2.5
−3
−3.5
0
Error in Current Magnitude (nA)
G017
Figure 17.
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OVERVIEW
The ADS1299 is a low-noise, low-power, multichannel, simultaneously-sampling, 24-bit, delta-sigma (ΔΣ) analogto-digital converter (ADC) with an integrated programmable gain amplifier (PGA). This device integrates various
EEG-specific functions that makes it well-suited for scalable electroencephalography (EEG) applications. The
device can also be used in high-performance, multichannel, data acquisition systems by powering down the
EEG-specific circuitry.
The ADS1299 has a highly-programmable multiplexer that allows for temperature, supply, input short, and bias
measurements. Additionally, the multiplexer allows any input electrodes to be programmed as the patient
reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 4, 6, 8, 12, and 24). The ADCs in
the device offer data rates from 250 SPS to 16 kSPS. Communication to the device is accomplished using an
SPI-compatible interface. The device provides four general-purpose input/output (GPIO) pins for general use.
Multiple devices can be synchronized using the START pin.
The internal reference can be programmed to 4.5 V. The internal oscillator generates a 2.048-MHz clock. The
versatile patient bias drive block allows the average of any electrode combination to be chosen in order to
generate the patient drive signal. Lead-off detection can be accomplished by using a current source or sink. A
one-time, in-band, lead-off option and a continuous, out-of-band, internal lead-off option are available. Refer to
Figure 18 for a block diagram.
14
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AVDD AVDD1
DVDD
VREFP VREFN
Test Signal
Temperature Sensor Input
Lead-Off Excitation Source
Power-Supply Signal
Reference
DRDY
IN1P
DS
ADC1
Low-Noise
PGA1
IN1N
SPI
IN2P
Low-Noise
PGA2
DS
ADC2
Low-Noise
PGA3
DS
ADC3
CS
SCLK
DIN
DOUT
IN2N
IN3P
IN3N
CLKSEL
IN4P
DS
ADC4
Low-Noise
PGA4
Oscillator
CLK
IN4N
Control
MUX
GPIO1
IN5P
GPIO4
GPIO3
DS
ADC5
Low-Noise
PGA5
IN5N
GPIO2
IN6P
DS
ADC6
Low-Noise
PGA6
IN6N
PWDN
IN7P
Low-Noise
PGA7
DS
ADC7
Low-Noise
PGA8
DS
ADC8
RESET
IN7N
START
IN8P
IN8N
SRB1
SRB2
AVSS AVSS1
BIASIN
BIAS
Amplifier
BIAS BIAS
REF OUT
BIAS
INV
DGND
Figure 18. Functional Block Diagram
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THEORY OF OPERATION
This section contains details of the ADS1299 internal functional elements. The analog blocks are discussed first,
followed by the digital interface. Blocks implementing EEG-specific functions are covered at the end of this
document.
Throughout this document, fCLK denotes the CLK pin signal frequency, tCLK denotes the CLK pin signal period,
fDR denotes the output data rate, tDR denotes the output data time period, and fMOD denotes the frequency at
which the modulator samples the input.
INPUT MULTIPLEXER
The ADS1299 input multiplexers are very flexible and provide many configurable signal-switching options.
Figure 19 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks,
one for each channel. SRB1, SRB2, and BIASIN are common to all eight blocks. VINP and VINN are separate
for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration,
and configuration. Switch setting selections for each channel are made by writing the appropriate values to the
CHnSET[3:0] register (see the CHnSET: Individual Channel Settings section for details) by writing the
BIAS_MEAS bit in the CONFIG3 register and the SRB1 bit in the MISC1 register (see the CONFIG3:
Configuration Register 3 subsection of the Register Map section for details). Refer to the Input Multiplexer
subsection of the EEG-Specifc Functions section for further information regarding the EEG-specific features of
the multiplexer.
To Next Channels
To Next Channels
Device
MUX
INT_TEST
TESTP
MUX[2:0] = 101
MUX[2:0] =100
TempP
MUX[2:0] =011
MVDDP
From LOFFP
MAIN(1)
VINP
To PGAP
MUX[2:0] =110
MUX[2:0] = 010 AND
BIAS_MEAS
CHxSET[3] = 1
MUX[2:0] =001
(VREFP + VREFN)
2
MUX[2:0] =111
MUX[2:0] =001
MAIN(1) AND SRB1
VINN
To PGAN
MAIN(1)
AND SRB1
From LoffN
(AVDD+AVSS)
2
MVDDN
TempN
BIASREF_INT=1
BIASREF_INT=0
MUX[2:0] = 010
AND
BIAS_MEAS
MUX[2:0] = 011
MUX[2:0] = 100
MUX[2:0] = 101
INT_TEST
SRB2
BIAS_IN
TESTM
BIASREF
SRB1
(1) MAIN is equal to either MUX[2:0] = 000, MUX[2:0] = 110, or MUX[2:0] = 111.
Figure 19. Input Multiplexer Block for One Channel
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Device Noise Measurements
Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(VREFP + VREFN) / 2] to both channel inputs.
This setting can be used to test inherent device noise in the user system.
Test Signals (TestP and TestN)
Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at powerup. This functionality allows the device internal signal chain to be tested out.
Test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 subsection in
the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls
switching at the required frequency.
Temperature Sensor (TempP, TempN)
The ADS1299 contains an on-chip temperature sensor. This sensor uses two internal diodes with one diode
having a current density 16x that of the other, as shown in Figure 20. The difference in diode current densities
yields a voltage difference proportional to absolute temperature.
As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device
temperature tracks PCB temperature closely. Note that self-heating of the ADS1299 causes a higher reading
than the temperature of the surrounding PCB.
The scale factor of Equation 1 converts the temperature reading to degrees Celsius. Before using this equation,
the temperature reading code must first be scaled to microvolts.
Temperature (°C) =
Temperature Reading (mV) - 145,300 mV
490 mV/°C
+ 25°C
(1)
Temperature Sensor Monitor
AVDD
1x
2x
To MUX TempP
To MUX TempN
8x
1x
AVSS
Figure 20. Temperature Sensor Measurement in the Input
Supply Measurements (MVDDP, MVDDN)
Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2,
5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD + AVSS)]; for channels 3 and 4, (MVDDP – MVDDN) is
DVDD / 4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'.
Lead-Off Excitation Signals (LoffP, LoffN)
The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the
lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of
the lead-off block, refer to the Lead-Off Detection subsection in the EEG-Specific Functions section.
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Auxiliary Single-Ended Input
The BIASIN pin is primarily used for routing the bias signal to any electrodes in case the bias electrode falls off.
However, the BIASIN pin can be used as a multiple single-ended input channel. The signal at the BIASIN pin can
be measured with respect to the voltage at the BIASREF pin using any of the eight channels. This measurement
is done by setting the channel multiplexer setting to '010' and the BIAS_MEAS bit of the CONFIG3 register to '1'.
ANALOG INPUT
The ADS1299 analog input is fully differential. Assuming PGA = 1, the input (INP – INN) can span between
–VREF to +VREF. Refer to Table 7 for an explanation of the correlation between the analog input and digital codes.
There are two general methods of driving the ADS1299 analog input: single-ended or differential (as shown in
Figure 21 and Figure 22, respectively). Note that INP and INN are 180°C out-of-phase in the differential input
method. When the input is single-ended, the INN input is held at the common-mode voltage, preferably at midsupply. The INP input swings around the same common voltage and the peak-to-peak amplitude is (commonmode + 1/2 VREF) and (common-mode – 1/2 VREF). When the input is differential, the common-mode is given by
[(INP + INN) / 2]. Both INP and INN inputs swing from (common-mode + 1/2 VREF) to (common-mode – 1/2
VREF). For optimal performance, the ADS1299 is recommended to be used in a differential configuration.
-1/2 VREF to
+1/2 VREF
VREF
peak-to-peak
Device
Common
Voltage
Common
Voltage
Single-Ended Input
Device
VREF
peak-to-peak
Differential Input
Figure 21. Methods of Driving the ADS1299: Single-Ended or Differential
CM + 1/2 VREF
+1/2 VREF
INP
CM Voltage
-1/2 VREF
INN = CM Voltage
CM - 1/2 VREF
t
Single-Ended Inputs
INP
CM + 1/2 VREF
+VREF
CM Voltage
CM - 1/2 VREF
INN
-VREF
t
Differential Inputs
(INP) + (INN)
, Common-Mode Voltage (Single-Ended Mode) = INN.
2
Input Range (Differential Mode) = (AINP - AINN) = VREF - (-VREF) = 2 VREF.
Common-Mode Voltage (Differential Mode) =
Figure 22. Using the ADS1299 in Single-Ended and Differential Input Modes
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PGA SETTINGS AND INPUT RANGE
The low-noise PGA is a differential input and output amplifier, as shown in Figure 23. The PGA has seven gain
settings (1, 2, 4, 6, 8, 12, and 24) that can be set by writing to the CHnSET register (see the CHnSET: Individual
Channel Settings subsection of the Register Map section for details). The ADS1299 has CMOS inputs and
therefore has negligible current noise. Table 5 shows the typical bandwidth values for various gain settings. Note
that Table 5 shows small-signal bandwidth. For large signals, performance is limited by PGA slew rate.
From MuxP
Low-Noise
PgaP
R2
18.15 kW
R1
3.3 kW
(for Gain = 12)
Low-Noise
PgaN
To ADC
R2
18.15 kW
From MuxN
Figure 23. PGA Implementation
Table 5. PGA Gain versus Bandwidth
GAIN
NOMINAL BANDWIDTH AT ROOM
TEMPERATURE (kHz)
1
662
2
332
4
165
6
110
8
83
12
55
24
27
The PGA resistor string that implements the gain has 39.6 kΩ of resistance for a gain of 12. This resistance
provides a current path across the PGA outputs in the presence of a differential input signal. This current is in
addition to the quiescent current specified for the device in the presence of a differential signal at the input.
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Input Common-Mode Range
The usable input common-mode range of the front-end depends on various parameters, including the maximum
differential input signal, supply voltage, PGA gain, and so forth. This range is described in Equation 2:
AVDD - 0.2 -
Gain VMAX_DIFF
2
> CM > AVSS + 0.2 +
Gain VMAX_DIFF
2
where:
VMAX_DIFF = maximum differential signal at the PGA input
CM = common-mode range
(2)
For example:
If VDD = 5 V, gain = 12, and VMAX_DIFF = 350 mV
Then 2.3 V < CM < 2.7 V
Input Differential Dynamic Range
The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This
range is shown in Equation 3.
VREF
±VREF
2 VREF
Max (INP - INN) <
;
Full-Scale Range =
=
Gain
Gain
Gain
(3)
The 5-V supply, with a reference of 4.5 V and a gain of 12 for EEGs, is optimized for power with a differential
input signal of approximately 300 mV.
ADC ΔΣ Modulator
Power Spectral Density (dB)
Each ADS1299 channel has a 24-bit, ΔΣ ADC. This converter uses a second-order modulator optimized for lownoise applications. The modulator samples the input signal at the rate of (fMOD = fCLK / 2). As in the case of any
ΔΣ modulator, the ADS1299 noise is shaped until fMOD / 2, as shown in Figure 24. The on-chip digital decimation
filters explained in the next section can be used to filter out the noise at higher frequencies. These on-chip
decimation filters also provide antialias filtering. This ΔΣ converter feature drastically reduces the complexity of
the analog antialiasing filters typically required with nyquist ADCs.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0.001
0.01
0.1
Normalized Frequency (fIN/fMOD)
1
G001
Figure 24. Modulator Noise Spectrum Up To 0.5 × fMOD
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DIGITAL DECIMATION FILTER
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rates. Higher data rates are typically used in EEG applications for ac lead-off detection.
The digital filter on each channel consists of a third-order sinc filter. The sinc filter decimation ratio can be
adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a
global setting that affects all channels and, therefore, all channels operate at the same data rate in a device.
Sinc Filter Stage (sinx / x)
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of fMOD. The sinc filter attenuates the modulator high-frequency noise, then
decimates the data stream into parallel data. The decimation rate affects the overall converter data rate.
Equation 4 shows the scaled Z-domain transfer function of the sinc filter.
½H(z)½ =
1 - Z- N
3
1 - Z- 1
(4)
The frequency domain transfer function of the sinc filter is shown in Equation 5.
sin
½H(f)½ =
N ´ sin
Npf
fMOD
3
pf
fMOD
where:
N = decimation ratio
(5)
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0
0
-20
-0.5
-40
-1
Gain (dB)
Gain (dB)
The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has infinite attenuation. Figure 25 shows the sinc filter frequency response and Figure 26
shows the sinc filter roll-off. With a step change at input, the filter takes 3 × tDR to settle. After a rising edge of the
START signal, the filter takes tSETTLE time to give the first data output. The settling time of the filters at various
data rates are discussed in the START subsection of the SPI Interface section. Figure 27 and Figure 28 show
the filter transfer function until fMOD / 2 and fMOD / 16, respectively, at different data rates. Figure 29 shows the
transfer function extended until 4 × fMOD. The ADS1299 pass band repeats itself at every fMOD. The input R-C
antialiasing filters in the system should be chosen such that any interference in frequencies around multiples of
fMOD are attenuated sufficiently.
-60
-80
-1.5
-2
-100
-2.5
-120
-3
-140
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
5
0.05
Figure 25. Sinc Filter Frequency Response
0.25
0.3
0.35
0
DR[2:0] = 000
DR[2:0] = 001
DR[2:0] = 010
DR[2:0] = 011
−20
−40
DR[2:0] = 100
DR[2:0] = 101
DR[2:0] = 110
DR[2:0] = 000
DR[2:0] = 001
DR[2:0] = 010
DR[2:0] = 011
−20
−40
−60
Gain (dB)
Gain (dB)
0.2
Figure 26. Sinc Filter Roll-Off
0
−80
−100
DR[2:0] = 100
DR[2:0] = 101
DR[2:0] = 110
−60
−80
−100
−120
−120
−140
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (fIN/fMOD)
G027
Figure 27. Transfer Function of On-Chip
Decimation Filters Until fMOD / 2
22
0.15
Normalized Frequency (fIN / fDR)
Normalized Frequency (fIN / fDR)
−160
0.1
−140
0
0.01
0.02
0.03
0.04
0.05
Normalized Frequency (fIN/fMOD)
0.06
0.07
G028
Figure 28. Transfer Function of On-Chip
Decimation Filters Until fMOD / 16
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0
−20
Gain (dB)
−40
−60
−80
−100
−120
−140
0
0.5
1
1.5
2
2.5
3
Normalized Frequency (fIN/fMOD)
3.5
4
G029
Figure 29. Transfer Function of On-Chip Decimation Filters
Until 4 fMOD for DR[2:0] = 000 and DR[2:0] = 110
REFERENCE
Figure 30 shows a simplified block diagram of the ADS1299 internal reference. The 4.5-V reference voltage is
generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS.
100 mF
VCAP1
R1
(1)
Bandgap
4.5 V
R3
VREFP
(1)
10 mF
R2
(1)
VREFN
AVSS
To ADC Reference Inputs
(1) For VREF = 4.5 V: R1 = 9.8 kΩ, R2 = 13.4 kΩ, and R3 = 36.85 kΩ.
Figure 30. Internal Reference
The external band-limiting capacitors determine the amount of reference noise contribution. For high-end EEG
systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz so that the
reference noise does not dominate system noise.
Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 31
shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the
CONFIG3 register. This power-down is also used to share internal references when two devices are cascaded.
By default, the device wakes up in external reference mode.
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100 kW
10 pF
+5 V
0.1 mF
100 W
+5 V
VIN
10 mF
OUT
22 mF
REF5025
TRIM
To VREFP Pin
OPA211
100 W
0.1 mF
100 mF
22 mF
Figure 31. External Reference Driver
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CLOCK
The ADS1299 provides two methods for device clocking: internal and external. Internal clocking is ideally suited
for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature.
Accuracy varies over the specified temperature range; see the Electrical Characteristics. Clock selection is
controlled by the CLKSEL pin and the CLK_EN register bit.
The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables
and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 6.
The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. During power-down, the
external clock is recommended be shut down to save power.
Table 6. CLKSEL Pin and CLK_EN Bit
CLKSEL PIN
CONFIG1.CLK_EN
BIT
CLOCK SOURCE
CLK PIN STATUS
0
X
External clock
Input: external clock
1
0
Internal clock oscillator
3-state
1
1
Internal clock oscillator
Output: internal clock oscillator
DATA FORMAT
The ADS1299 outputs 24 bits of data per channel in binary twos complement format, MSB first. The LSB has a
weight of [VREF / (223 – 1)]. A positive full-scale input produces an output code of 7FFFFFh and the negative fullscale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale.
Table 7 summarizes the ideal output codes for different input signals. All 24 bits toggle when the analog input is
at positive or negative full-scale.
Table 7. Ideal Output Code versus Input Signal (1)
INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE (2)
≥ VREF
7FFFFFh
+VREF / (223 – 1)
000001h
0
000000h
23
–VREF / (2
– 1)
≤ –VREF (223 / 223 – 1)
(1)
(2)
FFFFFFh
800000h
Only valid for 24-bit resolution data rates.
Excludes effects of noise, linearity, offset, and gain error.
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SPI INTERFACE
The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads
conversion data, reads and writes registers, and controls ADS1299 operation. The DRDY output is used as a
status signal to indicate when data are ready. DRDY goes low when new data are available.
Chip Select (CS)
Chip select (CS) selects the ADS1299 for SPI communication. CS must remain low for the entire serial
communication duration. After the serial communication is finished, always wait four or more tCLK cycles before
taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT
enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is
high or low.
Serial Clock (SCLK)
SCLK is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts out data from the
device. SCLK features a Schmitt-triggered input and clocks data on the DIN and DOUT pins into and out of the
ADS1299. Even though the input has hysteresis, it is recommended to keep SCLK as clean as possible to
prevent glitches from accidentally forcing a clock event. The absolute maximum SCLK limit is specified in the
Serial Interface Timing table. When shifting in commands with SCLK, make sure that the entire set of SCLKs is
issued to the device. Failure to do so can result in the device serial interface being placed into an unknown state,
thus requiring CS to be taken high to recover.
For a single device, the minimum speed required for SCLK depends on the number of channels, number of bits
of resolution, and output data rate. (For multiple cascaded devices, see the Standard Mode subsection of the
Multiple Device Configuration section.)
For example, if the ADS1299 is used in a 500-SPS mode (8 channels, 24-bit resolution), the minimum SCLK
speed is 110 kHz.
Data retrieval can be accomplished either by placing the device in RDATAC mode or by issuing an RDATA
command for data on demand. The SCLK rate limitation in Equation 6 applies to RDATAC. For the RDATA
command, the limitation applies if data must be read in between two consecutive DRDY signals. Equation 6
assumes that there are no other commands issued in between data captures.
tDR - 4 tCLK
tSCLK <
NBITS ´ NCHANNELS + 24
(6)
Data Input (DIN)
The data input pin (DIN) is used along with SCLK to communicate with the ADS1299 (opcode commands and
register data). The device latches data on DIN on the SCLK falling edge.
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Data Output (DOUT)
The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1299. Data on
DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. In read
data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also
indicates when new data are available. This feature can be used to minimize the number of connections between
the device and system controller.
Figure 32 shows the ADS1299 data output protocol.
DRDY
CS
SCLK
216 SCLKs
DOUT
STAT
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
24-Bit
24-Bit
24-Bit
24-Bit
24-Bit
24-Bit
24-Bit
24-Bit
24-Bit
DIN
Figure 32. SPI Bus Data Output
Data Retrieval
Data retrieval can be accomplished in one of two methods. The read data continuous command (see the
RDATAC: Read Data Continuous section) can be used to set the device in a mode to read data continuously
without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read
just one data output from the device (see the SPI Command Definitions section for more details). Conversion
data are read by shifting data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK
rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read
operation.
The number of bits in the data output depends on the number of channels and the number of bits per channel.
For the ADS1299, the number of data outputs is [(24 status bits + 24 bits × 8 channels) = 216 bits]. The format of
the 24 status bits is: (1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO register). The data format for
each channel data are twos complement and MSB first. When channels are powered down using the user
register setting, the corresponding channel output is set to '0'. However, the channel output sequence remains
the same.
The ADS1299 also provides a multiple readback feature. Data can be read out multiple times by simply giving
more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_EN bit in the
CONFIG1 register must be set to '1' for multiple readbacks.
Data Ready (DRDY)
DRDY is an output. When DRDY transitions low, new conversion data are ready. The CS signal has no effect on
the data ready signal. DRDY behavior is determined by whether the device is in RDATAC mode or the RDATA
command is used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read Data
subsections of the SPI Command Definitions section for further details).
When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence
without data corruption.
The START pin or the START command places the device either in normal data capture mode or pulse data
capture mode.
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Figure 33 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1299
with a selected data rate that gives 24-bit resolution). DOUT is latched out at the SCLK rising edge. DRDY is
pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge, regardless of
whether data are being retrieved from the device or a command is being sent through the DIN pin.
DRDY
DOUT
Bit 215
X
Bit 214
Bit 213
SCLK
Figure 33. DRDY with Data Retrieval (CS = 0)
GPIO
The ADS1299 has a total of four general-purpose digital I/O (GPIO) pins available in normal mode of operation.
The digital I/O pins are individually configurable as either inputs or outputs through the GPIOC bits register. The
GPIOD bits in the GPIO register control the pin level. When reading the GPIOD bits, the data returned are the
logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as
an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the
GPIOD bit sets the output value.
If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on
or after a reset. Figure 34 shows the GPIO port structure. The pins should be shorted to DGND if not used.
GPIO Data (read)
GPIO Pin
GPIO Data (write)
GPIO Control
Figure 34. GPIO Port Pin
Power-Down (PWDN)
When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin
high. Upon exiting from power-down mode, the internal oscillator and the reference require time to wake up.
During power-down, the external clock is recommended to be shut down to save power.
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Reset (RESET)
There are two methods to reset the ADS1299: pull the RESET pin low, or send the RESET opcode command.
When using the RESET pin, take the pin low to force a reset. Make sure to follow the minimum pulse width
timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth
SCLK falling edge of the opcode command. On reset, 18 tCLK cycles are required to complete initialization of the
configuration registers to default states and start the conversion cycle. Note that an internal RESET is
automatically issued to the digital filter whenever the CONFIG1 register is set to a new value with a WREG
command.
START
The START pin must be set high or the START command sent to begin conversions. When START is low or if
the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).
When using the START opcode to control conversions, hold the START pin low. The ADS1299 features two
modes to control conversions: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT
(bit 3 of the CONFIG4 register). In multiple device configurations, the START pin is used to synchronize devices
(see the Multiple Device Configuration subsection of the SPI Interface section for more details).
Settling Time
The settling time (tSETTLE) is the time required for the converter to output fully-settled data when the START
signal is pulled high. When START is pulled high, DRDY is also pulled high. The next DRDY falling edge
indicates that data are ready. Figure 35 shows the timing diagram and Table 8 shows the settling time for
different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in
the CONFIG1 register). Table 7 shows the settling time as a function of tCLK. Note that when START is held high
and there is a step change in the input signal, 3 × tDR is required for the filter to settle to the new value. Settled
data are available on the fourth DRDY pulse.
tSETTLE
START Pin
or
START Opcode
DIN
tDR
4 / fCLK
DRDY
Figure 35. Settling Time
Table 8. Settling Time for Different Data Rates
DR[2:0]
NORMAL MODE
UNIT
000
521
tCLK
001
1033
tCLK
010
2057
tCLK
011
4105
tCLK
100
8201
tCLK
101
16393
tCLK
110
32777
tCLK
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Continuous Mode
Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in
Figure 36, the DRDY output goes high when conversions are started and goes low when data are ready.
Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to
complete. Figure 37 and Table 9 show the required DRDY timing to the START pin and the START and STOP
opcode commands when controlling conversions in this mode. To keep the converter running continuously, the
START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the
START signal is pulsed or a STOP command must be issued followed by a START command. This conversion
mode is ideal for applications that require a fixed continuous stream of conversions results.
START Pin
or
or
(1)
DIN
(1)
START
Opcode
STOP
Opcode
tDR
DRDY
(1)
tSETTLE
START and STOP opcode commands take effect on the seventh SCLK falling edge.
Figure 36. Continuous Conversion Mode
tSDSU
DRDY and DOUT
tDSHD
START Pin
or
STOP Opcode
(1)
STOP(1)
STOP(1)
START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
Figure 37. START to DRDY Timing
Table 9. Timing Characteristics for Figure 37 (1)
(1)
30
SYMBOL
DESCRIPTION
MIN
UNIT
tSDSU
START pin low or STOP opcode to DRDY setup time to halt further
conversions
16
1/fCLK
tDSHD
START pin low or STOP opcode to complete current conversion
16
1/fCLK
START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
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Single-Shot Mode
Single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG4 register to '1'. In single-shot
mode, the ADS1299 performs a single conversion when the START pin is taken high or when the START
opcode command is sent. As seen in Figure 38, when a conversion is complete, DRDY goes low and further
conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To
begin a new conversion, take the START pin low and then back high, or transmit the START opcode again. Note
that when switching from continuous mode to pulse mode, make sure the START signal is pulsed or issue a
STOP command followed by a START command.
START
tSETTLE
4 / fCLK
4 / fCLK
Data Updating
DRDY
Figure 38. DRDY with No Data Retrieval in Single-Shot Mode
This conversion mode is provided for applications that require non-standard or non-continuous data rates.
Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data
rate by a factor of four. This mode leaves the system more susceptible to aliasing effects, requiring more
complex analog or digital filtering. Loading on the host processor increases because the processor must toggle
the START pin or send a START command to initiate a new conversion cycle.
MULTIPLE DEVICE CONFIGURATION
The ADS1299 is designed to provide configuration flexibility when multiple devices are used in a system. The
serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal
per device, multiple devices can be connected together. The number of signals needed to interface n devices is
3 + n.
The bias drive amplifiers can be daisy-chained, as explained in the Bias Configuration with Multiple Devices
subsection of the EEG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,
one device must be set as the master for the clock source with the internal oscillator enabled (CLKSEL pin = 1)
and the internal oscillator clock brought out of the device by setting the CLK_EN register bit to '1'. This master
device clock is used as the external clock source for other devices.
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When using multiple devices, the devices can be synchronized with the START signal. The delay from START to
the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more
details on the settling times). Figure 39 shows the behavior of two devices when synchronized with the START
signal.
There are two ways to connect multiple devices with a optimal number of interface pins: cascade mode and
daisy-chain mode.
Device 1
START
CLK
START1
DRDY
DRDY1
CLK
Device 2
START2
DRDY
DRDY2
CLK
CLK
START
DRDY1
DRDY2
Figure 39. Synchronizing Multiple Converters
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Standard Mode
Figure 40a shows a configuration with two devices cascaded together. Together, the devices create a system
with 16 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not
selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This
structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the
majority of applications.
Daisy-Chain Mode
Daisy-chain mode is enabled by setting the DAISY_EN bit in the CONFIG1 register. Figure 40b shows the daisychain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT of one
device is hooked up to the DAISY_IN of the other device, thereby creating a chain. Also, when using daisy-chain
mode, the multiple readback feature is not available. Short the DAISY_IN pin to digital ground if not used.
Figure 2 describes the required timing for the device shown in the configurations of Figure 40. Data from the
ADS1299 appear first on DOUT, followed by the status and data words.
START
(1)
CLK
START
CLK
INT
DRDY
CS
GPO0
START
(1)
CLK
START
DRDY
CLK
INT
CS
GPO
GPO1
Device 1
SCLK
SCLK
DIN
MOSI
DIN
MOSI
DOUT
MISO
DOUT0
MISO
Device 1
DAISY_IN0
SCLK
SCLK
Host Processor
START
CLK
Host Processor
DOUT1
DRDY
CS
SCLK
SCLK
CLK
DIN
Device 2
DRDY
CS
START
DIN
Device 2
DOUT
DAISY_IN1
0
b) Daisy-Chain Configuration
a) Standard Configuration
(1) To reduce pin count, set the START pin low and use the START serial command to synchronize and start conversions.
Figure 40. Multiple Device Configurations
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When all devices in the chain operate in the same register setting, DIN can be shared as well. This configuration
reduces the SPI communication signals to four, regardless of the number of devices. However, because the
individual devices cannot be programmed, the BIAS driver cannot be shared among the multiple devices.
Furthermore, an external clock must be used.
Note that from Figure 2, the SCLK rising edge shifts data out of the ADS1299 on DOUT. The SCLK rising edge
is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster
SCLK rate speed, but also makes the interface sensitive to board-level signal delays. The more devices in the
chain, the more challenging it could become to adhere to setup and hold times. A star-pattern connection of
SCLK to all devices, minimizing DOUT length, and other printed circuit board (PCB) layout techniques helps.
Placing delay circuits (such as buffers) between DOUT and DAISY_IN are ways to mitigate this challenge. One
other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Note also that
daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries.
Figure 41 shows a timing diagram for this mode.
DOUT1
DAISY_IN0
1
SCLK
DOUT
LSB1
MSB1
0
2
3
216
217
LSB0
MSB0
218
219
MSB1
Data From Device 1
337
LSB1
Data From Device 2
Figure 41. Daisy-Chain Timing
The maximum number of devices that can be daisy-chained depends on the data rate at which the device is
operated at. The maximum number of devices can be approximately calculated with Equation 7.
fSCLK
NDEVICES =
fDR (NBITS)(NCHANNELS) + 24
where:
NBITS = device resolution (depending on data rate), and
NCHANNELS = number of channels in the device.
(7)
For example, when the ADS1299 is operated at a 2-kSPS data rate with a 4-MHz fSCLK, 10 devices can be daisychained.
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SPI COMMAND DEFINITIONS
The ADS1299 provides flexible configuration control. The opcode commands, summarized in Table 10, control
and configure device operation. The opcode commands are stand-alone, except for the register read and write
operations that require a second command byte plus data. CS can be taken high or held low between opcode
commands but must stay low for the entire command operation (especially for multi-byte commands). System
opcode commands and the RDATA command are decoded by the ADS1299 on the seventh SCLK falling edge.
The register read and write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing
requirements when pulling CS high after issuing a command.
Table 10. Command Definitions
COMMAND
DESCRIPTION
FIRST BYTE
SECOND BYTE
System Commands
WAKEUP
Wake-up from standby mode
0000 0010 (02h)
STANDBY
Enter standby mode
0000 0100 (04h)
RESET
Reset the device
0000 0110 (06h)
START
Start and restart (synchronize) conversions
0000 1000 (08h)
STOP
Stop conversion
0000 1010 (0Ah)
Data Read Commands
RDATAC
Enable Read Data Continuous mode.
This mode is the default mode at power-up. (1)
0001 0000 (10h)
SDATAC
Stop Read Data Continuously mode
0001 0001 (11h)
RDATA
Read data by command; supports multiple read back.
0001 0010 (12h)
Register Read Commands
RREG
Read n nnnn registers starting at address r rrrr
001r rrrr (2xh) (2)
000n nnnn (2)
WREG
Write n nnnn registers starting at address r rrrr
010r rrrr (4xh) (2)
000n nnnn (2)
(1)
(2)
When in RDATAC mode, the RREG command is ignored.
n nnnn = number of registers to be read or written – 1. For example, to read or write three registers, set n nnnn = 0 (0010). r rrrr =
starting register address for read or write opcodes.
WAKEUP: Exit STANDBY Mode
This opcode exits low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the SPI
Command Definitions section. Time is required when exiting standby mode (see the Electrical Characteristics for
details). There are no SCLK rate restrictions for this command and it can be issued at any time. Any
following commands must be sent after a delay of 4 tCLK cycles.
STANDBY: Enter STANDBY Mode
This opcode command enters low-power standby mode. All parts of the circuit are shut down except for the
reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are
no SCLK rate restrictions for this command and it can be issued at any time. Do not send any other
commands other than the wakeup command after the device enters standby mode.
RESET: Reset Registers to Default Values
This command resets the digital filter cycle and returns all register settings to default values. See the Reset
(RESET) subsection of the SPI Interface section for more details. There are no SCLK rate restrictions for this
command and it can be issued at any time. 18 tCLK cycles are required to execute the RESET command.
Avoid sending any commands during this time.
START: Start Conversions
This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions
are in progress, this command has no effect. The STOP opcode command stops conversions. If the START
command is immediately followed by a STOP command, then there must be a 4-tCLK cycle delay between them.
When the START opcode is sent to the device, keep the START pin low until the STOP command is issued.
(See the START subsection of the SPI Interface section for more details.) There are no SCLK rate restrictions
for this command and it can be issued at any time.
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STOP: Stop Conversions
This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no SCLK rate restrictions for this command and it
can be issued at any time.
RDATAC: Read Data Continuous
This opcode enables conversion data output on each DRDY without the need to issue subsequent read data
opcodes. This mode places the conversion data in the output register and may be shifted out directly. The read
data continuous mode is the device default mode; the ADS1299 defaults to this mode on power-up.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a
SDATAC command must be issued before any other commands can be sent to the device. There are no SCLK
rate restrictions for this command. However, subsequent data retrieval SCLKs or the SDATAC opcode
command should wait at least 4 tCLK cycles. RDATAC timing is shown in Figure 42. As Figure 42 shows, there is
a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued in. If no data are
retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from the device after
the RDATAC command is issued, make sure either the START pin is high or the START command is issued.
Figure 42 shows the recommended way to use the RDATAC command. RDATAC is ideally-suited for
applications such as data loggers or recorders, where registers are set one time and do not need to be
reconfigured.
START
DRDY
tUPDATE
CS
SCLK
RDATAC Opcode
DIN
Hi-Z
DOUT
Status Register + 8-Channel Data (216 Bits)
(1)
Next Data
tUPDATE = 4 / fCLK. Do not read data during this time.
Figure 42. RDATAC Usage
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SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There are no SCLK rate restrictions for this command,
but the next command must wait for 4 tCLK cycles.
RDATA: Read Data
Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There are no SCLK rate restrictions for this command, and there is no wait time needed for the subsequent
commands or data retrieval SCLKs. To retrieve data from the device after the RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the next DRDY occurrence without data corruption. Figure 43 shows
the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type systems,
where register settings must be read or changed often between conversion cycles.
START
DRDY
CS
SCLK
RDATA Opcode
DIN
RDATA Opcode
Hi-Z
DOUT
Status Register+ 8-Channel Data (216 Bits)
Figure 43. RDATA Usage
Sending Multi-Byte Commands
The ADS1299 serial interface decodes commands in bytes and requires 4 tCLK cycles to decode and execute.
Therefore, when sending multi-byte commands, a 4 tCLK period must separate the end of one byte (or opcode)
and the next.
Assuming CLK is 2.048 MHz, then tSDECODE (4 tCLK) is 1.96 µs. When SCLK is 16 MHz, one byte can be
transferred in 500 ns. This byte transfer time does not meet the tSDECODE specification; therefore, a delay must be
inserted so the end of the second byte arrives 1.46 µs later. If SCLK is 4 MHz, one byte is transferred in 2 µs.
Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without
delay. In this later scenario, the serial port can be programmed to move from single-byte transfers per cycle to
multiple bytes.
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RREG: Read From Register
This opcode reads register data. The Register Read command is a two-byte opcode followed by the register data
output. The first byte contains the command opcode and register address. The second opcode byte specifies the
number of registers to read – 1.
First opcode byte: 001r rrrr, where r rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.
The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 44. When
the device is in read data continuous mode, an SDATAC command must be issued before the RREG command
can be issued. The RREG command can be issued any time. However, because this command is a multi-byte
command, there are SCLK rate restrictions depending on how the SCLKs are issued. See the Serial Clock
(SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire
command.
CS
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA
DOUT
REG DATA + 1
Figure 44. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)
(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)
WREG: Write to Register
This opcode writes register data. The Register Write command is a two-byte opcode followed by the register data
input. The first byte contains the command opcode and register address. The second opcode byte specifies the
number of registers to write – 1.
First opcode byte: 010r rrrr, where r rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.
After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 45. The WREG
command can be issued any time. However, because this command is a multi-byte command, there are SCLK
rate restrictions depending on how the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI
Interface section for more details. Note that CS must be low for the entire command.
CS
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA 1
REG DATA 2
DOUT
Figure 45. WREG Command Example: Write Two Registers Starting from 00h (ID Register)
(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)
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REGISTER MAP
Table 11 describes the various ADS1299 registers.
Table 11. Register Assignments
ADDRESS
REGISTER
RESET
VALUE
(Hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00
REV_ID3
REV_ID2
REV_ID1
1
DEV_ID2
DEV_ID1
NU_CH2
NU_CH1
Device Settings (Read-Only Registers)
00h
ID
Global Settings Across Channels
01h
CONFIG1
96
1
DAISY_EN
CLK_EN
1
0
DR2
DR1
DR0
02h
CONFIG2
C0
1
1
0
INT_CAL
0
CAL_AMP0
CAL_FREQ1
CAL_FREQ0
03h
CONFIG3
60
PD_REFBUF
1
1
BIAS_MEAS
BIASREF_INT
PD_BIAS
BIAS_LOFF_
SENS
BIAS_STAT
04h
LOFF
00
COMP_TH2
COMP_TH1
COMP_TH0
0
ILEAD_OFF1
ILEAD_OFF0
FLEAD_OFF1
FLEAD_OFF0
Channel-Specific Settings
05h
CH1SET
61
PD1
GAIN12
GAIN11
GAIN10
SRB2
MUX12
MUX11
MUX10
06h
CH2SET
61
PD2
GAIN22
GAIN21
GAIN20
SRB2
MUX22
MUX21
MUX20
07h
CH3SET
61
PD3
GAIN32
GAIN31
GAIN30
SRB2
MUX32
MUX31
MUX30
08h
CH4SET
61
PD4
GAIN42
GAIN41
GAIN40
SRB2
MUX42
MUX41
MUX40
09h
CH5SET
61
PD5
GAIN52
GAIN51
GAIN50
SRB2
MUX52
MUX51
MUX50
0Ah
CH6SET
61
PD6
GAIN62
GAIN61
GAIN60
SRB2
MUX62
MUX61
MUX60
0Bh
CH7SET
61
PD7
GAIN72
GAIN71
GAIN70
SRB2
MUX72
MUX71
MUX70
0Ch
CH8SET
61
PD8
GAIN82
GAIN81
GAIN80
SRB2
MUX82
MUX81
MUX80
0Dh
BIAS_SENSP
00
BIASP8
BIASP7
BIASP6
BIASP5
BIASP4
BIASP3
BIASP2
BIASP1
0Eh
BIAS_SENSN
00
BIASN8
BIASN7
BIASN6
BIASN5
BIASN4
BIASN3
BIASN2
BIASN1
0Fh
LOFF_SENSP
00
LOFFP8
LOFFP7
LOFFP6
LOFFP5
LOFFP4
LOFFP3
LOFFP2
LOFFP1
10h
LOFF_SENSN
00
LOFFM8
LOFFM7
LOFFM6
LOFFM5
LOFFM4
LOFFM3
LOFFM2
LOFFM1
11h
LOFF_FLIP
00
LOFF_FLIP8
LOFF_FLIP7
LOFF_FLIP6
LOFF_FLIP5
LOFF_FLIP4
LOFF_FLIP3
LOFF_FLIP2
LOFF_FLIP1
Lead-Off Status Registers (Read-Only Registers)
12h
LOFF_STATP
00
IN8P_OFF
IN7P_OFF
IN6P_OFF
IN5P_OFF
IN4P_OFF
IN3P_OFF
IN2P_OFF
IN1P_OFF
13h
LOFF_STATN
00
IN8M_OFF
IN7M_OFF
IN6M_OFF
IN5M_OFF
IN4M_OFF
IN3M_OFF
IN2M_OFF
IN1M_OFF
GPIO and OTHER Registers
14h
GPIO
0F
GPIOD4
GPIOD3
GPIOD2
GPIOD1
GPIOC4
GPIOC3
GPIOC2
GPIOC1
15h
MISC1
00
0
0
SRB1
0
0
0
0
0
16h
MISC2
00
0
0
0
0
0
0
0
0
0
SINGLE_
SHOT
0
PD_LOFF_
COMP
0
17h
CONFIG4
00
0
0
0
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User Register Description
ID: ID Control Register (Factory-Programmed, Read-Only)
Address = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REV_ID3
REV_ID2
REV_ID1
1
DEV_ID2
DEV_ID1
NU_CH2
NU_CH1
This register is programmed during device manufacture to indicate device characteristics.
Bits[7:5]
Not used
Bit 4
Must be set to '1'
Bits[3:0]
Factory-programmed device identification bits
1110 = ADS1299
CONFIG1: Configuration Register 1
Address = 01h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
DAISY_EN
CLK_EN
1
0
DR2
DR1
DR0
This register configures the DAISY_EN bit, clock, and data rate.
Bit 7
Must be set to '1'
Bit 6
DAISY_EN: Daisy-chain and multiple readback mode
This bit determines which mode is enabled.
0 = Daisy-chain mode (default)
1 = Multiple readback mode
CLK_EN: CLK connection (1)
Bit 5
This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bits[4:3]
Must always be set to '10'
Bits[2:0]
DR[2:0]: Output data rate
fMOD = fCLK / 2.
These bits determine the output data rate of the device.
(1)
(1)
40
Additional power is consumed when driving external devices.
BIT
DATA RATE
SAMPLE RATE (1)
000
fMOD / 64
16 kSPS
001
fMOD / 128
8 kSPS
010
fMOD / 256
4 kSPS
011
fMOD / 512
2 kSPS
100
fMOD / 1024
1 kSPS
101
fMOD / 2048
500 SPS
110 (default)
fMOD / 4096
250 SPS
111
Do not use
n/a
fCLK = 2.048 MHz.
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CONFIG2: Configuration Register 2
Address = 02h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
1
0
INT_CAL
0
CAL_AMP0
CAL_FREQ1
CAL_FREQ0
This register configures the test signal generation. See the Input Multiplexer section for more details.
Bits[7:5]
Must always be set to '110'
Bit 4
INT_CAL: TEST source
This bit determines the source for the Test signal.
0 = Test signals are driven externally (default)
1 = Test signals are generated internally
Bit 3
Must always be set to '0'
Bit 2
CAL_AMP0: Test signal amplitude
This bit determines the calibration signal amplitude.
0 = 1 × (VREFP – VREFN) / 2.4 mV (default)
1 = 2 × (VREFP – VREFN) / 2.4 mV
Bits[1:0]
CAL_FREQ[1:0]: Test signal frequency
These bits determine the calibration signal frequency.
00 = Pulsed at fCLK / 221 (default)
01 = Pulsed at fCLK / 220
10 = Not used
11 = At dc
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CONFIG3: Configuration Register 3
Address = 03h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PD_REFBUF
1
1
BIAS_MEAS
BIASREF_INT
PD_BIAS
BIAS_LOFF_SENS
BIAS_STAT
This register configures multi-reference and bias operations.
Bit 7
PD_REFBUF: Power-down reference buffer
This bit determines the power-down reference buffer state.
0 = Power-down internal reference buffer (default)
1 = Internal reference buffer enabled
Bits[6:5]
Must always be set to '1'
Bit 4
BIAS_MEAS: BIAS measurement
This bit enables BIAS measurement. The BIAS signal may be measured with any channel.
0 = Open (default)
1 = BIASIN signal is routed to the channel that has the MUX_Setting 010 (VREF)
Bit 3
BIASREF_INT: BIASREF signal
This bit determines the BIASREF signal source.
0 = BIASREF signal fed externally (default)
1 = BIASREF signal (AVDD – AVSS) / 2 generated internally
Bit 2
PD_BIAS: BIAS buffer power
This bit determines the BIAS buffer power state.
0 = BIAS buffer is powered down (default)
1 = BIAS buffer is enabled
Bit 1
BIAS_LOFF_SENS: BIAS sense function
This bit enables the BIAS sense function.
0 = BIAS sense is disabled (default)
1 = BIAS sense is enabled
Bit 0
BIAS_STAT: BIAS lead-off status
This bit determines the BIAS status.
0 = BIAS is connected (default)
1 = BIAS is not connected
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LOFF: Lead-Off Control Register
Address = 04h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COMP_TH2
COMP_TH1
COMP_TH0
0
ILEAD_OFF1
ILEAD_OFF0
FLEAD_OFF1
FLEAD_OFF0
This register configures the lead-off detection operation.
Bits[7:5]
COMP_TH[2:0]: Lead-off comparator threshold
These bits determine the lead-off comparator threshold level setting. See the Lead-Off Detection subsection of the EEGSpecific Functions section for a detailed description.
Comparator positive side
000 = 95% (default)
001 = 92.5%
010 = 90%
011 = 87.5%
100 = 85%
101 = 80%
110 = 75%
111 = 70%
Comparator negative side
000 = 5% (default)
001 = 7.5%
010 = 10%
011 = 12.5%
100 = 15%
101 = 20%
110 = 25%
111 = 30%
Bit 4
Must always be set to '0'
Bits[3:2]
ILEAD_OFF[1:0]: Lead-off current magnitude
These bits determine the magnitude of current for the current lead-off mode.
00 = 6 nA (default)
01 = 24 nA
10 = 6 µA
11 = 24 µA
Bits[1:0]
FLEAD_OFF[1:0]: Lead-off frequency
These bits determine the frequency of lead-off detect for each channel.
00 = DC lead-off detection (default)
01 = AC lead-off detection at 7.8 Hz (SYS_CLK / 218)
10 = AC lead-off detection at 31.2 Hz (SYS_CLK / 216)
11 = AC lead-off detection at fDR / 4
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CHnSET: Individual Channel Settings (n = 1:8)
Address = 05h to 0Ch
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PD1
GAIN12
GAIN11
GAIN10
SRB2
MUX12
MUX11
MUX10
This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer
section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels.
Bit 7
PD: Power-down
This bit determines the channel power mode for the corresponding channel.
0 = Normal operation (default)
1 = Channel power-down
Bits[6:4]
GAIN[2:0]: PGA gain
These bits determine the PGA gain setting.
000 = 1
001 = 2
010 = 4
011 = 6
100 = 8
101 = 12
110 = 24 (default)
111 = n/a
Bit 3
SRB2: Source, reference bias channel
This bit determines the SRB2 connection for the corresponding channel.
0 = Open (off) (default)
1 = Closed (on)
Bits[2:0]
MUXn[2:0]: Channel input
These bits determine the channel input selection.
000 = Normal electrode input (default)
001 = Input shorted (for offset or noise measurements)
010 = Used in conjunction with BIAS_MEAS bit for BIAS measurements. See the Bias Drive (DC Bias Circuit) subsection of
the EEG-Specific Functions section for more details.
011 = MVDD for supply measurement
100 = Temperature sensor
101 = Test signal
110 = BIAS_DRP (positive electrode is the driver)
111 = BIAS_DRN (negative electrode is the driver)
BIAS_SENSP: Bias Drive Positive Sense Selection
Address = 0Dh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIASP8
BIASP7
BIASP6
BIASP5
BIASP4
BIASP3
BIASP2
BIASP1
This register controls the selection of positive signals from each channel for bias drive derivation. See the Bias
Drive (DC Bias Circuit) subsection of the EEG-Specific Functions section for details.
BIAS_SENSN: Bias Drive Negative Sense Selection
Address = 0Eh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIASN8
BIASN7
BIASN6
BIASN5
BIASN4
BIASN3
BIASN2
BIASN1
This register controls the selection of negative signals from each channel for bias drive derivation. See the Bias
Drive (DC Bias Circuit) subsection of the EEG-Specific Functions section for details.
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LOFF_SENSP: Lead Off Positive Sense Selection
Address = 0Fh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOFFP8
LOFFP7
LOFFP6
LOFFP5
LOFFP4
LOFFP3
LOFFP2
LOFFP1
This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection
subsection of the EEG-Specific Functions section for details. Note that the LOFF_STATP register bits are only
valid if the corresponding LOFF_SENSP bits are set to '1'.
LOFF_SENSN: Lead Off Negative Sense Selection
Address = 10h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOFFM8
LOFFM7
LOFFM6
LOFFM5
LOFFM4
LOFFM3
LOFFM2
LOFFM1
This register selects the negative side from each channel for lead-off detection. See the Lead-Off Detection
subsection of the EEG-Specific Functions section for details. Note that the LOFF_STATN register bits are only
valid if the corresponding LOFF_SENSN bits are set to '1'.
LOFF_FLIP: Lead Off Current Direction Control
Address = 11h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOFF_FLIP8
LOFF_FLIP7
LOFF_FLIP6
LOFF_FLIP5
LOFF_FLIP4
LOFF_FLIP3
LOFF_FLIP2
LOFF_FLIP1
This register controls the current direction used for lead-off derivation. See the Lead-Off Detection subsection of
the EEG-Specific Functions section for details.
LOFF_STATP: Lead-Off Positive Input Status
Address = 12h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN8P_OFF
IN7P_OFF
IN6P_OFF
IN5P_OFF
IN4P_OFF
IN3P_OFF
IN2P_OFF
IN1P_OFF
This register stores the status of whether the positive electrode on each channel is on or off. See the Lead-Off
Detection subsection of the EEG-Specific Functions section for details. Ignore the LOFF_STATP values if the
corresponding LOFF_SENSP bits are not set to '1'.
'0' is lead-on (default) and '1' is lead-off. When the LOFF_SENSP bits are '0', the LOFF_STATP bits should be
ignored.
LOFF_STATN: Lead-Off Negative Input Status
Address = 13h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN8M_OFF
IN7M_OFF
IN6M_OFF
IN5M_OFF
IN4M_OFF
IN3M_OFF
IN2M_OFF
IN1M_OFF
This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off
Detection subsection of the EEG-Specific Functions section for details. Ignore the LOFF_STATN values if the
corresponding LOFF_SENSN bits are not set to '1'.
'0' is lead-on (default) and '1' is lead-off. When the LOFF_SENSN bits are '0', the LOFF_STATP bits should be
ignored.
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GPIO: General-Purpose I/O Register
Address = 14h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIOD4
GPIOD3
GPIOD2
GPIOD1
GPIOC4
GPIOC3
GPIOC2
GPIOC1
This register controls the action of the four GPIO pins.
Bits[7:4]
GPIOD[4:1]: GPIO data
These bits are used to read and write data to the GPIO ports.
When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are
programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the
GPIOD has no effect.
Bits[3:0]
GPIOC[4:1]: GPIO control (corresponding GPIOD)
These bits determine if the corresponding GPIOD pin is an input or output.
0 = Output
1 = Input (default)
MISC1: Miscellaneous 1
Address = 15h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
SRB1
0
0
0
0
0
This register is for miscellaneous use.
Bits[7:6]
Must always be set to '0'
Bit 5
SRB1: Stimulus, reference, and bias 1
This bit connects the SRB1 to all eight channels inverting inputs.
0 = Switches open (default)
1 = Switches closed
Bits[4:0]
Must always be set to '0'
MISC2: Miscellaneous 2
Address = 16h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
This register is for miscellaneous use.
Bits[7:0]
46
Must always be set to '0'
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CONFIG4: Configuration Register 4
Address = 17h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
SINGLE_SHOT
0
PD_LOFF_COMP
0
Bits[7:4]
Must always be set to '0'
Bit 3
SINGLE_SHOT: Single-shot conversion
This bit sets the conversion mode.
0 = Continuous conversion mode (default)
1 = Single-shot mode
Bit 2
Must always be set to '0'
Bit 1
PD_LOFF_COMP: Lead-off comparator power-down
This bit powers down the lead-off comparators.
0 = Lead-off comparators disabled (default)
1 = Lead-off comparators enabled
Bit 0
Must always be set to '0'
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EEG-SPECIFIC FUNCTIONS
INPUT MULTIPLEXER (Rerouting the BIAS Drive Signal)
The input multiplexer has EEG-specific functions for the bias drive signal. The BIAS signal is available at the
BIASOUT pin when the appropriate channels are selected for BIAS derivation, feedback elements are installed
external to the chip, and the loop is closed. This signal can either be fed after filtering or fed directly into the
BIASIN pin, as shown in Figure 46. This BIASIN signal can be multiplexed into any input electrode by setting the
MUX bits of the appropriate channel set registers to '110' for P-side or '111' for N-side. Figure 46 shows the BIAS
signal generated from channels 1, 2, and 3 and routed to the N-side of channel 8. This feature can be used to
dynamically change the electrode that is used as the reference signal to drive the patient body.
BIAS_SENSP[0] = 1
IN1P
Low-Noise
PGA1
BIAS_SENSN[0] = 1
MUX1[2:0] = 000
IN1N
BIAS_SENSP[1] = 1
IN2P
Low-Noise
PGA2
BIAS_SENSN[1] = 1
MUX2[2:0] = 000
IN2N
BIAS_SENSP[2] = 1
IN3P
Low-Noise
PGA3
BIAS_SENSN[2] = 1
MUX3[2:0] = 000
¼
¼
¼
IN3N
BIAS_SENSP[7] = 0
IN8P
Low-Noise
PGA8
MUX8[2:0] = 111
BIAS_SENSN[7] = 0
IN8N
BIASREF_INT = 1
MUX
(AVDD + AVSS)
2
BIASREF_INT = 0
BIAS_AMP
Device
BIASIN
BIASREF
Filter or
Feedthrough
BIASOUT
1 MW
BIASINV
(1)
1.5 nF
(1)
(1) Typical values for example only.
Figure 46. Example of BIASOUT Signal Configured to be Routed to IN8N
48
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INPUT MULTIPLEXER (Measuring the BIAS Drive Signal)
Also, the BIASOUT signal can be routed to a channel (that is not used for the calculation of BIAS) for
measurement. Figure 47 shows the register settings to route the BIASIN signal to channel 8. The measurement
is done with respect to the voltage on the BIASREF pin. If BIASREF is chosen to be internal, it would be at
[(AVDD + AVSS) / 2]. This feature is useful for debugging purposes during product development.
BIAS_SENSP[0] = 1
IN1P
Low-Noise
PGA1
MUX1[2:0] = 000
BIAS_SENSN[0] = 1
IN1N
BIAS_SENSP[1] = 1
IN2P
Low-Noise
PGA2
BIAS_SENSN[1] = 1
MUX2[2:0] = 000
IN2N
BIAS_SENSP[2] = 1
IN3P
Low-Noise
PGA3
MUX3[2:0] = 000
BIAS_SENSN[2] = 1
¼
¼
¼
IN3N
BIAS_SENSP[7] = 0
IN8P
Low-Noise
PGA8
MUX8[2:0] = 111
BIAS_SENSN[7] = 0
IN8N
MUX
MUX8[2:0] = 010
AND
BIAS_MEAS = 1
BIASREF_INT = 1
(AVDD + AVSS)
2
BIAS_AMP
BIASREF_INT = 0
Device
BIASIN
BIASREF
Filter or
Feedthrough
BIASOUT
1 MW
BIASINV
(1)
1.5 nF
(1)
(1) Typical values for example only.
Figure 47. BIASOUT Signal Configured to be Read Back by Channel 8
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LEAD-OFF DETECTION
Patient electrode impedances are known to decay over time. These electrode connections must be continuously
monitored to verify that a suitable connection is present. The ADS1299 lead-off detection functional block
provides significant flexibility to the user to choose from various lead-off detection strategies. Though called leadoff detection, this is in fact an electrode-off detection.
The basic principle is to inject an excitation signal and measure the response to determine if the electrode is off.
As shown in the lead-off detection functional block diagram in Figure 48, this circuit provides two different
methods of determining the state of the patient electrode. The methods differ in the frequency content of the
excitation signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENSP and
LOFF_SENSN registers. Also, the internal excitation circuitry can be disabled and just the sensing circuitry can
be enabled.
Patient
Skin,
Electrode Contact
Model
Patient
Protection
Resistor
Z1
47 nF
51 kW
VINP
VINN
51 kW
Z2
47 nF
LOFF_SENSP
To ADC
LOFF_SENSN
FLEAD_OFF[0:1]
Z3
47 nF
6 nA and 24 nA
6 mA and 24 mA
51 kW
BIAS OUT
AVDD
AVSS
Figure 48. Lead-Off Detection
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DC Lead-Off
In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an
external pull-up or pull-down resistor or an internal current source or sink, as shown in Figure 49. One side of the
channel is pulled to supply and the other side is pulled to ground. The pull-up and pull-down current can be
swapped (as shown in Figure 49b and Figure 49c) by setting the bits in the LOFF_FLIP register. In case of a
current source or sink, the magnitude of the current can be set by using the ILEAD_OFF[1:0] bits in the LOFF
register. The current source or sink gives larger input impedance compared to the 10-MΩ pull-up or pull-down
resistor.
AVDD
AVDD
Device
AVDD
Device
Device
10 MW
INP
INP
Low-Noise
PGAn
INN
INP
Low-Noise
PGAn
INN
Low-Noise
PGAn
INN
10 MW
AVSS
a) External Pull-Up or Pull-Down Resistors
b) Input Current Source
(LOFF_FLIP = 0)
c) Input Current Source
(LOFF_FLIP = 1)
Figure 49. DC Lead-Off Excitation Options
Sensing of the response can be done either by searching the digital output code from the device or by monitoring
the input voltages with an on-chip comparator. If either electrode is off, the pull-up and pull-down resistors
saturate the channel. Searching the output code determines if either the P-side or the N-side is off. To pinpoint
which one is off, the comparators must be used. The input voltage is also monitored using a comparator and a 3bit DAC whose levels are set by the COMP_TH[2:0] bits in the LOFF register. The output of the comparators are
stored in the LOFF_STATP and LOFF_STATN registers. These registers are available as a part of the output
data stream. (See the Data Output (DOUT) subsection of the SPI Interface section.) If dc lead-off is not used, the
lead-off comparators can be powered down by setting the PD_LOFF_COMP bit in the CONFIG4 register.
An example procedure to turn on dc lead-off is given in the Lead-Off subsection of the Quick-Start Guide section.
AC Lead-Off (One Time or Periodic)
In this method, an in-band ac signal is used for excitation. The ac signal is generated by alternatively providing a
current source and sink at the input with a fixed frequency. The frequency can be chosen by the
FLEAD_OFF[1:0] bits in the LOFF register. The excitation frequency is chosen to be one of the two in-band
frequency selections (7.8 Hz or 31.2 Hz). This in-band excitation signal is passed through the channel and
measured at the output.
Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the
output. The ac excitation signals are introduced at a frequency that is in the band of interest. The signal can be
filtered out separately and processed. By measuring the magnitude of the excitation signal at the output
spectrum, the electrode impedance can be calculated.
For continuous lead-off, an out-of-band ac current source or sink must be externally applied to the inputs. This
signal can then be digitally post processed to determine the electrode impedance.
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BIAS LEAD-OFF
The ADS1299 provides two modes for determining whether the BIAS is correctly connected:
• BIAS lead-off detection during normal operation
• BIAS lead-off detection during power-up
The following sections provide details of the two modes of operation.
BIAS Lead-Off Detection During Normal Operation
During normal operation, the ADS1299 BIAS lead-off at power-up function cannot be used because it is
necessary to power off the BIAS amplifier.
BIAS Lead Off Detection At Power-Up
This feature is included in the ADS1299 for use in determining whether the bias electrode is suitably connected.
At power-up, the ADS1299 provides two measurement procedures to determine the BIAS electrode connection
status using either a current or an external pull-down resistor, as shown in Figure 50. The reference level of the
comparator is set to determine the acceptable BIAS impedance threshold.
Patient
Skin,
Electrode Contact
Model
Patient
Protection
Resistor
To ADC input (through VREF
connection to any of the channels).
47 nF
BIAS_STAT
51 kW
BIAS_SENS
ILGND_OFF[1:0]
AVSS
Figure 50. BIAS Lead-Off Detection at Power-Up
When the BIAS amplifier is powered on, the current source has no function. Only the comparator can be used to
sense the voltage at the output of the BIAS amplifier. The comparator thresholds are set by the same LOFF[7:5]
bits used to set the thresholds for other negative inputs.
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BIAS DRIVE (DC BIAS CIRCUIT)
The bias circuitry is used as a means to counter the common-mode interference in a EEG system as a result of
power lines and other sources, including fluorescent lights. The bias circuit senses the common-mode of a
selected set of electrodes and creates a negative feedback loop by driving the body with an inverted commonmode signal. The negative feedback loop restricts the common-mode movement to a narrow range, depending
on the loop gain. Stabilizing the entire loop is specific to the individual user system based on the various poles in
the loop. The ADS1299 integrates the muxes to select the channel and an operational amplifier. All amplifier
terminals are available at the pins, allowing the user to choose the components for the feedback loop. The circuit
in Figure 52 illustrates the overall functional connectivity for the bias circuit.
The reference voltage for the bias drive can be chosen to be internally generated [(AVDD + AVSS) / 2] or it can
be provided externally with a resistive divider. The selection of an internal versus external reference voltage for
the bias loop is defined by writing the appropriate value to the BIASREF_INT bit in the CONFIG2 register.
If the bias function is not used, the amplifier can be powered down using the PD_BIAS bit (see the CONFIG3:
Configuration Register 3 subsection of the Register Map section for details). This bit is also used in daisy-chain
mode to power-down all but one of the bias amplifiers.
The BIASIN pin functionality is explained in the Input Multiplexer section. An example procedure to use the bias
amplifier is shown in the Bias Drive subsection of the Quick-Start Guide section.
Bias Configuration with Multiple Devices
Figure 51 shows multiple devices connected to the bias drive.
BIASIN BIAS BIAS
REF OUT
VA1-8 VA1-8
BIASINV
Device 1
Power-Down
VA1-8 VA1-8
BIASIN BIAS BIAS
REF OUT
BIASINV
To Input MUX
Device 2
To Input MUX
To Input MUX
Device N
Power-Down
BIASIN BIAS BIAS
REF OUT
VA1-8 VA1-8
BIASINV
Figure 51. Bias Drive Connection for Multiple Devices
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From
MUX1P
BIAS1P
220 kW
PGA1P
18.15 kW
220 kW
From
MUX2P
BIAS2P
PGA2P
3.3 kW
18.15 kW
18.15 kW
3.3 kW
220 kW
PGA1N
From
MUX1N
BIAS1N
From
MUX3P
BIAS3P
18.15 kW
220 kW
PGA2N
From
MUX2N
BIAS2N
220 kW
PGA3P
18.15 kW
220 kW
From
MUX4P
BIAS4P
PGA4P
3.3 kW
18.15 kW
18.15 kW
3.3 kW
220 kW
PGA3N
From
MUX3N
BIAS3N
From
MUX5P
BIAS5P
18.15 kW
220 kW
PGA4N
BIAS4N
From
MUX4N
BIAS6P
From
MUX6P
220 kW
PGA5P
18.15 kW
220 kW
PGA6P
3.3 kW
18.15 kW
18.15 kW
3.3 kW
220 kW
PGA5N
From
MUX5N
BIAS5N
From
MUX7P
BIAS7P
18.15 kW
220 kW
PGA6N
From
MUX6N
BIAS6N
220 kW
PGA7P
18.15 kW
220 kW
From
MUX8P
BIAS8P
PGA8P
3.3 kW
18.15 kW
18.15 kW
3.3 kW
220 kW
PGA7N
From
MUX7N
BIAS7N
PGA8N
BIASINV
(1)
CEXT
1.5 nF
18.15 kW
220 kW
From
MUX8N
BIAS8N
(1)
REXT
1 MW
BIASOUT
BIAS
Amp
(AVDD + AVSS) / 2
BIASREF_INT = 1
BIASREF
BIASREF_INT = 0
(1) Typical values.
Figure 52. Bias Channel Selection
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QUICK-START GUIDE
PCB LAYOUT
Power Supplies and Grounding
The ADS1299 has three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as
possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, AVDD1
and AVSS1 are recommended to be star-connected to AVDD and AVSS. It is important to eliminate noise from
AVDD and AVDD1 that is non-synchronous with the ADS1299 operation. Each ADS1299 supply should be
bypassed with 10-μF and a 0.1-μF solid ceramic capacitors. Placement of the digital circuits [(such as digital
signal processors (DSPs), microcontrollers, and field-programmable gate arrays (FPGAs)] in the system is
recommenced to done such that the return currents on those devices do not cross the analog return path of the
ADS1299. The ADS1299 can be powered from unipolar or bipolar supplies.
The capacitors used for decoupling can be surface-mount, low-cost, low-profile multi-layer ceramic capacitors. In
most cases, the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected
to high- or low-frequency vibration, it is recommend that a non-ferroelectric capacitor such as a tantalum or class
1 capacitor (for example, C0G or NPO) be installed. EIA class 2 and class 3 dielectrics (such as X7R, X5R, and
X8R) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming from
the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation.
Connecting the Device to Unipolar (+5 V and +3.3 V) Supplies
Figure 53 illustrates the ADS1299 connected to a unipolar supply. In this example, analog supply (AVDD) is
referenced to analog ground (AVSS) and digital supply (DVDD) is referenced to digital ground (DGND).
+3.3 V
+5 V
0.1 mF
1 mF
1 mF
0.1 mF
AVDD AVDD1
DVDD
VREFP
VREFN
0.1 mF
10 mF
VCAP1
RESV1
Device
VCAP2
VCAP3
VCAP4
AVSS1 AVSS
DGND
1 mF
1 mF
0.1 mF
1 mF
100 mF
NOTE: Place the capacitors for supply, reference, and VCAP1 to VCAP4 as close to the package as possible.
Figure 53. Single-Supply Operation
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Connecting the Device to Bipolar (±2.5 V and 3.3 V) Supplies
Figure 54 illustrates the ADS1299 connected to a bipolar supply. In this example, the analog supplies connect to
the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital
supply (DVDD) is referenced to the device digital ground return (DGND).
+2.5 V
+3.3 V
1 mF
0.1 mF
0.1 mF
1 mF
AVDD AVDD1 DVDD
VREFP
VREFN
0.1 mF
10 mF
-2.5 V
VCAP1
Device
VCAP2
RESV1
VCAP3
VCAP4
AVSS1 AVSS
DGND
1 mF
1 mF
1 mF
0.1 mF
1 mF
100 mF
0.1 mF
-2.5 V
NOTE: Place the capacitors for supply, reference, and VCAP1 to VCAP4 as close to the package as possible.
Figure 54. Bipolar Supply Operation
Shielding Analog Signal Paths
As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS.
These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should
be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding.
Leakage currents between the PCB traces can exceed the input bias current of the ADS1299 if shielding is not
implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB.
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POWER-UP SEQUENCING
Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals
should remain low until the power supplies have stabilized, as shown in Figure 55. At this time, begin supplying
the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse. After releasing RESET,
the configuration register must be programmed; see the CONFIG1: Configuration Register 1 subsection of the
Register Map section for details. The power-up sequence timing is shown in Table 12.
tPOR
Power Supplies
tRST
RESET
18 tCLK
Start Using the Device
Figure 55. Power-Up Timing Diagram
Table 12. Power-Up Sequence Timing
SYMBOL
DESCRIPTION
MIN
tPOR
Wait after power-up until reset
216
TYP
MAX
UNIT
tCLK
tRST
Reset low width
2
tCLK
SETTING THE DEVICE FOR BASIC DATA CAPTURE
This section outlines the procedure to configure the device in a basic state and capture data. This procedure is
intended to put the device in a data sheet condition to check if the device is working properly in the user system.
This procedure is recommended to be followed initially to get familiar with the device settings. When this
procedure is verified, the device can be configured as needed. For details on the timings for commands, refer to
the appropriate sections in the data sheet. Also, some sample programming codes are added for the EEGspecific functions.
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Analog and Digital Power-Up
Set CLKSEL Pin = 0
and Provide External Clock
fCLK = 2.048 MHz
Yes
// Follow Power-Up Sequencing
External
Clock
No
Set CLKSEL Pin = 1
and Wait for Oscillator
to Wake Up
Set PDWN = 1
Set RESET = 1
Wait for 1 s for
Power-On Reset
Issue Reset Pulse,
Wait for 18 tCLKs
Set PDB_REFBUF = 1
and Wait for Internal Reference
to Settle
// If START is Tied High, After This Step
// DRDY Toggles at fCLK / 8192
// Delay for Power-On Reset and Oscillator Start-Up
// Activate DUT
// CS can be Either Tied Permanently Low
// Or Selectively Pulled Low Before Sending
// Commands or Reading or Sending Data from or to the Device
Send SDATAC
Command
// Device Wakes Up in RDATAC Mode, so Send
// SDATAC Command so Registers can be Written
SDATAC
External
Reference
// If Using Internal Reference, Send This Command
¾WREG CONFIG3 E0h
No
Yes
Write Certain Registers,
Including Input Short
// Set Device for DR = fMOD / 4096
WREG CONFIG1 96h
WREG CONFIG2 C0h
// Set All Channels to Input Short
WREG CHnSET 01h
Set START = 1
// Activate Conversion
// After This Point DRDY Should Toggle at
// fCLK / 8192
RDATAC
// Put the Device Back in RDATAC Mode
RDATAC
Capture Data
and Check Noise
// Look for DRDY and Issue 24 + n ´ 24 SCLKs
Set Test Signals
// Activate a (1 mV ´ VREF / 2.4) Square-Wave Test Signal
// On All Channels
SDATAC
WREG CONFIG2 D0h
WREG CHnSET 05h
RDATAC
Capture Data
and Test Signal
// Look for DRDY and Issue 24 + n ´ 24 SCLKs
Figure 56. Initial Flow at Power-Up
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Lead-Off
Sample code to set dc lead-off with pull-up and pull-down resistors on all channels.
WREG LOFF 00h // Comparator threshold at 95% and 5%, pull-up or pull-down current source // DC lead-off
WREG CONFIG4 02h // Turn-on dc lead-off comparators
WREG LOFF_SENSP FFh // Turn on the P-side of all channels for lead-off sensing
WREG LOFF_SENSN FFh // Turn on the N-side of all channels for lead-off sensing
Observe the status bits of the output data stream to monitor lead-off status.
Bias Drive
Sample code to choose bias as an average of the first three channels.
WREG BIAS_SENSP 07h // Select channel 1—3 P-side for bias sensing
WREG BIAS_SENSN 07h // Select channel 1—3 N-side for bias sensing
WREG CONFIG3 b’x11x 1100 // Turn on bias amplifier, set internal BIASREF voltage
Sample code to route the BIASOUT signal through channel 4 N-side and measure bias with channel 5. Make
sure the external side to the chip BIASOUT is connected to BIASIN.
WREG CONFIG3 b’x111 1100 // Turn on bias amplifier, set internal BIASREF voltage, set bias measurement bit
WREG CH4SET b’xxxx 0111 // Route BIASIN to channel 4 N-side
WREG CH5SET b’xxxx 0010 // Route BIASIN to be measured at channel 5 w.r.t BIASREF
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Product Folder Link(s): ADS1299
59
ADS1299
SBAS499A – JULY 2012 – REVISED AUGUST 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2012) to Revision A
•
60
Page
Changed product column of Family and Ordering Information table .................................................................................... 2
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Product Folder Link(s): ADS1299
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
ADS1299IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
ADS1299IPAGR
ACTIVE
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS1299IPAGR
Package Package Pins
Type Drawing
TQFP
PAG
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1500
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1299IPAGR
TQFP
PAG
64
1500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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