Intersil EL7583IR 3-channel dc/dc converter Datasheet

EL7583
®
Data Sheet
May 12, 2006
3-Channel DC/DC Converter
Features
The EL7583 is a 3-channel DC/DC converter IC which is
designed primarily for use in TFT-LCD applications. It
features a PWM boost converter with 2.7V to 14V input
capability and 5V to 17V output, which powers the column
drivers and provides up to 470mA @ 12V, 370mA @ 15V
from 5V supply. A pair of charge pump control circuits
provide regulated outputs of VON and VOFF supplies at 8V
to 40V and -5V to -40V, respectively, each at up to 60mA.
• TFT-LCD display supply
- Boost regulator
- VON charge pump
- VOFF charge pump
The EL7583 features adjustable switching frequency,
adjustable soft start, and a separate output VON enable
control to allow selection of supply start-up sequence. An
over-temperature feature is provided to allow the IC to be
automatically protected from excessive power dissipation.
FN7335.5
• 2.7V to 14V VIN supply
• 5V < VBOOST < 17V
• 5V < VON < 40V
• -40V < VOFF < 0V
• VBOOST = 12V @ 470mA
• VBOOST = 15V @ 370mA
• High frequency, small inductor DC/DC boost circuit
The EL7583 is available in a standard 20 Ld TSSOP
package and the Pb-free 20 Ld HTSSOP package. Both are
specified for operation over the full -40°C to +85°C
temperature range.
Ordering Information
PART
NUMBER
• Over 90% efficient DC/DC boost converter capability
• Adjustable frequency
• Adjustable soft-start
• Adjustable outputs
PART
TAPE &
MARKING REEL
PACKAGE
PKG.
DWG. #
• Small parts count
• Pb-free plus anneal available (RoHS compliant)
EL7583IR
7583IR
-
20 Ld TSSOP
MDP0044
EL7583IR-T7
7583IR
7”
20 Ld TSSOP
MDP0044
Applications
EL7583IR-T13
7583IR
13”
20 Ld TSSOP
MDP0044
• TFT-LCD panels
EL7583IREZ
(See Note)
7583IREZ
-
20 Ld HTSSOP MDP0048
(Pb-free)
EL7583IREZ-T7
(See Note)
7583IREZ
7”
20 Ld HTSSOP MDP0048
(Pb-free)
EL7583IREZ-T13 7583IREZ
(See Note)
13”
20 Ld HTSSOP MDP0048
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• PDAs
Pinout
EL7583
(20 LD TSSOP/HTSSOP)
TOP VIEW
VSSB 1
SS 2
20 ROSC
19 ENP
FBB 3
18 ENBN
VDDB 4
17 VREF
LX 5
16 PGND
LX 6
15 PGND
LX 7
14 DRVP
DRVN 8
13 VDDP
VDDN 9
12 FBP
FBN 10
11 VSSP
REFER TO PCB LAYOUT GUIDELINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7583
Absolute Maximum Ratings (TA = 25°C)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
VIN Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V
VDDB, VDDP, VDDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . . 0.5A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
VIN = 3.3V, VBOOST = 12V, ROSC = 100kΩ, TA = 25°C Unless Otherwise Specified
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
DC/DC BOOST CONVERTER
IQ1_B
Quiescent Current - Shut-down
ENBN = ENP = 0V
0.8
10
µA
IQ2_B
Quiescent Current - Switching
ENBN = VDDB
4.8
8
mA
V(FBB)
Feedback Voltage
1.275
1.300
1.325
V
VREF
Reference Voltage
1.260
1.310
1.360
V
VROSC
Oscillator Set Voltage
1.260
1.325
1.390
V
I(FBB)
Feedback Input Bias Current
VDDB
Boost Converter Supply Range
2.7
DMAX
Maximum Duty Cycle
85
I(LX)MAX
Peak Internal FET Current
RDS-ON
Switch On Resistance
at VBOOST = 10V, I(LX) total = 350mA
ILEAK-SWITCH
Switch Leakage Current
I(LX) total
VBOOST
Output Range
VBOOST > VIN + VDIODE
∆VBOOST/∆VIN
Line Regulation
2.7V < VIN < 13.2V, VBOOST = 15V
0.1
%
∆VBOOST/∆IO1
Load Regulation
50mA < IO1 < 250mA
0.5
%
FOSC-RANGE
Frequency Range
ROSC range = 240kΩ to 60kΩ
200
FOSC1
Switching Frequency
ROSC = 100kΩ
620
0.1
µA
17
V
92
%
1.75
A
0.22
Ω
5
680
1
µA
17
V
1000
kHz
750
kHz
POSITIVE REGULATED CHARGE PUMP (VON)
Most positive VON output depends on the magnitude of the VDDP input voltage (normally connected to VBOOST) and the external component
configuration (doubler or tripler)
VDDP
Supply Input for Positive Charge Pump
Usually connected to VBOOST output
IQ1(VDDP)
Quiescent Current - Shut-down
ENP = 0V
IQ2(VDDP)
Quiescent Current - Switching
ENBN = ENP = VDDB
V(FBP)
Feedback Reference Voltage
I(FBP)
Feedback Input Bias Current
I(DRVP)
RMS DRVP Output Current
1.245
VDDP = 12V
VDDP = 6V
ILR_VON
Load Regulation
5mA < IL < 15mA
FPUMP
Charge Pump Frequency
Frequency set by ROSC - see boost section
2
5
17
V
11.5
20
µA
2.3
5
mA
1.310
1.375
V
0.1
µA
60
mA
15
-0.5
mA
0.03
0.5
%/mA
0.5*FOSC
FN7335.5
May 12, 2006
EL7583
VIN = 3.3V, VBOOST = 12V, ROSC = 100kΩ, TA = 25°C Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
NEGATIVE REGULATED CHARGE PUMP (VOFF)
Most negative VOFF output depends on the magnitude of the VDDN input voltage (normally connected to VBOOST) and the external component
configuration (doubler or tripler)
VDDN
Supply Input for Negative Charge Pump
Usually connected to VBOOST output
IQ1(VDDN)
Quiescent Current - Shut-down
ENBN = 0V
IQ2(VDDN)
Quiescent Current - Switching
ENBN = VDDB
V(FBN)
Feedback Reference Voltage
I(FBN)
Feedback Input Bias Current
Magnitude of input bias
0.1
µA
I(DRVN)
RMS DRVN Output Current
VDDN = 12V
60
mA
5
-80
VDDN = 6V
ILR_VOFF
Load Regulation
-15mA < IL < -5mA
FPUMP
Charge Pump Frequency
Frequency set by ROSC - see boost section
17
V
1.2
10
µA
2.3
5
mA
0
+80
mV
15
-0.5
mA
0.03
0.5
%/mA
0.5*FOSC
ENABLE CONTROL LOGIC
VHI-ENX
Enable Input High Threshold
x = “BN”, “P”
VLO-ENX
Enable Input Low Threshold
x = “BN”, “P”
IL(EN”X”)
Logic Low Bias Current
X = “BN”, “P” = 0V
0.1
IL(ENBN)
Logic High Bias Current
ENBN = 5V
7.5
15
µA
IL(ENP)
Logic High Bias Current
ENP = 5V
3.3
7.5
µA
1.6
V
0.8
V
µA
OVER-TEMPERATURE PROTECTION
TOT
Over-temperature Threshold
130
°C
THYS
Over-temperature Hysteresis
40
°C
3
FN7335.5
May 12, 2006
EL7583
Pin Descriptions
I = Input, O = Output, S = Supply
PIN NUMBER
PIN NAME
PIN TYPE
1
VSSB
S
Ground for DC/DC boost and reference circuits; chip substrate
2
SS
I
Soft-start input; the capacitor connected to this pin sets the current limited start time
3
FBB
I
Voltage feedback input for boost circuit; determines boost output voltage, VBOOST
4
VDDB
S
Positive supply input for DC/DC boost circuits
5
LX
O
Boost regulator inductor drive connected to drain of internal NFET
6
LX
O
Boost regulator inductor drive connected to drain of internal NFET
7
LX
O
Boost regulator inductor drive connected to drain of internal NFET
8
DRVN
O
Driver output for the external generation of negative charge pump voltage, VOFF
9
VDDN
S
Positive supply for input for VOFF generator
10
FBN
I
Voltage feedback input to determine negative charge pump output, VOFF
11
VSSP
S
Negative supply pin for both the positive and negative charge pumps
12
FBP
I
Voltage feedback to determine positive charge pump output, VON
13
VDDP
S
Positive supply input for VON generator
14
DRVP
O
Voltage driver output for the external generation of positive charge pump, VON
15
PGND
O
Power ground, connected to source of internal NFET
16
PGND
O
Power ground, connected to source of internal NFET
17
VREF
I
Voltage reference for charge pump circuits; decouple to ground
18
ENBN
I
Enable pin for boost (VBOOST generation) and negative charge pump (VOFF generation);
active high
19
ENP
I
Enable for DRVP (VON generation); active high
20
ROSC
I
Connected to an external resistor to ground; sets the switching frequency of the DC/DC
boost
4
PIN FUNCTION
FN7335.5
May 12, 2006
EL7583
Typical Performance Curves
95
95
90
15V
EFFICIENCY (%)
EFFICIENCY (%)
12V
9V
80
9V
90
5V
85
12V
75
70
65
85
15V
80
75
70
60
65
VIN=3.3V
FREQ=1MHz
55
VIN=5V
FREQ=1MHz
60
50
0
100
200
300
400
500
600
700
800
0
100
200
300
FIGURE 1. EFFICIENCY vs IOUT
600
700
800
FIGURE 2. EFFICIENCY vs IOUT
95
95
90
90
5V
85
9V
12V
15V
80
EFFICIENCY (%)
EFFICIENCY (%)
500
IOUT (mA)
IOUT (mA)
75
70
65
12V
15V
85
9V
80
75
70
65
VIN=3.3V
FREQ=700kHz
60
VIN=5V
FREQ=700kHz
60
0
100
200
300
400
500
600
700
800
0
100
200
IOUT (mA)
300
400
500
600
700
800
IOUT (mA)
FIGURE 3. EFFICIENCY vs IOUT
FIGURE 4. EFFICIENCY vs IOUT
1.27
970
ROSC = 61.9kΩ
969
1.265
968
VOLTAGE (V)
FREQUENCY (kHz)
400
967
966
965
1.26
1.255
964
963
962
3
3.5
4
4.5
5
VDDB (V)
FIGURE 5. FS vs VDDB
5
5.5
6
1.25
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 6. VREF vs TEMPERATURE
FN7335.5
May 12, 2006
EL7583
Typical Performance Curves (Continued)
f=675kHz, VIN=3.3V
1.5
1.0
1.0
LOAD REGULATION (%)
LOAD REGULATION (%)
f=675kHz, VIN=5.0V
1.5
0.5
0.0
-0.5
0.5
0.0
-0.5
15V
-1.0
-1.0
18V
15V
-1.5
0
100
200
300
12V
9V
0
700
600
100
200
300
600
700
800
f=1MHz, VIN=3.3V
f=1MHz, VIN=5.0V
1.5
1.0
1.0
LOAD REGULATION (%)
LOAD REGULATION (%)
500
FIGURE 8. LOAD REGULATION vs IOUT
FIGURE 7. LOAD REGULATION vs IOUT
0.5
0.0
-0.5
-1.0
18V
9V
12V
0.5
0.0
-0.5
15V 12V
-1.0
9V
18V
15V
-1.5
5V
-1.5
0
100
200
300
500
400
600
700
0
100
200
300
400
500
600
700
800
IOUT (mA)
IOUT (mA)
FIGURE 9. LOAD REGULATION vs IOUT
FIGURE 10. LOAD REGULATION vs IOUT
6.5
20
19
VDDN = 15V
6
VDDP = 15V
VDDN = 12V
5.5
18
VDDP = 12V
VOFF (-V)
VON (V)
400
IOUT (mA)
IOUT (mA)
1.5
5V
-1.5
500
400
12V
18V
9V
17
16
5
4.5
4
15
3.5
14
0
10
20
30
40
50
ILOAD (mA)
FIGURE 11. VON vs ION
6
60
70
80
0
10
20
30
40
50
60
70
80
ILOAD (mA)
FIGURE 12. VOFF vs IOFF
FN7335.5
May 12, 2006
EL7583
Typical Performance Curves (Continued)
SWITCHING PERIOD(µs)=0.0118 ROSC+0.378)
6
1200
5
SWITCHING PERIOD (µs)
FREQUENCY (kHz)
f(MHz)=1/(0.0118 ROSC+0.378)
1400
1000
800
600
400
200
4
3
2
1
0
0
0
50
100
150
200
250
300
350
400
450
0
50
100
150
200
250
300
100K & 0.1µF DELAY NETWORK ON ENP, CSS=0.1µF
100K & 0.1µF DELAY NETWORK ON ENP, CSS=0.1µF
VBOOST
5V/DIV
VBOOST
5V/DIV
10V/DIV
VON
VON
VOFF
200ms/DIV
FIGURE 15. POWER-DOWN
VIN=3.3V, VOUT=11.3V, IOUT=50mA
FIGURE 17. LX WAVEFORM - DISCONTINUOUS MODE
7
450
FIGURE 14. FS vs ROSC
FIGURE 13. FS vs ROSC
2V/DIV
400
ROSC (kΩ)
ROSC (kΩ)
10V/DIV
350
2V/DIV
VOFF
1ms/DIV
FIGURE 16. POWER-UP
VIN=3.3V, VOUT=11.3V, IOUT=250mA
FIGURE 18. LX WAVEFORM - CONTINUOUS MODE
FN7335.5
May 12, 2006
EL7583
Typical Performance Curves (Continued)
1
3
HTSSOP20
2.5
θJA=35°C/W
2
1.5
1 1.111W
TSSOP20
0.5
0
25
50
800mW
0.8
HTSSOP20
0.7 714mW
0.6
θJA = 125°C/W
0.5
TSSOP20
0.4
θJA=140°C/W
0.3
0.2
0.1
θJA=90°C/W
0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.9
2.857W
POWER DISSIPATION (W)
POWER DISSIPATION (W)
3.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
HTSSOP EXPOSED DIEPAD SOLDERED TO PCB
PER JESD51-5
75 85
125
100
0
150
0
25
AMBIENT TEMPERATURE (°C)
75 85
50
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Functional Block Diagram
VOUT
10µH
R2
R1
13kΩ
VIN
110kΩ
49Ω
10µF
10µF
0.1µF
FBB
VDDB
LX
MAX_DUTY
ROSC
R3
62kΩ
REFERENCE
GENERATOR
VREF
VRAMP
PWM
LOGIC
PWM
COMPARATOR
0.22Ω
ENBN
12µA
+
START-UP
OSCILLATOR
ILOUT
VSSB
7.2K
160mΩ
SS
PGND
0.1µF
8
FN7335.5
May 12, 2006
EL7583
Applications Information
Steady-State Operation
The EL7583 is high efficiency multiple output power solution
designed specifically for thin-film transistor (TFT) liquid
crystal display (LCD) applications. The device contains one
high current boost converter and two low power charge
pumps (VON and VOFF).
When the output reaches the preset voltage, the regulator
operates at steady state. Depending on the input/output
condition and component, the inductor operates at either
continuous-conduction mode or discontinuous-conduction
mode.
The boost converter contains an integrated N-channel
MOSFET to minimize the number of external components.
The converter output voltage can be set from 5V to 18V with
external resistors. The VON and VOFF charge pumps are
independently regulated to positive and negative voltages
using external resistors. Output voltages as high as 40V can
be achieved with additional capacitors and diodes.
In the continuous-conduction mode, the inductor current is a
triangular waveform and LX voltage a pulse waveform. In the
discontinuous-conduction mode, the inductor current is
completely ‘dried-out’ before the MOSFET is turned on
again. The input voltage source, the inductor, and the
MOSFET and output diode parasitic capacitors forms a
resonant circuit. Oscillation will occur in this period. This
oscillation is normal and will not affect the regulation.
Boost Converter
The boost converter operates in constant frequency pulsewidth-modulation (PWM) mode. Quiescent current for the
EL7583 is only 5mA when enabled, and since only the low
side MOSFET is used, switch drive current is minimized.
90% efficiency is achieved in most common application
operating conditions.
A functional block diagram with typical circuit configuration is
shown on previous page. Regulation is performed by the
PWM comparator which regulates the output voltage by
comparing a divided output voltage with an internal
reference voltage. The PWM comparator outputs its result to
the PWM logic. The PWM logic switches the MOSFET on
and off through the gate drive circuit. Its switching frequency
is external adjustable with a resistor from timing control pin
(ROSC) to ground. The boost converter has 200kHz to
1.2MHz operating frequency range.
At very low load, the MOSFET will skip pulse sometimes.
This is normal.
Current Limit
The MOSFET current limit is nominal ILMT = 1.75. This
restricts the maximum output current IOMAX based on the
following formula:
V IN
I OMAX = ⎛ I LMT – ∆L
-------⎞ × --------⎝
⎠
VO
2
where:
• ∆IL is the inductor peak-to-peak current ripple and is
decided by:
V IN D
∆I L = --------- × ------L
FS
Start-Up
• D is the MOSFET turn-on radio and is decided by:
After VDDB reaches a threshold of about 2V, the power
MOSFET is controlled by the start-up oscillator, which
generates fixed duty-ratio of 0.5 - 0.7 at a frequency of
several hundred kilohertz. This will boost the output voltage,
providing the initial output current load is not too great
(<250mA).
V O - V IN
D = ----------------------VO
• FS is the switching frequency.
When VDDB reaches about 3.7V, the PWM comparator
takes over the control. The duty ratio will be decided by the
multiple-input direct summing comparator, Max_Duty signal
(about 90% duty-ratio), and the Current Limit Comparator,
whichever is the smallest.
The soft-start is provided by the current limit comparator. As
the internal 12µA current source charges the external softstart capacitor, the peak MOSFET current is limited by the
voltage on the capacitor. This in turn controls the rising rate
of output voltage.
The regulator goes through the start-up sequence as well
after the ENBN signal is pulled to HI.
9
FN7335.5
May 12, 2006
EL7583
The following table gives typical values:
(Margins are considered 10%, 3%, 20%, 10%, and 15% on
VIN, VO, L, FS, and ILMT, respectively)
TABLE 1. MAXIMUM CONTINUOUS OUTPUT CURRENT
VIN (V)
VO (V)
L (µH)
FS (kHz)
IOMAX (mA)
3.3
9
10
1000
430
3.3
12
10
1000
320
3.3
15
10
1000
250
5
9
10
1000
650
5
12
10
1000
470
5
15
10
1000
370
12
18
10
1000
830
A 1nF compensation capacitor across the feedback resistor
to ground is recommended to keep the converter in stable
operation at low output current and high frequency
conditions.
Schottky Diode
Speed, forward voltage drop, and reverse current are the
three most critical specifications for selecting the Schottky
diode. The entire output current flows through the diode, so
the diode average current is the same as the average load
current and the peak current is the same as the inductor
peak current. When selecting the diode, one must consider
the forward voltage drop at the peak diode current. On the
Elantec demo board, MBRM120 is selected. Its forward
voltage drop is 450mV at 1A forward current.
Output Capacitor
Component Considerations
Input Capacitor
It is recommended that CIN is larger than 10µF.
Theoretically, the input capacitor has ripple current of ∆IL.
Due to high-frequency noise in the circuit, the input current
ripple may exceed the theoretical value. Larger capacitor will
reduce the ripple further.
Boost Inductor
The inductor has peak and average current decided by:
∆I
I LPK = I LAVG + --------L
2
The EL7583 is specially compensated to be stable with
capacitors which have a worst-case minimum value of 10µF
at the particular VOUT being set. Output ripple voltage
requirements also determine the minimum value and the
type of capacitors. Output ripple voltage consists of two
components - the voltage drop caused by the switching
current though the ESR of the output capacitor and the
charging and discharging of the output capacitor:
I OUT
V OUT - V IN
V RIPPLE = I LPK × ESR + ------------------------------- × -----------------------------C
× FS
V
OUT
OUT
For low ESR ceramic capacitors, the output ripple is
dominated by the charging/discharging of the output
capacitor.
IO
I LAVG = ------------1-D
The inductor should be chosen to be able to handle this
current. Furthermore, due to the fixed internal
compensation, it is recommended that maximum inductance
of 10µH and 15µH to be used in the 5V and 12V or higher
output voltage, respectively.
The output diode has average current of IO, and peak current
the same as the inductor's peak current. Schottky diode is
recommended and it should be able to handle those currents.
Feedback Resistor Network
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 200kΩ is
recommended. The boost converter output voltage is
determined by the following relationship:
R1 + R2
V BOOST = --------------------- × V FBB
R1
In addition to the voltage rating, the output capacitor should
also be able to handle the RMS current is given by:
I CORMS =
2
⎛
⎞
∆I L
1
( 1 - D ) × ⎜ D + ------------------- × ------ ⎟ × I LAVG
⎜
2 12 ⎟
I LAVG
⎝
⎠
Positive and Negative Charge Pump (VON and
VOFF)
The EL7583 contains two independent charge pumps (see
charge pump block and connection diagram.) The negative
charge pump inverts the VDDN supply voltage and provides
a regulated negative output voltage. The positive charge
pump doubles the VDDP supply voltage and provides a
regulated positive output voltage. The regulation of both the
negative and positive charge pumps is generated by the
internal comparator that senses the output voltage and
compares it with and internal reference. The switching
frequency of the charge pump is set to ½ the boost converter
switching frequency.
The pumps use pulse width modulation to adjust the pump
period, depending on the load present. The pumps are shortcircuit protected to 180mA at 12V supply and can provide
15mA to 60mA for 6V to 12V supply.
where VFBB is 1.300V.
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EL7583
Single Stage Charge Pump
VDDN
5V TO
17V
VDDP
5V TO
17V
0.1µF
0.1µF
CCPP
RONP
RONP
DRVN
OSC
DRVP
CCPN
VOFF
RONN
COUT2
RONN
3.3µF
R21
FBN
V
COUT1ON
VSSP
VSSN
2.2µF
FBP
+
+
-
R12
+
-
VFBP
R11
RON IS 30 - 40Ω FOR VDD 6V TO 12V
R22
VREF
Positive Charge Pump Design Considerations
A single stage charge pump is shown above. The maximum
VON output voltage is determined by the following equation:
1
1
V ON ( max ) ≤ 2 × V DDCPP - I OUT × 2 × ( R ONN + R ONP ) - 2 × V DIODE - I OUT × -------------------------------------------- - I OUT × -----------------------------------------------0.5 × F × C
0.5 × F × C
S
CPP
S
OUT1
where:
• RONN and RONP resistance values depend on the VDDP
voltage levels. For 12V supply, RON is typically 33Ω. For
6V supply, RON is typically 45Ω.
If additional stage is required, the LX switching signal is
recommended to drive the additional charge pump diodes.
The drive impedance at the LX switching is typically 220mΩ.
The figure below illustrates an implementation for two-stage
positive charge pump circuit.
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EL7583
Two-Stage Positive Charge Pump Circuit
VDDP
VBOOST
(5V-17V)
VLX
RONP
CCPP
DRNP
VON
CCPP
RONN
COUT1
COUT1
VSSP
R12
+
FBP
1.265V
+
-
R11
The maximum VON output voltage for N+1 stage charge pump is:
1
V ON ( max ) ≤ 2 × V DDP - I OUT × 2 × ( R ONN + R ONP ) - 2 × V DIODE - I OUT × -------------------------------------------- - I OUT ×
0.5 × F × C
S
CPP
1
1
1
------------------------------------------------ + N × V LX ( max ) - N × ⎛ 2 × V DIODE + I OUT × -------------------------------------------- + I OUT × ------------------------------------------------ ⎞
⎝
0.5 × F S × C OUT1
0.5 × F S × C CPP
0.5 × F S × C OUT1 ⎠
R11 and R12 set the VON output voltage:
R 11 + R 12
V ON = V FBP × --------------------------R
11
where VFBP is 1.310V.
Negative Charge Pump Design Considerations
The criteria for the negative charge pump is similar to the
positive charge pump. For a single stage charge pump, the
maximum VOFF output voltage is:
1
1
V OFF ( max ) ≥ I OUT × 2 × ( R ONN + R ONP ) + 2 × V DIODE - IOUT × -------------------------------------------- - I OUT × ------------------------------------------------ - V DDN
0.5 × F × C
0.5 × F × C
S
CPN
S
OUT2
Similar to positive charge pump, if additional stage is
required, the LX switching signal is recommended to drive
the additional charge pump diodes. The figure on the next
page shows a two stage negative charge pump circuit.
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EL7583
Two-Stage Negative Charge Pump Circuit
VDDN
5V-17V
VLX
RONP
CCPN
DRVN
RONN
VOFF
CCPN
COUT2
COUT2
VSSN
+
-
R21
FBN
R22
VREF
The maximum VOFF output voltage for N+1 stage charge pump is:
1
1
V OFF ( max ) ≥ I OUT × 2 × ( R ONN + R ONP ) + 2 × V DIODE - I OUT × -------------------------------------------- - I OUT × ------------------------------------------------ 0.5 × F × C
0.5 × F × C
S
CPN
1
1
V DDN - N × V LX ( max ) + N × ⎛ 2 × V DIODE + I OUT × -------------------------------------------- + I OUT × ------------------------------------------------ ⎞
⎝
⎠
0.5 × F × C
0.5 × F × C
S
CPN
S
S
OUT2
OUT2
R21 and R22 determine VOFF output voltage:
R 21
V OFF = -V REF × ---------R 22
where VREF is 1.310V.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
130°C and 90°C respectively.
PCB Layout Guidelines
Careful layout is critical in the successful operation of the
application. The following layout guidelines are
recommended to achieve optimum performance.
shielding trace or layer. This is to prevent undesirable
switching interactions coupling into the feedback inputs.
• Place the charge pump feedback resistor network after the
diode and output capacitor node to avoid switching noise.
• All low-side feedback resistors should be connected
directly to VSSB. VSSB should be connected to the power
ground close at one point only.
A demo board is available to illustrate the proper layout
implementation.
• VREF and VDDB bypass capacitors should be placed next
to the pins.
• Place the boost converter diode and inductor close to the
LX pins.
• Place the boost converter output capacitor close to the
PGND pins.
• Locate feedback dividers close to their respected
feedback pins to avoid switching noise coupling into the
high impedance node.
• Switching output PCB traces should not cross, or be laid
out adjacent to, feedback traces without using a grounded
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EL7583
Typical Application Circuit
R2
R3
110K
C7
C10
1 VSSB
ROSC 20
61.9K
ENP 19
2 SS
0.1µF
OPEN
R1
13K
C6
0.1µF
C5
10µF
+
C3
C4
4 VDDB
VREF 17
5 LX
PGND 16
6 LX
PGND 15
7 LX
DRVP 14
8 DRVN
VDDP 13
9 VDDN
FBP 12
L1
VIN
VOFF
(-6V@
15mA)
GND
C1
10µF
+
C2
4.7µF
10µH
C21
R21
154K
C27
0.1µF
C26
3.3µF
0.1µF
10 FBN
VSSP 11
R6
0
C8
C50
0.1µF
OPEN
1nF
C12
0.1µF
VON
(18V@18mA)
D11**
C22
0.1µF
497K
C9
D1*
22µF
OPEN
ENBN 18
R4
49.9
VBOOST
(12V@
500mA)
3 FBB
R5
C11
0.1µF
C16
C17
R12
0.1µF
2.2µF
51K
R11
3.9K
D21**
R22
33.2K
* MBRM120LT3
** BAT54S
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EL7583
TSSOP Package Outline Drawing
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EL7583
HTSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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