ON MMDF5N02Z Nâ channel power mosfet Datasheet

MMDF5N02Z
Power MOSFET
5 Amps, 20 Volts
N−Channel SO−8, Dual
EZFETs are an advanced series of Power MOSFETs which contain monolithic back−to−back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature low RDS(on) and true logic
level performance. They are capable of withstanding high energy in
the avalanche and commutation modes and the drain−to−source diode
has a very low reverse recovery time. EZFET devices are designed for
use in low voltage, high speed switching applications where power efficiency is important.
• Zener Protected Gates Provide Electrostatic Discharge Protection
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Mounting Information for SO−8 Package Provided
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5 AMPERES
20 VOLTS
RDS(on) = 40 mΩ
N−Channel
D
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
20
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
20
Vdc
Gate−to−Source Voltage − Continuous
VGS
± 12
Vdc
Drain Current − Continuous @ TA = 25°C
Drain Current − Continuous @ TA = 70°C
Drain Current − Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TA = 25°C (Note 1.)
ID
ID
IDM
5.0
4.5
40
Adc
Apk
PD
2.0
Watts
Operating and Storage Temperature Range
TJ, Tstg
− 55
to 150
°C
Thermal Resistance − Junction to Ambient
RθJA
62.5
°C/W
260
°C
Maximum Temperature for Soldering
TL
1. When mounted on 1 inch square FR−4 or G−10 board
(VGS = 4.5 V, @ 10 Seconds).
MARKING
DIAGRAM
SO−8, Dual
CASE 751
STYLE 11
8
5N02Z
LYWW
1
5N02Z
L
Y
WW
= Device Code
= Location Code
= Year
= Work Week
PIN ASSIGNMENT
Source−1
1
8
Drain−1
Gate−1
2
7
Drain−1
Source−2
3
6
Drain−2
Gate−2
4
5
Drain−2
Top View
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. XXX
1
Device
Package
MMDF5N02ZR2
SO−8
Shipping
2500 Tape & Reel
Publication Order Number:
MMDF5N02Z/D
MMDF5N02Z
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
20
−
−
15
−
−
−
−
−
−
−
−
0.5
15
150
−
−
1.5
0.5
−
0.78
3.0
1.1
−
−
−
34
44
40
50
gFS
3.0
5.6
−
Mhos
pF
OFF CHARACTERISTICS
(Cpk ≥ 2.0)
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Note 4.)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 12 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 12 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
µAdc
ON CHARACTERISTICS (Note 2.)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 2.0)
Static Drain−to−Source On−Resistance
(VGS = 4.5 Vdc, ID = 5.0 Adc)
(VGS = 2.7 Vdc, ID = 2.5 Adc)
(Cpk ≥ 2.0)
(Note 4.)
(Note 4.)
Forward Transconductance (VDS = 9.0 Vdc, ID = 2.0 Adc)
VGS(th)
Vdc
RDS(on)
mV/°C
mΩ
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 10 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Transfer Capacitance
Ciss
−
450
630
Coss
−
330
460
Crss
−
160
225
td(on)
−
29
37
SWITCHING CHARACTERISTICS (Note 3.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 6.0 Vdc, ID = 5.0 Adc,
VGS = 4.5 Vdc, RG = 6 Ω)
Fall Time
Gate Charge
(VDS = 10 Vdc, ID = 5.0 Adc,
VGS = 4.5 Vdc)
tr
−
182
258
td(off)
−
190
238
tf
−
225
274
QT
−
10.7
12
Q1
−
1.1
−
Q2
−
5.4
−
Q3
−
3.5
−
−
−
0.78
0.65
1.0
−
trr
−
195
−
ta
−
72
−
tb
−
123
−
QRR
−
0.5
−
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 5.0 Adc, VGS = 0 Vdc)
(IS = 5.0 Adc, VGS = 0 Vdc,
TJ = 125°C)
Reverse Recovery Time
(IS = 5.0
5 0 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs)
Reverse Recovery Storage Charge
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
4. Reflects typical values.
Max limit − Typ
Cpk =
3 x SIGMA
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2
VSD
Vdc
ns
µC
MMDF5N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 12 V
4.5 V
2.7 V
8
8
TJ = 25°C
VDS ≥ 10 V
TJ = 25°C
7
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
10
2.0 V
2.3 V
1.9 V
6
1.8 V
4
1.7 V
2
1.6 V
1.5 V
6
5
4
3
100°C
2
25°C
1
0
0.4
1.2
0.8
1.6
0
2
1.5
2
2.5
Figure 2. Transfer Characteristics
0.06
0.05
0.04
0.03
0.02
0.01
2
3
4
6
7
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
8
0.08
TJ = 25°C
0.07
0.06
0.05
VGS = 2.7 V
0.04
4.5 V
0.03
0.02
0.01
0
0
1
2
3
4
5
6
7
8
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10000
1.6
VGS = 0 V
VGS = 4.5 V
ID = 2.5 A
TJ = 125°C
1000
1.2
I DSS , LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
1
Figure 1. On−Region Characteristics
ID = 5 A
TJ = 25°C
1.4
0.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.07
0
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
TJ = −55°C
1
0.8
0.6
0.4
100°C
100
10
25°C
1
0.2
0
−50
−25
0
25
50
75
100
125
0.1
150
0
2.5
5
7.5
10
12.5
15
17.5
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation
with Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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20
MMDF5N02Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are
determined by how fast the FET input capacitance can be
charged by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data
is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure
is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be
safely operated into an inductive load; however, snubbing
reduces switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1400
VDS = 0 V
TJ = 25°C
VGS = 0 V
C, CAPACITANCE (pF)
1200
1000
Ciss
800
Crss
600
Ciss
400
Coss
200
Crss
0
−10
−5
5
0
10
15
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
6
VDS
5
5
QT
VGS
4
4
Q3
3
3
Q1
Q2
2
2
ID = 5 A
TJ = 25°C
1
0
0
2
4
6
8
10
1
1000
t, TIME (ns)
6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MMDF5N02Z
tf
td(off)
tr
100
td(on)
0
14
12
VDD = 6 V
ID = 5 A
VGS = 4.5 V
TJ = 25°C
10
1
10
RG, GATE RESISTANCE (OHMS)
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
5
di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the
high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter recovery time and lower switching losses.
VGS = 0 V
TJ = 25°C
4.5
I S , SOURCE CURRENT (AMPS)
4
3.5
3
2.5
2
1.5
1
0.5
0
0
0.1
0.2
0.4
0.3
0.5
0.6
0.7
0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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5
MMDF5N02Z
di/dt = 300 A/µs
I S , SOURCE CURRENT
Standard Cell Density
trr
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature
(TC ) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient
Thermal Resistance − General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM ) nor rated voltage (VDSS ) is exceeded, and that the
transition time (tr, tf ) does not exceed 10 µs. In addition
I D , DRAIN CURRENT (AMPS)
100
the total power averaged over a complete switching cycle
must not exceed (T J(MAX) − TC )/(RθJC ).
A power MOSFET designated E−FET can be safely
used in switching circuits with unclamped inductive
loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be
adjusted for operating conditions differing from those
specified. Although industry practice is to rate in terms
of energy, avalanche energy capability is not a constant.
The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction
temperature.
VGS = 12 V
SINGLE PULSE
TC = 25°C
1 ms
10
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
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100
MMDF5N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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1.0E+02
1.0E+03
MMDF5N02Z
INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection inter-
face between the board and the package. With the correct
pad geometry, the packages will self−align when subjected
to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO−8 POWER DISSIPATION
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 2.0 Watts.
The power dissipation of the SO−8 is a function of the input pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature
of the die, RθJA, the thermal resistance from the device
junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO−8
package, PD can be calculated as follows:
PD =
PD = 150°C − 25°C = 2.0 Watts
62.5°C/W
The 62.5°C/W for the SO−8 package assumes the recommended footprint on a glass epoxy printed circuit board to
achieve a power dissipation of 2.0 Watts using the footprint
shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad.
Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to
the device.
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MMDF5N02Z
TYPICAL SOLDER HEATING PROFILE
ture versus time. The line on the graph shows the actual
temperature that might be experienced on the surface of a
test board at or near a central solder joint. The two profiles
are based on a high density and a low density board. The
Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177 −189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend
to heat first. The components on the board are then heated
by conduction. The circuit board, because it has a large
surface area, absorbs the thermal energy more efficiently,
then distributes this energy to the components. Because of
this effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows temperaSTEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 15. Typical Solder Heating Profile
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MMDF5N02Z
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE W
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
K
−Y−
G
C
N
X 45 SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
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SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
MMDF5N02Z
Notes
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MMDF5N02Z
EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
Thermal Clad is a registered trademark of the Bergquist Company.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
Fax Response Line: 303−675−2167 or 800−344−3810 Toll Free USA/Canada
N. American Technical Support: 800−282−9855 Toll Free USA/Canada
CENTRAL/SOUTH AMERICA:
Spanish Phone: 303−308−7143 (Mon−Fri 8:00am to 5:00pm MST)
Email: ONlit−[email protected]
ASIA/PACIFIC: LDC for ON Semiconductor − Asia Support
Phone: 303−675−2121 (Tue−Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001−800−4422−3781
Email: ONlit−[email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4−32−1 Nishi−Gotanda, Shinagawa−ku, Tokyo, Japan 141−0031
Phone: 81−3−5740−2745
Email: [email protected]
EUROPE: LDC for ON Semiconductor − European Support
German Phone: (+1) 303−308−7140 (Mon−Fri 2:30pm to 7:00pm CET)
Email: ONlit−[email protected]
French Phone: (+1) 303−308−7141 (Mon−Fri 2:00pm to 7:00pm CET)
Email: ONlit−[email protected]
English Phone: (+1) 303−308−7142 (Mon−Fri 12:00pm to 5:00pm GMT)
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL−FREE ACCESS*: 00−800−4422−3781
*Available from Germany, France, Italy, UK
For additional information, please contact your local
Sales Representative.
http://onsemi.com
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