TECHNICAL DATA IW4040B 12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS N SUFFIX PLASTIC DIP The IW4040B is ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. • • • 16 1 Operating Voltage Range: 3.0 to 18 V Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply 16 1 ORDERING INFORMATION IW4040BN IW4040BD IZ4040B Plastic DIP SOIC chip TA = -55° to 125° C for all packages LOGIC DIAGRAM 9 Q1 PIN ASSIGNMENT 7 Q2 6 Q3 CLOCK 10 5 3 2 4 13 12 14 15 Q12 1 16 V CC Q6 2 15 Q11 Q4 Q5 3 14 Q10 Q5 Q7 4 13 Q8 Q4 5 12 Q9 Q6 Q3 6 11 RESET Q7 Q2 7 10 CLOCK Q8 GND 8 9 Q1 Q9 FUNCTION TABLE Q10 Inputs Q11 1 Q12 Clock Output Reset Output state L No change L Advance to next state H All Outputs are low 11 RESET X PIN 16 =VCC PIN 8 = GND INTEGRAL H= high level L = low level X=don’t care 1 IW4040B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V ±10 mA 500* 1 mW 100 mW -65 to +150 °C 260 °C VOUT IIN DC Input Current, per Pin PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Ptot Power Dissipation per Output Transistor Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 For TA=-55 to 100°C (package plastic DIP), for TA=-55 to 65°C (package SOIC) +Derating - Plastic DIP: - 12 mW/°C from 100°Ñ to 125°C SOIC Package: : - 7 mW/°C from 65°Ñ to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IW4040B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Guaranteed Limit Test Conditions -55°C 25°C 125° C Unit V VIH Minimum High-Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 3.5 7.0 11.0 3.5 7.0 11.0 3.5 7.0 11.0 V VIL Maximum Low -Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 1.5 3.0 4.0 1.5 3.0 4.0 1.5 3.0 4.0 V VOH Minimum High-Level Output Voltage VIN= GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN= GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High (Source) Current VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 IOH INTEGRAL mA mA 3 IW4040B AC ELECTRICAL CHARACTERISTICS (CL=50 pF, RL=200 kΩ, t r=t f=20 ns) Symbol Parameter VCC Guaranteed Limit Unit V -55°C 25°C 125°C Maximum Clock Frequency (Figure 1) 5.0 10 15 3.5 8 12 3.5 8 12 1.75 4.0 6.0 MHz tPLH, t PHL Maximum Propagation Delay, Clock to Q1 (Figure 1) 5.0 10 15 360 160 130 360 160 130 720 320 260 ns tPLH, t PHL Maximum Propagation Delay, Qn to Qn+1 (Figure 2) 5.0 10 15 330 80 60 330 80 60 660 160 120 ns Maximum Propagation Delay, Reset to Any Q (Figure 3) 5.0 10 15 280 120 100 280 120 100 560 240 200 ns Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns fmax tPHL tTLH, t THL CIN Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS (CL=50 pF, RL=200 kΩ, t r=t f=20 ns) Symbol Parameter VCC Guaranteed Limit V -55°C 25°C 125°C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 140 60 40 140 60 40 280 120 80 ns tw Minimum Pulse Width, Reset (Figure 3) 5.0 10 15 200 80 60 200 80 60 400 160 120 ns trem Minimum Removal Time, Reset(Figure 3) 5.0 10 15 350 150 100 350 150 100 700 300 200 ns tr, tf Maximum Input Rise and Fall Times, Clock (Figure 1) 5.0 10 15 Figure 1. Switching Waveforms INTEGRAL ns Unlimited Figure 2. Switching Waveforms 4 IW4040B VCC 50% GND CLOCK trem tw VCC 50% RESET GND t PHL VCC 50% ANY Q GND Figure 3. Switching Waveforms TIMING DIAGRAM 0 1 2 4 8 16 32 128 64 256 512 1024 2048 4096 Clock Reset Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 EXPANDED LOGIC DIAGRAM Q1 CL1 CL2 FF1 CLOCK RESET CL3 Q11 CL7 FF2 CL1 Q1 CL2 R Q1 R Q1 INTEGRAL Q2 Q12 FFI2 Q2 CL3 Q11 FF3-FF11 Q2 Q3 Q11 CL7 Q12 R Q12 5 IW4040B INTEGRAL 6 IW4040B CHIP PAD DIAGRAM Chip marking 4040 11 14 13 12 2.02 + 0.03 15 10 16 09 01 02 Y 08 03 (0,0) 04 05 06 07 2.28 + 0.03 X Location of marking (mm): left lower corner x=0.199, y=1.792. Chip thickness: 0.46 ± 0.02 (0.35 ± 0.02 ) mm. PAD LOCATION Pad No Symbol 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND Q1 INPUT RES Q9 Q8 Q10 Q11 VCC Location (left lower corner), mm X Y 0.1525 0.9025 0.1525 0.2315 0.4515 0.1525 0.8115 0.1525 1.1715 0.1525 1.5315 0.1525 2.0270 0.3365 2.0270 0.7995 2.0270 1.0135 2.0270 1.4760 1.8470 1.7675 1.2430 1.7675 0.9965 1.7675 0.4445 1.7675 0.1525 1.5980 0.1525 1.2140 Pad size, mm 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 Note: Pad location is given as per passivation layer INTEGRAL 7