Exar MP7543JN 5 v cmos serial input 12-bit digital-to-analog converter Datasheet

MP7543
5 V CMOS
Serial Input 12-Bit
Digital-to-Analog Converter
FEATURES
BENEFITS
•
•
•
•
•
•
•
•
•
•
•
• Compatible with Serial Addressing Systems
12-Bit DAC with Serial Digital Input Interface
Nonlinearity +1/2 LSB from Tmin to Tmax
Lowest Sensitivity to Amplifier VOS
Low Output Capacitance
Full 4-Quadrant Multiplication
Latch-Up Free
Asynchronous CLEAR Input
Serial Load On Positive or Negative Strobes
+5 V Supply Operation
3 V Version: MP75L43
4-Bit Parallel Version: MP7542
GENERAL DESCRIPTION
The MP7543 is a precision, 12-bit CMOS 4-quadrant multiplying Digital-to-Analog Converter designed for serial interface
applications.
under control of the Load inputs.
The MP7543 consists of two 12-bit registers, control logic and
a 12-bit multiplying D/A converter. The input register (register A)
is a 12-bit serial-in parallel-out shift register. Serial data at the
SR1 pin is clocked into Register A on the leading or trailing edge
(user selected) of the strobe input, with the MSB loaded first.
Register B is a 12-bit parallel-in parallel-out register that follows
register A. The contents of register A are loaded into register B
The MP7543 is manufactured using an advanced thin film
monolithic CMOS fabrication process. A unique decoding technique is utilized yielding excellent accuracy and stability. 12-bit
linearity is achieved without laser trimming.
A CLEAR input is provided for the asynchronous resetting of
register B to all 0’s.
The MP7543 reduces the additional linearity errors due to
output amplifier offset to only 330 µV per millivolt of offset - half
the value of a standard R-2R CMOS DAC design approach.
SIMPLIFIED BLOCK DIAGRAM
RFB
VREF
12-Bit D/A Converter
IOUT1
IOUT2
AGND
CLR
LD1
LD2
STB1
DAC Register B
Load
Register A
12-Bit Shift Register
SRI
STB4
VDD
DGND
STB3
STB2
Rev. 2.00
1
MP7543
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
INL
(LSB)
DNL
(LSB)
Gain Error
(LSB)
Plastic Dip
–40 to +85°C
MP7543JN
+1
+2
+14.5
Plastic Dip
–40 to +85°C
MP7543KN
+1/2
+1
+14.5
SOIC
–40 to +85°C
MP7543JS
+1
+2
+14.5
SOIC
–40 to +85°C
MP7543KS
+1/2
+1
+14.5
PLCC
–40 to +85°C
MP7543JP
+1
+2
+14.5
PLCC
–40 to +85°C
MP7543KP
+1/2
+1
+14.5
Ceramic Dip
–40 to +85°C
MP7543AD
+1
+2
+14.5
Ceramic Dip
–40 to +85°C
MP7543BD
+1/2
+1
+14.5
Ceramic Dip
–55 to +125°C
MP7543SD*
+1
+2
+14.5
Ceramic Dip
–55 to +125°C
MP7543TD*
+1/2
+1
+14.5
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
See Packaging Section for
Package Dimensions
RFB
IOUT1
N/C
IOUT2
VREF
3
IOUT1
IOUT2
AGND
STB1
LD1
N/C
SRI
STB2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
RFB
VREF
VDD
CLR
DGND
STB4
STB3
LD2
1
16
2
15
3
14
4
5
See
Pin Out
at Left
13
12
6
11
7
10
8
9
2
Rev. 2.00
2
19
4
18
VDD
STB1
5
17
CLR
N/C
6
16
N/C
LD1
7
15
DGND
N/C
8
14
STB4
10
SRI
16 Pin SOIC (Jedec, 0.300”)
S16
20
AGND
9
16 Pin CDIP, PDIP (0.300”)
D16, N16
1
11
12
13
N/C
STB3
STB2
LD2
20 Pin PLCC
P20
MP7543
PIN OUT DEFINITIONS
PDIP, CDIP and SOIC
PIN NO.
NAME
PLCC
DESCRIPTION
1
IOUT1
DAC current output pin. Normally
terminated at op amp virtual ground.
2
IOUT2
DAC current output pin. Normally
terminated at AGND.
3
AGND
Analog Ground.
4
STB1
5
LD1
PIN NO.
NAME
DESCRIPTION
1
N/C
No Connection.
2
IOUT1
DAC current output pin. Normally
terminated at op amp virtual ground.
3
IOUT2
DAC current output pin. Normally
terminated at AGND.
Register A Strobe 1 input, See Table 1.
4
AGND
Analog Ground.
DAC Register B Load 1 input. When
LD1 and LD2 go low the contents of
Register A are loaded into DAC
Register B.
5
STB1
Register A Strobe 1 input, See Table 1.
6
N/C
No Connection.
7
LD1
DAC Register B Load 1 input. When
LD1 and LD2 go low the contents of
Register A are loaded into DAC
Register B.
6
N/C
No Connection.
7
SRI
Serial Data Input to Register A.
8
STB2
Register A Strobe 2 input, See Table 1.
8
N/C
No Connection.
9
LD2
DAC Register B Load 2 input. When
LD1 and LD2 go low the contents of
Register A are loaded into DAC
Register B.
9
SR1
Serial Data Input to Register A.
10
STB2
Register A Strobe 2 input, See Table 1.
11
N/C
No Connection.
12
LD2
DAC Register B Load 2 input. When
LD1 and LD2 go low the contents of
Register A are loaded into DAC
Register B.
10
STB3
Register A Strobe 3 input, See Table 1.
11
STB4
Register A Strobe 4 input, See Table 1.
12
DGND
Digital Ground.
13
CLR
Register B CLEAR input (active
LOW), can be used to asynchronously
reset Register B to 0000 0000 0000.
13
STB3
Register A Strobe 3 input, See Table 1.
14
STB4
Register A Strobe 4 input, See Table 1.
14
VDD
+5 V Supply Input.
15
DGND
Digital Ground.
15
VREF
Reference input. Can be positive or
negative DC voltage or AC signal.
16
N/C
No Connection.
17
CLR
16
RFB
DAC Feedback Resistor.
Register B CLEAR input (active
LOW), can be used to asynchronously
reset Register B to 0000 0000 0000.
18
VDD
+5 V Supply Input.
19
VREF
Reference input. Can be positive or
negative DC voltage or AC signal.
20
RFB
DAC Feedback Resistor.
Rev. 2.00
3
MP7543
ELECTRICAL CHARACTERISTICS
(VDD = + 5 V, VREF = +10 V unless otherwise noted)
Parameter
Symbol
Min
N
12
25°C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
J, A, S
K, B, T
Differential Non-Linearity
J, A, S
K, B, T
Gain Error
J, A, K, B, S, T
Bits
INL
LSB
Best Fit Straight Line Spec.
(Max INL – Min INL) / 2
LSB
Monotonicity:
11 Bits Guaranteed
12 Bits Guaranteed
LSB
Using Internal RFB
+2
ppm/°C
∆Gain/∆Temperature
+50
+100
ppm/%
|∆Gain/∆VDD| ∆VDD = + 5%
+10
+10
+10
+200
+1
+1/2
+1
+1/2
+2
+1
+2
+1
+12.3
+14.5
DNL
GE
Gain Temperature Coefficient2
TCGE
Power Supply Rejection Ratio
PSRR
Output Leakage Current
J, K, A, B
S, T
12
IOUT
nA
DYNAMIC PERFORMANCE
µs
Current Output Settling Time2
tS
2
2
AC Feedthrough at IOUT12
FT
2.5
2.5
mV p-p
20
kΩ
ILKG
0.8
+1
0.8
+1
V
V
µA
COUT1
COUT1
COUT2
COUT2
260
100
50
210
260
100
50
210
pF
pF
pF
pF
DAC Inputs all 1’s
DAC Inputs all 0’s
DAC Inputs all 1’s
DAC Inputs all 0’s
5.25
V
VDD = +5 V +5% for specified
performance
All digital inputs = 0 V or all = 5 V
RL=100Ω, CL=13pF
Full Scale Output Settles to
1/2 LSB of Final Value
VREF = 10kHz, 20 Vp-p, sinewave
REFERENCE INPUT
Input Resistance
RIN
5
VIH
VIL
3.0
10
20
5
DIGITAL INPUTS3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
3.0
ANALOG OUTPUTS2
Output Capacitance
POWER SUPPLY
Supply Voltage
VDD
Supply Current
IDD
4.75
5.25
2.5
Rev. 2.00
4
4.75
2.5
mA
MP7543
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
25°C
Typ
Max
Tmin to Tmax
Min
Max
Symbol
Min
Units
tDS1
tDS4
tDS3
tDS2
tDH1
tDH4
tDH3
tDH2
tSRI
tLD1, 2
tASB
50
0
0
20
30
80
80
60
80
80
100
100
80
150
0
100
0
0
40
60
160
160
120
160
160
200
200
160
300
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
200
400
ns
Test Conditions/Comments
SWITCHING
CHARACTERISTICS2, 4
Serial Input to Strobe Set-up Time
Serial Input to Strobe Set-up Time
Serial Input to Strobe Set-up Time
Serial Input to Strobe Set-up Time
Serial Input to Strobe Hold Time
Serial Input to Strobe Hold Time
Serial Input to Strobe Hold Time
Serial Input to Strobe Hold Time
SRI Data Pulse Width
STB1 Pulse Width
STB4 Pulse Width
STB3 Pulse Width
STB2 Pulse Width
Load Pulse Width
Minimum time between strobing
Reg. A and loading Reg. B
CLR pulse width
tSTB1
tSTB4
tSTB3
tSTB2
STB1 used as a strobe
STB4 used as a strobe
STB3 used as a strobe
STB2 used as a strobe
STB1 used as a strobe
STB4 used as a strobe
STB3 used as a strobe
STB2 used as a strobe
NOTES:
1
2
3
4
Full Scale Range (FSR) is 10V for unipolar mode.
Guaranteed but not production tested.
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
See timing diagram.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Digital Input Voltage to GND (2) . GND –0.5 to VDD +0.5 V
IOUT1, IOUT2 to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V
VREF to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
VRFB to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V
(Functionality Guaranteed +0.5 V)
Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C
Package Power Dissipation Rating to 75°C
CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . 700mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 10mW/°C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.
3
GND refers to AGND and DGND.
Rev. 2.00
5
MP7543
TIMING DIAGRAM
tSRI
Bit 1
MSB
SR1
Bit 2
tDS1, tDS2, tDS4
Bit 11
Bit 12
LSB
11
12
tDH1, tDH2, tDH4
1
Strobe Input
(STB1, STB2, STB4
(Note)
2
tSTB1
tSTB2
tSTB4
LOADING REGISTER A
tASB
tLD1
tLD2
LD1 AND LD2
Note:
Strobe Waveform is Inverted if
STB3 is Used to Strobe Serial Data Bits
into Register A
Loading Register B
with Contents of Register A
MP7543 Logic Inputs
Register A Control Inputs
STB4
STB3
STB2
0
1
0
0
1
0
STB1
CLR
LD2
LD1
MP7543 Operation
Notes
X
X
X
Data appearing at SRI strobed into Register A
2, 3
0
X
X
X
Data appearing at SRI strobed into Register A
2, 3
0
0
X
X
X
Data appearing at SRI strobed into Register A
2, 3
X
X
X
Data appearing at SRI strobed into Register A
2, 3
1
0
0
X
X
X
X
0
X
X
X
X
1
X
X
X
X
1
1
Register B Control Inputs
No Operation (Register A)
0
X
X
1
1
X
1
X
1
1
0
0
Clear Register B to code 0000 0000 0000 (Asynchronous)
3
1, 3
No Operation (Register B)
3
Load Register B with the contents of Register A
3
NOTES
1. CLR = 0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A.
2. Serial data is loaded into Register A MSB first, on edges shown
is positive edge,
is negative edge.
3. 0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.
Table 1. Truth Table
Rev. 2.00
6
MP7543
APPLICATION NOTES
Refer to Section 8 for Applications Information
(8)
ADDRESS BUS (16)
A0-15
8085
ALE
E3
+5 V
R/W
8205
DECODER
ADDRESS (16)
E1
φ2
E3
E2
WR
(8) AD0-7
6800
E1
8212
ADDRESS BUS (16)
A0-15
ADDRESS (16)
8205
DECODER
E2
D0
DATA (8)
DATA
DATA BUS (8)
DATA (8)
D7
SOD
SR1 LD2 STB2
STB3
MP7543
STB1
STB4
CLR
LD1
+5 V
+5 V
FROM SYSTEM RESET
SR1 LD2 STB1
STB3
MP7543
STB2
STB4
LD1
CLR
FROM SYSTEM RESET
Figure 1. MP7543 8085 Interface
Figure 2. MP7543 MC6800 Interface
Digital Input
VIN
RFB
VREF
IOUT1
MP7543
IOUT2
–
+
VOUT
Figure 3. Digitally Programmable
Gain Amplifier
Graph 1. Relative Accuracy vs. Digital Code
Rev. 2.00
7
MP7543
16 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
N16
S
16
9
1
8
Q1
E1
E
D
A1
Seating
Plane
A
L
B
B1
e
α
MILLIMETERS
INCHES
SYMBOL
MIN
MAX
MIN
––
0.200
––
5.08
A1
0.015
––
0.38
––
B
0.014
0.023
0.356
0.584
B1 (1)
0.038
0.065
0.965
1.65
C
0.008
0.015
0.203
0.381
D
0.745
0.785
18.92
19.94
E
0.295
0.325
7.49
8.26
E1
0.220
0.310
5.59
7.87
A
e
0.100 BSC
MAX
2.54 BSC
L
0.115
0.150
2.92
3.81
α
0°
15°
0°
15°
Q1
0.055
0.070
1.40
1.78
S
0.020
0.080
0.51
2.03
Note:
(1)
The minimum limit for dimensions B1 may be 0.023”
(0.58 mm) for all four corner leads only.
Rev. 2.00
8
C
MP7543
16 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
D16
S1
See
Note 1
S
16
9
1
8
E1
E
D
Q
Base
Plane
Seating
Plane
A
L
e
c
b
INCHES
SYMBOL
L1
b1
NOTES
MILLIMETERS
MIN
MAX
MIN
A
––
0.200
––
5.08
––
b
0.014
0.023
0.356
0.584
––
b1
0.038
0.065
0.965
1.65
2
c
0.008
0.015
0.203
0.381
––
D
––
0.840
––
21.34
4
E
0.220
0.310
5.59
7.87
4
E1
0.290
0.320
7.37
8.13
7
e
0.100 BSC
MAX
2.54 BSC
NOTES
5
L
0.125
0.200
3.18
5.08
––
L1
0.150
––
3.81
––
––
Q
0.015
0.060
0.381
1.52
3
S
––
0.080
––
2.03
6
0.005
––
0.13
––
6
0°
15°
0°
15°
––
S1
α
α
Rev. 2.00
9
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one and is within the
shaded area shown.
2. The minimum limit for dimension b1 may be 0.023
(0.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating
plane to the base plane.
4. This dimension allows for off-center lid, meniscus and
glass overrun.
5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines.
6. Applies to all four corners.
7. This is measured to outside of lead, not center.
MP7543
16 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
S16
D
16
9
E
H
8
h x 45°
C
A
Seating
Plane
B
e
α
A1
L
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.097
0.104
2.46
2.64
A1
0.0050
0.0115
0.127
0.292
B
0.014
0.019
0.356
0.482
C
0.0091
0.0125
0.231
0.318
D
0.402
0.412
10.21
10.46
E
0.292
0.299
7.42
7.59
e
0.050 BSC
1.27 BSC
H
0.400
0.410
10.16
10.41
h
0.010
0.016
0.254
0.406
L
0.016
0.035
0.406
0.889
α
0°
8°
0°
8°
Rev. 2.00
10
MP7543
20 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
P20
D
D1
Seating
Plane
A2
1
D
B
D1
D2
e1
C
D3
A1
A
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.165
0.180
4.19
4.57
A1
0.100
0.110
2.54
2.79
A2
0.148
0.156
3.76
3.96
B
0.013
0.021
0.330
0.533
C
0.008
0.012
0.203
0.305
D
0.385
0.395
9.78
10.03
D1 (1)
0.350
0.354
8.89
8.99
D2
0.290
0.330
7.37
8.38
D3
0.200 Ref
5.08 Ref.
e1
0.050 BSC
1.27 BSC
Note:
(1)
Dimension D1 does not include mold protrusion.
Allowed mold protrusion is 0.254 mm/0.010 in.
Rev. 2.00
11
MP7543
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00
12