AD AD9600ABCPZ-150 10-bit, 105 msps/125 msps/150 msp Datasheet

10-Bit, 105 MSPS/125 MSPS/150 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9600
FEATURES
I/Q demodulation systems
Smart antenna systems
Digital predistortion
General-purpose software radios
Broadband data applications
Data acquisition
Nondestructive testing
SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS
SFDR = 81 dBc to 70 MHz at 150 MSPS
Low power: 825 mW at 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply
Integer 1 to 8 input clock divider
Intermediate frequency (IF) sampling frequencies up to 450 MHz
Internal analog-to-digital converter (ADC) voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input: 1 V p-p to 2 V p-p range
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
APPLICATIONS
7.
Point-to-point radio receivers (GPSK, QAM)
Diversity radio systems
Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
Fast overrange detect and signal monitor with serial output.
Signal monitor block with dedicated serial output mode.
Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
The AD9600 operates from a single 1.8 V supply and
features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or gray coding), enabling the
clock DCS, power-down mode, and voltage reference mode.
The AD9600 is pin compatible with the AD9627-11, AD9627,
and AD9640, allowing a simple migration from 10 bits to
11 bits, 12 bits, or 14 bits.
FUNCTIONAL BLOCK DIAGRAM
FD[0:3]A
SDIO/ SCLK/
DCS DFS CSB
FD BITS/THRESHOLD
DETECT
SPI
AD9600
PROGRAMMING DATA
VIN + A
SHA
ADC
VIN – A
– +
SENSE
CML
DUTY CYCLE
STABLIZER
DCO
GENERATION
VIN – B
SHA
ADC
SERIAL MONITOR
DATA
VIN + B
MULTICHIP
SYNC
AGND SYNC
SERIAL MONITOR
INTERFACE
FD BITS/THRESHOLD
DETECT
FD[0:3]B
D0A
CLK–
SIGNAL
MONITOR
REFERENCE
SELECT
D9A
CLK+
DIVIDE 1
TO 8
SMI
SMI
SMI
SDFS SCLK/ SDO/
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
CMOS/LVDS
OUTPUT BUFFER
VREF
DRVDD
DCOA
DCOB
D9B
D0B
DRGND
06909-001
DVDD
CMOS/LVDS
OUTPUT BUFFER
AVDD
Figure 1.
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
AD9600
TABLE OF CONTENTS
Features .............................................................................................. 1
Peak Detector Mode................................................................... 33
Applications ....................................................................................... 1
RMS/MS Magnitude Mode ....................................................... 33
Product Highlights ........................................................................... 1
Threshold Crossing Mode ......................................................... 34
Functional Block Diagram .............................................................. 1
Additional Control Bits ............................................................. 34
Revision History ............................................................................... 3
DC Correction ............................................................................ 35
General Description ......................................................................... 4
Signal Monitor SPORT Output ................................................ 35
Specifications..................................................................................... 5
Built-In Self-Test (BIST) and Output Test .................................. 36
DC Specifications ......................................................................... 5
Built-In Self-Test (BIST) ............................................................ 36
AC Specifications.......................................................................... 6
Output Test Modes ..................................................................... 36
Digital Specifications ................................................................... 7
Channel/Chip Synchronization .................................................... 37
Switching Specifications .............................................................. 9
Serial Port Interface (SPI) .............................................................. 38
Timing Characteristics .............................................................. 10
Configuration Using the SPI ..................................................... 38
Timing Diagrams........................................................................ 10
Hardware Interface..................................................................... 38
Absolute Maximum Ratings.......................................................... 12
Configuration Without the SPI ................................................ 39
Thermal Characteristics ............................................................ 12
SPI Accessible Features .............................................................. 39
ESD Caution ................................................................................ 12
Memory Map .................................................................................. 40
Pin Configuration and Function Descriptions ........................... 13
Reading the Memory Map Table .............................................. 40
Equivalent Circuits ......................................................................... 17
Memory Map .............................................................................. 41
Typical Performance Characteristics ........................................... 18
Memory Map Register Description ......................................... 44
Theory of Operation ...................................................................... 23
Applications Information .............................................................. 47
ADC Architecture ...................................................................... 23
Design Guidelines ...................................................................... 47
Analog Input Considerations.................................................... 23
Evaluation Board ............................................................................ 48
Voltage Reference ....................................................................... 25
Power Supplies ............................................................................ 48
Clock Input Considerations ...................................................... 26
Input Signals................................................................................ 48
Power Dissipation and Standby Mode ..................................... 28
Output Signals ............................................................................ 48
Digital Outputs ........................................................................... 28
Default Operation and Jumper Selection Settings ................. 49
Timing .......................................................................................... 29
Alternative Clock Configurations ............................................ 49
ADC Overrange and Gain Control .............................................. 30
Alternative Analog Input Drive Configuration...................... 50
Fast Detect Overview ................................................................. 30
Schematics ................................................................................... 51
ADC Fast Magnitude ................................................................. 30
Evaluation Board Layouts ......................................................... 61
ADC Overrange (OR) ................................................................ 31
Bill of Materials ........................................................................... 69
Gain Switching ............................................................................ 31
Outline Dimensions ....................................................................... 71
Signal Monitor ................................................................................ 33
Ordering Guide .......................................................................... 72
Rev. B | Page 2 of 72
AD9600
REVISION HISTORY
Added new models to Specifications Section ................................ 5
Changes to Table 7 ..........................................................................12
Updated Outline Dimensions ........................................................71
Changes to Ordering Guide ...........................................................72
Changes to Configuration Using the SPI Section ....................... 37
Changes to Table 22 ........................................................................ 40
Changes to Signal Monitor Period (Register 0x113 to
Register 0x115) Section .................................................................. 45
Added Exposed Pad Notation to Outline Dimensions .............. 70
6/09—Rev. 0 to Rev. A
11/07—Revision 0: Initial Version
12/09—Rev. A to Rev. B
Changes to Specifications Section................................................... 4
Changes to Figure 3.........................................................................10
Changes to Figure 11, Figure 12, and Figure 14 ..........................16
Changes to Table 12 ........................................................................28
Rev. B | Page 3 of 72
AD9600
GENERAL DESCRIPTION
The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS
ADC. It is designed to support communications applications
where low cost, small size, and versatility are desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
The AD9600 has several functions that simplify the automated
gain control (AGC) function in a communications receiver. For
example, the fast detect feature allows fast overrange detection
by outputting four bits of input level information with very
short latency.
In addition, the programmable threshold detector allows monitoring the amplitude of the incoming signal with short latency,
using the four fast detect bits of the ADC. If the input signal level
exceeds the programmable threshold, the fine upper threshold
indicator goes high. Because this threshold is set from the four
MSBs, the user can quickly adjust the system gain to avoid an
overrange condition.
Another AGC-related function of the AD9600 is the signal
monitor. This block allows the user to monitor the composite
magnitude of the incoming signal, which aids in setting the gain
to optimize the dynamic range of the overall system.
The ADC output data can be routed directly to the two external
10-bit output ports. These outputs can be set from 1.8 V to 3.3 V
CMOS or 1.8 V LVDS. In addition, flexible power-down options
allow significant power savings.
Rev. B | Page 4 of 72
AD9600
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTICS
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance 2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
Supply Current
IAVDD1
IDVDD1
IAVDD and IDVDD1, 3
IDRVDD (3.3 V CMOS)
IDRVDD (1.8 V CMOS)
IDRVDD (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1
DRVDD = 1.8 V
DRVDD = 3.3 V
Standby Power 3
Power-Down Power
Temp
Full
AD9600ABCPZ-105/
AD9600BCPZ-105
Min
Typ
Max
10
AD9600ABCPZ-125/
AD9600BCPZ-125
Min
Typ
Max
10
AD9600ABCPZ-150/
AD9600BCPZ-150
Min
Typ
Max
10
Unit
Bits
Full
Full
Full
Full
25°C
Full
25°C
Guaranteed
±0.3
±0.7
−3.6
−2.2
−1.0
±0.2
±0.1
±0.3
±0.1
Guaranteed
±0.3
±0.7
−4.0
−2.5
−1.3
±0.2
±0.1
±0.3
±0.1
Guaranteed
±0.3
±0.7
−4.3
−3.0
−1.6
±0.2
±0.1
±0.4
±0.1
% FSR
% FSR
LSB
LSB
LSB
LSB
Full
Full
±0.3
±0.2
Full
Full
±15
±95
Full
Full
±5
7
25°C
0.1
0.1
0.1
LSB rms
Full
Full
Full
2
8
6
2
8
6
2
8
6
V p-p
pF
kΩ
Full
Full
1.7
1.7
±0.7
±0.8
±0.3
±0.3
Full
Full
310
34
Full
Full
35
15
42
Full
600
Full
Full
Full
Full
645
740
68
2.5
±0.2
±0.2
±15
±95
±16
1.8
3.3
±0.7
±0.8
1.9
3.6
±5
7
1.7
1.7
1.8
3.3
±15
±95
±16
1.9
3.6
385
42
365
1.7
1.7
1.8
3.3
455
750
6
813
900
77
2.5
1
±5
7
% FSR
% FSR
ppm/°C
ppm/°C
±16
1.9
3.6
419
50
36
18
44
650
±0.7
±0.8
mV
mV
V
V
mA
mA
495
42
22
46
800
825
6
892
990
77
2.5
mA
mA
mA
890
mW
6
mW
mW
mW
mW
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure.
3
Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND.
2
Rev. B | Page 5 of 72
AD9600
AC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 29.1 MHz, 32.1 MHz (−7 dBFS )
fIN = 169.1 MHz, 172.1 MHz (−7 dBFS )
CROSSTALK 2
ANALOG INPUT BANDWIDTH
1
2
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
AD9600ABCPZ-105/
AD9600BCPZ-105
AD9600ABCPZ-125/
AD9600BCPZ-125
AD9600ABCPZ-150/
AD9600BCPZ-150
Min
Min
Min
Typ
Max
60.7
60.6
Typ
Max
60.6
60.6
60.3
Typ
Max
60.6
60.6
60.3
dB
dB
dB
dB
dB
60.3
60.6
60.5
60.6
60.5
60.5
60.4
60.6
60.5
60.5
60.5
60.5
60.5
Unit
60.5
60.4
60.5
60.4
60.4
60.3
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−87.0
−85.0
−86.5
−85.0
−88.5
−84.0
−84.0
−83.0
−84.0
−83.0
−83.5
−77
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
85.5
85.0
85.5
85.0
85.5
84.0
60.2
60.2
60.1
−72.0
72.0
−72.0
72.0
−72.0
dBc
dBc
dBc
dBc
dBc
72.0
83.0
81.0
84.0
81.0
83.5
77
25°C
25°C
Full
25°C
25°C
−92
−88
−92
-88
−92
−88
−86
−86
−86
−86
−86
−86
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
84
82
95
650
84
82
95
650
84
82
95
650
dBc
dBc
dB
MHz
−81
−81
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. B | Page 6 of 72
−80
AD9600
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
1.2
0.2
6
GND − 0.3
AVDD + 1.6
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
4
8
10
12
Full
Full
Full
Full
Full
Full
Full
Full
Max
CMOS
1.2
GND − 0.3
1.2
0
−10
−10
8
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Rev. B | Page 7 of 72
Typ
AVDD + 1.6
3.6
0.8
+10
+10
4
10
12
V
V p-p
V
V
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
3.6
0.6
+10
132
V
V
μA
μA
kΩ
pF
3.6
0.6
−135
+10
V
V
μA
μA
kΩ
pF
3.6
0.6
+10
128
V
V
μA
μA
kΩ
pF
26
2
26
2
26
5
Unit
AD9600
Parameter
LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
1
2
Temperature
Min
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
Full
Full
Full
Full
3.29
3.25
Full
Full
Full
Full
1.79
1.75
Full
Full
Full
Full
250
1.15
150
1.15
Pull up.
Pull down.
Rev. B | Page 8 of 72
Typ
Max
Unit
3.6
0.6
−134
+10
V
V
μA
μA
kΩ
pF
26
5
350
1.25
200
1.25
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
450
1.35
280
1.35
mV
V
mV
V
AD9600
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled
DCS Disabled
CLK Period (tCLK)
CLK Pulse Width High
Divide-by-1 Mode,
DCS Enabled
Divide-by-1 Mode,
DCS Disabled
Divide-by-2 Mode,
DCS Enabled
Divide-by-3 Through Divideby-8 Modes, DCS Enabled
DATA OUTPUT PARAMETERS
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD) 1
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)1
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)1
DCO Propagation Delay (tDCO)
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay
(Latency) Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time 2
OUT-OF-RANGE RECOVERY TIME
1
2
Temp
AD9600ABCPZ-105/
AD9600BCPZ-105
Min
Typ
Max
Full
AD9600ABCPZ-125/
AD9600BCPZ-125
Min
Typ
Max
625
AD9600ABCPZ-150/
AD9600BCPZ-150
Min
Typ
Max
625
105
105
20
10
8
4.75
6.65
2.4
4.75
5.23
3.6
Unit
625
MHz
150
150
MSPS
MSPS
ns
Full
Full
Full
20
10
9.5
125
125
20
10
6.66
Full
2.85
4
5.6
2.0
3.33
4.66
ns
Full
4.28
4
4.4
3.0
3.33
3.66
ns
Full
1.6
1.6
1.6
ns
Full
0.8
0.8
0.8
ns
Full
Full
Full
Full
2.2
3.8
4.5
5.0
5.25
4.25
6.4
6.8
2.2
3.8
4.5
5.0
4.5
3.5
6.4
6.8
2.2
3.8
4.5
5.0
3.83
2.83
6.4
6.8
ns
ns
ns
ns
Full
Full
Full
Full
2.4
4.0
5.2
5.6
5.25
4.25
6.9
7.3
2.4
4.0
5.2
5.6
4.5
3.5
6.9
7.3
2.4
4.0
5.2
5.6
3.83
2.83
6.9
7.3
ns
ns
ns
ns
Full
Full
Full
3.0
5.2
3.7
6.4
12
4.4
7.6
3.0
5.0
3.8
6.2
12
4.5
7.4
3.0
4.8
3.8
5.9
12
4.5
7.3
ns
ns
Cycles
Full
12/12.5
12/12.5
12/12.5
Cycles
Full
Full
Full
Full
1.0
0.1
350
2
1.0
0.1
350
3
1.0
0.1
350
3
ns
ps rms
μs
Cycles
Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors.
Rev. B | Page 9 of 72
AD9600
TIMING CHARACTERISTICS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Conditions
Min
Setup time between SYNC and the rising edge of CLK+
Hold time between SYNC and the rising edge of CLK+
SPORT TIMING REQUIREMENTS
tCSSCLK
tSSCLKSDO
tSSCLKSDFS
Delay from the rising edge of CLK+ to the rising edge of SMI SCLK
Delay from the rising edge of SMI SCLK to SMI SDO
Delay from the rising edge of SMI SCLK to SMI SDFS
10
ns
3.2
−0.4
−0.4
4.5
0
0
N+3
N
N+4
N+8
N+5
N+6
N+7
tCLK
CLK+
CLK–
CH A/CH B DATA
N – 13
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
CH A/CH B FAST
DETECT
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
tH
tDCO
tCLK
DCOA/DCOB
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing
Rev. B | Page 10 of 72
06909-012
tPD
tS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
N+2
tA
Unit
2
2
40
2
2
10
10
10
TIMING DIAGRAMS
N+1
Max
0.24
0.40
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
tDIS_SDIO
Typ
6.2
0.4
0.4
ns
ns
ns
AD9600
N+2
N+1
N+3
N
N+4
N+8
tA
N+5
N+6
N+7
tCLK
CLK+
CLK–
tPD
CH A/CH B DATA
A
B
A
N – 12
N – 13
CH A/CH B FAST
DETECT
A
B
B
A
N–7
B
N–6
A
B
N – 11
A
B
N–5
A
B
N – 10
A
B
N–4
A
B
A
N–9
A
B
N–8
B
A
N–3
B
N–2
tDCO
A
B
N–7
A
B
N–1
A
B
A
N–6
A
B
B
N–5
A
N
B
N+1
A
N–4
A
N+2
tCLK
06909-089
DCO+
DCO–
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
CLK+
tHSYNC
06909-072
tSSYNC
SYNC
Figure 4. SYNC Input Timing Requirements
CLK+
CLK–
tCSSCLK
SMI SCLK/PDWN
tSSCLKSDFS
tSSCLKSDO
SMI SDO/OEB
DATA
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)
Rev. B | Page 11 of 72
DATA
06909-082
SMI SDFS
AD9600
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
ELECTRICAL
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
VIN + A/VIN + B, VIN − A/VIN − B to
AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
Output Data Pins to DRGND1
Fast Detect Output Pins to DRGND2
Data Clock Output Pins to DRGND3
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
THERMAL CHARACTERISTICS
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Airflow
Velocity
Package Type
(m/s)
64-Lead, 9 mm × 9 mm 0
LFCSP (CP-64-3,
1.0
CP-64-6)
2.0
θJC1, 3
0.6
θJB1, 4
6.0
15.8
1
Per JEDEC 51-7 standard and JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
3
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal (such as metal traces through holes, ground,
and power planes) that is in direct contact with the package
leads reduces the θJA.
ESD CAUTION
−40°C to +85°C
θJA1, 2
18.8
16.5
150°C
−65°C to +150°C
1
The output data pins are D0A/D0B to D9A/D9B for the CMOS configuration
and D0+/D0− to D9+/D9− for the LVDS configuration.
2
The fast detect output pins are FD0A/FD0B to FD3A/FD3B for the CMOS
configuration and FD0+/FD0− to FD3+/FD3−.
3
The data clock output pins are DCOA and DCOB for the CMOS configuration
and DCO+ and DCO− for the LVDS configuration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 12 of 72
Unit
°C/W
°C/W
°C/W
AD9600
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
D1B
D0B (LSB)
DNC
DNC
DNC
DNC
DVDD
FD3B
FD2B
FD1B
FD0B
SYNC
CSB
CLK–
CLK+
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9600
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN + B
VIN – B
RBIAS
CML
SENSE
VREF
VIN – A
VIN + A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
06909-002
D1A
D2A
D3A
DRGND
DRVDD
D4A
D5A
DVDD
D6A
D7A
D8A
(MSB) D9A
FD0A
FD1A
FD2A
FD3A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
D2B
D3B
D4B
D5B
D6B
D7B
D8B
(MSB) D9B
DCOB
DCOA
DNC
DNC
DNC
DNC
(LSB) D0A
Figure 6. Parallel CMOS Mode Pin Configuration (Top View)
Table 8. Parallel CMOS Mode Pin Function Descriptions
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
ADC Inputs
37
38
44
43
39
40
42
41
49
50
Mnemonic
Type
Description
DRGND
DRVDD
DVDD
AVDD
AGND
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
VIN + A
VIN − A
VIN + B
VIN − B
VREF
SENSE
RBIAS
CML
CLK+
Input
Input
Input
Input
I/O
Input
Input
Output
Input
CLK−
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select (see Table 11 for details).
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Master Clock True. The ADC clock can be driven using a single-ended
CMOS (see Figure 60 and Figure 61 for the recommended connection).
ADC Master Clock Complement. The ADC clock can be driven using a singleended CMOS (see Figure 60 and Figure 61 for the recommended connection).
Rev. B | Page 13 of 72
AD9600
Pin No.
ADC Fast Detect Outputs
29
30
31
32
53
54
55
56
Digital Inputs
52
Digital Outputs
16 to 19, 22, 23,
25 to 28
62, 63, 2 to 9
11
10
SPI Control
48
47
51
Signal Monitor Port
33
35
34
Do Not Connect
12 to 15, 58 to 61
Mnemonic
Type
Description
FD0A
FD1A
FD2A
FD3A
FD0B
FD1B
FD2B
FD3B
Output
Output
Output
Output
Output
Output
Output
Output
Channel A Fast Detect Indicator (see Table 14 for details).
Channel A Fast Detect Indicator (see Table 14 for details).
Channel A Fast Detect Indicator (see Table 14 for details).
Channel A Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
SYNC
Input
Digital Synchronization Pin (Slave Mode Only).
D0A to D9A
Output
Channel A CMOS Output Data.
D0B to D9B
DCOA
DCOB
Output
Output
Output
Channel B CMOS Output Data.
Channel A Data Clock Output.
Channel B Data Clock Output.
SCLK/DFS
SDIO/DCS
CSB
Input
I/O
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode.
SPI Chip Select (Active Low).
SMI SDO/OEB
I/O
SMI SDFS
SMI SCLK/PDWN
Output
I/O
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in
External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
DNC
N/A
Do Not Connect.
Rev. B | Page 14 of 72
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
DNC
DNC
FD3+
FD3–
FD2+
FD2–
DVDD
FD1+
FD1–
FD0+
FD0–
SYNC
CSB
CLK–
CLK+
AD9600
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9600
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN + B
VIN – B
RBIAS
CML
SENSE
VREF
VIN – A
VIN + A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
06909-003
D3+
D4–
D4+
DRGND
DRVDD
D5–
D5+
DVDD
D6–
D6+
D7–
D7+
D8–
D8+
D9–
(MSB) D9+
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
DNC
DNC
DNC
DNC
DNC
DNC
(LSB) D0–
D0+
DCO–
DCO+
D1–
D1+
D2–
D2+
D3–
Figure 7. Interleaved Parallel LVDS Mode Pin Configuration (Top View)
Table 9. Interleaved Parallel LVDS Mode Pin Function Descriptions
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
ADC Inputs
37
38
44
43
39
40
42
41
49
50
Mnemonic
Type
Description
DRGND
DRVDD
DVDD
AVDD
AGND
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
VIN + A
VIN − A
VIN + B
VIN − B
VREF
SENSE
RBIAS
CML
CLK+
Input
Input
Input
Input
I/O
Input
Input
Output
Input
CLK−
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select (see Table 11 for details).
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Master Clock True. The ADC clock can be driven using a single-ended CMOS
(see Figure 60 and Figure 61 for the recommended connection).
ADC Master Clock Complement. The ADC clock can be driven using a single-ended
CMOS (see Figure 60 and Figure 61 for the recommended connection).
Rev. B | Page 15 of 72
AD9600
Pin No.
ADC Fast Detect Outputs
54
53
Mnemonic
Type
Description
FD0+
FD0−
Output
Output
56
55
FD1+
FD1−
Output
Output
59
58
FD2+
FD2−
Output
Output
61
60
FD3+
FD3−
Output
Output
Channel A/Channel B LVDS Fast Detect Indicator 0 True (see Table 14 for full details).
Channel A/Channel B LVDS Fast Detect Indicator 0 Complement (see Table 14
for details).
Channel A/Channel B LVDS Fast Detect Indicator 1 True (see Table 14 for details).
Channel A/Channel B LVDS Fast Detect Indicator 1 Complement (see Table 14
for details).
Channel A/Channel B LVDS Fast Detect Indicator 2 True (see Table 14 for details).
Channel A/Channel B LVDS Fast Detect Indicator 2 Complement (see Table 14
for details).
Channel A/Channel B LVDS Fast Detect Indicator 3 True (see Table 14 for details).
Channel A/Channel B LVDS Fast Detect Indicator 3 Complement (see Table 14
for details).
SYNC
Input
Digital Synchronization Pin (Slave Mode Only).
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
DCO+
DCO−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0 True.
Channel A/Channel B LVDS Output Data 0 Complement.
Channel A/Channel B LVDS Output Data 1 True.
Channel A/Channel B LVDS Output Data 1 Complement.
Channel A/Channel B LVDS Output Data 2 True.
Channel A/Channel B LVDS Output Data 2 Complement.
Channel A/Channel B LVDS Output Data 3 True.
Channel A/Channel B LVDS Output Data 3 Complement.
Channel A/Channel B LVDS Output Data 4 True.
Channel A/Channel B LVDS Output Data 4 Complement.
Channel A/Channel B LVDS Output Data 5 True.
Channel A/Channel B LVDS Output Data 5 Complement.
Channel A/Channel B LVDS Output Data 6 True.
Channel A/Channel B LVDS Output Data 6 Complement.
Channel A/Channel B LVDS Output Data 7 True.
Channel A/Channel B LVDS Output Data 7 Complement.
Channel A/Channel B LVDS Output Data 8 True.
Channel A/Channel B LVDS Output Data 8 Complement.
Channel A/Channel B LVDS Output Data 9 True.
Channel A/Channel B LVDS Output Data 9 Complement.
Channel A/Channel B LVDS Data Clock Output True.
Channel A/Channel B LVDS Data Clock Output Complement.
SCLK/DFS
SDIO/DCS
CSB
Input
I/O
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode.
SPI Chip Select (Active Low).
SMI SDO/OEB
I/O
SMI SDFS
SMI SCLK/PDWN
Output
I/O
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in
External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
DNC
N/A
Do Not Connect.
Digital Inputs
52
Digital Outputs
9
8
13
12
15
14
17
16
19
18
23
22
26
25
28
27
30
29
32
31
11
10
SPI Control
48
47
51
Signal Monitor Port
33
35
34
Do Not Connect
2 to 7, 62, 63
Rev. B | Page 16 of 72
AD9600
EQUIVALENT CIRCUITS
DVDD
1kΩ
SCLK/DFS
26kΩ
06909-004
06909-008
VIN
Figure 12. Equivalent SCLK/DFS Input Circuit
Figure 8. Analog Input Circuit
AVDD
1kΩ
SENSE
1.2V
10kΩ
10kΩ
CLK+
06909-005
06909-009
CLK–
Figure 13. Equivalent SENSE Circuit
Figure 9. Equivalent Clock Input Circuit
DRVDD
DVDD
26kΩ
DVDD
1kΩ
06909-081
06909-010
CSB
DRGND
Figure 14. Equivalent CSB Input Circuit
Figure 10. Digital Output
DRVDD
DVDD
26kΩ
DVDD
1kΩ
SDIO/DCS
AVDD
06909-007
6kΩ
Figure 11. Equivalent SDIO/DCS Input Circuit
06909-011
VREF
DRVDD
Figure 15. Equivalent VREF Circuit
Rev. B | Page 17 of 72
AD9600
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1 V internal reference, 2 V p-p differential input,
VIN = −1.0 dBFS, 64k sample, and TA = 25°C, unless otherwise noted.
0
0
150MSPS
2.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.9 BITS
SFDR = 85.5dBc
–20
AMPLITUDE (dBFS)
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
20
30
40
50
60
70
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
Figure 19. AD9600-150 Single-Tone FFT with fIN = 140 MHz
0
0
150MSPS
30.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.9 BITS
SFDR = 84.0dBc
–40
–60
THIRD HARMONIC
SECOND
HARMONIC
–80
150MSPS
220MHz @ –1dBFS
SNR = 60.4dB (61.4dBFS)
ENOB = 9.7 BITS
SFDR = 77.0dBc
–20
AMPLITUDE (dBFS)
–20
–100
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
10
20
30
40
50
60
70
FREQUENCY (MHz)
–120
06909-030
0
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
06909-120
AMPLITUDE (dBFS)
THIRD HARMONIC
–80
–120
Figure 16. AD9600-150 Single-Tone FFT with fIN = 2.3 MHz
Figure 20. AD9600-150 Single-Tone FFT with fIN = 220 MHz
Figure 17. AD9600-150 Single-Tone FFT with fIN = 30.3 MHz
0
0
150MSPS
70MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 84.0dBc
–40
–60
SECOND HARMONIC
150MSPS
337MHz @ –1dBFS
SNR = 60.2dB (61.2dBFS)
ENOB = 9.7 BITS
SFDR = 74.0dBc
–20
AMPLITUDE (dBFS)
–20
THIRD HARMONIC
–80
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
–100
–120
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
06909-118
AMPLITUDE (dBFS)
SECOND HARMONIC
06909-119
10
06909-029
0
FREQUENCY (MHz)
–120
–60
–100
–100
–120
–40
–120
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
Figure 21. AD9600-150 Single-Tone FFT with fIN = 337 MHz
Figure 18. AD9600-150 Single-Tone FFT with fIN = 70 MHz
Rev. B | Page 18 of 72
06909-121
AMPLITUDE (dBFS)
–20
150MSPS
140MHz @ –1dBFS
SNR = 60.5dB (61.5dBFS)
ENOB = 9.8 BITS
SFDR = 83.5dBc
AD9600
0
0
150MSPS
440MHz @ –1dBFS
SNR = 60.0dB (61.0dBFS)
ENOB = 9.6 BITS
SFDR = 70.0dBc
–20
AMPLITUDE (dBFS)
–40
SECOND HARMONIC
–60
THIRD HARMONIC
–80
THIRD HARMONIC
SECOND HARMONIC
–80
10
20
30
40
50
FREQUENCY (MHz)
60
70
–120
0
Figure 22. AD9600-150 Single-Tone FFT with fIN = 440 MHz
10
20
30
40
FREQUENCY (MHz)
50
60
06909-125
0
06909-122
–120
Figure 25. AD9600-125 Single-Tone FFT with fIN = 70.1 MHz
0
0
125MSPS
2.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 86.5dBc
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
125MSPS
140.1MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 84.0dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
–100
0
10
20
30
40
FREQUENCY (MHz)
50
60
–120
06909-123
–120
0
Figure 23. AD9600-125 Single-Tone FFT with fIN = 2.3 MHz
10
20
30
40
FREQUENCY (MHz)
50
60
06909-126
AMPLITUDE (dBFS)
–60
–100
–100
Figure 26. AD9600-125 Single-Tone FFT with fIN = 140.1 MHz
0
0
125MSPS
30.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 85.0dBc
125MSPS
220.1MHz @ –1dBFS
SNR = 60.5dB (61.5dBFS)
ENOB = 9.7 BITS
SFDR = 81.0dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
–100
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
06909-124
AMPLITUDE (dBFS)
–40
Figure 24. AD9600-125 Single-Tone FFT with fIN = 30.3 MHz
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
Figure 27. AD9600-125 Single-Tone FFT with fIN = 220.1 MHz
Rev. B | Page 19 of 72
06909-127
AMPLITUDE (dBFS)
–20
125MSPS
70.1MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 85.0dBc
AD9600
95
120
90
SFDR +25°C
SFDR (dBFS)
SNR (dBFS)
SFDR –40°C
85
80
SNR/SFDR (dBc)
SNR/SFDR (dBc AND dBm)
100
60
85dB REFERENCE LINE
40
80
75
SFDR +85°C
70
SNR +25°C
SNR +85°C
SNR –40°C
65
SFDR (dBc)
20
60
–40
–30
–20
–10
0
AMPLITUDE (dBm)
55
Figure 28. AD9600-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 2.4 MHz
0
50
100
150
200
250
350
400
–2.5
0.5
SFDR (dBFS)
80
GAIN
–3.0
GAIN ERROR (%FSR)
SNR (dBFS)
60
85dB REFERENCE LINE
40
450
Figure 31. AD9600-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with12 V p-p Full Scale
100
SNR/SFDR (dBc AND dBm)
300
INPUT FREQUENCY (MHz)
0.4
OFFSET
–3.5
0.3
–4.0
0.2
–4.5
0.1
SNR (dBc)
20
OFFSET ERROR (%FSR)
–50
06909-031
0
–60
06909-034
SNR (dBc)
–50
–40
–30
–20
–10
0
AMPLITUDE (dBm)
–5.0
–40
06909-032
0
–60
0
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 29. AD9600-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 98.12 MHz
06909-132
SFDR (dBc)
Figure 32. AD9600-150 Gain and Offset vs. Temperature
95
0
90
–20
SFDR/IMD3 (dBc AND dBFS)
SFDR +85°C
SNR/SFDR (dBc)
85
SFDR +25°C
80
SFDR –40°C
75
70
SNR +25°C
SNR +85°C
SNR –40°C
65
SFDR (dBc)
–40
–60
IMD3 (dBc)
SFDR (dBFS)
–80
–100
60
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
350
400
450
–120
–60
Figure 30. AD9600-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2 V p-p Full Scale
–48
–36
–24
INPUT AMPLITUDE (dBFS)
–12
06909-133
0
06909-033
55
IMD3 (dBFS)
Figure 33. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
Rev. B | Page 20 of 72
AD9600
0
0
150MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 83.1dBc (90.1dBFS)
SFDR (dBc)
–20
AMPLITUDE (dBFS)
–40
IMD3 (dBc)
–60
SFDR (dBFS)
–80
–60
–80
IMD3 (dBFS)
–100
–100
–36
–24
INPUT AMPLITUDE (dBFS)
–12
–120
Figure 34. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
0
20
30
40
50
INPUT FREQUENCY (MHz)
60
70
Figure 37. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency (fIN) with
fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
0
0
NPR = 54.3dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–100
15.36
30.72
46.08
61.44
FREQUENCY (MHz)
–120
0
10
20
30
40
50
60
06909-138
0
06909-135
–120
70
FREQUENCY (MHz)
Figure 35. AD9600-125 Two 64k WCDMA Carriers with
fIN = 170 MHz, fS = 125 MSPS
Figure 38. AD9600-150 Noise Power Ratio (NPR)
100
0
150MSPS
29.1MHz @ –7dBFS
32.1MHz @ –7dBFS
SFDR = 86.1dBc (93.1dBFS)
–20
SFDR—SIDE B
90
–40
SNR/SFDR (dBc)
AMPLITUDE (dBFS)
10
06909-137
–48
06909-134
–120
–60
AMPLITUDE (dBFS)
–40
–60
–80
80
SFDR—SIDE A
70
SNR—SIDE A
SNR—SIDE B
60
–100
0
10
20
30
40
50
INPUT FREQUENCY (MHz)
60
70
50
06909-136
–120
Figure 36. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency (fIN) with
fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
0
25
50
75
ENCODE (MSPS)
100
125
150
06909-035
SFDR/IMD3 (dBc AND dBFS)
–20
Figure 39. AD9600-150 Single-Tone SNR/SFDR vs. Clock Frequency (fS ) with
fIN1 = 2.3 MHz
Rev. B | Page 21 of 72
AD9600
12
100
0.10 LSB rms
95
SFDR DCS ON
90
8
SNR/SFDR (dBc)
NUMBER OF HITS (1M)
10
6
4
85
80
SFDR DCS OFF
75
SNR DCS ON
70
2
65
N–2
N–1
N
N+1
N+2
N+3
OUTPUT CODE
06909-140
N–3
60
20
40
60
80
DUTY CYCLE (%)
Figure 40. AD9600 Grounded Input Histogram
06909-143
SNR DCS OFF
0
Figure 43. AD9600-150 SNR/SFDR vs. Duty Cycle with fIN1 = 10.3 MHz
95
0.10
90
SNR/SFDR (dBc)
INL ERROR (LSB)
SFDR
85
0.05
0
80
75
70
65
–0.05
SNR
0
128
256
384
512
640
768
896
1024
OUTPUT CODE
55
0.2
06909-036
–0.10
Figure 41. AD9600 INL with fIN1 = 10.3 MHz
0.025
0
–0.025
–0.050
–0.075
256
384
512
640
768
OUTPUT CODE
896
1024
06909-037
DNL ERROR (LSB)
0.050
128
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Figure 44. AD9600-150 SNR/SFDR vs. Input Common-Mode Voltage (VCM) with
fIN1 = 30 MHz
0.075
0
0.4
INPUT COMMON-MODE VOLTAGE (V)
0.100
–0.100
0.3
06909-144
60
Figure 42. AD9600 DNL with fIN1 = 10.3 MHz
Rev. B | Page 22 of 72
AD9600
THEORY OF OPERATION
The AD9600 dual ADC design can be used for diversity
reception of signals, where the ADCs are operating identically
on the same carrier but from two separate antennae. The ADCs
can also be operated with independent analog inputs. The user
can sample any fS/2 frequency segment from dc to 200 MHz
using appropriate low-pass or band-pass filtering at the ADC
inputs with little loss in ADC performance. Although operation
of up to 450 MHz analog input is permitted, ADC distortion
increases at frequencies toward the higher end of this range.
In nondiversity applications, the AD9600 can be used as a
baseband receiver where one ADC is used for I input data and
the other used for Q input data.
Synchronization capability is provided to allow synchronized
timing among multiple channels or multiple devices.
Programming and control of the AD9600 is accomplished using
a 3-bit SPI-compatible serial interface.
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. A shunt capacitor can be placed
across the inputs to provide dynamic charging currents. This
passive network creates a low-pass filter at the ADC’s input;
therefore, the precise values are dependent on the application.
In undersampling (IF sampling) applications, any shunt capacitors
should be reduced. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth. See
the AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article “Transformer-Coupled
Front-End for Wideband A/D Converters” (Volume 39, April 2005)
for more information. In general, the precise values are dependent
on the application.
S
ADC ARCHITECTURE
CH
The AD9600 architecture consists of a dual front-end sampleand-hold amplifier (SHA) followed by a pipelined switchedcapacitor ADC. The quantized outputs from each stage are
combined into a final 10-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample while the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline excluding the last consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(a multiplying digital-to-analog converter (MDAC)). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the
pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, corrects errors, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9600 is a differential switchedcapacitor SHA that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternatively switches the SHA between
sample mode and hold mode (see Figure 45). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
S
CS
VIN+
CPIN, PAR
S
H
CS
VIN–
CH
S
06909-013
CPIN, PAR
Figure 45. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core.
The span of the ADC core is set by the buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9600 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide this
bias externally. Setting the device so that VCM = 0.55 × AVDD is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance (see
Figure 44). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage (typically
0.55 × AVDD). The CML pin must be decoupled to ground by a
0.1 μF capacitor as described in the Applications Information
section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9600
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the
Rev. B | Page 23 of 72
AD9600
An alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone is to use the AD8352
differential driver. An example is shown in Figure 50. See the
AD8352 data sheet for more information.
ADC. The output common-mode voltage of the AD8138 is
easily set with the CML pin of the AD9600 (see Figure 46), and
the driver can be configured in a Sallen-Key filter topology to
band limit the input signal.
AVDD
VIN+
R
499Ω
AD9600
C
AD8138
R
523Ω
VIN–
CML
499Ω
Table 10. Example RC Network
Figure 46. Differential Input Configuration Using the AD8138
Frequency Range (MHz)
0 to 70
70 to 200
200 to 300
>300
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 47. The CML
voltage can be connected to the center tap of the transformer’s
secondary winding to bias the analog input.
49.9Ω
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 48
details a typical single-ended input configuration.
VIN+
AD9600
C
R
AVDD
10µF
VIN–
1kΩ
CML
R
06909-015
0.1µF
2V p-p
49.9Ω
0.1µF
AVDD
Figure 47. Differential Transformer-Coupled Configuration
0.1µF
10µF
0.1µF
ADC
AD9600
C
1kΩ
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9600. For applications where
SNR is a key parameter, differential double-balun coupling is
the recommended input configuration. An example is shown
in Figure 49.
VIN+
1kΩ
R
VIN–
1kΩ
Figure 48. Single-Ended Input Configuration
0.1µF
R
VIN+
2V p-p
25Ω
PA
S
S
P
AD9600
C
25Ω
0.1µF
0.1µF
R
CML
VIN–
06909-228
2V p-p
Figure 49. Differential Double-Balun Input Configuration
VCC
0.1µF
0Ω
ANALOG INPUT
16
0.1µF
8, 13
1
11
0.1µF
RD
RG
3
200Ω
AD8352
10
4
5
ANALOG INPUT
0.1µF
0Ω
R
VIN+
2
CD
C Differential (pF)
15
5
5
Open
Single-Ended Input Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz. Excessive signal power can cause core
saturation, which leads to distortion.
R
R Series (Ω, Each)
33
33
15
15
C
0.1µF
200Ω
R
AD9600
VIN–
CML
14
0.1µF
0.1µF
Figure 50. Differential Input Configuration Using the AD8352
Rev. B | Page 24 of 72
06909-270
0.1µF
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and source impedance and may
need to be reduced or removed. Table 10 lists the recommended
values to set the RC network. However, the actual values are
dependent on the input signal; therefore, Table 10 should only
be used as a starting guide.
499Ω
06909-018
49.9Ω
06909-014
1V p-p
AD9600
VOLTAGE REFERENCE
VIN + A/VIN + B
VIN – A/VIN – B
A stable and accurate voltage reference is built into the AD9600.
The input range can be adjusted by varying the reference voltage
applied to the AD9600, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in this section. The Reference
Decoupling section describes the best PCB layout practices
for the reference.
ADC
CORE
VREF
1µF
0.1µF
R2
SELECT
LOGIC
SENSE
R1
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN + A/VIN + B
VIN – A/VIN – B
Figure 52. Programmable Reference Configuration
If the internal reference of the AD9600 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 53 depicts
how the internal reference voltage is affected by loading.
0
VREF = 0.5V
ADC
CORE
–0.25
VREF = 1.0V
–0.50
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
2.0
LOAD CURRENT (mA)
VREF
1µF
Figure 53. VREF Accuracy vs. Load
0.1µF
SELECT
LOGIC
SENSE
AD9600
06909-019
0.5V
Figure 51. Internal Reference Configuration
Table 11. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Resulting VREF (V)
N/A
0.5
Internal Fixed Reference
AGND to 0.2 V
1.0
R2 ⎞ (see Figure 52)
0 . 5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
Rev. B | Page 25 of 72
Resulting Differential Span (V p-p)
2 × external reference
1.0
2 × VREF
2.0
06909-280
R2 ⎞
VREF = 0.5 × ⎛⎜1 +
⎟
⎝ R1 ⎠
0.5V
AD9600
REFERENCE VOLTAGE ERROR (%)
A comparator within the AD9600 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Table 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 51), setting VREF to 1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V
reference output. If a resistor divider is connected external to
the chip as shown in Figure 52, the switch again selects the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
06909-020
Internal Reference Connection
AD9600
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve the thermal drift
characteristics. Figure 54 shows the typical drift characteristics
of the internal reference in 1.0 V mode.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9600 while
preserving the fast rise and fall times of the signal that are
critical to low jitter performance.
2.0
1.5
1.0
0
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
XFMR
–0.5
0.1µF
–1.0
CLK+
CLK+
ADC
AD9600
100Ω
50Ω
0.1µF
–1.5
CLK–
–2.0
SCHOTTKY
DIODES:
HSMS2822
–2.5
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
06909-299
0.1µF
06909-024
REFERENCE VOLTAGE ERROR (mV)
2.5
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
secondary transformer or balun limit clock excursions into the
AD9600 to approximately 0.8 V p-p differential.
Figure 56. Transformer-Coupled Differential Clock (up to 200 MHz)
Figure 54. Typical VREF Drift
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9600 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
1nF
0.1µF
CLK+
CLK+
ADC
AD9600
50Ω
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 57. Balun-Coupled Differential Clock (up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers excellent
jitter performance.
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
AVDD
0.1µF
0.1µF
CLK+
CLK+
1.2V
0.1µF
CLK–
100Ω
0.1µF
CLK–
ADC
AD9600
50kΩ
240Ω
06909-025
CLK–
50kΩ
2pF
06909-023
2pF
PECL
DRIVER
240Ω
Figure 58. Differential PECL Sample Clock (up to 150 MSPS)
Figure 55. Equivalent Clock Input Circuit
Clock Input Options
The AD9600 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
Figure 56 and Figure 57 show preferred methods for clocking the
AD9600 (at clock rates of up to 625 MHz). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offer excellent jitter performance.
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
0.1µF
0.1µF
CLK+
CLK+
0.1µF
CLK–
LVDS
DRIVER
100Ω
0.1µF
ADC
AD9600
CLK–
50kΩ
50kΩ
Figure 59. Differential LVDS Sample Clock (up to 150 MSPS)
Rev. B | Page 26 of 72
06909-026
CLK+
06909-057
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
AD9600
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 60). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V and therefore offers
several selections for the drive logic voltage.
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
VCC
1kΩ
CLK+
50Ω
OPTIONAL
100Ω
CMOS
DRIVER
0.1µF
1kΩ
CLK+
ADC
AD9600
Jitter Considerations
CLK–
39kΩ
06909-027
0.1µF
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated as
SNR = −20 log (2πf IN × t J )
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (up to 150 MSPS)
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter. IF undersampling
applications are particularly sensitive to jitter (see Figure 62).
VCC
1kΩ
50Ω
1kΩ
CMOS
DRIVER
OPTIONAL
100Ω
CLK+
0.1µF
0.1µF
ADC
AD9600
CLK–
65
06909-028
0.1µF
CLK+
0.05ps
60
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (up to 150 MSPS)
0.20ps
Input Clock Divider
The AD9600 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD9600 clock divider can be synchronized by using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized either on every SYNC signal
or on only the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows aligning the clock dividers of
multiple devices to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a ±5% tolerance
is required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9600 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling (or falling) edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock
input duty cycles without affecting the performance of the
AD9600. When the SDIO/DCS pin functions as DCS, noise and
distortion performance are nearly flat for a wide range of duty
cycles, as shown in Figure 43.
SNR (dBc)
MEASURED
0.5ps
55
1.0ps
1.50ps
50
2.00ps
45
2.50ps
3.00ps
1
10
100
1000
INPUT FREQUENCY (MHz)
06909-162
0.1µF
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 20 MHz
nominally. The loop has a time constant associated with it that
needs to be considered if the clock rate may change dynamically.
This requires a wait time of 1.5 μs to 5 μs after a dynamic clock
frequency increase or decrease before the DCS loop is relocked
to the input signal. During this time, the loop is not locked, the
DCS loop is bypassed, and the internal device timing is dependent
on the duty cycle of the input clock signal. In such applications,
it may be appropriate to disable the duty clock stabilizer. In all
other applications, enabling the DCS circuit is recommended to
maximize ac performance.
Figure 62. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9600.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
Rev. B | Page 27 of 72
AD9600
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load presented
to the output drivers can minimize digital power consumption.
The data in Figure 63 was taken with the same operating
conditions as the Typical Performance Characteristics, with a
5 pF load on each output driver.
0.5
IAVDD
TOTAL POWER
0.2
0.50
0.25
0.1
IDRVDD
IDVDD
0
0
25
50
75
100
SUPPLY CURRENT (A)
0.3
0.75
125
0
150
ENCODE (MSPS)
Figure 63. AD9600-150 Power and Current vs. Sample Rate
0.5
1.00
0.4
0.3
0.75
TOTAL POWER
0.2
0.50
0.25
0
0
25
50
75
100
0
125
ENCODE (MSPS)
Figure 64. AD9600-125 Power and Current vs. Sample Rate
IDRVDD
IDVDD
0
0
0
25
50
ENCODE (MSPS)
75
100
Figure 65. AD9600-105 Power and Current vs. Sample Rate
By asserting the PDWN mode (either through the SPI port or
by asserting the PDWN pin high), the AD9600 is placed into
power-down mode. In this state, the ADC typically dissipates
2.5 mW. During power-down, the output drivers are placed in a
high impedance state. Asserting the PDWN pin low returns the
AD9600 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI port interface, the user can place the ADC
into power-down or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map
Register Description section for more details.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies and may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
0.1
IDRVDD
IDVDD
0.1
0.25
The AD9600 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic.
06909-039
TOTAL POWER (W)
IAVDD
0.2
DIGITAL OUTPUTS
SUPPLY CURRENT (A)
1.25
TOTAL POWER
0.50
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and must be recharged when returning to
normal operation. As a result, the wake-up time is related to the
time spent in power-down mode: shorter power-down cycles
result in proportionally shorter wake-up times.
06909-038
TOTAL POWER (W)
0.4
0.3
SUPPLY CURRENT (A)
where N is the number of output bits (22 in the case of AD9600
with the fast detect output pins disabled).
TOTAL POWER (W)
I DRVDD = V DRVDD × C LOAD × f CLK × N
1.00
IAVDD
0.75
06909-999
As shown in Figure 63, the power dissipated by the AD9600 is
proportional to its sample rate. In CMOS output mode, the
digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
1.25
0.4
1.00
POWER DISSIPATION AND STANDBY MODE
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when
operating in the external pin mode (see Table 12). As detailed in
the Memory Map Register Description section, the data format
can be selected for offset binary, twos complement, or gray code
when using the SPI control.
Rev. B | Page 28 of 72
AD9600
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
TIMING
Voltage at Pin
AGND
AVDD
The AD9600 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled (default)
Digital Output Enable Function (OEB)
The AD9600 has a flexible three-state ability for the digital
output pins. The three-state mode can be enabled by using the
SMI SDO/OEB pin or the SPI interface. If the SMI SDO/OEB pin
is low, the output data drivers are enabled. If the SMI SDO/OEB pin
is high, the output data drivers are placed into a high impedance
state. This output enable function is not intended for rapid access
to the data bus. Note that OEB is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply voltage.
When the device uses the SPI interface, each channel’s data and
fast detect output pins can be independently three-stated by
using the output enable bar bit in Register 0x14.
The length of the output data lines and the loads placed on them
should be minimized to reduce transients within the AD9600.
These transients can degrade the dynamic performance of the
converter. The lowest typical conversion rate of the AD9600 is
typically 10 MSPS. At clock rates below 10 MSPS, dynamic
performance may degrade.
Data Clock Output (DCO)
The AD9600 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the polarity
has been changed via the SPI. See the timing diagrams shown
in Figure 2 and Figure 3 for more information.
Table 13. Output Data Format
Input (V)
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
Condition (V)
< −VREF − 0.5 LSB
= –VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Binary Output Mode
00 0000 0000
00 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
Rev. B | Page 29 of 72
Twos Complement Mode
10 0000 0000
10 0000 0000
00 0000 0000
01 1111 1111
01 1111 1111
Overrange
1
0
0
0
1
AD9600
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness.
Therefore, it is helpful to have a programmable threshold below
full scale that allows time to reduce the gain before the clip
actually occurs. In addition, because input signals can have
significant slew rates, latency of this function is of major concern.
Highly pipelined converters can have significant latency. A good
compromise is to use the output bits from the first stage of the
ADC for this function. Latency for these output bits is very low,
and overall resolution is not highly significant. Peak input signals
are typically between full scale and 6 dB to 10 dB below full
scale. A 3-bit or 4-bit output provides adequate range and
resolution for this function.
Via the SPI port, the user can provide a threshold above which
an overrange output would be active. As long as the signal is below
that threshold, the output should remain low. The fast detect
output pins can also be programmed via the SPI port so that one of
the pins functions as a traditional overrange pin for customers
who currently use this feature. In this mode, all 12 bits of the
converter are examined in the traditional manner, and the output is
high for the condition normally defined as overflow. In either
mode, the magnitude of the data is considered in the calculation
of the condition (but the sign of the data is not considered). The
threshold detection responds identically to positive and negative
signals outside the desired magnitude range.
FAST DETECT OVERVIEW
The AD9600 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control implementations.
Each ADC has four fast detect output pins that are used to output
information about the current state of the ADC input level. The
function of these pins is programmable via the fast detect mode
select bits and the fast detect enable bit in Register 0x104, allowing
range information to be output from several points in the internal
datapath. These pins can also be set up to indicate the presence of
overrange or underrange conditions, according to programmable
threshold levels. Table 14 shows the six configurations available
for the fast detect pins.
Table 14. Fast Detect Mode Select Bits Settings
Fast Detect
Mode Select Bits
(Register 0x104 [3:1])
000
001
010
011
100
101
Information Presented on
Fast Detect (FD) Pins of Each ADC1, 2
FD [3]
FD [2]
FD [1]
FD [0]
ADC fast magnitude (see Table 15)
OR
ADC fast magnitude
(see Table 16)
ADC fast magnitude
OR
F_LT
(see Table 17)
ADC fast magnitude
C_UT
F_LT
(see Table 17)
OR
C_UT
F_UT
F_LT
OR
F_UT
IG
DG
1
The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode
configuration and FD0+/FD0− to FD9+/FD9− for the LVDS mode
configuration.
2
See the ADC Overrange (OR) and Gain Switching sections for more
information about OR, C_UT, F_UT, F_LT, IG, and DG.
ADC FAST MAGNITUDE
When the fast detect output pins are configured to output the ADC
fast magnitude (that is, when the fast detect mode select bits are
set to 0b000), the information presented is the ADC level from an
early converter stage with only a two-clock-cycle latency (when
in CMOS output mode). Using the fast detect output pins in
this configuration provides the earliest possible level indication
information. Because this information is provided early in the
datapath, there is a significant uncertainty in the level indicated.
The nominal levels, along with the uncertainty indicated by the
ADC fast magnitude, are shown in Table 15.
Table 15. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 000
ADC Fast Magnitude on
FD [3:0] Pins
0000
0001
0010
0011
0100
0101
0110
0111
1000
Rev. B | Page 30 of 72
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to −0.56
−0.56 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to FS
−1.16 to 0
AD9600
When the fast detect mode select bits are set to 0b001, 0b010, or
0b011, a subset of the fast detect output pins is available. In these
modes, the fast detect output pins have a latency of six clock cycles.
Table 16 shows the corresponding ADC input levels when the
fast detect mode select bits are set to 0b001 (that is, when ADC
fast magnitude is presented on the FD [3:1] pins).
Table 16. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 001
ADC Fast Magnitude on
FD [3:1] Pins
000
001
010
011
100
101
110
111
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to 0
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD [3:2]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 17.
Table 17. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 010 or 011
ADC Fast Magnitude on
FD [3:2] Pins
00
01
10
11
Nominal Input
Magnitude
Below FS (dB)
<−14.5
−14.5 to −7
−7 to −3.25
−3.25 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −12.04
−18.07 to −6.02
−8.52 to −2.5
−4.08 to 0
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in the
coarse upper threshold register at Address 0x105 [2:0]. The coarse
upper threshold output is output two clock cycles after the level
is exceeded at the input and therefore provides a fast indication
of the input signal level. The coarse upper threshold levels are
shown in Table 18. This indicator remains asserted for a minimum of two ADC clock cycles or until the signal drops below
the threshold level.
Table 18. Coarse Upper Threshold Levels
Coarse Upper Threshold
(Register 0x105 [2:0])
000
001
010
011
100
101
110
111
C_UT Is Active When Signal
Magnitude Below FS
Is Greater Than (dB)
<−24
−24
−14.5
−10
−7
−5
−3.25
−1.8
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input magnitude exceeds the value programmed in the fine upper threshold
register located at Address 0x106 and Address 0x107. The 13-bit
threshold register is compared with the signal magnitude at the
output of the ADC. This comparison is subject to the ADC clock
latency but is accurate in terms of the converter resolution. The
fine threshold magnitude is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
(1)
Fine Lower Threshold (F_LT)
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and therefore is
subject to the 12-clock-cycle latency. An overrange at the input
would be indicated by this bit 12 clock cycles after it occurred.
GAIN SWITCHING
The AD9600 includes circuitry that is useful in applications
either where large dynamic ranges exist or where gain ranging
converters are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed. Fast detect mode select bit = 010 through fast
detect mode select bit = 101 support various combinations of the
gain switching options.
The fine lower threshold indicator is asserted if the input magnitude is less than the value programmed in the fine lower threshold
register located at Address 0x108 and Address 0x109. The fine
lower threshold register is a 13-bit register that is compared with
the signal magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but provides a comparison
accurate to the converter resolution. The fine threshold magnitude
is defined in Equation 1.
The operation of the F_UT and F_LT indicators is shown in
Figure 66.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Rev. B | Page 31 of 72
AD9600
Increment Gain (IG) and Decrement Gain (DG)
fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine threshold magnitude is defined
in Equation 1 (see the Fine Upper Threshold (F_UT) section).
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external gain
control. The decrement gain indicator works in conjunction with
the coarse upper threshold bits, asserting when the input
magnitude is greater than the 3-bit value in the coarse upper
threshold register (Address 0x105). The increment gain indicator,
similarly, corresponds with the fine lower threshold bits, except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. This dwell time is set by the 16-bit increase
gain dwell time register (Address 0x10A and Address 0x10B) and
is in units of ADC input clock cycles ranging from 1 to 65,535. The
The decrement gain output is influenced by the fast detect output
pins, which provide a fast indication of potential overrange
conditions. Assertion of the increment gain indicator is based
on the comparison at the output of the ADC, requiring the input
magnitude to remain below an accurate, programmable level for a
predefined period before signaling external circuitry to increase
the gain.
The operation of the IG and DG indicators is shown in Figure 66.
UPPER THRESHOLD (COARSE OR FINE)
DWELL TIME
TIMER RESET BY
RISE ABOVE F_LT
FINE LOWER THRESHOLD
DWELL TIME
C_UT OR F_UT*
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
F_LT
DG
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF TWO ADC CLOCK CYCLES.
Figure 66. Threshold Settings for C_UT, F_UT, F_LT, IG, and DG
Rev. B | Page 32 of 72
06909-097
IG
AD9600
SIGNAL MONITOR
The signal monitor result values can be obtained from the part by
reading back Register 0x116 to Register 0x11B, using the SPI port
or the signal monitor SPORT output. The output contents of the
SPI-accessible signal monitor registers are set via the two signal
monitor mode bits of the signal monitor control register
(Address 0x112). Both ADC channels must be configured for
the same signal monitor mode. Separate SPI-accessible, 20-bit
signal monitor result (SMR) registers (Address 0x116 to Address
0x11B) are provided for each ADC channel. Any combination of
the signal monitor functions can also be output to the user via
the serial SPORT interface. These outputs are enabled using the
peak detector output enable, rms magnitude output enable, and
threshold crossing output enable bits in the signal monitor
SPORT control register (Address 0x111).
For each of the signal monitor measurements, a programmable
signal monitor period register (SMPR) controls the duration of
the measurement. This period is programmed as the number of
input clock cycles in the 24-bit signal monitor period register
located at Address 0x113, Address 0x114, and Address 0x115.
This register can be programmed with a period from 128 samples
to 16.78 (224) million samples.
Because the dc offset of the ADC can be significantly larger
than the signal of interest (affecting the results from the signal
monitor), a dc correction circuit is included as part of the signal
monitor block to null the dc offset before measuring the power.
PEAK DETECTOR MODE
The magnitude of the input port signal is monitored over a
programmable period (determined by SMPR) to give the peak
value detected. This function is enabled by programming a
Logic 1 in the signal monitor mode bits of the signal monitor
control register (Address 0x112) or by setting the peak detector
output enable bit in the signal monitor SPORT control register
(Address 0x111). The 24-bit SMPR must be programmed before
activating this mode.
After enabling this mode, the value in the SMPR is loaded into
a monitor period timer and the countdown is started. The magnitude of the input signal is compared with the value in the
internal peak level holding register (not accessible to the user),
and the greater of the two values is updated as the current peak
level. The initial value in the peak level holding register is set to
the current ADC input signal magnitude, and the comparison
continues until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
value in the peak level holding register is transferred to the signal
monitor holding register (not accessible to the user) and can be
read through the SPI port or output through the SPORT serial
interface. The monitor period timer is reloaded with the value in
the SMPR, and the countdown is restarted. In addition, the value in
the peak level holding register is reset to the magnitude of the
first input sample, and the previously explained comparison and
update procedure continues.
Figure 67 is a block diagram of the peak detector logic. The
SMR register contains the absolute magnitude of the peak
detected by the peak detector logic.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
CLEAR
MAGNITUDE
STORAGE
REGISTER*
LOAD
TO
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)*
LOAD
COMPARE
A>B
* THESE ARE INTERNAL REGISTERS. THEY ARE NOT IN THE REGISTER
MAP AND CANNOT BE ACCESSED BY USERS.
06909-044
The signal monitoring block provides additional information about
the signal being digitized by the ADC. The signal monitor computes
the rms input magnitude, the peak magnitude, and/or the number
of samples by which the magnitude exceeds a particular threshold.
Together, these functions can be used to gain insight into the
signal characteristics and to estimate the peak/average ratio or
even the shape of the complementary cumulative distribution
function (CCDF) curve of the input signal. This information
can be used to drive an AGC loop to optimize the range of the
ADC in the presence of real-world signals.
Figure 67. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE
In this mode, the root-mean-square (rms) or mean-square (ms)
magnitude of the input port signal is integrated (by adding an
accumulator) over a programmable period (determined by SMPR)
to give the rms or ms magnitude of the input signal. This mode
is set by programming Logic 0 in the signal monitor mode bits
of the signal monitor control register (Address 0x112) or by setting
the rms magnitude output enable bit in the signal monitor
SPORT control register (Address 0x111). The 24-bit SMPR,
representing the period over which integration is performed,
must be programmed before activating this mode.
After enabling the rms/ms magnitude mode, the value in the SMPR
is loaded into a monitor period timer, and the countdown is started
immediately. Each input sample is converted to floating-point
format and squared. It is then converted to an 11-bit fixed-point
format and added to the contents of the 24-bit accumulator. The
integration continues until the monitor period timer reaches a
count of 1.
When the monitor period timer reaches a count of 1, the square
root of the value in the accumulator is taken and transferred
(after some formatting) to the signal monitor holding register,
which can be read through the SPI port or output through the
SPORT serial port. The monitor period timer is reloaded with
the value in the SMPR, and the countdown is restarted. In addition,
Rev. B | Page 33 of 72
AD9600
the value of the accumulator is reset to the first input sample
signal power, and the accumulation continues with the
subsequent input samples.
cycle. If the input signal has a magnitude greater than the value
set in the fine upper threshold register, the value in the internal
count register (not accessible to the user) is incremented by 1.
Figure 68 illustrates the rms magnitude monitoring logic.
The initial value of the internal count register is set to 0. The
comparison and incrementing of this value continues until the
monitor period timer reaches a count of 1.
SIGNAL MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
LOAD
CLEAR
ACCUMULATOR
TO
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)*
LOAD
06909-092
FROM
INPUT
PORTS
*THIS IS AN INTERNAL REGISTER. IT IS NOT IN THE REGISTER
MAP AND CANNOT BE ACCESSED BY USERS.
Figure 68. ADC Input RMS Magnitude Monitoring Block Diagram
For rms magnitude mode, the value in the signal monitor result
(SMR) register is a 20-bit fixed-point number. The following
equation can be used to determine the rms magnitude in decibels
full scale (dBFS) from the MAG value in the register:
MAG
SMP
RMS Magnitude = 20 log ⎛⎜ 20 ⎞⎟ − 10 log ⎡⎢ ceil [log (SMP )] ⎤⎥
2
⎝ 2
⎠
⎣2
⎦
where if the signal monitor period (SMP) is a power of 2, the
second term in the equation becomes 0.
For ms magnitude mode, the value in the SMR is a 20-bit fixedpoint number. The following equation can be used to determine
the ms magnitude in decibels full scale (dBFS) from the MAG
value in the register:
MAG
SMP
MS Magnitude = 10 log ⎛⎜ 20 ⎞⎟ − 10 log ⎡⎢ ceil [log (SMP )] ⎤⎥
2
⎝ 2
⎠
⎣2
⎦
where if the SMP is a power of 2, the second term in the
equation becomes 0.
THRESHOLD CROSSING MODE
In the threshold crossing mode of operation, the magnitude of
the input port signal is monitored over a programmable period
(determined by SMPR) to count the number of times it crosses a
certain programmable threshold value. This mode is set by
programming Logic 1x (where x is a don’t care bit) in the signal
monitor mode bits of the signal monitor control register
(Address 0x112) or by setting the threshold crossing output
enable bit in the signal monitor SPORT control register
(Address 0x111). Before activating this mode, the user needs to
program the 24-bit signal monitor period register (Address 0x113
to Address 0x115) and the 13-bit fine upper threshold register
(Address 0x106 and Address 0x107) for each individual input
port. The same fine upper threshold register is used for both
signal monitoring and gain control (see the ADC Overrange
and Gain Control section).
After entering this mode, the value in the SMPR is loaded
into a monitor period timer and the countdown is started. The
magnitude of the input signal is compared with the previously
programmed fine upper threshold register on each input clock
When the monitor period timer reaches a count of 1, the value
in the internal count register is transferred to the signal monitor
holding register (not accessible to the user), which can be read
through the SPI port or output through the SPORT serial port.
The monitor period timer is reloaded with the value in the SMPR,
and the countdown is restarted. The internal count register is
also cleared to a value of 0. Figure 69 illustrates the threshold
crossing logic. The value in the SMR register is the number of
samples that have a magnitude greater than the fine upper
threshold register.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
CLEAR
A COMPARE
A>B
FROM
MEMORY
MAP
FINE UPPER
THRESHOLD
REGISTER
COMPARE
A>B
TO
LOAD
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)*
B
*THIS IS AN INTERNAL REGISTER. IT IS NOT IN THE REGISTER
MAP AND CANNOT BE ACCESSED BY USERS.
06909-046
FROM
MEMORY
MAP
Figure 69. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
For additional flexibility in the signal monitoring process, two
control bits are provided in the signal monitor control register
(Address 0x112). They are the signal monitor enable bit and the
complex power calculation mode enable bit.
Signal Monitor Enable Bit
The signal monitor enable bit, located in Bit 0 of Register 0x112,
enables operation of the signal monitor block. If the signal monitor
function is not needed in a particular application, this bit should
be cleared (default) to conserve power.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is digitizing
the I data and Channel B is digitizing the Q data for a complex
input signal (or vice versa). In this mode, the power reported is
equal to
I 2 + Q2
This result is presented in the signal monitor DC value Channel A
register (Address 0x10D and Address 0x10E) if the signal monitor
mode bits are set to 00. The signal monitor DC value Channel B
register (Address 0x10F and Address 0x110) continues to compute
the Channel B value.
Rev. B | Page 34 of 72
AD9600
DC CORRECTION
DC Correction Enable Bits
Because the dc offset of the ADC may be significantly larger
than the signal being measured, a dc correction circuit is included
to null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path, but this
may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
Setting Bit 0 (the dc correction for SM enable bit) of Register 0x10C
enables the dc correction for use in the signal monitor calculations.
Setting Bit 1 (the dc correction for signal path enable bit) of
Register 0x10C enables the calculated dc correction value to
be added to the output data signal path.
DC Correction Bandwidth
The SPORT is a serial interface with three output pins:
SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and
SMI SDO (SPORT data). The SPORT is the master and drives
all three SPORT output pins on the chip.
SIGNAL MONITOR SPORT OUTPUT
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing the 4-bit dc correction
bandwidth register located at Register 0x10C, Bits [5:2].
SMI SCLK
The following equation can be used to compute the bandwidth
value for the dc correction circuit:
DC _ Corr _ BW = 2 − k − 14 ×
The data and frame sync are driven on the positive edge of the
SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4,
or 1/8 the ADC clock rate, based on the SPORT controls. In
addition, by using the SPORT SMI SCLK sleep bit, the SMI SCLK
can be gated to remain low when the signal monitor block is not
sending any data. Using this bit to disable the SMI SCLK when it is
not needed can reduce coupling errors in the return signal path.
Doing so, however, has the disadvantage of spreading the
frequency content of the clock; if desired, the SMI SCLK can be
left enabled to ease frequency planning.
f CLK
2× π
where:
k is the 4-bit value programmed in Register 0x10C, Bits [5:2]
(values between 0 and 13 are valid for k; programming 14 or
15 provides the same result as programming 13).
fCLK is the AD9600 ADC sample rate in hertz.
DC Correction Readback
SMI SDFS
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and Register 0x10F and
Register 0x110 for Channel B. The dc correction value is a 10-bit
value that can span the entire input range of the ADC.
The SMI SDFS is the serial data frame sync. It defines the start
of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
DC Correction Freeze
SMI SDO
Setting the dc correction freeze bit (Bit 6 of Register 0x10C) halts
the dc correction at its current state and continues to use the last
updated value as the dc correction value. Clearing this bit restarts
dc correction and adds the currently calculated value to the data.
The SMI SDO is the serial data output of the block. The data is sent
MSB first on the first positive edge after the SMI SDFS. Each data
output block includes one or more rms magnitude value, peak level
value, and threshold crossing value from each datapath in the stated
order. If enabled, the data is sent, rms first, followed by the peak
value and the threshold crossing value, as shown in Figure 70.
GATED, BASED ON CONTROL
SMI SCLK/PDWN
SMI SDFS
MSB
RMS/MS CH A LSB
20 CYCLES
PK CH A
16 CYCLES
THR CH A
MSB
16 CYCLES
RMS/MS CH B LSB
20 CYCLES
PK CH B
16 CYCLES
THR CH B
RMS/MS CH A
06909-094
SMI SDO/OEB
16 CYCLES
Figure 70. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
GATED, BASED ON CONTROL
SMI SCLK/PDWN
SMI SDFS
MSB
RMS/MS CH A LSB
20 CYCLES
THR CH A
16 CYCLES
MSB
RMS/MS CH B LSB
20 CYCLES
THR CH B
16 CYCLES
Figure 71. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
Rev. B | Page 35 of 72
RMS/MS CH A
06909-095
SMI SDO/OEB
AD9600
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9600 includes built-in test features to enable verification
of the integrity of each channel as well as to facilitate board level
debugging. A BIST feature is included that verifies the integrity
of the digital datapath of the AD9600. Various output test options
are also provided to place predictable values on the outputs of
the AD9600.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9600 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath,
starting at the ADC block output. The BIST sequence runs for
512 cycles and then stops. The BIST signature value for Channel
A or Channel B is placed in Register 0x24 and Register 0x25. If
one channel is chosen, its BIST signature is written to the two
registers. If both channels are chosen, the results of the two
channels are XOR’ed and placed in the BIST signature registers.
The outputs are not disconnected during this test; therefore, the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or started from the beginning, based
on the value programmed in Bit 2 of Register 0x0E. The BIST
signature result varies depending on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 22. When an output
test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks, and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced by setting Bit 4 or Bit 5 of
the test mode register (Address 0x0D) to hold the generator in
reset mode. These tests can be performed with or without an
analog signal (if present, the analog signal is ignored), but they
do require an encode clock. For more information, see AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Rev. B | Page 36 of 72
AD9600
CHANNEL/CHIP SYNCHRONIZATION
The AD9600 has a SYNC input that offers the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful to guarantee synchronized
sample clocks across multiple ADCs. The signal monitor block can
also be synchronized using the SYNC input, allowing properties of
the input signal to be measured during a specific period. The
input clock divider can be enabled to synchronize on a single
occurrence of the sync signal or on every occurrence. The signal
monitor block is synchronized on every SYNC input signal.
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally
synchronized to the input clock signal, meeting the setup and
hold times shown in Table 5. The SYNC input should be driven
using a single-ended CMOS-type signal.
Rev. B | Page 37 of 72
AD9600
SERIAL PORT INTERFACE (SPI)
The AD9600 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. This may provide the user
with additional flexibility and customization, depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational
information, see AN-877 Application Note, Interfacing to High
Speed ADCs via SPI.
CONFIGURATION USING THE SPI
There are three pins that define the SPI: SCLK, SDIO, and CSB
(see Table 19). The SCLK pin is used to synchronize the read
and write data presented from and to the ADC. The SDIO pin is
a dual-purpose pin that allows data to be sent to and read from
the internal ADC memory map registers. The CSB pin is an activelow control that enables or disables the read and write cycles.
SDIO
CSB
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the SDIO pin to change direction
from an input to an output at the appropriate point in the
serial frame.
Data can be sent in MSB-first mode or LSB-first mode. MSB-first
mode is the default on power-up and can be changed via the SPI
port configuration register (Address 0x00). For more information
about this and other features, see AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
Table 19. Serial Port Interface Pins
Pin
SCLK
All data is composed of 8-bit words. The first bit of the first
byte in a multibyte serial data transfer frame indicates whether
a read command or a write command is issued. This allows the
serial data input/output (SDIO) pin to change direction from an
input to an output.
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active-low control that gates the read
and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 72
and Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any secondary functions of the SPI pin.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits. W0 and W1 represent the number of
data bytes to transfer for either a read or a write. The value
represented by W1:W0 + 1 is the number of bytes to transfer.
The pins described in Table 19 constitute the physical interface
between the user programming device and the serial port of the
AD9600. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in AN-812 Application Note, MicrocontrollerBased Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9600 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to AVDD or ground
during device power-on, they are associated with a specific
function. The Theory of Operation section describes the
strappable functions supported on the AD9600.
Rev. B | Page 38 of 72
AD9600
CONFIGURATION WITHOUT THE SPI
SPI ACCESSIBLE FEATURES
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOScompatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Brief descriptions of the general features available on many
Analog Devices, Inc., high speed ADCs, including the AD9600,
that are accessible via the SPI are included in Table 21. These
features are described in detail in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI. The AD9600 part-specific
features are described in the Memory Map Register Description
section.
Table 21. Features Accessible Using the SPI
Feature Name
Modes
Table 20. Mode Selection
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
Pin
SDIO/DCS
SCLK/DFS
SMI SDO/OEB
SMI SCLK/PDWN
AGND (default)
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or
standby
Normal operation
tHIGH
tDS
tS
tDH
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Description
Allows the user to set either the power-down
mode or the standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set the test modes to have
known data on the output bits
Allows the user to set up the outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
tCLK
tH
tLOW
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
06909-049
SDIO DON’T CARE
DON’T CARE
Figure 72. Serial Port Interface Timing Diagram
Rev. B | Page 39 of 72
AD9600
MEMORY MAP
READING THE MEMORY MAP TABLE
Logic Levels
Each row in the memory map registers table (Table 22) has eight
bit locations. The memory map is divided into four sections: the
chip configuration registers (Address 0x00 to Address 0x02), the
channel index and transfer registers (Address 0x05 and Address
0xFF), the ADC functions registers (Address 0x08 to Address
0x25), and the digital feature control registers (Address 0x100 to
Address 0x11B).
An explanation of logic level terminology follows:
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The (MSB) Bit 7 column is the start of the
default hexadecimal value given. For example, Address 0x18, the
VREF select register, has a default value of 0xC0, meaning that
Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the
default reference selection setting. The default value uses a 2.0 V
peak-to-peak reference. For more information on this function and
others, see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This application note details the functions controlled
by Register 0x00 to Register 0xFF. The remaining registers
(from Register 0x100 to Register 0x11B) are documented in
the Memory Map Register Description section.
Open Locations
All address and bit locations that are not included in Table 22
are currently not supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
When the AD9600 comes out of a reset, critical registers are
loaded with default values. The default values for the registers
are given in the memory map registers table (Table 22).
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit (Bit 0 of Register 0xFF) is set. The
internal update takes place when the transfer bit is set, and the
bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be individually programmed for each channel.
In these cases, channel address locations are internally
duplicated for each channel. These registers are designated as
local registers in Table 22 and can be accessed by setting the
appropriate Channel A or Channel B bits in Register 0x05. If
both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are
set during an SPI read cycle, the part returns the value for
Channel A.
On the other hand, registers that are designated as global registers
in Table 22 affect the entire part or the channel features for which
independent settings are not allowed between the channels. The
settings in Register 0x05 do not affect the global registers.
Rev. B | Page 40 of 72
AD9600
MEMORY MAP
All address and bit locations that are not included in Table 22 are currently not supported for this device.
Table 22. Memory Map Registers
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0x00
0
SPI Port
Configuration
(Global)
0x01
Chip ID
(Global)
0x02
Chip Grade
(Global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
8-bit Chip ID [7:0]
(AD9600 = 0x21)
(default)
Open
Default
Notes/
Comments
0x18
The nibbles
are mirrored
so that LSB- or
MSB-first mode
is set correctly,
regardless of
shift mode.
Read only.
0x21
Read
only
Read
only
Speed grade ID
00 = 150 MSPS
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Open
Open
Open
Open
Channel Index and Transfer Registers
0x05
Channel Index
Open
Open
Open
Open
Open
Open
Data
Channel B
(default)
Data
Channel A
(default)
0x03
0xFF
Transfer
Open
Default
Value
(Hex)
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Functions Registers
0x08
Power Modes
Open
Open
Open
Open
Open
Internal power-down
mode (local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
0x00
0x09
Global Clock
(Global)
Open
Open
External
powerdown pin
function
(global)
0 = powerdown
1 = standby
Open
Open
Open
Open
Open
0x01
0x0B
Clock Divide
(Global)
Open
Open
Open
Open
Open
0x0D
Test Mode
(Local)
Open
Open
Reset PN23
gen
Reset
PN9 gen
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN 23 sequence
110 = PN 9 sequence
111 = one/zero word toggle
Open
Rev. B | Page 41 of 72
Duty cycle
stabilizer
(default)
Speed grade
ID used to
differentiate
devices.
Bits are set
to determine
which on-chip
device receives
the next write
command;
applies to local
registers.
Synchronously
transfers data
from the
master shift
register to the
slave.
Determines
various generic
modes of chip
operation.
0x00
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active.
0x00
When this
register is set,
the test data is
placed on the
output pins in
place of normal
data.
AD9600
Addr
(Hex)
0x0E
0x10
0x14
Register
Name
BIST Enable
(Local)
Offset Adjust
(Local)
Output Mode
Bit 7
(MSB)
Open
Bit 6
Open
Open
Open
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS:
1 V to 1.8 V
CMOS or
reduced:
LVDS
(global)
Invert DCO
clock
Output type
0 = CMOS
1 = LVDS
(global)
Open
Output
enable bar
(local)
Open
Open
Open
Open
Open
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Open
Open
Open
0x16
Clock Phase
Control
(Global)
0x17
DCO Output
Delay (Global)
Open
0x18
VREF Select
(Global)
Reference voltage selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
Bit 5
Open
Bit 3
Open
Bit 2
Reset BIST
sequence
Bit 1
Open
Open
Open
Open
Output
invert
(local)
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
0x00
Allows
selection of
clock delays
into the input
clock divider.
0x00
Open
Open
0xC0
BIST signature [15:8]
0x00
Read only.
Open
Open
Open
Open
Open
Open
Open
Clock
Clock
divider
divider
next sync
sync
only
enable
Fast Detect Mode Select [2:0]
Open
Fine Upper Threshold [12:8]
Fine Lower Threshold [7:0]
Fine Lower Threshold [12:8]
Rev. B | Page 42 of 72
Master
sync
enable
Fast detect
enable
Coarse Upper Threshold [2:0]
Fine Upper Threshold [7:0]
Open
Configures the
outputs and
the format of
the data.
Read only.
Open
Open
0x00
0x00
Open
Open
Default
Notes/
Comments
BIST signature [7:0]
Open
Open
Default
Value
(Hex)
0x00
0x00
Offset adjust in LSBs from +31 to −32
(twos complement format)
0x24
BIST Signature
LSB (Local)
0x25
BIST Signature
MSB (Local)
Digital Feature Control Registers
0x100
Sync Control
Signal
monitor
(Global)
sync
enable
0x104 Fast Detect
Open
Control (Local)
0x105 Coarse Upper
Open
Threshold
(Local)
0x106 Fine Upper
Threshold
Register 0
(Local)
0x107 Fine Upper
Open
Threshold
Register 1
(Local)
0x108 Fine Lower
Threshold
Register 0
(Local)
0x109 Fine Lower
Open
Threshold
Register 1
(Local)
Bit 4
Open
Bit 0
(LSB)
BIST enable
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD9600
Addr
(Hex)
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
Register
Name
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain
Dwell Time
Register 1
(Local)
Signal Monitor
DC Correction
Control
(Global)
Signal Monitor
DC Value
Channel A
Register 0
(Global)
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Signal Monitor
DC Value
Channel B
Register 0
(Global)
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Signal Monitor
SPORT Control
(Global)
0x112
Signal Monitor
Control
(Global)
0x113
Signal Monitor
Period
Register 0
(Global)
Signal Monitor
Period
Register 1
(Global)
Signal Monitor
Period
Register 2
(Global)
Signal Monitor
Result
Channel A
Register 0
(Global)
Signal Monitor
Result
Channel A
Register 1
(Global)
0x114
0x115
0x116
0x117
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Increase Gain Dwell Time [7:0]
Bit 1
Bit 0
(LSB)
Increase Gain Dwell Time [15:8]
Open
DC Correction Bandwidth [3:0]
DC
correction
freeze
DC
correction
for signal
path
enable
DC
correction
for signal
monitor
enable
Default
Value
(Hex)
0x00
Default
Notes/
Comments
In ADC clock
cycles.
0x00
In ADC clock
cycles.
0x00
DC Value Channel A [7:0]
Open
Open
Read only.
DC Value Channel A [13:8]
Read only.
DC Value Channel B [7:0]
Open
Open
Open
RMS/MS
magnitude
output
enable
Peak
detector
output
enable
Complex
power
calculation
mode
enable
Open
Open
Read only.
DC Value Channel B [13:8]
Threshold
crossing
output
enable
SPORT SMI
SPORT
SCLK divide
SMI SCLK
sleep
00 = undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
Open
Signal monitor mode
Signal
monitor 00 = rms/ms magnitude
rms/ms
01 = peak power
select
10 = threshold crossing
0 = rms
11 = threshold crossing
1 = ms
Signal Monitor Period [7:0]
Read only
Signal
monitor
SPORT
output
enable
0x04
Signal
monitor
enable
0x00
0x40
In ADC clock
cycles.
Signal Monitor Period [15:8]
0x00
In ADC clock
cycles.
Signal Monitor Period [23:16]
0x00
In ADC clock
cycles.
Signal Monitor Result Channel A [7:0]
Read only.
Signal Monitor Result Channel A [15:8]
Read only.
Rev. B | Page 43 of 72
AD9600
Addr
(Hex)
0x118
0x119
0x11A
0x11B
Register
Name
Signal Monitor
Result
Channel A
Register 2
(Global)
Signal Monitor
Result
Channel B
Register 0
(Global)
Signal Monitor
Result
Channel B
Register 1
(Global)
Signal Monitor
Result
Channel B
Register 2
(Global)
Bit 7
(MSB)
Open
Open
Bit 6
Open
Open
Bit 5
Open
Open
Bit 4
Open
Bit 0
Bit 3
Bit 2
Bit 1
(LSB)
Signal Monitor Value Channel A [19:16]
Default
Value
(Hex)
Default
Notes/
Comments
Read only.
Signal Monitor Result Channel B [7:0]
Read only.
Signal Monitor Result Channel B [15:8]
Read only.
Open
Signal Monitor Result Channel B [19:16]
Read only.
MEMORY MAP REGISTER DESCRIPTION
Bit 0—Fast Detect Enable
For information about functions controlled in Register 0x00 to
Register 0xFF, see Application Note AN-877, Interfacing to High
Speed ADCs via SPI.
Bit 0 is used to enable the fast detect output pins. When the fast
detect output pins are disabled, the outputs go into a high
impedance state. In LVDS mode, when the fast detect output
pins are interleaved, the outputs go high-Z only if both channels
are turned off (power-down/standby/output disabled). If only one
channel is turned off (power-down/standby/output disabled), the
fast detect output pins repeat the data of the active channel.
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external sync input to the
signal monitor block. The sync signal is passed when both Bit 7
and Bit 0 are high. This is continuous sync mode.
Bits [6:3]—Reserved
Coarse Upper Threshold (Register 0x105)
Bits [7:3]—Reserved
Bits [2:0]—Coarse Upper Threshold
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100 [0]) is high and the
clock divider sync enable bit (Address 0x100 [1]) is high, the
clock divider next sync only bit (Address 0x100 [2]) allows the
clock divider to sync to the first sync pulse it receives and ignore
the rest. The clock divider sync enable bit (Address 0x100 [1])
resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
passed when both Bit 1 and Bit 0 are high. This is continuous
sync mode.
Bit 0—Master Sync Enable
These bits set the level required to assert the coarse upper
threshold indication (see Table 18).
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0]
Register 0x107, Bits [7:5]—Reserved
Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8]
These registers provide the fine upper limit threshold. This 13-bit
value is compared with the 10-bit magnitude from the ADC
block. If the ADC magnitude exceeds this threshold value, the
F_UT indicator is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0]
Register 0x109, Bits [7:5]—Reserved
Register 0x109, Bits [4:0]—Fine Lower Threshold [12:8]
Bit 0 must be high to enable the sync functions.
Fast Detect Control (Register 0x104)
Bits [7:4]—Reserved
Bits [3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output pins according
to Table 14.
These registers provide a fine lower limit threshold. This 13-bit
value is compared with the 10-bit magnitude from the ADC
block. If the ADC magnitude is less than this threshold value,
the F_LT indicator is set.
Rev. B | Page 44 of 72
AD9600
Increase Gain Dwell Time (Register 0x10A and
Register 0x10B)
Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0]
Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8]
These registers are programmed with the dwell time in ADC
clock cycles. The signal must be below the fine lower threshold
value before the increase gain (IG) indicator is asserted.
Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved
Bit 6—DC Correction Freeze
When Bit 6 is set high, the dc correction is not updated to the
signal monitor block; therefore, the block continues to hold the last
dc value that it calculated.
Bits [5:2]—DC Correction Bandwidth
These bits set the averaging time of the power monitor dc
correction function. This 4-bit word sets the bandwidth of the
correction block according to the following equation:
DC _ Corr _ BW = 2 −k − 14
f
× CLK
2× π
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved
Bit 6—RMS/MS Magnitude Output Enable
These bits enable the 20-bit rms or ms magnitude measurement
as output on the SPORT.
Bit 5—Peak Detector Output Enable
Bit 5 enables the 10-bit peak measurement as output on the SPORT.
Bit 4—Threshold Crossing Output Enable
Bit 4 enables the 10-bit threshold measurement as output on
the SPORT.
Bits [3:2]—SPORT SMI SCLK Divide
The values of these bits set the SPORT SMI SCLK divide ratio
from the input clock. A value of 0x01 sets divide by 2 (default),
a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.
Bit 1— SPORT SMI SCLK Sleep
Setting Bit 1 high causes the SMI SCLK to remain low when the
signal monitor block has no data to transfer.
Bit 0—Signal Monitor SPORT Output Enable
where:
k is the 4-bit value programmed in Register 0x10C, Bits [5:2]
(values between 0 and 13 are valid for k; programming 14 or
15 provides the same result as programming 13).
fCLK is the AD9600 ADC sample rate in hertz.
When set, Bit 0 enables the SPORT output of the signal monitor
to begin shifting out the result data from the signal monitor block.
Bit 1—DC Correction for Signal Path Enable
This mode assumes that I data is present on one channel and
Q data is present on the opposite channel. The result reported
is the complex power, measured as
Setting Bit 1 high causes the output of the dc measurement block to
be summed with the data in the signal path to remove the dc offset
from the signal path.
Bit 0—DC Correction for Signal Monitor Enable
Bit 0 enables the dc correction function in the signal monitor block.
The dc correction is an averaging function that can be used by
the signal monitor to remove dc offset in the signal. Removing
this dc from the measurement allows a more accurate reading.
Signal Monitor DC Value Channel A (Register 0x10D and
Register 0x10E)
Register 0x10D, Bits [7:0]—DC Value Channel A [7:0]
Register 0x10E, Bits [7:6]—Reserved
Register 0x10E, Bits [5:0]—DC Value Channel A [13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel A.
Signal Monitor DC Value Channel B (Register 0x10F and
Register 0x110)
Register 0x10F Bits [7:0]—DC Value Channel B [7:0]
Signal Monitor Control (Register 0x112)
Bit 7—Complex Power Calculation Mode Enable
I 2 + Q2
Bits [6:4]—Reserved
Bit 3—Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting
Bit 3 high selects ms power measurement mode.
Bits [2:1]—Signal Monitor Mode
Bit 2 and Bit 1 set the mode of the signal monitor for the data
output of Register 0x116 to Register 0x11B. Setting Bit 2 and Bit 1
to 00 selects rms/ms magnitude output, setting these bits to 01
selects peak power output, and setting to 10 or 11 selects threshold
crossing output.
Bit 0—Signal Monitor Enable
Setting Bit 0 high enables the signal monitor block.
Register 0x110 Bits [7:6]—Reserved
Register 0x110 Bits [5:0]—DC Value Channel B [13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel B.
Rev. B | Page 45 of 72
AD9600
Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x113, Bits [7:0]—Signal Monitor Period [7:0]
Register 0x114, Bits [7:0]—Signal Monitor Period [15:8]
Register 0x115, Bits [7:0]—Signal Monitor Period [23:16]
This 24-bit value sets the number of clock cycles over which
the signal monitor performs its operation. Although this
register defaults to 64 (0x40), the minimum value for this
register is 128 (0x80) cycles—writing values less than 128
can cause inaccurate results.
Signal Monitor Result Channel B (Register 0x119 to
Register 0x11B)
Register 0x119, Bits [7:0]— Signal Monitor Result
Channel B [7:0]
Register 0x11A, Bits [7:0]—Signal Monitor Result
Channel B [15:8]
Register 0x11B, Bits [7:4]—Reserved
Register 0x11B, Bits [3:0]—Signal Monitor Result
Channel B [19:16]
Signal Monitor Result Channel A (Register 0x116 to
Register 0x118)
Register 0x116, Bits [7:0]—Signal Monitor Result
Channel A [7:0]
This 20-bit value contains the result calculated by the signal
monitoring block for Channel B. The content is dependent on
the settings in Bits [2:1] of Register 0x112.
Register 0x117, Bits [7:0]—Signal Monitor Result
Channel A [15:8]
Register 0x118, Bits [7:4]—Reserved
Register 0x118, Bits [3:0]—Signal Monitor Result
Channel A [19:16]
This 20-bit value contains the result calculated by the signal
monitoring block for Channel A. The content is dependent on the
settings in Bits [2:1] of Register 0x112.
Rev. B | Page 46 of 72
AD9600
APPLICATIONS INFORMATION
DESIGN GUIDELINES
When designing the AD9600 into a system, the designer
should, before starting design and layout, become familiar with
these guidelines, which discuss the special circuit connections
and layout requirements for certain pins.
Power and Ground Recommendations
When connecting power to the AD9600, the designer should use
two separate 1.8 V supplies: one supply should be used for AVDD
and DVDD and a separate supply for DRVDD. The AVDD and
DVDD supplies, although derived from the same source, should be
isolated with a ferrite bead or filter choke and have separate
decoupling capacitors. The user can employ several different
decoupling capacitors to cover both high and low frequencies.
These should be located close to the point of entry at the PC
board level and close to the part’s pins with minimal trace
length.
A single PC board ground plane should be sufficient when
using the AD9600. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
To achieve the best electrical and thermal performance of the
AD9600, the exposed paddle on the underside of the ADC must
be connected to analog ground (AGND). A continuously exposed
(no solder mask) copper plane on the PCB should mate to the
exposed paddle, Pin 0, of the AD9600. In addition, the copper
plane should have several vias to achieve the lowest possible
resistive thermal path for heat dissipation to flow through the
bottom of the PCB, and these vias should be filled or plugged
with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the ADC and PCB during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and PCB. See the evaluation board
layout figures (Figure 84 to Figure 91) for an example of a PCB
layout. For detailed information on packaging and the PCB layout
of chip scale packages, see the AN-772 Application Note, A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 47.
RBIAS
The AD9600 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This register sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a
low-ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic lowESR capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade the converter’s
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9600 in order to keep these signals from transitioning at the
converter inputs during critical sampling periods.
Rev. B | Page 47 of 72
AD9600
EVALUATION BOARD
The AD9600 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially using the
double-balun configuration (default) or an AD8352 differential
driver. The ADC can also be driven in a single-ended fashion.
Separate power pins are provided to isolate the DUT from the
AD8352 drive circuitry. Each input configuration can be selected
by properly connecting various components (see Figure 74 to
Figure 83). Figure 73 shows the typical bench characterization
setup used to evaluate the ac performance of the AD9600.
The evaluation board can be operated using external supplies
by removing L1, L3, L4, and L13 to disconnect the voltage
regulators supplied from the switching power supply. This
enables the user to individually bias each section of the board.
Use P3 and P4 to connect a different supply for each section.
At least one 1.8 V supply is needed with a 1 A current capability
for AVDD and DVDD; a separate 1.8 V to 3.3 V supply is
recommended for DRVDD. To operate the evaluation board
using the AD8352 driver, a separate 5.0 V supply (AMP VDD)
with a 1 A current capability is needed. To operate the evaluation
board using the alternative SPI options, a separate 3.3 V analog
supply (VS) is needed in addition to the other supplies. The
3.3 V supply (VS) should also have a 1 A current capability.
Using Solder Jumper SJ35 allows the user to separate AVDD
and DVDD if desired.
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
INPUT SIGNALS
See Figure 74 to Figure 91 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
When connecting the clock and analog sources to the evaluation
board, use clean signal generators with low phase noise, such as
Rohde & Schwarz SMA100A or Agilent HP8644 signal generators
or the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial
cable. Enter the desired frequency and amplitude for the ADC.
The AD9600 evaluation board from Analog Devices can accept
a ~2.8 V p-p or a 13 dBm sine wave input for the clock. When
connecting the analog input source, it is recommended to use a
multipole, narrow-band, band-pass filter with 50 Ω terminations.
Good choices of such band-pass filters are available from TTE,
Allen Avionics, and K&L Microwave, Inc. Connect the filter
directly to the evaluation board, if possible.
POWER SUPPLIES
The evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The output of the supply is a 2.1 mm inner diameter
circular jack that connects to the PCB at J16. Once on the PC
board, the 6 V supply is fused and conditioned before connecting
to six low dropout linear regulators that supply the proper bias
to each of the various sections of the board.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog
Devices standard ADC data capture board (HSC-ADCEVALCZ). For more information on the ADC data capture
boards and their optional settings, visit www.analog.com/FIFO.
WALL OUTLET
100V AC TO 240V AC
47Hz TO 63Hz
–
+
GND
VCP
AD9600
EVALUATION BOARD
10-BIT
PARALLEL
CMOS
10-BIT
PARALLEL
CMOS
CLK
SPI
Figure 73. Evaluation Board Connection
Rev. B | Page 48 of 72
HSC-ADC-EVALCZ
FPGA BASED
DATA
CAPTURE BOARD
USB
CONNECTION
SPI
PC RUNNING
VISUAL ANALOG
AND SPI
CONTROLLER
SOFTWARE
06909-300
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
+
VS
AINB
3.3V
–
GND
BAND-PASS
FILTER
3.3V
+
DRVDD IN
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
3.3V
–
GND
AINA
–
GND
BAND-PASS
FILTER
+
AMP VDD
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
1.8V
+
–
GND
5.0V
SWITCHING
POWER
SUPPLY
AVDD IN
6V DC
2A MAX
AD9600
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings, or
modes, allowed on the AD9600 evaluation board.
POWER
Connect the switching power supply that is provided with the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double-balun configuration analog input with an optimum 50 Ω impedance matching
from 70 MHz to 200 MHz. For more bandwidth response, the
differential capacitor across the analog inputs can be changed or
removed (see Table 10). The common mode of the analog inputs is
developed from the center tap of the transformer via the CML
pin of the ADC (see the Analog Input Considerations section).
VREF
VREF is set to 1.0 V by tying the SENSE pin to ground and
adding a jumper on Header J5 (Pin 1 to Pin 2). This causes the
ADC to operate in the 2.0 V p-p full-scale range. To place the
ADC in the 1.0 V p-p mode (VREF = 0.5 V), a jumper should
be placed on Header J4. A separate external reference option is
also included on the evaluation board. To use an external reference,
connect Pin 1 of J6 to Pin 2 of J6 and provide an external
reference at TP5. Proper use of the VREF options is detailed in
the Voltage Reference section.
RBIAS
RBIAS requires that a 10 kΩ resistor (R503) be connected to
ground. This pin is used to set the ADC core bias current.
CLOCK
The default clock input circuitry is derived from a simple baluncoupled circuit using a high bandwidth 1:1 impedance ratio balun
(T5) that adds a very low amount of jitter to the clock path. The
clock input is 50 Ω terminated and ac-coupled to handle singleended sine wave inputs. The transformer converts the single-ended
input to a differential signal that is clipped before entering the
ADC clock inputs. When the AD9600 input clock divider is used,
clock frequencies up to 625 MHz can be input into the evaluation
board through Connector S5.
CSB
The CSB pin is internally pulled up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect Pin 1 of J21 to Pin 2 of J21.
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets
the data format of the outputs. If the pin is left floating, the pin
is internally pulled down, setting the default data format
condition to offset binary. Connecting Pin 1 of J2 to Pin 2 of J2
sets the format to twos complement. If the SPI port is in serial pin
mode, connecting Pin 2 of J2 to Pin 3 of J2 connects the SCLK
pin to the on-board SPI circuitry (see the Serial Port Interface
(SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect Pin 1 of J1 to Pin 2 of J1. If the SPI
port is in serial pin mode, connecting Pin 2 of J1 to Pin 3 of J1
connects the SDIO pin to the on-board SPI circuitry (see the
Serial Port Interface (SPI) section).
ALTERNATIVE CLOCK CONFIGURATIONS
Two clocking options are provided on the AD9600 evaluation
board. The first option is to use the on-board crystal oscillator
(Y1) to provide the clock input to the part. To enable this
crystal, Resistors R8 (0 Ω) and R85 (10 kΩ) should be installed
and Resistors R82 and R30 should be removed.
The second option is to use a differential LVPECL clock to
drive the ADC input using the AD9516-4 (U2). When using
this option, the AD9516-4 charge-pump filter components need
to be populated (see Figure 78). Consult the AD9516-4 data
sheet for more information.
To configure the clock input (from S5) to drive the AD9516
reference input instead of directly driving the ADC, the
following components need to be added, removed, and/or
changed.
1.
2.
PDWN
To enable the power-down feature, connect J7, shorting the
PDWN pin to AVDD.
Remove R32, R33, R99, and R101 in the default clock path.
Populate C78 and C79 with 0.001 μF capacitors and R78
and R79 with 0 Ω resistors in the clock path.
Additionally, unused AD9516 outputs (one LVDS and one
LVPECL) are routed to optional Connectors S8 through S11 on
the evaluation board.
Rev. B | Page 49 of 72
AD9600
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
1.
Remove C1, C17, C18, and C117 in the default analog
input path.
This section provides a brief description of the alternative analog
input drive configuration using the AD8352. When using this
drive option, some additional components need to be populated.
For more details on the AD8352 differential driver, including
how it works and its optional pin settings, consult the AD8352
data sheet.
2.
Populate C8 and C9 with 0.1 μF capacitors in the analog
input path. To drive the AD8352 in the differential input
mode populate Transformer T10; Resistors R1, R37, R39,
R126, and R127; and Capacitors C10, C11, and C125.
3.
Populate the optional amplifier output path with the
desired components, including an optional low-pass filter.
Install 0 Ω Resistors R44 and R48. Resistors R43 and R47
should be increased (typically to 100 Ω) to increase the
output impedance seen by the AD8352 to 200 Ω.
To configure the analog input to drive the AD8352 instead of
the default transformer option, the following components need
to be added, removed, and/or changed for Channel A. In addition,
the corresponding components for Channel B should be changed.
Rev. B | Page 50 of 72
AIN+
AIN-
S1
2
S2
1
2
1
INA+
R1
57.6OHM
R28
R121
0 OHM
RES0402
R120
0 OHM
0.1U
C9
0.1U
C117
0.1U
C1
0 OHM
R2
INA+
0.1U
C47
INA-
4
5
T10
R54
3
0.1U
C11
0.1U
C10
4.12 K
DNP
C125
.3PF
5
4
5
4
ETC1-1-1 3
P
T1
1ADT1_1W T6
2
3
T7
0 OHM
R110
S
1
2
3
CML
1
2
3
ETC1-1-1 3
S
T2
P
5
4
0.1U
C18
0.1U
C17
DEFAULT AMPLIFIER INPUT PATH
0 OHM
P
1
S 2
ETC1-1-13
0 OHM
F
0.1U
R29
R35
R31
24.9OHM
24.9OHM
C8
R126
INA-
F
100OHM
0 OHM
R48
0 OHM
R44
0 OHM
R39
DNP
R38
0 OHM
R37
R127
CML
0 OHM
R42
VIN
RDN
RGN
RGP
RDP
5
16
VIP
AMP+A
AMP-A
4
3
2
1
R40
6
ENB
15
A B
W1
10KOHM
7
GND
Z1
C3
0.1U
9
10
11
12
C22
0.1U
GND
VON
VCC
8
GND
VOP
VCC
13
AD8352
VCM
14
AMPVDD
R41
R5
OPTIONAL AMPLIFIER INPUT PATH
57.6OHM
Figure 74. Evaluation Board Schematic, Channel A Analog Inputs
R4
R43
R47
10KOHM
57.6OHM
R36
F
0 OHM
33OHM
33OHM
Rev. B | Page 51 of 72
33OHM
R27
33OHM
R26
C23
0.1U
C27
10U
0.001U
C16
0.001U
C12
AMPVDD
C2
0.1U
C5
4.7PF
L15 1
IND0603
L14 1
IND0603
120NH
DNP
120NH
DNP
2
2
0 OHM
R49
180NH
DNP
R50
0 OHM
VIN+A
TP15
1
L16
180NH
DNP
VIN-A
TP14
1
L17 1
IND0603
C4
18PF
DNP
1
IND0603
2
2
AVDD
AVDD
AMP+A
C139
12PF
DNP
AMP-A
06909-301
AMPVDD
AD9600
SCHEMATICS
AIN+
AIN-
S4
S3
1
1
57.6OHM
R52
57.6OHM
R51
RES0402
0 OHM
R123
RES0402
0 OHM
R122
INB-
0.1U
C31
INB+
0.1U
C6
0.1U
C28
0 OHM
R67
INB-
4
5
R66
S
F
3
2
1
DNP
0.1U
0.1U
C39
.3PF
C128
0.1U
4
5
T8
P
T3
4
5
6
S
ETC1-1-13
3
2
1
ADT1_1W
T
0 OHM
R111
3
2
1
CML
4
5
P
T4
S
ETC1-1-13
3
2
1
R132
DNP
R133
0 OHM
R6
0 OHM
DEFAULT AMPLIFIER INPUT PATH
0 OHM
R55
T11
C51
P
ETC1-1-1
3
0 OHM
R134
R135
0.1U
R128
INB+
24.9OHM
24.9OHM
C38
R129
C30
F
2
R68
F
Figure 75. Evaluation Board Schematic, Channel B Analog Inputs
2
0.1U
C82
0.1U
C7
100OHM
4
3
2
1
VIN
RDN
RGN
RGP
RDP
5
16
VIP
R94
Z2
7
AMP+B
0 OHM
R96
AMP-B
GND
VON
VCC
8
GND
R53
VOP
VCC
13
AMPVDD
AD8352
VCM
14
GND
0 OHM
R95
CML
0 OHM
6
ENB
15
A B
10KOHM
W2
C60
0.1U
9
10
11
12
R70
R71
4.12 K
R69
10KOHM
33OHM
33OHM
Rev. B | Page 52 of 72
0 OHM
C61
0.1U
C24
0.1U
C62
10U
C83
0.1U
R72
OPTIONAL AMPLIFIER INPUT PATH
AMPVDD
0.001U
C140
0.001U
C46
57.6OHM
R131
33OHM
R74
33OHM
R73
L19 1
IND0603
L18 1
IND0603
120NH
DNP
120NH
DNP
2
2
C84
4.7PF
L21 1
IND0603
C19
18PF
DNP
L20 1
IND0603
180NH
DNP
180NH
DNP
2
2
R81
0 OHM
R80
0 OHM
TP17
1
TP16
1
AMP-B
C29
12PF
DNP
AMP+B
VIN+B
VIN-B
AVDD
AVDD
06909-302
AMPVDD
AD9600
S6
SMA200U P
ENC\
ENC
S5
1
1
R30
R7
R8
57.6OHM
57.6OHM
0 OHM
10KOHM
10KOHM
R85
R82
0 OHM
R3
0 OHM
R90
Figure 76. Evaluation Board Schematic, DUT Clock Input
0.001U
C77
0.001U
C94
0.001U
C63
0.001U
4
5
0.1U
OPT_CLK-
3
S 2
T5
ETC1-1-13
P
1
6 T9
5
4
ADT1_1W
T
1
2
3
C56
OPT_CLK+
0.1U
0.001U
C79
0 OHM
R33
0 OHM
R32
0.001U
C78
OPT_CLK-
ALTCLK-
OPT_CLK+
ALTCLK+
R78
0 OHM
R79
0 OHM
R101
0 OHM
R99
0 OHM
R83
0.1U
C21
24.9OHM
R84
0.1U
C20
24.9OHM
C145
1
C64
F
SMA200U P
2
2
Rev. B | Page 53 of 72
2
VS
CLK-
CLK+
AD9600
06909-303
TP2
DNP
R34
1
S7
1
AD9516
CLK IN
TEST
C104
0.1U
VS_OUT_D
R
VCXO_CLK-
RES0402
0 OHM
R125
RES0402
R89
C100
0.1U
0 OHM
R124
VCXO_CLK+
LD
0 OHM
R10
49.9OHM
C101
0.1U
C98
0.1U
0.1U
C143
0.1U
C142
C80
18PF
C99
0.1U
VS
SCLK
VCP
BYPASS_LDO
9
LF
BYPASS_LDO
CLK
C96
0.1U
SCLK
16
NC1
15
CLKB
14
13
C97
0.1U
VS_CLK_DIST
12
VS_VCO
11
10
LF
SYNCB
REF_SEL
7
STATUS
6
8
STATUS
CP
VCP
5
4
LD
REFMON
2
3
SYNCB
CP
VCP
REFMON
VS_PLL_1
1
REF_SEL
TP18
TEST
1
TP19
TEST
1
VS
OPT_CLK
+
R12
AGND
U2
AD9516_64LFCSP
RSET_CLOCK58
4.12 K
VS
OUT056
OUT4
25
TP20
2
OUT0B55
OUT4B
26
VS_OUT01_DRV54
VS_OUT45_DRV
27
R11
REFINB63
18
NC2
VS_OUT_DR
OUT153
OUT5
28
VS
OUT1B52
OUT5B
29
OPT_CLK
-
REFIN64
CSB
17
CSB_2
CP_RSET62
5.1 K
NC3
19
VS_PLL_261
NC4
20
VS_PRESCALER60
SDO
21
SDO
GND_REF59
22
SDIO
SDI
RESETB
23
RESETB
VS_OUT67_250
VS_OUT45_DIV
30
VS_OUT01_DIV51
VS_OUT89_1
VS_REF57
PDB
24
PDB
Figure 77. Evaluation Board Schematic, Optional AD9516 Clock Circuit
VS_OUT_DR
VS_OUT67_149
VS_OUT89_2
Rev. B | Page 54 of 72
31
VS
38
37
36
35
34
33
GND_OUT89_DIV
OUT9B
OUT9
OUT8B
OUT8
VS
39
OUT3B
R88
200
AGND
VS
R92
200
R91
200
40
OUT3
VS_OUT23_DIV
41
R86
200
ALTCLK+
42
OUT2B
VS_OUT23_DRV
VS_OUT_DR
ALTCLK-
43
LVPECL
TO ADC
1TP8
0.001U
C141
44
AGND
R9
OUT2
45
46
47
48
100OHM
GND_ESD
OUT7B
OUT7
OUT6B
OUT6
OUT6N
SYNC
0.1U
C86
0.1U
C85
0.1U
C87
0.1U
C88
1
1
1
1
S8
S9
S10
S11
2
32
2
PAD
2
LVPECL
OUTPUT
LVDS
OUTPUT
06909-304
OUT6P
AD9600
2
100OHM
R75
CP
Figure 78. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input
Rev. B | Page 55 of 72
BYPASS_LDO
VAL
R136
SYNC
S12
SMA200U P
2
R98
VAL
C90
SEL
RES060 3
57.6OHM
R45
C89
SEL
R93
VAL
VAL
R137
C25
SEL
C91
C144
SEL
0.1U
Charge Pump Filter
1
VAL
R97
3
2
A2
NL27WZ04
C92
SEL
GND
U3
4
5
6
RES0402
0 OHM
R117
RES0402
0 OHM
R116
Y2
VCC
Y1
R46
LF
RES0402
TP1
1
R104
R87
OSCVECTRON_VS50 0
RES0402
0 OHM
U25
4
OUT2
3
GND
6
VCC
5
OUT1
24.9OHM
2
OUT_DISABLE
VS-500
1
FREQ_CTRL_V
33OHM
SYNC
R106
R108
A1
10KOHM
10KOHM
1
RES0402
RES040 2
LD
R107
R109
VS
10KOHM
10KOHM
C26
0.1U
RES0402
RES040 2
R76
200
R100
RES0402
0 OHM
0 OHM
R139
R114
RES0402
VCP
VCP
VS
R102
VCXO_CLK-
VCXO_CLK+
REF_SE L
VS
PD B
VS
SYNC B
VS
RESET B
06909-305
VS
AD9600
AC
RES040 2
10KOHM
R105
RES040 2
10KOHM
R103
RES040 2
10KOHM
RES040 2
10KOHM
Rev. B | Page 56 of 72
1
Figure 79. Evaluation Board Schematic, DUT
NC
D5A
NC
DVDD
FD3B
FD2B
FD1B
D9A(MSB)
FD0B
FD0A
SYNC
FD1A
SPI_CSB
FD2A
CLK-
FD3A
CLK+
57
52
51
50
49
C137
0.001U
D4A
C121
0.1U
C120
0.1U
NC
U1
SPI_SCLK/DFS
SPI_SDIO/DCS
DRVDD
C109
0.1U
C40
0.1U
48
47
AVDD3
AVDD2
VIN+B
VIN-B
RBIAS
CML
NC
C122
0.001U
C126
0.001U
SPI_SCLK
SPI_SDIO
46
45
44
43
42
41
0.001U
DRGND
C127
0.001U
R64
AVDD
AVDD
VIN+B
VIN-B
CML
C36
0.1U
C35
DRVDD
D0B(LSB)
DCOB
DCOA
NC
NC
NC
NC
17
(LSB)
D0A
63
62
61
60
58
59
56
55
54
53
R57
22ohm
9
10
11
12
13
14
15
16
RPAK8
DRVDD
8
7
6
5
4
3
2
1
1
D2B
4
5
6
7
8
9
DRVDD
10
11
12
13
14
15
16
D3B
D4B
D5B
D6B
D7B
D8B
D9B(MSB)
18
64
AVDD
TP6
R63RES0402
0 OHM
10KOHM
0.1U
TP3
D3A
DVDD
AVDD
RES0402
C32
D8A
AD9600
D7A
SENSE
VREF
VIN-A
D6A
40
39
38
1
DVDD
TP5
VIN-A
R112
VIN+A
32
AVDD
31
36
30
37
29
C14
0.1U
AVDD
28
VIN+A
27
35
26
SMI_SDFS
RES0402
0 OHM
25
PWR_SDFS
SMI_SCLK/PDWN
R62
24
34
33
RES040 2
SMI_SDO/OEB
0 OHM
R115
23
1
C15
1U
J4 - INSTALLFOR 0.5V VREF/IV INPUTSPAN
J5 - INSTALLFORIV VREF/2VINPUTSPAN
J6 - INSTALLFOR EXTERNALREFERENCEMODE
J7 - INSTALLFOR PDWN
J8 - INSTALLFOROUTPUTDISABLE
RES0402
RPAK8
R113
22ohm
PWR_SCL
K
PWR_SDO
FD3A
FD2A
FD1A
FD0A
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
0 OHM
21
D1B
CLK+
22
DRGND
CLK-
D2A
SPI_CSB
DVDD
20
2
SYNC
D1A
3
DVDD
19
5
6
7
8
RPAK4
22ohm
SPARE2
SPARE1
FD3B
FD2B
FD1B
FD0B
R58
C34
R59
RPAK8
22ohm
4
3
2
1
0.001U
9
10
11
12
13
14
15
16
R60
RPAK8
22ohm
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
0.1U
R61
RPAK8
22ohm
C33
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
D1B
D0B
SPARE4
SPARE3
1
1
1
1
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D9B
D8B
D7B
D6B
D5B
D4B
D3B
D2B
D3A
D2A
SPARE8
SPARE7
SPARE6
SPARE5
DCOA
DCOB
06909-306
DRVDD
AD9600
D3A
D2A
Figure 80. Evaluation Board Schematic, Digital Output Interface
FD1B
FD0B
V_DIG
SPARE2
SPARE1
FD3B
FD2B
D1B
D0B
V_DIG
SPARE4
SPARE3
D3B
D2B
D5B
D4B
D9B
D8B
V_DIG
D7B
D6B
SPARE6
SPARE5
DCOA
DCOB
D1A
D0A
V_DIG
SPARE8
SPARE7
D5A
D4A
D9A
D8A
V_DIG
D7A
D6A
FD3A
FD2A
FD1A
FD0A
V_DIG
PWR_SDO
PWR_SDFS
PWR_SCLK
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
74VCX162244MTD
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
U17
74VCX162244MTD
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
U16
74VCX162244MTD
V_DIG
V_DIG
V_DIG
V_DIG
SDO_OUT
SDFS_OUT
SCLK_OUT
OUT6P
OUT6N
J11
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
CSB
TYCO_HM-ZD
CHANNELB
B1
C10
D10
C9
D9
A9
B9
C8
D8
A8
B8
C7
D7
A7
B7
C6
D6
A6
B6
A10
B10
C5
D5
A5
B5
C4
D4
A4
B4
C3
D3
A3
B3
C2
D2
A2
B2
C1
D1
A1
CSB_2
SCLK
TYCO_HM-ZD
J10
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
R140
RES0402
0 OHM
R145
RES0402
0 OHM
R144
VS
0 OHM
SCLK_OUT
OUT6N
TP22
TEST
1
TP23 TEST
1
TP24 TEST
1
OUT6P
SYNC
SDI
RES0402
0 OHM
R143
SDO_OUT
SDFS_OU
T
RES0402
0 OHM
R142
RES0402
0 OHM
R119
R141
RES0402
SDO
RESETB
TP21
TEST
1
VS
R118
CHANNELA
B1
C10
D10
C9
D9
A9
B9
C8
D8
A8
B8
C7
D7
A7
B7
C6
D6
A6
B6
A10
B10
C5
D5
A5
B5
C4
D4
A4
B4
C3
D3
A3
B3
C2
D2
A2
B2
C1
D1
A1
A1
D1
C1
B2
A2
D2
C2
B3
A3
D3
C3
B4
A4
D4
C4
B5
A5
D5
C5
B10
A10
B6
A6
D6
C6
B7
A7
D7
C7
B8
A8
D8
C8
B9
A9
D9
C9
D10
C10
B1
J12
DG10
DG9
DG8
DG7
DG6
DG5
DG4
DG3
DG2
DG1
BG10
BG9
BG8
BG7
BG6
BG5
BG4
BG3
BG2
BG1
TYCO_HM-ZD
V_DIG
V_DIG
C65
0.1U
C66
0.1U
C72
0.1U
C67
0.1U
C73
0.1U
C68
0.1U
C74
0.1U
C69
0.1U
C75
0.1U
C70
0.1U
C76
0.1U
C71
0.1U
06909-307
DIGITAL/HSC-ADC-EVALCZ INTERFACE
10KOHM
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RES040 2
U15
R130
VAL
R77
Rev. B | Page 57 of 72
100OHM
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AD9600
RES040 2
10KOHM
Rev. B | Page 58 of 72
CSB
SDO
SDI
SCLK
CSB_2
V_DIG
CSB
SCLK
10KOHM
RES0402
C13
0.1U
R24
A2
GND
A1
3
2
1
RES0402
A2
Y1
Y2
VCC
Y1
U8
NC7WZ07P6 X
Y2
VCC
NC7WZ16P6 X
GND
A1
R19
1KOHM
RES0603
10KOHM
3
2
1
RES0402
R18
U7
4
5
6
4
5
6
SDO
V_DIG
C81
0.1U
V_DIG
R20
V_DIG
V_DIG
RES0603
1KOHM
R21
RES0603
1KOHM
R17
RES0603
100KOHM
VS
V_DIG
3
SPI_CSB
RES0603
100KOHM
R23
RES0603
100KOHM
R22
J2
3
1
J1
SPI_SCLK
SPI_SDIO
1
V_DIG
J1 - JUMPER PINS 2 TO 3 FOR SPI OPERATION
JUMPER PINS 1 TO 2 FOR DCS ENABLE
J2 - JUMPER PINS 2 TO 3 FOR SPI OPERATION
JUMPER PINS 1 TO 2 FOR TWOS COMPLEMENT OUTPUT
J21 - INSTALL JUMPER FOR SPI OPERATION
06909-308
SDI
AD9600
Figure 81. Evaluation Board Schematic, SPI Circuitry
10KOHM
R65
POWER_JAC K
2
Figure 82. Evaluation Board Schematic, Power Supply
Rev. B | Page 59 of 72
P4
P3
P2
P1
VCP
VS
DRVDDIN
SJ35
P4
6
P6
5
P5
4
P4
3
P3
2
P2
1
1
AVDDIN
SMDC110F
C41
10U
F2
OPTIONALPOWERSUPPLYINPUTS
P3
1
P1
1
3
L6
IND1210
10UH
10uh
L10
IND1210
L9
IND1210
10UH
1
2
1
2
2
CR7
2
C53
10U
C102
10U
C52
10U
BNX-016
3 PSG
1 BIAS
C58
0.1U
C103
0.1U
C57
0.1U
CG6
CG5
CG 4
CB 2
1
CR8
10uh
IND1210
L11
1
R16
DRVDD
2
PWR_IN
DVDD
AVDD
2
C54
10U
RES060 3
SHOT_RECT
261OHM
TP25
1
C59
0.1U
1
2
V_DIG
CR10
S2A_RECT
CR11
2
1
1TP4
1
1
TP13
1
TP12
1
TP10
1
1TP9
C42
1U
SD
6
8 IN
7 IN2
ADP3334
2
C44
1U
CR12
S2A_RECT
GND TESTPOINTS
1
S2A_RECT
3
VR3
PAD
5
GND
OUT
ADP333 9
C43
1U
DRVDD
3.3
2.5
1.8
R13
140K
107K
76.8K
1
R14
78.7K
94.0K
147K
DRVDDSETTING
VR1
OUT 1
OUT2 2
FB 3
IN
4
GND
1
F1
R13
J16
140KOHM
R14
S2A_REC
T
78.7KOHM
AC
10uh
2
C93
0.001U
L3
IND1210
C45
1U
AVDDIN
1
10uh
L4
IND1210
2
DRVDDIN
06909-309
POWERINPUT
6V, 2A MAX
AD9600
PWR_IN
PWR_IN
Rev. B | Page 60 of 72
Figure 83. Evaluation Board Schematic, Power Supply (Continued)
PAD
ADP333 9
VCP
5
C119
10U
GND
OUT 1
OUT2 2
FB 3
VR2
OUT
OUT
C124
10U
VS_OUT_D
R
Power Supply ByPass Capacitors
VCP
SD
6
8 IN
7 IN2
ADP3334
C132
1U
IN
VR6
C135
1U
3
C133
1U
PAD
ADP333 9
4
GND
1
4
GND
1
IN
VS
C136
1U
C134
1U
C118
10U
R25
VR5
140KOHM
R15
0.001U
C95
SJ36
78.7KOHM
1
1
1
2
2
C131
1U
L13
IND1210
10uh
L12
IND1210
10uh
L8
IND1210
10UH
2
VS
VCP
VS
VS_OUT_DR
C110
0.1U
PWR_IN
C112
0.1U
C108
0.1U
C129
1U
3
IN
PAD
ADP333 9
VR4
4
GND
C111
0.1U
1
3
C115
0.1U
OUT
C114
0.1U
C113
0.1U
C130
1U
1
2
C107
0.1U
L1
IND1210
10UH
C116
0.1U
C105
0.1U
AMPVDD
06909-310
PWR_IN
AD9600
SJ37
AD9600
06909-185
EVALUATION BOARD LAYOUTS
Figure 84. Evaluation Board Layout, Primary Side
Rev. B | Page 61 of 72
06909-186
AD9600
Figure 85. Evaluation Board Layout, Ground Plane
Rev. B | Page 62 of 72
06909-187
AD9600
Figure 86. Evaluation Board Layout, Power Plane
Rev. B | Page 63 of 72
06909-188
AD9600
Figure 87. Evaluation Board Layout, Power Plane
Rev. B | Page 64 of 72
06909-189
AD9600
Figure 88. Evaluation Board Layout, Ground Plane
Rev. B | Page 65 of 72
06909-190
AD9600
Figure 89. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. B | Page 66 of 72
06909-191
AD9600
Figure 90. Evaluation Board Layout, Silkscreen, Primary Side
Rev. B | Page 67 of 72
06909-192
AD9600
Figure 91. Evaluation Board Layout, Silk Screen, Secondary Side
Rev. B | Page 68 of 72
AD9600
BILL OF MATERIALS
Table 23. Evaluation Board Bill of Materials (BOM) 1, 2
Item
1
2
Qty
1
55
3
1
Reference
Designator
AD9600CE_REVB
C1 to C3, C6, C7,
C13, C14, C17, C18,
C20 to C26, C32,
C57 to C61, C65
to C76, C81 to
C83, C96 to C101,
C103, C105, C107,
C108, C110 to
C116, C145
C80
4
2
C5, C84
5
10
6
13
7
10
8
1
C33, C35, C63,
C93 to C95, C122,
C126, C127, C137
C15, C42 to C45,
C129 to C136
C27, C41, C52 to
C54, C62, C102,
C118, C119, C124
CR5
9
2
CR6, CR9
Description
PCB
0.1 μF, 16 V ceramic
capacitor, SMT 0402
Package
PCB
C0402SM
Manufacturer
Analog Devices
Murata
Mfg. Part Number
GRM155R71C104KA88D
18 pF, COG, 50 V, 5% ceramic
capacitor, SMT 0402
4.7 pF, COG, 50 V, 5% ceramic
capacitor, SMT 0402
0.001 μF, X7R, 25 V, 10%
ceramic capacitor, SMT 0402
C0402SM
Murata
GJM1555C1H180JB01J
C0402SM
Murata
GJM1555C1H4R7CB01J
C0402SM
Murata
GRM155R71H102KA01D
1 μF, X5R, 25 V, 10% ceramic
capacitor, SMT 0805
10 μF, X5R, 10 V, 10% ceramic
capacitor, SMT 1206
C0805
Murata
GR4M219R61A105KC01D
C1206
Murata
GRM31CR61C106KC31L
Schottky diode HSMS2822, SOT23
SOT23
Avago Technologies
HSMS-2822-BLKG
LED RED, SMT, 0603, SS-type
LED0603
Panasonic
LNJ208R8ARA
10
4
CR7, CR10 to CR12
50 V, 2 A diode
DO_214AA
Micro Commercial Components
S2A-TP
11
1
CR8
30 V, 3 A diode
DO_214AB
Micro Commercial Components
SK33-TP
12
1
F1
EMI filter
FLTHMURATABNX01
Murata
BNX016-01
13
1
F2
L1206
Tyco Raychem
NANOSMDC150F-2
14
2
J1 to J2
HDR3
Samtec
TWS-1003-08-G-S
15
9
HDR2
Samtec
TWS-102-08-G-S
16
3
J4 to J9, J18, J19,
J21
J10 to J12
6.0 V, 3.0 A, trip current
resettable fuse
3-pin, male, single row,
straight header
2-pin, male, straight header
Interface connector
TYCO_HM_ZD
Tyco
6469169-1
17
1
J14
8-pin, male, double row,
straight header
DC power jack connector
CNBERG2X4H350LD
Samtec
TSW-104-08-T-D
PWR_JACK1
Cui Stack
PJ-002A
10 μH, 2 A bead core, 1210
1210
Panasonic
EXC-CL3225U1
6-terminal connector
PTMICRO6
Weiland Electric, Inc.
Z5.531.3625.0
18
1
J16
19
10
20
1
L1, L3, L4, L6, L8
to L13
P3
21
1
P4
4-terminal connector
PTMICRO4
Weiland Electric, Inc.
Z5.531.3425.0
22
3
R7, R30, R45
R0603
NIC Components
NRC06F57R6TRF
23
27
R0402SM
NIC Components
NRC04ZOTRF
24
2
R2, R3, R4, R32,
R33, R42, R64,
R67, R69, R90,
R96, R99, R101,
R104, R110 to
R113, R115, R119,
R121, R123, R141
to R145
R13, R25
57.6 Ω, 0603, 1/10 W,
1% resistor
0 Ω, 1/16 W, 5% resistor
R0603
NIC Components
NRC06F1403TRF
25
2
R14, R15
R0603
NIC Components
NRC06F7872TRF
140 kΩ, 0603, 1/10 W,
1% resistor
78.7 kΩ, 0603, 1/10 W,
1% resistor
Rev. B | Page 69 of 72
AD9600
Item
26
Qty
1
Reference
Designator
R16
27
3
R17, R22, R23
28
7
29
3
R18, R24, R63, R65,
R82, R118, R140
R19, R20, R21
30
9
31
5
R26, R27, R43,
R46, R47, R70,
R71, R73, R74
R57, R59 to R62
32
1
R58
33
1
R76
34
4
S2, S3, S5 ,S12
Description
261 Ω, 0603, 1/10 W,
1% resistor
100 kΩ, 0603, 1/10 W,
1% resistor
10 kΩ, 0402, 1/16 W,
1% resistor
1 kΩ, 0603, 1/10 W,
1% resistor
33 Ω, 0402, 1/16 W,
5% resistor
Package
R0603
Manufacturer
NIC Components
Mfg. Part Number
NRC06F2610TRF
R0603
NIC Components
NRC06F1003TRF
R0402SM
NIC Components
NRC04F1002TRF
R0603
NIC Components
NRC06F1001TRF
R0402SM
NIC Components
NRC04J330TRF
22 Ω, 16-pin, 8-resistor,
resistor array
R_742
CTS Corporation
742C163220JPTR
RES_ARRY
CTS Corporation
742C083220JPTR
R0402SM
NIC Components
NCR04F2000TRF
SMA_EDGE
142-0701-201
35
1
SJ35
22 Ω, 8-pin, 4-resistor,
resistor array
200 Ω, 0402, 1/16 W,
1% resistor
SMA, inline, male,
coaxial connector
0 Ω, 1/8 W, 1% resistor
SLDR_PAD2MUYLAR
Emerson Network
Power
NIC Components
36
5
T1 to T5
Balun
TRAN6B
M/A-COM
MABA-007159-000000
37
1
U1
IC, AD9600
LFCSP64-9X9-9E
Analog Devices
38
1
U2
Clock distribution, PLL IC
LFCSP64-9X9
Analog Devices
AD9600BCPZ/AD9600AB
CPZ
AD9516-4BCPZ
39
1
U3
Dual inverter IC
SC70_6
Fairchild Semiconductor
NC7WZ04P6X_NL
40
1
U7
SC70_6
Fairchild Semiconductor
NC7WZ07P6X_NL
NRC10ZOTRF
41
1
U8
Dual buffer IC,
open-drain circuits
UHS dual buffer IC
SC70_6
Fairchild Semiconductor
NC7WZ16P6X_NL
42
3
U15 to U17
16-bit CMOS buffer IC
TSOP48_8_1MM
Fairchild Semiconductor
74VCX16244MTDX_NL
43
2
VR1, VR2
Adjustable regulator
LFCSP8-3X3
Analog Devices
ADP3334ACPZ
44
1
VR3
1.8 V high accuracy regulator
SOT223-HS
Analog Devices
ADP3339AKCZ-1.8
45
1
VR4
5.0 V high accuracy regulator
SOT223-HS
Analog Devices
ADP3339AKCZ-5.0
46
2
VR5, VR6
3.3 V high accuracy regulator
SOT223-HS
Analog Devices
ADP3339AKCZ-3.3
47
1
Y1
Oscillator clock, VFAC3
OSC-CTS-CB3
Valpey Fisher
VFAC3-BHL
48
2
Z1, Z2
High speed IC, op amp
LFCSP16-3X3-PAD
Analog Devices
AD8352ACPZ
1
2
This bill of materials is RoHS compliant.
The bill of materials lists only those items that are normally installed in the default condition. Items that are not installed are not included in the BOM.
Rev. B | Page 70 of 72
AD9600
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
64 1
49
48
PIN 1
INDICATOR
PIN 1
INDICATOR
8.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
7.25
7.10 SQ
6.95
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
080108-C
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 92. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
0.60 MAX
9.00
BSC SQ
0.60
MAX
64 1
49
PIN 1
INDICATOR
48
PIN 1
INDICATOR
8.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
SEATING
PLANE
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
7.65
7.50 SQ
7.35
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 93. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-6)
Dimensions shown in millimeters
Rev. B | Page 71 of 72
041509-A
TOP VIEW
AD9600
ORDERING GUIDE
Model
AD9600ABCPZ-150 1,2
AD9600ABCPZ-1251,2
AD9600ABCPZ-1051,2
AD9600BCPZ-1501
AD9600BCPZ-1251
AD9600BCPZ-1051
AD9600-150EBZ1
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board with AD9600 and Software
Z = RoHS Compliant Part.
Recommended for use in new designs; reference PCN 09_0156.
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06909-0-12/09(B)
Rev. B | Page 72 of 72
Package Option
CP-64-6
CP-64-6
CP-64-6
CP-64-3
CP-64-3
CP-64-3